WO2024021533A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2024021533A1
WO2024021533A1 PCT/CN2023/070663 CN2023070663W WO2024021533A1 WO 2024021533 A1 WO2024021533 A1 WO 2024021533A1 CN 2023070663 W CN2023070663 W CN 2023070663W WO 2024021533 A1 WO2024021533 A1 WO 2024021533A1
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Prior art keywords
layer
along
electrode layer
substrate
opening
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PCT/CN2023/070663
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English (en)
French (fr)
Inventor
黄猛
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长鑫存储技术有限公司
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Priority to US18/449,018 priority Critical patent/US20240040777A1/en
Publication of WO2024021533A1 publication Critical patent/WO2024021533A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or writing data information into the capacitor.
  • memories such as DRAM are gradually developing from two-dimensional structures to three-dimensional structures.
  • it is necessary to provide multiple support frames in the DRAM and multiple lower electrode isolation structures for isolating adjacent capacitors.
  • three support frames are usually required (i.e., two support frames located on opposite sides of the transistor channel region, and one support frame located on the side of the capacitor away from the transistor) and two lower support frames.
  • Electrode isolation structure located at opposite ends of the capacitor).
  • Both the support frame and the lower electrode isolation structure need to occupy the space of the semiconductor structure, thereby affecting further shrinkage of the size of the semiconductor structure.
  • the size of the word line in DRAM is limited by the gap size between the two support frames, and the support frame will be affected by many accidental factors during the formation process, resulting in large fluctuations in the size of the support frame. properties, resulting in reduced controllability of the semiconductor manufacturing process.
  • the semiconductor structure and its formation method provided by some embodiments of the present disclosure are used to reduce the size of the semiconductor structure while ensuring the stability of the semiconductor structure, and improve the controllability of the semiconductor structure manufacturing process.
  • the present disclosure provides a semiconductor structure, including:
  • a stacked structure, located on the substrate, the stacked structure includes a plurality of storage areas spaced apart along a first direction, and isolation walls located between the storage areas; the storage area includes a plurality of storage areas spaced apart along a second direction.
  • a plurality of memory cells are arranged, the memory cells include a transistor structure and a capacitor structure located on the side of the transistor structure along the third direction and electrically connected to the transistor structure, the capacitor structure is on the substrate
  • the projected contour line on the top surface is a rectangle or a rounded rectangle.
  • the width of the transistor structure is equal to the width of the capacitor structure; along the third direction, the width of the transistor structure The structure is aligned with the capacitor structure; both the first direction and the third direction are parallel to the top surface of the substrate, the second direction is perpendicular to the top surface of the substrate, and the The first direction intersects the third direction.
  • the stacked structure further includes:
  • An isolation layer is located between adjacent storage units in the storage area, and the isolation layer is connected to the side wall of the isolation wall.
  • the thickness of the isolation layer is 20 nm to 30 nm.
  • it further includes a word line located in the storage area, the word line extends along the second direction, and a plurality of the word lines are spaced apart along the first direction;
  • the transistor structure include:
  • the channel layer is distributed around the periphery of the gate layer, and the projected outline of the channel layer on the top surface of the substrate is a rectangle or a rounded rectangle, and the word line is connected to the storage area.
  • the source region and the drain region are distributed at opposite ends of the channel layer along the third direction.
  • it further includes a word line located in the storage area, the word line extends along the second direction, and a plurality of the word lines are spaced apart along the first direction;
  • the transistor structure include:
  • the gate layer is distributed around the periphery of the channel layer, the outline of the gate layer projected on the top surface of the substrate is a rectangle or a rounded rectangle, and the word lines are connected The adjacent gate layers in the storage area along the second direction;
  • the source region and the drain region are distributed at opposite ends of the channel layer along the third direction.
  • the width of the gate layer is greater than or equal to the width of the word line in a direction parallel to the top surface of the substrate.
  • the transistor structure further includes a gate dielectric layer located between the gate layer and the channel layer, and the thickness of the gate dielectric layer is greater than 10 nm.
  • the capacitive structure includes:
  • a dielectric layer distributed around the periphery of the upper electrode layer is a dielectric layer distributed around the periphery of the upper electrode layer
  • a lower electrode layer is distributed around the periphery of the dielectric layer, the lower electrode layer is electrically connected to the transistor structure, and the outline of the projection of the lower electrode layer on the top surface of the substrate is a rectangle or a circle. corner rectangle.
  • the capacitive structure includes:
  • a dielectric layer distributed around the periphery of the upper electrode layer is a dielectric layer distributed around the periphery of the upper electrode layer
  • the lower electrode layer includes a first conductive layer distributed around the periphery of the dielectric layer, and a second conductive layer distributed around the periphery of the first conductive layer, the second conductive layer being electrically connected to the transistor structure, And the outline of the projection of the second conductive layer on the top surface of the substrate is a rectangle or a rounded rectangle.
  • the drain region in the transistor structure is integrally formed with the second conductive layer.
  • the material of the first conductive layer is different from the material of the second conductive layer, and the material of the second conductive layer is a silicon material including doped ions.
  • the capacitive structure includes:
  • An upper electrode layer, the projection of the upper electrode layer on the top surface of the substrate is a long strip, and the upper electrode layer extends along the third direction;
  • a dielectric layer, the dielectric layer is distributed around the periphery of the upper electrode layer, and the outline of the projection of the dielectric layer on the top surface of the substrate is a rectangle or a rounded rectangle;
  • a lower electrode layer is distributed around the periphery of the dielectric layer, the lower electrode layer is electrically connected to the transistor structure, and the outline of the projection of the lower electrode layer on the top surface of the substrate is a rectangle or a circle. corner rectangle.
  • the capacitive structure includes:
  • the upper electrode layer includes a plurality of sub-upper electrode layers spaced apart along the third direction;
  • the dielectric layer includes a plurality of sub-dielectric layers arranged at intervals along the third direction, and the sub-dielectric layers are distributed around the periphery of the sub-upper electrode layer;
  • the lower electrode layer extends along the third direction and continuously covers the outer periphery of a plurality of the sub-dielectric layers spaced along the third direction.
  • the lower electrode layer is electrically connected to the transistor structure, and the lower electrode layer is electrically connected to the transistor structure.
  • the outline of the projection of the lower electrode layer on the top surface of the substrate is a rectangle or a rounded rectangle.
  • the capacitive structure includes:
  • a common electrode layer located in the storage area, the common electrode layer extending along the second direction and connecting the upper electrode layers adjacent along the second direction;
  • a width of the common electrode layer is less than or equal to a width of the upper electrode layer.
  • it also includes:
  • Bit lines a plurality of the bit lines are arranged at intervals along the second direction, the bit lines are electrically connected to a plurality of the transistor structures arranged at intervals along the first direction, and the material of the bit lines is Includes ion-doped silicon materials.
  • the source region and the bit line in the transistor structure are integrally formed.
  • the present disclosure also provides a method for forming a semiconductor structure, including the following steps:
  • a stacked structure is formed on the substrate, the stacked structure includes a plurality of storage areas spaced apart along a first direction, and isolation walls located between the storage areas; the storage area includes a plurality of storage areas spaced apart along a second direction.
  • a plurality of memory cells are arranged, the memory cells include a transistor structure and a capacitor structure located on the side of the transistor structure along the third direction and electrically connected to the transistor structure, the capacitor structure is on the substrate
  • the projected contour line on the top surface is a rectangle or a rounded rectangle.
  • the width of the transistor structure is equal to the width of the capacitor structure; along the third direction, the width of the transistor structure The structure is aligned with the capacitor structure; both the first direction and the third direction are parallel to the top surface of the substrate, the second direction is perpendicular to the top surface of the substrate, and the The first direction intersects the third direction.
  • the specific steps of forming a stacked structure on the substrate include:
  • the stacked layer including a plurality of semiconductor layers spaced apart along the second direction;
  • a plurality of the storage units are formed in the storage area and are spaced apart along the second direction.
  • the specific step of forming a first trench penetrating the stacked layer along the second direction includes:
  • the semiconductor layer serves as a bit line.
  • the outline of the projection of the storage area on the top surface of the substrate is a rectangle or a rounded rectangle, and the storage area includes a transistor area and is located along the third direction. a capacitance area outside the transistor area; the specific steps of forming a plurality of memory cells spaced apart along the second direction in the storage area include:
  • the projections of the first opening and the second opening on the top surface of the substrate are both rectangular or rounded rectangles, and along the first direction, the width of the first opening is the same as the width of the first opening.
  • the widths of the second openings are equal; the first openings and the second openings are aligned and arranged along the third direction; the remaining semiconductor layer in the transistor region serves as a channel layer, and the remaining semiconductor layer along the third direction Source regions and drain regions located at both ends of the channel layer in three directions;
  • At least an upper electrode layer and a dielectric layer distributed around the periphery of the upper electrode layer are formed in the second opening.
  • the width of the first opening is equal to the width of the second opening
  • the first opening and the second opening are aligned and arranged.
  • the stacked layer includes the semiconductor layer and the sacrificial layer alternately stacked along the second direction; forming a first opening penetrating the stacked layer along the second direction through the transistor region, and after forming the second opening penetrating the stacked layer of the capacitor region along the second direction, the following steps are also included:
  • the channel layer in the semiconductor layer remaining in the transistor region is distributed around the periphery of the first opening; or,
  • the channel layer in the remaining semiconductor layer in the transistor region penetrates the first opening along the third direction.
  • the specific steps of forming a gate layer in the first opening include:
  • the specific steps of forming at least an upper electrode layer and a dielectric layer distributed around the periphery of the upper electrode layer in the second opening include:
  • An upper electrode layer covering the dielectric layer is formed in the third opening to form a capacitor structure including the lower electrode layer, the dielectric layer and the upper electrode layer.
  • the specific steps of forming at least an upper electrode layer and a dielectric layer distributed around the periphery of the upper electrode layer in the second opening include:
  • An upper electrode layer covering the dielectric layer is formed in the second opening to form a capacitor structure including the first conductive layer, the second conductive layer, the dielectric layer and the upper electrode layer.
  • the semiconductor structure and its formation method provided by some embodiments of the present disclosure can not only electrically isolate the adjacent storage areas by setting isolation walls between any adjacent storage areas, but also can support the stacked structure. This eliminates the need to provide additional support frames and lower electrode isolation structures, thereby ensuring the stability of the semiconductor structure while further reducing the size of the semiconductor structure and improving the integration and storage density of the semiconductor structure. Moreover, since there is no support frame in the semiconductor structure, the size of the transistor structure (especially the size of the gate layer and channel layer in the transistor structure) is no longer affected by the fluctuation of the manufacturing process of the support frame, thereby improving The controllability of the semiconductor structure manufacturing process helps to further improve the yield of the semiconductor structure.
  • an isolation layer is also provided between adjacent storage units in the storage area, and the isolation layer is connected to the side wall of the isolation wall.
  • the isolation layer isolates adjacent storage units.
  • the storage unit; on the other hand, the isolation layer and the isolation wall jointly support the stacked structure, thereby further improving the stability of the stacked structure.
  • the projection of the capacitor structure in the memory unit in some embodiments of the present disclosure on the top surface of the substrate is a regular rectangle or a rounded rectangle, and along the first direction, the width of the transistor structure is the same as the width of the transistor structure.
  • the width of the capacitor structure is equal, and the transistor structure and the capacitor structure are arranged in alignment along the third direction.
  • it helps to improve the consistency of the morphology between each memory unit, thereby improving the
  • the consistency of the electrical properties of each storage unit within the semiconductor structure is used to improve the performance stability of the semiconductor structure; on the other hand, the space of the storage area can be fully utilized, and no additional isolation structure or support is required inside the storage unit.
  • the structure maximizes the utilization of the storage area space and improves the utilization rate of the internal space of the semiconductor structure, thereby further improving the integration degree and storage density of the semiconductor structure.
  • FIG. 1 is a schematic three-dimensional structural diagram of a semiconductor structure in the first embodiment of the present disclosure
  • Figure 2 is a schematic top view of the structure of Figure 1;
  • FIG. 3 is a schematic three-dimensional structural diagram of a semiconductor structure in a second embodiment of the present disclosure.
  • Figure 4 is a schematic top view of the structure of Figure 3;
  • FIG. 5 is a schematic top view of a semiconductor structure in a third embodiment of the present disclosure.
  • Figure 6 is a schematic cross-sectional view of Figure 2 at position a-a;
  • Figure 7 is another schematic cross-sectional view of Figure 2 at position a-a;
  • Figure 8 is a schematic cross-sectional view of Figure 4 at position b-b;
  • Figure 9 is another schematic cross-sectional view of Figure 4 at position b-b;
  • Figure 10 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure
  • 11-23 are schematic diagrams of the main process structures in the process of forming semiconductor structures according to specific embodiments of the present disclosure.
  • Figure 1 is a schematic three-dimensional structural diagram of the semiconductor structure in the first embodiment of the specific implementation of the present disclosure.
  • Figure 2 is a top structural schematic diagram of Figure 1.
  • the semiconductor structure includes:
  • the memory cells include a transistor structure TR and a capacitor structure CAP located on the side of the transistor structure TR along the third direction D3 and electrically connected to the transistor structure TR.
  • the projected outline of the capacitor structure CAP on the top surface of the substrate is a rectangle or a rounded rectangle, and along the first direction D1, the width of the transistor structure TR is the same as that of the capacitor structure CAP are equal in width; along the third direction D3, the transistor structure TR and the capacitor structure CAP are aligned and arranged; both the first direction D1 and the third direction D3 are aligned with the top of the substrate.
  • the second direction D2 is perpendicular to the top surface of the substrate, and the first direction D1 intersects the third direction D3.
  • the semiconductor structure described in this specific embodiment may be, but is not limited to, DRAM.
  • the substrate (not shown in the figure) may be but is not limited to a silicon substrate.
  • This specific embodiment will be described by taking the substrate 20 as a silicon substrate as an example.
  • the substrate 20 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI.
  • the substrate is used to support the stacked structure thereon.
  • the top surface of the substrate in this specific embodiment refers to the surface of the substrate facing the stacked structure.
  • the plurality mentioned in this specific embodiment refers to two or more.
  • the stacked structure includes the storage areas PM and the isolation walls 10 alternately arranged along the first direction D1, and the storage area PM includes a plurality of storage areas arranged at intervals along the second direction. unit, the storage area PM adjacent along the first direction D1 can be electrically isolated by the isolation wall 10 .
  • the plurality of storage units in the storage area PM are all in contact with the side walls of the isolation wall 10 to support the plurality of storage units in the storage area PM through the isolation wall 10, thereby improving The overall stability of the stacked structure.
  • the stacking structure is supported by the isolation wall located outside the storage unit, thereby eliminating the need to set up a support structure inside the storage unit, thereby improving the utilization of the internal space of the storage unit.
  • the outline of the projection of the capacitor structure CAP on the top surface of the substrate is a rectangle or a rounded rectangle means that the entirety of the lower electrode layer, dielectric layer and upper electrode layer in the capacitor structure CAP is located there.
  • the shape of the projected contour line on the top surface of the substrate is a rectangle or a rounded rectangle.
  • the outline of the projection of the transistor structure TR on the top surface of the substrate is a rectangle or a rounded rectangle.
  • the outline of the projection of the transistor structure TR on the top surface of the substrate is a rectangle or a rounded rectangle means that the channel layer, gate layer, source region and drain region in the transistor structure TR
  • the shape of the contour line projected on the top surface of the substrate as a whole is a rectangle or a rounded rectangle.
  • the storage units are separated and supported by the isolation wall 10, so that any of the storage units has a regular shape.
  • the projection of the storage unit on the top surface of the substrate The shape of the outline is a rectangle or a rounded rectangle.
  • the isolation wall 10 is used to separate and support the memory cells, so that the shape of the projected outline of the capacitor structure in any of the memory cells on the top surface of the substrate can be a regular rectangle or circle.
  • Corner rectangle (or the shape of the projected outline of the capacitor structure and transistor structure in the memory unit on the top surface of the substrate is a regular rectangle or a rounded rectangle), which simplifies the manufacturing process of the memory unit, It also helps to improve the consistency of the morphology of each memory unit, thereby improving the consistency of the electrical properties of each memory unit within the semiconductor structure, so as to improve the performance stability of the semiconductor structure.
  • the rounded rectangle described in this specific embodiment refers to a rectangle in which at least one inner corner is an arc-shaped inner corner.
  • Alignment of the transistor structure TR and the capacitor structure CAP along the third direction D3 means that the central axis of the transistor structure TR extending along the third direction D3 is aligned with the capacitor structure CAP.
  • the central axis extending in the third direction D3 is aligned along the third direction D3.
  • the width of the transistor structure TR along the first direction D1 is equal to the width of the capacitor structure CAP along the first direction D1, and the transistor structure TR and the capacitor structure CAP extend along the third direction D1.
  • the aligned arrangement in direction D3 not only forms the transistor structure TR and the capacitor structure CAP in regular shapes in each storage area PM, but also combines part of the process technology of the transistor structure TR with part of the process technology of the capacitor structure CAP. Compatible, thereby simplifying the manufacturing process of the semiconductor structure, and also making maximum use of the space inside the storage area, while improving the controllability of the transistor structure TR, and increasing the electrical conductivity of the capacitor structure CAP capacity.
  • the stacked structure further includes:
  • the isolation layer 16 is located between adjacent storage units in the storage area PM, and the isolation layer 16 is connected to the side wall of the isolation wall 10 .
  • the memory area PM includes the memory cells and the isolation layer 16 alternately stacked along the second direction D2.
  • the isolation layer 16 can isolate the adjacent storage units along the second direction D2 in the storage area PM, and on the other hand, it can also support the stacked structure together with the isolation wall 10, thereby further The stability of the stacked structure is enhanced and the probability of the semiconductor structure toppling or collapsing during the manufacturing process is reduced.
  • the thickness of the isolation layer 16 is 20 nm to 30 nm.
  • the thickness of the isolation layer 16 should not be too small, otherwise it will not only increase the parasitic capacitance effect between the adjacent memory cells along the second direction D2 or cause the parasitic capacitance effect along the second direction D2 Leakage between adjacent memory cells will also increase the capacitive coupling effect between adjacent bit lines.
  • the thickness of the isolation layer 16 should not be too large, otherwise the size of the semiconductor structure will be increased.
  • the thickness of the isolation layer 16 along the second direction D2 is 20 nm to 30 nm. In an example, the thickness of the isolation layer 16 along the second direction D2 is 25 nm.
  • the material of the isolation layer 16 and the isolation wall 10 are Materials are the same.
  • the materials of the isolation layer 16 and the isolation wall 10 are both oxide materials, such as silicon dioxide.
  • the transistor structure includes:
  • the channel layer 20 is distributed around the periphery of the gate layer 11 , and the projected outline of the channel layer 20 on the top surface of the substrate is a rectangle or a rounded rectangle, and the word lines 60 are connected to The adjacent gate layers 11 in the storage area PM along the second direction D2;
  • the source region and the drain region are distributed at opposite ends of the channel layer 20 along the third direction D3.
  • FIG. 6 is a schematic cross-sectional view of FIG. 2 at position a-a
  • FIG. 7 is another schematic cross-sectional view of FIG. 2 at position a-a
  • the transistor structure TR includes the gate layer 11, the gate dielectric layer 12 surrounding and covering the surface of the gate layer 11, and the channel layer surrounding and covering the surface of the gate dielectric layer 12. 20.
  • the source region and the drain region distributed at the opposite ends of the channel layer 20 along the third direction D3, forming a channel full surrounding structure, and the drain region and the The capacitor structure CAP is in direct contact with the electrical connection.
  • the channel layer 20 , the source region and the drain region may all be made of silicon material.
  • the width of the gate layer 11 is greater than or equal to the width of the word line 60 in a direction parallel to the top surface of the substrate.
  • the width of the gate layer 11 is greater than the width of the word line 60 .
  • the gate layer The width of 11 is equal to the width of the word line 60 .
  • a word line 60 located in the storage area PM is also included, the word line 60 extends along the second direction D2, and a plurality of the word lines 60 are spaced apart along the first direction D1.
  • the transistor structure includes:
  • the gate layer 11 is distributed around the periphery of the channel layer 20, and the projected outline of the gate layer 11 on the top surface of the substrate is a rectangle or a rounded rectangle, so
  • the word line 60 connects the adjacent gate layers 11 along the second direction D2 in the storage area PM;
  • the source region and the drain region are distributed at opposite ends of the channel layer 20 along the third direction D3.
  • the transistor structure TR includes the channel layer 20, a gate dielectric layer 12 surrounding and covering the surface of the channel layer 20, and then the gate covering the surface of the gate dielectric layer 12.
  • the capacitor structure CAP is in direct contact with the electrical connection.
  • the channel layer 20 , the source region and the drain region may all be made of silicon material.
  • the transistor structure TR further includes a gate dielectric layer 12 located between the gate layer 11 and the channel layer 20, The thickness of the gate dielectric layer 12 is greater than 10 nm.
  • the capacitor structure CAP includes:
  • the dielectric layer 13 is distributed around the periphery of the upper electrode layer 14;
  • the lower electrode layer 15 is distributed around the periphery of the dielectric layer 13, the lower electrode layer 15 is electrically connected to the transistor structure TR, and the outline of the projection of the lower electrode layer 15 on the top surface of the substrate Lines are rectangles or rounded rectangles.
  • the capacitor structure CAP includes the lower electrode layer 15, the dielectric layer 13 and the upper electrode layer 14, wherein the lower electrode layer 15 and the drain electrode in the transistor structure TR
  • the lower electrode layer 15 has a rectangular annular structure or a rounded rectangular surrounding structure.
  • the dielectric layer 13 is located between the upper electrode layer 14 and the lower electrode layer 15 .
  • the upper electrode 14 and the lower electrode layer 15 may be made of the same material, for example, both metal tungsten or TiN.
  • FIG. 3 is a schematic three-dimensional structural diagram of the semiconductor structure in the second embodiment of the present disclosure
  • FIG. 4 is a schematic top structural diagram of FIG. 3 .
  • the capacitor structure includes:
  • the dielectric layer 13 is distributed around the periphery of the upper electrode layer 14;
  • the lower electrode layer includes a first conductive layer 151 distributed around the periphery of the dielectric layer 14 and a second conductive layer 30 distributed around the periphery of the first conductive layer 151 .
  • the second conductive layer 30 and the The transistor structure TR is electrically connected, and the projected outline of the second conductive layer 30 on the top surface of the substrate is a rectangle or a rounded rectangle.
  • the drain region in the transistor structure TR is integrally formed with the second conductive layer 30 .
  • the material of the first conductive layer 151 is different from the material of the second conductive layer 30 , and the material of the second conductive layer 30 is a silicon material including doped ions.
  • the capacitor structure CAP includes the lower electrode layer, the dielectric layer 13 and the upper electrode layer 14.
  • the dielectric layer 13 covers the surface of the upper electrode layer 14, and the lower electrode layer covers The dielectric layer 13 faces away from the surface of the upper electrode layer 14
  • the lower electrode layer includes the first conductive layer 151 and the second conductive layer 30 .
  • the material of the first conductive layer 151 may be the same as the material of the upper electrode layer 14 , for example, both are metal tungsten or TiN.
  • the second conductive layer 30 is electrically connected to the drain region in the transistor structure TR.
  • the drain region and the second conductive layer 30 in the transistor structure TR By integrating the drain region and the second conductive layer 30 in the transistor structure TR, not only the drain region in the transistor structure and the second conductive layer in the capacitor structure CAP can be integrated
  • the formation process of layer 30 is compatible, thereby simplifying the manufacturing process of the semiconductor structure, and can also increase the contact area between the second conductive layer 30 and the drain region, reducing the distance between the transistor structure TR and the Contact resistance between capacitive structures CAP.
  • the material of the second conductive layer 30 is a silicon material including doped ions, so as to enhance the conductivity of the second conductive layer 30 while reducing the resistance between the second conductive layer 30 and the transistor structure TR. Contact resistance between the drain regions.
  • the drain region and the second conductive layer 30 in the transistor structure TR are integrally formed, which means that there is no contact interface between the drain region and the second conductive layer 30 .
  • the capacitor structure CAP includes:
  • Upper electrode layer 14 the projection of the upper electrode layer 14 on the top surface of the substrate is a long strip, and the upper electrode layer 14 extends along the third direction D3;
  • Dielectric layer 13, which is distributed around the periphery of the upper electrode layer 14, and the projected outline of the dielectric layer 13 on the top surface of the substrate is a rectangle or a rounded rectangle;
  • the lower electrode layer is distributed around the periphery of the dielectric layer 13 , the lower electrode layer is electrically connected to the transistor structure TR, and the outline of the projection of the lower electrode layer on the top surface of the substrate is rectangular. Or a rounded rectangle.
  • the projection of the upper electrode layer 14 in the memory unit on the top surface of the substrate 14 is a long strip structure, and the dielectric layer 13 and the The projected outlines of the first conductive layer 151 and the second conductive layer 30 in the lower electrode layer on the top surface of the substrate are both rectangular or rounded rectangles, thereby simplifying the design of the semiconductor structure.
  • the manufacturing process reduces the manufacturing cost of the semiconductor structure.
  • FIG. 5 is a schematic top structural view of a semiconductor structure in a third embodiment of the present disclosure.
  • the capacitor structure CAP includes:
  • the upper electrode layer includes a plurality of sub-upper electrode layers 141 spaced apart along the third direction D3;
  • the dielectric layer includes a plurality of sub-dielectric layers 131 arranged at intervals along the third direction D3, and the sub-dielectric layers 131 are distributed around the periphery of the sub-upper electrode layer 131;
  • the lower electrode layer extends along the third direction D3 and continuously covers the outer periphery of a plurality of sub-dielectric layers 131 arranged at intervals along the third direction D3.
  • the lower electrode layer is electrically connected to the transistor structure TR. connected, and the outline of the projection of the lower electrode layer on the top surface of the substrate is a rectangle or a rounded rectangle.
  • the capacitor structure CAP includes the patterned upper electrode layer, the dielectric layer and the lower electrode layer.
  • the lower electrode layer includes the first conductive layer 151 and covers the first A second conductive layer on the surface of the conductive layer 151 .
  • the patterned upper electrode layer includes a plurality of sub-upper electrode layers 141 spaced apart along the third direction D3, and the spacing between adjacent upper electrode layers 141 along the third direction D3 is The width is smaller than the spacing distance between two adjacent capacitive structures CAP along the second direction D2 in the storage area PM, so as to facilitate forming a structure extending along the third direction D3 and continuously covering multiple capacitive structures CAP.
  • the first conductive layer 151 on the surface of the sub-dielectric layer 131 is prevented from being connected to the first conductive layer 151 in the two adjacent capacitor structures CAP along the second direction D2.
  • Using the patterned upper electrode layer can help improve the efficiency of the capacitor structure CAP and increase the capacitance of the capacitor structure CAP.
  • Figure 8 is a schematic cross-sectional view of Figure 4 taken at position b-b
  • Figure 9 is another schematic cross-sectional view of Figure 4 taken at position b-b.
  • the capacitor structure CAP includes:
  • a common electrode layer 80 is located in the storage area PM.
  • the common electrode layer 80 extends along the second direction D2 and connects the upper electrode layers 14 adjacent along the second direction D2;
  • the width of the common electrode layer 80 is less than or equal to the width of the upper electrode layer 14 .
  • the common electrode layer 80 extends along the second direction D2 and continuously connects a plurality of electrodes arranged at intervals along the second direction D2 in the storage area PM. the upper electrode layer 14 .
  • the width of the common electrode layer 80 is equal to the width of the upper electrode layer 14 in width to simplify the manufacturing process of the semiconductor structure.
  • the width of the common electrode layer 80 is smaller than that of the upper electrode. The width of the layer 14 increases the facing area of the upper electrode layer 14 and the lower electrode layer, thereby increasing the capacitance of the capacitor structure.
  • the semiconductor structure further includes:
  • Bit lines 17, a plurality of the bit lines 17 are arranged at intervals along the second direction D2, and the bit lines 17 are electrically connected to a plurality of the transistor structures TR arranged at intervals along the first direction D1, so
  • the material of the bit line 17 is silicon material including doped ions.
  • the source region and the bit line 17 in the transistor structure TR are integrally formed.
  • bit lines 17 are arranged at intervals along the second direction D2, and the isolation layer 16 is provided between the adjacent bit lines 17 along the second direction D2 to electrically isolate them.
  • the adjacent bit lines 17 are isolated.
  • the bit line 17 extends along the first direction D1 and is continuously electrically connected to the source regions of a plurality of transistor structures TR arranged at intervals along the first direction D1.
  • the manufacturing process of the semiconductor structure is simplified, and the contact area between the bit line 17 and the source region can be increased, and the contact resistance between the transistor structure TR and the bit line 17 can be reduced.
  • the material of the bit line 17 may be the same as the material of the source region, for example, both are silicon materials including doped ions.
  • FIG. 10 is a flow chart of a method for forming a semiconductor structure in the specific embodiment of the present disclosure.
  • Figures 11 to 23 are diagrams of the method for forming a semiconductor structure in the specific embodiment of the present disclosure. Schematic diagram of the main process structure in the process. Schematic diagrams of the semiconductor structure formed in this specific embodiment can be seen in Figures 1-9.
  • the semiconductor structure described in this specific embodiment may be, but is not limited to, DRAM.
  • the method for forming the semiconductor structure includes the following steps:
  • Step S101 provide a substrate
  • Step S102 forming a stacked structure on the substrate.
  • the stacked structure includes a plurality of storage areas PM arranged at intervals along the first direction D1, and isolation walls 10 located between the storage areas PM;
  • the area PM includes a plurality of memory cells spaced apart along the second direction D2.
  • the memory cells include a transistor structure TR, and a memory unit located on the side of the transistor structure TR along the third direction D3 and electrically connected to the transistor structure TR.
  • Capacitor structure CAP the contour lines of the projection of the capacitor structure CAP on the top surface of the substrate are all rectangular or rounded rectangles, along the first direction D1, the width of the transistor structure TR is the same as the width of the transistor structure TR.
  • the capacitor structure CAP has the same width; along the third direction D3, the transistor structure TR and the capacitor structure CAP are aligned and arranged; both the first direction D1 and the third direction D3 are aligned with the capacitor structure CAP.
  • the top surface of the substrate is parallel, the second direction D2 is perpendicular to the top surface of the substrate, and the first direction D1 intersects the third direction D3.
  • the specific steps of forming a stacked structure on the substrate include:
  • a stacked layer is formed on the substrate.
  • the stacked layer includes a plurality of semiconductor layers 110 spaced apart along the second direction D2, as shown in FIGS. 11 and 12 , wherein FIG. 11 is the semiconductor structure.
  • FIG. 11 is the semiconductor structure.
  • FIG. 11 is the semiconductor structure.
  • FIG. 12 is a schematic cross-sectional view at position c-c in Figure 11;
  • the stacked layer is etched to form first trenches 130 penetrating the stacked layer along the second direction D2.
  • the plurality of first trenches 130 separate the stacked layer into spaced rows along the first direction D1.
  • a plurality of the storage areas PM are distributed, as shown in Figures 13 and 14, wherein Figure 13 is a schematic top view of the structure during the formation of the semiconductor structure, and Figure 14 is a schematic cross-sectional view of Figure 13 at the c-c position;
  • Figure 15 is a schematic top view of the semiconductor structure during the formation process, and Figure 16 It is a schematic cross-sectional view at position c-c in Figure 15;
  • a plurality of the memory cells arranged at intervals along the second direction D2 are formed in the memory area PM.
  • the specific steps of forming the first trench 130 penetrating the stacked layer along the second direction D2 include:
  • the stacked layer is etched along the third direction D3 to form the first trench 130 that does not penetrate the stacked layer along the third direction D3.
  • the end of the stacked layer along the third direction D3 is formed.
  • the remaining semiconductor layer 110 serves as the bit line 17 .
  • the semiconductor layer 110 and the sacrificial layer 120 can be alternately epitaxially grown on the top surface of the substrate along the second direction D2 to form a stacked layer with a superlattice stack structure, as shown in FIG. 11 and FIG. 12 shown. There should be a high etching selectivity ratio between the semiconductor layer 110 and the sacrificial layer 120 to facilitate subsequent selective removal of the sacrificial layer 120 .
  • the semiconductor layer 110 is made of silicon material
  • the sacrificial layer 120 is made of SiGe material.
  • the thickness of the semiconductor layer 110 along the second direction D2 may be 30 nm, and the thickness of the sacrificial layer 120 along the second direction D2 may be 20 nm ⁇ 30 nm.
  • a photolithography process may be used to etch the stacked layer to form a plurality of first trenches 130 penetrating the stacked layer along the second direction D2, and the plurality of first trenches 130 are formed along the
  • the storage areas PM are spaced apart in the first direction D1, thereby dividing the stacked layer into a plurality of storage areas PM spaced apart in the first direction D1, as shown in FIGS. 13 and 14 .
  • the plurality of first trenches 130 divide the semiconductor layer 110 into a plurality of rectangular semiconductor blocks 132 spaced apart along the first direction D1.
  • the first trench 130 does not penetrate the stacked layer along the third direction D3, and the semiconductor layer 110 remaining at the end of the stacked layer serves as the bit line 17.
  • the isolation wall 10 is used to isolate the adjacent storage area PM, and on the other hand, it is also used to support the stacked layer to prevent the stacked layer from tipping or collapsing in subsequent processes.
  • the memory cell is formed in the semiconductor block 132 .
  • This specific embodiment makes the formation process of the isolation wall 10, the formation process of the storage area PM, and the formation process of the bit line 17 compatible, which helps to further simplify the manufacturing process of the semiconductor structure and improve the Manufacturing efficiency of semiconductor structures.
  • the projected outline of the storage area PM on the top surface of the substrate is a rectangle or a rounded rectangle
  • the storage area PM includes a transistor area PT, and a transistor area PT along the third direction.
  • D3 is located in the capacitor area PC outside the transistor area PT, as shown in Figure 17; the specific steps of forming a plurality of memory cells spaced apart along the second direction D2 in the memory area PM include:
  • the second opening 171 of the layer, the projections of the first opening 170 and the second opening 171 on the top surface of the substrate are both rectangular or rounded rectangles, along the first direction D1, so
  • the width of the first opening 170 is equal to the width of the second opening 171; along the third direction D3, the first opening 170 and the second opening 171 are aligned and arranged; the transistor region PT
  • the remaining semiconductor layer 110 serves as the channel layer 20, and the source and drain regions located at both ends of the channel layer 20 along the third direction D3;
  • At least an upper electrode layer 14 and a dielectric layer 13 distributed around the periphery of the upper electrode layer 14 are formed in the second opening 171 , as shown in FIGS. 1 to 9 .
  • the stacked layer includes the semiconductor layer 110 and the sacrificial layer 120 that are alternately stacked along the second direction D2; forming the stacked layer penetrating the transistor region PT along the second direction D2 After the first opening 170 and the second opening 171 penetrating the stacked layer of the capacitor region PC along the second direction D2, the following steps are also included:
  • FIG. 18 is the semiconductor layer 190 .
  • Figure 19 is a schematic cross-sectional view at position c-c in Figure 18;
  • Figure 20 is a top structural schematic diagram during the formation of the semiconductor structure
  • Figure 21 is a diagram 20 Schematic cross-section at c-c position.
  • a dry etching process can be used to simultaneously etch the transistor region PT and the capacitor region PC in the storage region PM. Form the first opening 170 penetrating the semiconductor block 132 and the sacrificial layer 120 along the second direction D2, and simultaneously form the first opening 170 penetrating the semiconductor block 132 along the second direction D2 in the capacitor region PC. and the second opening 171 of the sacrificial layer 120 .
  • the projections of the first opening 170 and the second opening 171 on the top surface of the substrate are both rectangular or rounded rectangles, and along the first direction D1, the The width of the first opening 170 is equal to the width of the second opening 171 , and the first opening 170 and the second opening 171 are aligned in the third direction D3.
  • part of the semiconductor block 132 remains in the transistor region PT and the capacitor region PC, as shown in FIG. 17 .
  • the remaining semiconductor block 132 of the transistor region PT serves as the channel layer 20 and the source and drain regions located at both ends of the channel layer 20 along the third direction D3, and the capacitor region PC
  • the remaining semiconductor blocks 132 may be completely removed later, or may be used to form a capacitor structure.
  • a wet etching process is used to remove all the sacrificial layers 120 in the stacked layers, forming a layer between the adjacent semiconductor layers 110 and exposing the isolation layer 120 .
  • the second trench 190 of the wall 10 is filled with a second dielectric material such as oxide (such as silicon dioxide) in the second trench 190, the first opening 170 and the second opening 171, The isolation layer 160 is formed.
  • the channel layer 20 in the semiconductor layer 110 remaining in the transistor region PT is distributed around the periphery of the first opening 170; or,
  • the channel layer 20 in the remaining semiconductor layer 110 of the transistor region PT penetrates the first opening 170 along the third direction D3.
  • the channel layer 20 in the semiconductor layer 110 remaining in the transistor region PT is distributed around the periphery of the first opening 170 , so that the transistor structure with a channel full surround structure can be subsequently formed.
  • the channel layer 20 in the semiconductor layer 110 remaining in the transistor region PT penetrates the first opening 170 along the third direction D3, so as to facilitate the subsequent formation of the transistor structure with a full gate surround. Meet different semiconductor structure requirements and improve the manufacturing flexibility of the semiconductor structure.
  • the specific steps of forming the gate layer 11 in the first opening 170 include:
  • the word lines 60 of the gate layer 11 are adjacent along the second direction D2.
  • the isolation layer 16 in the first opening 170 is removed, as shown in FIG. 22 , and then an oxide (such as silicon dioxide) is deposited on the inner wall of the first opening 170 to form the gate. polar dielectric layer 12.
  • a first conductive material such as metal tungsten or TiN is deposited in the first opening 170 to form the gate layer 11 covering the surface of the gate dielectric layer 12 and extending along the second direction D2.
  • Word lines 60 connecting adjacent gate layers 11 along the second direction D2 are shown in FIGS. 1 to 9 and 23 .
  • the specific steps of forming at least the upper electrode layer 14 and the dielectric layer 13 distributed around the periphery of the upper electrode layer 14 in the second opening 171 include:
  • An upper electrode layer 14 covering the dielectric layer 13 is formed in the third opening 230 to form a capacitor structure CAP including the lower electrode layer 15 , the dielectric layer 13 and the upper electrode layer 14 , see FIG. 1 and Figure 2.
  • an etching process may be used to remove all the remaining semiconductor blocks 132 in the capacitor region PC to form the third opening 230 .
  • the lower electrode layer 15 , the dielectric layer 13 and the upper electrode layer 14 are formed in the third opening 230 in sequence.
  • the specific steps of forming at least the upper electrode layer 14 and the dielectric layer 13 distributed around the periphery of the upper electrode layer 14 in the second opening 171 include:
  • An upper electrode layer 14 covering the dielectric layer 13 is formed in the second opening 171 to include the first conductive layer 30 , the second conductive layer 151 , the dielectric layer 13 and the upper electrode layer. 14 capacitor structure.
  • the semiconductor block 132 remaining in the capacitive region PC may not be removed at all, or only the remaining portion of the capacitive region PC may be removed.
  • the semiconductor block 132 is implanted with doping ions into the remaining semiconductor layer 110 of the capacitor region PC to form a first conductive layer 30.
  • the first conductive layer 30 serves as the bottom layer in the capacitor structure. part of the electrode layer.
  • the second conductive layer 151 covering the first conductive layer 30 , the dielectric layer 13 covering the second conductive layer 151 , and the upper electrode layer 14 covering the dielectric layer 13 are formed.
  • the semiconductor structure and its formation method provided by some embodiments of this specific embodiment can not only electrically isolate the adjacent storage areas by setting isolation walls between any adjacent storage areas, but also can support the stack.
  • the function of the structure eliminates the need to provide additional support frames and lower electrode isolation structures, so that while ensuring the stability of the semiconductor structure, the size of the semiconductor structure can be further reduced, and the integration level and storage density of the semiconductor structure can be improved.
  • the size of the transistor structure (especially the size of the gate layer and channel layer in the transistor structure) is no longer affected by the fluctuation of the manufacturing process of the support frame, thereby improving
  • the controllability of the semiconductor structure manufacturing process helps to further improve the yield of the semiconductor structure.
  • an isolation layer is also provided between adjacent storage units in the storage area, and the isolation layer is connected to the side wall of the isolation wall.
  • isolation is performed by the isolation layer.
  • the adjacent storage units; on the other hand, the isolation layer and the isolation wall jointly support the stacked structure, thereby further improving the stability of the stacked structure.
  • the projection of the capacitor structure in the memory unit in some embodiments of this embodiment on the top surface of the substrate is a regular rectangle or a rounded rectangle, and along the first direction, the width of the transistor structure Equal to the width of the capacitor structure, the transistor structure and the capacitor structure are arranged in alignment along the third direction.
  • it helps to improve the consistency of the topography between each memory unit, thereby improving
  • the electrical performance of each memory unit within the semiconductor structure is consistent to improve the performance stability of the semiconductor structure; on the other hand, the space of the storage area can be fully utilized, and no additional isolation structure is required inside the memory unit.
  • a support structure which maximizes the utilization of the storage area space and improves the utilization rate of the internal space of the semiconductor structure, thereby further improving the integration and storage density of the semiconductor structure.

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Abstract

本公开涉及一种半导体结构及其形成方法。所述半导体结构包括：衬底；堆叠结构，位于衬底上，堆叠结构包括沿第一方向间隔排布的存储区域、以及位于所述存储区域之间的隔离墙；存储区域包括沿第二方向间隔排布的存储单元，所述存储单元包括晶体管结构和电容结构，电容结构在衬底的顶面上的投影的轮廓线均为矩形或者圆角矩形，在沿第一方向上，所述晶体管结构的宽度与所述电容结构的宽度相等；在沿第三方向上，所述晶体管结构与所述电容结构对齐排布。本公开能够提高半导体结构稳定性和集成度，且提高了各个存储单元之间形貌的一致性，从而提高所述半导体结构内部各存储单元电性能的一致性。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2022年07月27日递交的中国专利申请号202210888942.2、申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
为了满足高的存储密度和高的集成度的要求，DRAM等存储器逐渐由二维结构向三维结构发展。为了维持具有三维结构的DRAM等半导体结构的稳定性，需要在DRAM中设置多个支撑框架、以及设置多个用于隔离相邻电容器的下电极隔离结构。举例来说，在具有三维结构的DRAM中通常需要设置三个支撑框架(即位于晶体管沟道区域相对两侧的两个支撑框架、以及位于电容器远离晶体管一侧的一个支撑框架)和两个下电极隔离结构(位于电容器的相对两端)。所述支撑框架和所述下电极隔离结构都需要占用所述半导体结构的空间，从而影响了半导体结构尺寸的进一步微缩。另外，DRAM中的字线的尺寸受限于两个支撑框架之间的间隙尺寸，而支撑框架在形成过程中会受到很多偶然因素的影响，从而使得所述支撑框架的尺寸存在较大的波动性，导致半导体制程工艺的可控性降低。
因此，如何在确保半导体结构稳定性的同时缩小半导体结构的尺寸，并提高半导体结构制程工艺的可控性，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体结构及其形成方法，用于在确保半导体结构稳定性的同时缩小半导体结构的尺寸，并提高半导体结构制程工艺的可控性。
为了解决上述问题，本公开提供了一种半导体结构，包括：
衬底；
堆叠结构，位于所述衬底上，所述堆叠结构包括沿第一方向间隔排布的多个存储区域、以及位于所述存储区域之间的隔离墙；所述存储区域包括沿第二方向间隔排布的多个存储单元，所述存储单元包括晶体管结构、以及沿第三方向位于所述晶体管结构的侧面且与所述晶体管结构电连接的电容结构，所述电容结构在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形，在沿所述第一方向上，所述晶体管结构的宽度与所述电容结构的宽度相等；在沿所述第三方向上，所述晶体管结构与所述电容结构对齐排布；所述第一方向和所述第三方向均与所述衬底的顶面平行，所述第二方向与所述衬底的顶面垂直，且所述第一方向与所述第三方向相交。
在一些实施例中，所述堆叠结构还包括：
隔离层，位于所述存储区域内的相邻所述存储单元之间，且所述隔离层连接于所述隔离墙的侧壁。
在一些实施例中，所述隔离层的厚度为20nm～30nm。
在一些实施例中，还包括位于所述存储区域内的字线，所述字线沿所述第二方向延伸，多条所述字线沿所述第一方向间隔排布；所述晶体管结构包括：
栅极层；
沟道层，环绕所述栅极层的外周分布，且所述沟道层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形，所述字线连接所述存储区域内沿所述第二方向相邻的所述栅极层；
源极区和漏极区，沿所述第三方向分布于所述沟道层的相对两端。
在一些实施例中，还包括位于所述存储区域内的字线，所述字线沿所述第二方向延伸，多条所述字线沿所述第一方向间隔排布；所述晶体管结构包括：
栅极层；
沟道层，所述栅极层环绕所述沟道层的外周分布，所述栅极层在所述衬底的顶面上的投影的轮廓线 为矩形或者圆角矩形，所述字线连接所述存储区域内沿所述第二方向相邻的所述栅极层；
源极区和漏极区，沿所述第三方向分布于所述沟道层的相对两端。
在一些实施例中，在沿平行于所述衬底的顶面的方向上，所述栅极层的宽度大于或者等于所述字线的宽度。
在一些实施例中，所述晶体管结构还包括位于所述栅极层与所述沟道层之间的栅极介质层，所述栅极介质层的厚度大于10nm。
在一些实施例中，所述电容结构包括：
上电极层；
电介质层，环绕所述上电极层的外周分布；
下电极层，环绕所述电介质层的外周分布，所述下电极层与所述晶体管结构电连接，且所述下电极层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形。
在一些实施例中，所述电容结构包括：
上电极层；
电介质层，环绕所述上电极层的外周分布；
下电极层，包括环绕所述电介质层的外周分布的第一导电层、以及环绕所述第一导电层的外周分布的第二导电层，所述第二导电层与所述晶体管结构电连接，且所述第二导电层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形。
在一些实施例中，所述晶体管结构中的所述漏极区与所述第二导电层一体成型。
在一些实施例中，所述第一导电层的材料与所述第二导电层的材料不同，且所述第二导电层的材料为包括掺杂离子的硅材料。
在一些实施例中，所述电容结构包括：
上电极层，所述上电极层在所述衬底的顶面上的投影为长条形，且所述上电极层沿所述第三方向延伸；
电介质层，所述电介质层环绕所述上电极层的外周分布，且所述电介质层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形；
下电极层，环绕所述电介质层的外周分布，所述下电极层与所述晶体管结构电连接，且所述下电极层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形。
在一些实施例中，所述电容结构包括：
上电极层，包括沿所述第三方向间隔排布的多个子上电极层；
电介质层，包括沿所述第三方向间隔排布的多个子电介质层，所述子电介质层环绕所述子上电极层的外周分布；
下电极层，沿所述第三方向延伸，且连续覆盖沿所述第三方向间隔排布的多个所述子电介质层的外周，所述下电极层与所述晶体管结构电连接，且所述下电极层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形。
在一些实施例中，所述电容结构包括：
公共电极层，位于所述存储区域内，所述公共电极层沿所述第二方向延伸，并连接沿所述第二方向相邻的所述上电极层；
在沿平行于所述衬底的顶面的方向上，所述公共电极层的宽度小于或者等于所述上电极层的宽度。
在一些实施例中，还包括：
位线，多条所述位线沿所述第二方向间隔排布，所述位线与沿所述第一方向间隔排布的多个所述晶体管结构电连接，所述位线的材料为包括掺杂离子的硅材料。
在一些实施例中，所述晶体管结构中的所述源极区与所述位线一体成型。
根据另一些实施例，本公开还提供了一种半导体结构的形成方法，包括如下步骤：
提供衬底；
形成堆叠结构于所述衬底上，所述堆叠结构包括沿第一方向间隔排布的多个存储区域、以及位于所述存储区域之间的隔离墙；所述存储区域包括沿第二方向间隔排布的多个存储单元，所述存储单元包括 晶体管结构、以及沿第三方向位于所述晶体管结构的侧面且与所述晶体管结构电连接的电容结构，所述电容结构在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形，在沿所述第一方向上，所述晶体管结构的宽度与所述电容结构的宽度相等；在沿所述第三方向上，所述晶体管结构与所述电容结构对齐排布；所述第一方向和所述第三方向均与所述衬底的顶面平行，所述第二方向与所述衬底的顶面垂直，且所述第一方向与所述第三方向相交。
在一些实施例中，形成堆叠结构于所述衬底上的具体步骤包括：
形成堆叠层于所述衬底上，所述堆叠层包括沿所述第二方向间隔排布的多个半导体层；
刻蚀所述堆叠层，形成沿所述第二方向贯穿所述堆叠层的第一沟槽，多个所述第一沟槽将所述堆叠层分隔为沿第一方向间隔排布的多个所述存储区域；
填充第一介质材料于所述第一沟槽内，形成所述隔离墙；
于所述存储区域形成沿所述第二方向间隔排布的多个所述存储单元。
在一些实施例中，形成沿所述第二方向贯穿所述堆叠层的第一沟槽的具体步骤包括：
沿所述第三方向刻蚀所述堆叠层，形成沿所述第三方向未贯穿所述堆叠层的所述第一沟槽，所述堆叠层沿所述第三方向的端部残留的所述半导体层作为位线。
在一些实施例中，所述存储区域在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形，且所述存储区域包括晶体管区域、以及沿所述第三方向位于所述晶体管区域外部的电容区域；于所述存储区域形成沿所述第二方向间隔排布的多个所述存储单元的具体步骤包括：
刻蚀所述堆叠层，形成沿所述第二方向贯穿所述晶体管区域的所述堆叠层的第一开口、以及沿所述第二方向贯穿所述电容区域的所述堆叠层的第二开口，所述第一开口和所述第二开口在所述衬底的顶面上的投影均为矩形或者圆角矩形，在沿所述第一方向上，所述第一开口的宽度与所述第二开口的宽度相等；在沿所述第三方向上，所述第一开口与所述第二开口对齐排布；所述晶体管区域残留的所述半导体层作为沟道层、以及沿所述第三方向位于所述沟道层两端的源极区和漏极区；
于所述第一开口内形成栅极层；
于所述第二开口内至少形成上电极层、以及环绕所述上电极层的外周分布的电介质层。
在一些实施例中，在沿所述第一方向上，所述第一开口的宽度与所述第二开口的宽度相等；
在沿所述第三方向上，所述第一开口与所述第二开口对齐排布。
在一些实施例中，所述堆叠层包括沿所述第二方向交替堆叠的所述半导体层和牺牲层；形成沿所述第二方向贯穿所述晶体管区域的所述堆叠层的第一开口、以及沿所述第二方向贯穿所述电容区域的所述堆叠层的第二开口之后，还包括如下步骤：
去除所述牺牲层，形成位于相邻所述半导体层之间、且暴露所述隔离墙的第二沟槽；
沉积第二介质材料于所述第二沟槽内，形成隔离层。
在一些实施例中，所述晶体管区域残留的所述半导体层中的所述沟道层环绕所述第一开口的外周分布；或者，
所述晶体管区域残留的所述半导体层中的所述沟道层沿所述第三方向贯穿所述第一开口。
在一些实施例中，于所述第一开口内形成栅极层的具体步骤包括：
沿所述第一开口形成覆盖所述沟道层表面的栅极介质层；
沿所述第一开口沉积第一导电材料，于所述第一开口内形成覆盖所述栅极介质层表面的所述栅极层、以及沿所述第二方向延伸且连接沿所述第二方向相邻的所述栅极层的字线。
在一些实施例中，于所述第二开口内至少形成上电极层、以及环绕所述上电极层的外周分布的电介质层的具体步骤包括：
沿所述第二开口去除所述电容区域残留的所述半导体层，于所述电容区域的相邻所述隔离层之间的第三开口；
形成覆盖所述第三开口内壁的下电极层；
于所述第三开口内形成覆盖所述下电极层表面的电介质层；
于所述第三开口内形成覆盖所述电介质层的上电极层，形成包括所述下电极层、所述电介质层和所述上电极层的电容结构。
在一些实施例中，于所述第二开口内至少形成上电极层、以及环绕所述上电极层的外周分布的电介质层的具体步骤包括：
沿所述第二开口注入掺杂离子至所述电容区域残留的所述半导体层中，形成第一导电层；
于所述第二开口内形成覆盖所述第一导电层表面的第二导电层；
于所述第二开口内形成覆盖所述第二导电层的电介质层；
于所述第二开口内形成覆盖所述电介质层的上电极层，形成包括所述第一导电层、所述第二导电层、所述电介质层和所述上电极层的电容结构。
本公开一些实施例提供的半导体结构及其形成方法，通过在任意相邻的存储区域之间设置隔离墙，不仅可以电性隔离相邻的所述存储区域，而且还能够起到支撑堆叠结构的作用，从而无需再设置额外的支撑框架和下电极隔离结构，使得在能够确保半导体结构稳定性的同时，进一步缩小所述半导体结构的尺寸，提高所述半导体结构的集成度和存储密度。而且，由于所述半导体结构中没有支撑框架，因此，晶体管结构的尺寸(尤其是晶体管结构中栅极层和沟道层)的尺寸不再受支撑框架制成工艺波动性的影响，从而提高了半导体结构制程工艺的可控性，并有助于进一步提高所述半导体结构的良率。本公开一些实施例中还在所述存储区域内的相邻存储单元之间设置隔离层，且所述隔离层与所述隔离墙的侧壁连接，一方面，通过所述隔离层隔离相邻的所述存储单元；另一方面，所述隔离层与所述隔离墙共同支撑所述堆叠结构，从而进一步提高了所述堆叠结构的稳定性。
另外，本公开一些实施例的存储单元中的电容结构在衬底的顶面上的投影为规则的矩形或者圆角矩形，且在沿所述第一方向上，所述晶体管结构的宽度与所述电容结构的宽度相等，在沿所述第三方向上，所述晶体管结构与所述电容结构对齐排布，一方面，有助于提高各个存储单元之间形貌的一致性，从而提高所述半导体结构内部各存储单元电性能的一致性，以提高所述半导体结构的性能稳定性；另一方面，能够充分利用所述存储区域的空间，所述存储单元内部无需设置额外的隔离结构或者支撑结构，最大程度的实现了对存储区域空间的利用，提高了所述半导体结构内部空间的利用率，从而进一步提高了所述半导体结构的集成度和存储密度。
附图说明
附图1是本公开具体实施方式的第一实施例中半导体结构的立体结构示意图；
附图2是附图1的俯视结构示意图；
附图3是本公开具体实施方式的第二实施例中半导体结构的立体结构示意图；
附图4是附图3的俯视结构示意图；
附图5是本公开具体实施方式的第三实施例中半导体结构的俯视结构示意图；
附图6是附图2在a-a位置的一种截面示意图；
附图7是附图2在a-a位置的另一种截面示意图；
附图8是附图4在b-b位置的一截面示意图；
附图9是附图4在b-b位置的另一截面示意图；
附图10是本公开具体实施方式中半导体结构的形成方法流程图；
附图11-附图23是本公开具体实施方式在形成半导体结构的过程中主要的工艺结构示意图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构，附图1是本公开具体实施方式的第一实施例中半导体结构的立体结构示意图，附图2是附图1的俯视结构示意图。如图1和图2所示，所述半导体结构，包括：
衬底；
堆叠结构，位于所述衬底上，所述堆叠结构包括沿第一方向D1间隔排布的多个存储区域PM、以及位于所述存储区域PM之间的隔离墙10；所述存储区域PM包括沿第二方向D2间隔排布的多个存储单元，所述存储单元包括晶体管结构TR、以及沿第三方向D3位于所述晶体管结构TR的侧面且与所述晶体管结构TR电连接的电容结构CAP，所述电容结构CAP在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形，在沿所述第一方向D1上，所述晶体管结构TR的宽度与所述电容结构CAP的宽度相等；在沿所述第三方向D3上，所述晶体管结构TR与所述电容结构CAP对齐排布；所述第一方向D1和所 述第三方向D3均与所述衬底的顶面平行，所述第二方向D2与所述衬底的顶面垂直，且所述第一方向D1与所述第三方向D3相交。
本具体实施方式中所述的半导体结构可以是但不限于DRAM。具体来说，所述衬底(图中未示出)可以是但不限于硅衬底，本具体实施方式以所述衬底20为硅衬底为例进行说明。在其他实施例中，所述衬底20还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底用于支撑在其上的所述堆叠结构。本具体实施方式中所述衬底的顶面是指所述衬底朝向所述堆叠结构的表面。本具体实施方式中所述的多个是指两个以上。
所述堆叠结构包括沿所述第一方向D1交替排布的所述存储区域PM和所述隔离墙10，且所述存储区域PM包括沿所述第二方向间隔排布的多个所述存储单元，通过所述隔离墙10能够电性隔离沿所述第一方向D1相邻的所述存储区域PM。所述存储区域PM中的多个所述存储单元均与所述隔离墙10的侧壁接触连接，以通过所述隔离墙10支撑所述存储区域PM中的多个所述存储单元，从而提高所述堆叠结构整体的稳定性。而且，本具体实施方式通过位于所述存储单元外部的所述隔离墙来支撑所述堆叠结构，从而无需在所述存储单元内部再设置支撑结构，提高了所述存储单元内部空间的利用率，有助于进一步缩小存储单元的尺寸和提高存储单元的存储容量。另外，由于无需在所述存储单元内部设置支撑结构，从而减小甚至是避免了支撑结构的尺寸波动对存储单元性能的影响，改善了半导体结构的良率，提高了半导体结构制程工艺的可控性。
所述电容结构CAP在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形是指，所述电容结构CAP中的下电极层、电介质层和上电极层构成的整体在所述衬底的顶面上的投影的轮廓线的形状为矩形或者圆角矩形。在一示例中，所述晶体管结构TR在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形。所述晶体管结构TR在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形是指，所述晶体管结构TR中的沟道层、栅极层、源极区和漏极区构成的整体在所述衬底的顶面上的投影的轮廓线的形状为矩形或者圆角矩形。本具体实施方式通过所述隔离墙10分隔和支撑所述存储单元，从而任意所述存储单元均具有规则的形状，在一示例中，所述存储单元在所述衬底的顶面上的投影的轮廓线的形状为矩形或者圆角矩形。本具体实施方式通过所述隔离墙10分隔和支撑所述存储单元，从而能够使得任意所述存储单元中的电容结构在衬底的顶面上的投影的轮廓线的形状为规则的矩形或者圆角矩形(或者所述存储单元中的电容结构和晶体管结构在衬底的顶面上的投影的轮廓线的形状均为规则的矩形或者圆角矩形)，简化了所述存储单元的制程工艺，而且有助于提高各个存储单元之间形貌的一致性，从而提高所述半导体结构内部各存储单元电性能的一致性，以提高所述半导体结构的性能稳定性。本具体实施方式中所述的圆角矩形是指，至少一个内角为圆弧形内角的矩形。
在沿所述第三方向D3上，所述晶体管结构TR与所述电容结构CAP对齐排布是指，所述晶体管结构TR沿所述第三方向D3延伸的中心轴与所述电容结构CAP沿所述第三方向D3延伸的中心轴沿所述第三方向D3对齐。所述晶体管结构TR沿所述第一方向D1上的宽度与所述电容结构CAP沿所述第一方向D1上的宽度相等，且所述晶体管结构TR与所述电容结构CAP沿所述第三方向D3对齐排布，不仅能够在各个存储区域PM形成规则形状的所述晶体管结构TR和所述电容结构CAP，且将所述晶体管结构TR的部分制程工艺与所述电容结构CAP的部分制程工艺兼容，从而简化所述半导体结构的制造工艺，而且还能够最大程度的利用所述存储区域内部的空间，在提高所述晶体管结构TR的可控性的同时，增大所述电容结构CAP的电容量。
在一些实施例中，所述堆叠结构还包括：
隔离层16，位于所述存储区域PM内的相邻所述存储单元之间，且所述隔离层16连接于所述隔离墙10的侧壁。
具体来说，所述存储区域PM包括沿所述第二方向D2交替堆叠的所述存储单元和所述隔离层16。所述隔离层16一方面能够隔离所述存储区域PM内沿所述第二方向D2相邻的所述存储单元，另一方面还能够与所述隔离墙10共同支撑所述堆叠结构，从而进一步加强了所述堆叠结构的稳定性，降低了所述半导体结构在制程工艺中出现倾倒或者坍塌的概率。
在一些实施例中，所述隔离层16的厚度为20nm～30nm。
具体来说，所述隔离层16的厚度不宜过小，否则，不仅会增大沿所述第二方向D2相邻的所述存储 单元之间的寄生电容效应或者导致沿所述第二方向D2相邻的所述存储单元之间的漏电，而且还会增加相邻位线之间的电容耦合效应。所述隔离层16的厚度也不宜过大，否则会导致所述半导体结构尺寸的增加。为了在降低所述半导体结构内部的寄生电容效应的同时，进一步缩小所述半导体结构的尺寸，本具体实施方式中所述隔离层16沿所述第二方向D2的厚度为20nm～30nm。在一示例中，所述隔离层16沿所述第二方向D2的厚度为25nm。
为了增强所述隔离层16与所述隔离墙10之间的连接稳定性，从而进一步稳定的支撑所述堆叠结构，在一实施例中，所述隔离层16的材料与所述隔离墙10的材料相同。在一示例中，所述隔离层16与所述隔离墙10的材料均为氧化物材料，例如二氧化硅。
在一些实施例中，还包括位于所述存储区域PM内的字线60，所述字线60沿所述第二方向D2延伸，多条所述字线60沿所述第一方向D1间隔排布；所述晶体管结构包括：
栅极层11；
沟道层20，环绕所述栅极层11的外周分布，且所述沟道层20在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形，所述字线60连接所述存储区域PM内沿所述第二方向D2相邻的所述栅极层11；
源极区和漏极区，沿所述第三方向D3分布于所述沟道层20的相对两端。
附图6是附图2在a-a位置的一种截面示意图，附图7是附图2在a-a位置的另一种截面示意图。具体来说，所述晶体管结构TR所述栅极层11、环绕覆盖于所述栅极层11表面的栅极介质层12、环绕覆盖于所述栅极介质层12表面的所述沟道层20、以及沿所述第三方向D3分布于所述沟道层20的相对两端的所述源极区和所述漏极区，形成沟道全环绕结构，且所述漏极区与所述电容结构CAP直接接触电连接。其中，所述沟道层20、所述源极区和所述漏极区的材料可以均为硅材料。
在一些实施例中，在沿平行于所述衬底的顶面的方向上，所述栅极层11的宽度大于或者等于所述字线60的宽度。
具体来说，在一些实施例中，为了降低短沟道效应的影响，在沿平行于所述衬底的顶面的方向(例如所述第一方向D1和所述第三方向D3)上，所述栅极层11的宽度大于所述字线60的宽度。在另一些实施例中，为了简化半导体的制程工艺，在沿平行于所述衬底的顶面的方向(例如所述第一方向D1和所述第三方向D3)上，所述栅极层11的宽度等于所述字线60的宽度。
在另一些实施例中，还包括位于所述存储区域PM内的字线60，所述字线60沿所述第二方向D2延伸，多条所述字线60沿所述第一方向D1间隔排布；所述晶体管结构包括：
栅极层11；
沟道层20，所述栅极层11环绕所述沟道层20的外周分布，所述栅极层11在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形，所述字线60连接所述存储区域PM内沿所述第二方向D2相邻的所述栅极层11；
源极区和漏极区，沿所述第三方向D3分布于所述沟道层20的相对两端。
具体来说，所述晶体管结构TR包括所述沟道层20、环绕覆盖于所述沟道层20表面的栅极介质层12、然后覆盖于所述栅极介质层12表面的所述栅极层11、以及沿所述第三方向D3分布于所述沟道层20的相对两端的所述源极区和所述漏极区，形成栅极全环绕结构，且所述漏极区与所述电容结构CAP直接接触电连接。其中，所述沟道层20、所述源极区和所述漏极区的材料可以均为硅材料。
为了避免在所述晶体管结构TR内部产生反型层，在一些实施例中，所述晶体管结构TR还包括位于所述栅极层11与所述沟道层20之间的栅极介质层12，所述栅极介质层12的厚度大于10nm。
为了简化所述半导体结构的制造工艺，在一些实施例中，如图1和图2所示，所述电容结构CAP包括：
上电极层14；
电介质层13，环绕所述上电极层14的外周分布；
下电极层15，环绕所述电介质层13的外周分布，所述下电极层15与所述晶体管结构TR电连接，且所述下电极层15在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形。
具体来说，所述电容结构CAP包括所述下电极层15、所述电介质层13和所述上电极层14，其中，所述下电极层15与所述晶体管结构TR中的所述漏极区接触电连接，所述下电极层15呈矩形环状结构 或者圆角矩形环绕状结构。所述电介质层13位于所述上电极层14与所述下电极层15之间。其中，所述上电极14和所述下电极层15的材料可以相同，例如均为金属钨或者TiN。
附图3是本公开具体实施方式的第二实施例中半导体结构的立体结构示意图，附图4是附图3的俯视结构示意图。在另一些实施例中，如图3和图4所示，所述电容结构包括：
上电极层14；
电介质层13，环绕所述上电极层14的外周分布；
下电极层，包括环绕所述电介质层14的外周分布的第一导电层151、以及环绕所述第一导电层151的外周分布的第二导电层30，所述第二导电层30与所述晶体管结构TR电连接，且所述第二导电层30在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形。
在一些实施例中，所述晶体管结构TR中的所述漏极区与所述第二导电层30一体成型。
在一些实施例中，所述第一导电层151的材料与所述第二导电层30的材料不同，且所述第二导电层30的材料为包括掺杂离子的硅材料。
举例来说，所述电容结构CAP包括所述下电极层、所述电介质层13和所述上电极层14，所述电介质层13覆盖所述上电极层14的表面，所述下电极层覆盖所述电介质层13背离所述上电极层14的表面，且所述下电极层包括所述第一导电层151和所述第二导电层30。其中，所述第一导电层151的材料可以与所述上电极层14的材料相同，例如均为金属钨或者TiN。所述第二导电层30与所述晶体管结构TR中的所述漏极区接触电连接。通过将所述晶体管结构TR中的所述漏极区与所述第二导电层30一体成型，不仅能够将所述晶体管结构中所述漏极区与所述电容结构CAP中所述第二导电层30的形成工艺兼容，从而简化所述半导体结构的制造工艺，而且还能够增大所述第二导电层30与所述漏极区之间的接触面积，降低所述晶体管结构TR与所述电容结构CAP之间的接触电阻。所述第二导电层30的材料为包括掺杂离子的硅材料，以在增强所述第二导电层30的导电性的同时，降低所述第二导电层30与所述晶体管结构TR中的所述漏极区之间的接触电阻。本具体实施方式中所述晶体管结构TR中的所述漏极区与所述第二导电层30一体成型是指，所述漏极区与所述第二导电层30之间无接触界面。
在一些实施例中，所述电容结构CAP包括：
上电极层14，所述上电极层14在所述衬底的顶面上的投影为长条形，且所述上电极层14沿所述第三方向D3延伸；
电介质层13，所述电介质层13环绕所述上电极层14的外周分布，且所述电介质层13在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形；
下电极层，环绕所述电介质层13的外周分布，所述下电极层与所述晶体管结构TR电连接，且所述下电极层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形。
举例来说，如图3和图4所示，所述存储单元内的所述上电极层14在所述衬底14的顶面上的投影为长条形结构，所述电介质层13、所述下电极层中的所述第一导电层151和所述第二导电层30在所述衬底的顶面上的投影的轮廓线均为矩形或者圆角矩形，从而简化所述半导体结构的制造工艺，降低所述半导体结构的制造成本。
附图5是本公开具体实施方式的第三实施例中半导体结构的俯视结构示意图。在另一些实施例中，如图5所示，所述电容结构CAP包括：
上电极层，包括沿所述第三方向D3间隔排布的多个子上电极层141；
电介质层，包括沿所述第三方向D3间隔排布的多个子电介质层131，所述子电介质层131环绕所述子上电极层131的外周分布；
下电极层，沿所述第三方向D3延伸，且连续覆盖沿所述第三方向D3间隔排布的多个所述子电介质层131的外周，所述下电极层与所述晶体管结构TR电连接，且所述下电极层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形。
具体来说，所述电容结构CAP包括图案化的所述上电极层、所述电介质层和所述下电极层，所述下电极层包括所述第一导电层151和覆盖于所述第一导电层151表面的第二导电层。图案化的所述上电极层包括沿所述第三方向D3间隔排布的多个所述子上电极层141，且相邻所述上电极层141之间沿所述第三方向D3的间隔宽度小于所述存储区域PM内沿所述第二方向D2相邻的两个所述电容结构CAP之间 的间隔距离，以便于在形成沿所述第三方向D3延伸且连续覆盖多个所述子电介质层131的表面的所述第一导电层151的同时，避免沿所述第二方向D2相邻的两个所述电容结构CAP内的所述第一导电层151连接。采用图案化的所述上电极层，可以有助于提高所述电容结构CAP的效率，且增大所述电容结构CAP的电容量。
附图8是附图4在b-b位置的一截面示意图，附图9是附图4在b-b位置的另一截面示意图。在一些实施例中，如图8或图9所示，所述电容结构CAP包括：
公共电极层80，位于所述存储区域PM内，所述公共电极层80沿所述第二方向D2延伸，并连接沿所述第二方向D2相邻的所述上电极层14；
在沿平行于所述衬底的顶面的方向上，所述公共电极层80的宽度小于或者等于所述上电极层14的宽度。
举例来说，如图8或者图9所示，所述公共电极层80沿所述第二方向D2延伸，且连续连接所述存储区域PM内沿所述第二方向D2间隔排布的多个所述上电极层14。在一示例中，在沿平行于所述衬底的顶面的方向(例如所述第一方向D1和所述第三方向D3)上，所述公共电极层80的宽度等于所述上电极层14的宽度，以简化所述半导体结构的制程工艺。在另一示例中，在沿平行于所述衬底的顶面的方向(例如所述第一方向D1和所述第三方向D3)上，所述公共电极层80的宽度小于所述上电极层14的宽度，从而增大所述上电极层14与所述下电极层的正对面积，以增大所述电容结构的电容量。
在一些实施例中，所述半导体结构还包括：
位线17，多条所述位线17沿所述第二方向D2间隔排布，所述位线17与沿所述第一方向D1间隔排布的多个所述晶体管结构TR电连接，所述位线17的材料为包括掺杂离子的硅材料。
在一实施例中，所述晶体管结构TR中的所述源极区与所述位线17一体成型。
具体来说，多条所述位线17沿所述第二方向D2间隔排布，沿所述第二方向D2相邻的所述位线17之间设置有所述隔离层16，以电性隔离相邻的所述位线17。所述位线17沿所述第一方向D1延伸，并连续与沿所述第一方向D1间隔排布的多个所述晶体管结构TR的所述源极区电连接。通过将所述晶体管结构TR中的所述源极区与所述第二导电层30一体成型，不仅能够将所述晶体管结构中所述源极区与所述位线17的形成工艺兼容，从而简化所述半导体结构的制造工艺，而且还能够增大所述位线17与所述源极区之间的接触面积，降低所述晶体管结构TR与所述位线17之间的接触电阻。所述位线17的材料可以与所述源极区的材料相同，例如均为包括掺杂离子的硅材料。
本具体实施方式还提供了一种半导体结构的形成方法，附图10是本公开具体实施方式中半导体结构的形成方法流程图，附图11-附图23是本公开具体实施方式在形成半导体结构的过程中主要的工艺结构示意图。本具体实施方式形成的半导体结构的示意图可以参见图1-图9。本具体实施方式中所述的半导体结构可以是但不限于DRAM。如图1-图23所示，所述半导体结构的形成方法，包括如下步骤：
步骤S101，提供衬底；
步骤S102，形成堆叠结构于所述衬底上，所述堆叠结构包括沿第一方向D1间隔排布的多个存储区域PM、以及位于所述存储区域PM之间的隔离墙10；所述存储区域PM包括沿第二方向D2间隔排布的多个存储单元，所述存储单元包括晶体管结构TR、以及沿第三方向D3位于所述晶体管结构TR的侧面且与所述晶体管结构TR电连接的电容结构CAP，所述电容结构CAP在所述衬底的顶面上的投影的轮廓线均为矩形或者圆角矩形，在沿所述第一方向D1上，所述晶体管结构TR的宽度与所述电容结构CAP的宽度相等；在沿所述第三方向D3上，所述晶体管结构TR与所述电容结构CAP对齐排布；所述第一方向D1和所述第三方向D3均与所述衬底的顶面平行，所述第二方向D2与所述衬底的顶面垂直，且所述第一方向D1与所述第三方向D3相交。
在一些实施例中，形成堆叠结构于所述衬底上的具体步骤包括：
形成堆叠层于所述衬底上，所述堆叠层包括沿所述第二方向D2间隔排布的多个半导体层110，如图11和图12所示，其中，图11是所述半导体结构形成过程中的俯视结构示意图，图12是图11在c-c位置的截面示意图；
刻蚀所述堆叠层，形成沿所述第二方向D2贯穿所述堆叠层的第一沟槽130，多个所述第一沟槽130将所述堆叠层分隔为沿第一方向D1间隔排布的多个所述存储区域PM，如图13和图14所示，其中，图 13是所述半导体结构形成过程中的俯视结构示意图，图14是图13在c-c位置的截面示意图；
填充第一介质材料于所述第一沟槽130内，形成所述隔离墙10，如图15和图16所示，其中，图15是所述半导体结构形成过程中的俯视结构示意图，图16是图15在c-c位置的截面示意图；
于所述存储区域PM形成沿所述第二方向D2间隔排布的多个所述存储单元。
在一实施例中，形成沿所述第二方向D2贯穿所述堆叠层的第一沟槽130的具体步骤包括：
沿所述第三方向D3刻蚀所述堆叠层，形成沿所述第三方向D3未贯穿所述堆叠层的所述第一沟槽130，所述堆叠层沿所述第三方向D3的端部残留的所述半导体层110作为位线17。
具体来说，可以于所述衬底的顶面上沿所述第二方向D2交替外延生长所述半导体层110和牺牲层120，形成具有超晶格堆栈结构的堆叠层，如图11和图12所示。其中，所述半导体层110和所述牺牲层120之间应具有较高的刻蚀选择比，以便于后续选择性的去除所述牺牲层120。在一示例中，所述半导体层110的材料为硅材料，所述牺牲层120的材料为SiGe材料。所述半导体层110沿所述第二方向D2的厚度可以为30nm，所述牺牲层120沿所述第二方向D2的厚度可以为20nm～30nm。之后，可以采用光刻工艺刻蚀所述堆叠层，形成多个沿所述第二方向D2贯穿所述堆叠层的所述第一沟槽130，且多个所述第一沟槽130沿所述第一方向D1间隔排布，从而将所述堆叠层分隔为沿第一方向D1间隔排布的多个所述存储区域PM，如图13和图14所示。多个所述第一沟槽130将所述半导体层110分隔为沿所述第一方向D1间隔排布的多个矩形的半导体块132。所述第一沟槽130沿所述第三方向D3未贯穿所述堆叠层，残留于所述堆叠层端部的所述半导体层110作为位线17。填充氧化物(例如二氧化硅)等第一介质材料于所述第一沟槽130内，形成所述隔离墙10。所述隔离墙10一方面用于隔离相邻的所述存储区域PM，另一方面还用于支撑所述堆叠层，避免所述堆叠层在后续工艺中出现倾倒或者坍塌。之后，于所述半导体块132中形成所述存储单元。本具体实施方式将所述隔离墙10的形成工艺、所述存储区域PM的形成工艺、以及所述位线17的形成工艺兼容，有助于进一步简化所述半导体结构的制程工艺，提高所述半导体结构的制造效率。
在一些实施例中，所述存储区域PM在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形，且所述存储区域PM包括晶体管区域PT、以及沿所述第三方向D3位于所述晶体管区域PT外部的电容区域PC，如图17所示；于所述存储区域PM形成沿所述第二方向D2间隔排布的多个所述存储单元的具体步骤包括：
刻蚀所述堆叠层，形成沿所述第二方向D2贯穿所述晶体管区域PT的所述堆叠层的第一开口170、以及沿所述第二方向D2贯穿所述电容区域PC的所述堆叠层的第二开口171，所述第一开口170和所述第二开口171在所述衬底的顶面上的投影均为矩形或者圆角矩形，在沿所述第一方向D1上，所述第一开口170的宽度与所述第二开口171的宽度相等；在沿所述第三方向D3上，所述第一开口170与所述第二开口171对齐排布；所述晶体管区域PT残留的所述半导体层110作为沟道层20、以及沿所述第三方向D3位于所述沟道层20两端的源极区和漏极区；
于所述第一开口170内形成栅极层11；
于所述第二开口171内至少形成上电极层14、以及环绕所述上电极层14的外周分布的电介质层13，如图1-图9所示。
在一些实施例中，所述堆叠层包括沿所述第二方向D2交替堆叠的所述半导体层110和牺牲层120；形成沿所述第二方向D2贯穿所述晶体管区域PT的所述堆叠层的第一开口170、以及沿所述第二方向D2贯穿所述电容区域PC的所述堆叠层的第二开口171之后，还包括如下步骤：
去除所述牺牲层120，形成位于相邻所述半导体层110之间、且暴露所述隔离墙10的第二沟槽190，如图18和图19所示，其中，图18是所述半导体结构形成过程中的俯视结构示意图，图19是图18在c-c位置的截面示意图；
沉积第二介质材料于所述第二沟槽190内，形成隔离层16，如图20和图21所示，其中，图20是所述半导体结构形成过程中的俯视结构示意图，图21是图20在c-c位置的截面示意图。
具体来说，在形成所述隔离墙10之后，可以采用干法刻蚀工艺对所述存储区域PM中的所述晶体管区域PT和所述电容区域PC同步进行刻蚀，于所述晶体管区域PT形成沿所述第二方向D2贯穿所述半导体块132和所述牺牲层120的所述第一开口170、并同时于所述电容区域PC形成沿所述第二方向D2 贯穿所述半导体块132和所述牺牲层120的所述第二开口171。为了简化刻蚀工艺，所述第一开口170与所述第二开口171在所述衬底的顶面上的投影均为矩形或者圆角矩形，且在沿所述第一方向D1上，所述第一开口170的宽度与所述第二开口171的宽度相等，在沿所述第三方向D3上，所述第一开口170与所述第二开口171对齐排布。在形成所述第一开口170和所述第二开口171之后，所述晶体管区域PT和所述电容区域PC均残留部分的所述半导体块132，如图17所示。其中，所述晶体管区域PT残留的所述半导体块132作为沟道层20、以及沿所述第三方向D3位于所述沟道层20两端的源极区和漏极区，所述电容区域PC残留的所述半导体块132后续可以全部去除、也可以用于形成电容结构。
接着，在所述隔离墙10的支撑作用下，采用湿法刻蚀工艺去除所述堆叠层中全部的所述牺牲层120，形成位于相邻所述半导体层110之间、且暴露所述隔离墙10的第二沟槽190，并填充氧化物(例如二氧化硅)等第二介质材料于所述第二沟槽190内、所述第一开口170内和所述第二开口171内，形成所述隔离层160。
在一些实施例中，所述晶体管区域PT残留的所述半导体层110中的所述沟道层20环绕所述第一开口170的外周分布；或者，
所述晶体管区域PT残留的所述半导体层110中的所述沟道层20沿所述第三方向D3贯穿所述第一开口170。
具体来说，所述晶体管区域PT残留的所述半导体层110中的所述沟道层20环绕所述第一开口170的外周分布，从而后续可以形成沟道全环绕结构的所述晶体管结构。所述晶体管区域PT残留的所述半导体层110中的所述沟道层20沿所述第三方向D3贯穿所述第一开口170，以便于后续形成栅极全环绕的所述晶体管结构，以满足不同的半导体结构需求，提高所述半导体结构的制造灵活性。
在一些实施例中，于所述第一开口170内形成栅极层11的具体步骤包括：
沿所述第一开口170形成覆盖所述沟道层20表面的栅极介质层12；
沿所述第一开口170沉积第一导电材料，于所述第一开口170内形成覆盖所述栅极介质层12表面的所述栅极层11、以及沿所述第二方向D2延伸且连接沿所述第二方向D2相邻的所述栅极层11的字线60。
具体来说，去除所述第一开口170内的所述隔离层16，如图22所示，之后，沉积氧化物(例如二氧化硅)于所述第一开口170的内壁，形成所述栅极介质层12。接着，沉积金属钨或者TiN等第一导电材料于所述第一开口170内，形成覆盖所述栅极介质层12的表面的所述栅极层11、以及沿所述第二方向D2延伸且连接沿所述第二方向D2相邻的所述栅极层11的字线60，如图1-图9和图23所示。
在一些实施例中，于所述第二开口171内至少形成上电极层14、以及环绕所述上电极层14的外周分布的电介质层13的具体步骤包括：
沿所述第二开口171去除所述电容区域PC残留的所述半导体层110，于所述电容区域PC的相邻所述隔离层10之间的第三开口230，如图23所示；
形成覆盖所述第三开口230内壁的下电极层15；
于所述第三开口230内形成覆盖所述下电极层15表面的电介质层13；
于所述第三开口230内形成覆盖所述电介质层13的上电极层14，形成包括所述下电极层15、所述电介质层13和所述上电极层14的电容结构CAP，参见图1和图2。
具体来说，可以采用刻蚀工艺去除所述电容区域PC残留的所有的所述半导体块132，形成所述第三开口230。之后，依次于所述第三开口230内形成所述下电极层15、所述电介质层13和所述上电极层14。
在一些实施例中，于所述第二开口171内至少形成上电极层14、以及环绕所述上电极层14的外周分布的电介质层13的具体步骤包括：
沿所述第二开口171注入掺杂离子至所述电容区域PC残留的所述半导体层110中，形成第一导电层30；
于所述第二开口171内形成覆盖所述第一导电层30表面的第二导电层151；
于所述第二开口171内形成覆盖所述第二导电层151的电介质层13；
于所述第二开口171内形成覆盖所述电介质层13的上电极层14，形成包括所述第一导电层30、所述第二导电层151、所述电介质层13和所述上电极层14的电容结构。
具体来说，在去除所述第二开口171内的所述隔离层16之后，可以完全不去除所述电容区域PC残留的所述半导体块132、或者仅去除所述电容区域PC残留的部分的所述半导体块132，并注入掺杂离子至所述电容区域PC残留的所述半导体层110中，形成第一导电层30，所述第一导电层30作为所述电容结构中的所述下电极层的一部分。接着，形成覆盖所述第一导电层30的所述第二导电层151、覆盖所述第二导电层151的所述电介质层13、以及覆盖所述电介质层13的所述上电极层14。
本具体实施方式一些实施例提供的半导体结构及其形成方法，通过在任意相邻的存储区域之间设置隔离墙，不仅可以电性隔离相邻的所述存储区域，而且还能够起到支撑堆叠结构的作用，从而无需再设置额外的支撑框架和下电极隔离结构，使得在能够确保半导体结构稳定性的同时，进一步缩小所述半导体结构的尺寸，提高所述半导体结构的集成度和存储密度。而且，由于所述半导体结构中没有支撑框架，因此，晶体管结构的尺寸(尤其是晶体管结构中栅极层和沟道层)的尺寸不再受支撑框架制成工艺波动性的影响，从而提高了半导体结构制程工艺的可控性，并有助于进一步提高所述半导体结构的良率。本具体实施方式一些实施例中还在所述存储区域内的相邻存储单元之间设置隔离层，且所述隔离层与所述隔离墙的侧壁连接，一方面，通过所述隔离层隔离相邻的所述存储单元；另一方面，所述隔离层与所述隔离墙共同支撑所述堆叠结构，从而进一步提高了所述堆叠结构的稳定性。
另外，本具体实施方式一些实施例的存储单元中的电容结构在衬底的顶面上的投影为规则的矩形或者圆角矩形，且在沿所述第一方向上，所述晶体管结构的宽度与所述电容结构的宽度相等，在沿所述第三方向上，所述晶体管结构与所述电容结构对齐排布，一方面，有助于提高各个存储单元之间形貌的一致性，从而提高所述半导体结构内部各存储单元电性能的一致性，以提高所述半导体结构的性能稳定性；另一方面，能够充分利用所述存储区域的空间，所述存储单元内部无需设置额外的隔离结构或者支撑结构，最大程度的实现了对存储区域空间的利用，提高了所述半导体结构内部空间的利用率，从而进一步提高了所述半导体结构的集成度和存储密度。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (25)

  1. 一种半导体结构，包括：
    衬底；
    堆叠结构，位于所述衬底上，所述堆叠结构包括沿第一方向间隔排布的多个存储区域、以及位于所述存储区域之间的隔离墙；所述存储区域包括沿第二方向间隔排布的多个存储单元，所述存储单元包括晶体管结构、以及沿第三方向位于所述晶体管结构的侧面且与所述晶体管结构电连接的电容结构，所述电容结构在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形，在沿所述第一方向上，所述晶体管结构的宽度与所述电容结构的宽度相等；在沿所述第三方向上，所述晶体管结构与所述电容结构对齐排布；所述第一方向和所述第三方向均与所述衬底的顶面平行，所述第二方向与所述衬底的顶面垂直，且所述第一方向与所述第三方向相交。
  2. 根据权利要求1所述的半导体结构，其中，所述堆叠结构还包括：
    隔离层，位于所述存储区域内的相邻所述存储单元之间，且所述隔离层连接于所述隔离墙的侧壁。
  3. 根据权利要求2所述的半导体结构，其中，所述隔离层的厚度为20nm～30nm。
  4. 根据权利要求1所述的半导体结构，其中，还包括位于所述存储区域内的字线，所述字线沿所述第二方向延伸，多条所述字线沿所述第一方向间隔排布；所述晶体管结构包括：
    栅极层；
    沟道层，环绕所述栅极层的外周分布，且所述沟道层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形，所述字线连接所述存储区域内沿所述第二方向相邻的所述栅极层；
    源极区和漏极区，沿所述第三方向分布于所述沟道层的相对两端。
  5. 根据权利要求4所述的半导体结构，其中，还包括位于所述存储区域内的字线，所述字线沿所述第二方向延伸，多条所述字线沿所述第一方向间隔排布；所述晶体管结构包括：
    栅极层；
    沟道层，所述栅极层环绕所述沟道层的外周分布，所述栅极层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形，所述字线连接所述存储区域内沿所述第二方向相邻的所述栅极层；
    源极区和漏极区，沿所述第三方向分布于所述沟道层的相对两端。
  6. 根据权利要求4或5所述的半导体结构，其中，在沿平行于所述衬底的顶面的方向上，所述栅极层的宽度大于或者等于所述字线的宽度。
  7. 根据权利要求4或5所述的半导体结构，其中，所述晶体管结构还包括位于所述栅极层与所述沟道层之间的栅极介质层，所述栅极介质层的厚度大于10nm。
  8. 根据权利要求1所述的半导体结构，其中，所述电容结构包括：
    上电极层；
    电介质层，环绕所述上电极层的外周分布；
    下电极层，环绕所述电介质层的外周分布，所述下电极层与所述晶体管结构电连接，且所述下电极层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形。
  9. 根据权利要求4或5所述的半导体结构，其中，所述电容结构包括：
    上电极层；
    电介质层，环绕所述上电极层的外周分布；
    下电极层，包括环绕所述电介质层的外周分布的第一导电层、以及环绕所述第一导电层的外周分布的第二导电层，所述第二导电层与所述晶体管结构电连接，且所述第二导电层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形。
  10. 根据权利要求9所述的半导体结构，其中，所述晶体管结构中的所述漏极区与所述第二导电层一体成型。
  11. 根据权利要求9所述的半导体结构，其中，所述第一导电层的材料与所述第二导电层的材料不同，且所述第二导电层的材料为包括掺杂离子的硅材料。
  12. 根据权利要求1所述的半导体结构，其中，所述电容结构包括：
    上电极层，所述上电极层在所述衬底的顶面上的投影为长条形，且所述上电极层沿所述第三方向延伸；
    电介质层，所述电介质层环绕所述上电极层的外周分布，且所述电介质层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形；
    下电极层，环绕所述电介质层的外周分布，所述下电极层与所述晶体管结构电连接，且所述下电极层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形。
  13. 根据权利要求1所述的半导体结构，其中，所述电容结构包括：
    上电极层，包括沿所述第三方向间隔排布的多个子上电极层；
    电介质层，包括沿所述第三方向间隔排布的多个子电介质层，所述子电介质层环绕所述子上电极层的外周分布；
    下电极层，沿所述第三方向延伸，且连续覆盖沿所述第三方向间隔排布的多个所述子电介质层的外周，所述下电极层与所述晶体管结构电连接，且所述下电极层在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形。
  14. 根据权利要求12或13所述的半导体结构，其中，所述电容结构包括：
    公共电极层，位于所述存储区域内，所述公共电极层沿所述第二方向延伸，并连接沿所述第二方向相邻的所述上电极层；
    在沿平行于所述衬底的顶面的方向上，所述公共电极层的宽度小于或者等于所述上电极层的宽度。
  15. 根据权利要求4或5所述的半导体结构，还包括：
    位线，多条所述位线沿所述第二方向间隔排布，所述位线与沿所述第一方向间隔排布的多个所述晶体管结构电连接，所述位线的材料为包括掺杂离子的硅材料。
  16. 根据权利要求15所述的半导体结构，其中，所述晶体管结构中的所述源极区与所述位线一体成型。
  17. 一种半导体结构的形成方法，包括如下步骤：
    提供衬底；
    形成堆叠结构于所述衬底上，所述堆叠结构包括沿第一方向间隔排布的多个存储区域、以及位于所述存储区域之间的隔离墙；所述存储区域包括沿第二方向间隔排布的多个存储单元，所述存储单元包括晶体管结构、以及沿第三方向位于所述晶体管结构的侧面且与所述晶体管结构电连接的电容结构，所述电容结构在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形，在沿所述第一方向上，所述晶体管结构的宽度与所述电容结构的宽度相等；在沿所述第三方向上，所述晶体管结构与所述电容结构对齐排布；所述第一方向和所述第三方向均与所述衬底的顶面平行，所述第二方向与所述衬底的顶面垂直，且所述第一方向与所述第三方向相交。
  18. 根据权利要求17所述的半导体结构的形成方法，其中，形成堆叠结构于所述衬底上的具体步骤包括：
    形成堆叠层于所述衬底上，所述堆叠层包括沿所述第二方向间隔排布的多个半导体层；
    刻蚀所述堆叠层，形成沿所述第二方向贯穿所述堆叠层的第一沟槽，多个所述第一沟槽将所述堆叠层分隔为沿第一方向间隔排布的多个所述存储区域；
    填充第一介质材料于所述第一沟槽内，形成所述隔离墙；
    于所述存储区域形成沿所述第二方向间隔排布的多个所述存储单元。
  19. 根据权利要求18所述的半导体结构的形成方法，其中，形成沿所述第二方向贯穿所述堆叠层的第一沟槽的具体步骤包括：
    沿所述第三方向刻蚀所述堆叠层，形成沿所述第三方向未贯穿所述堆叠层的所述第一沟槽，所述堆叠层沿所述第三方向的端部残留的所述半导体层作为位线。
  20. 根据权利要求18所述的半导体结构的形成方法，其中，所述存储区域在所述衬底的顶面上的投影的轮廓线为矩形或者圆角矩形，且所述存储区域包括晶体管区域、以及沿所述第三方向位于所述晶体管区域外部的电容区域；于所述存储区域形成沿所述第二方向间隔排布的多个所述存储单元的具体步骤包括：
    刻蚀所述堆叠层，形成沿所述第二方向贯穿所述晶体管区域的所述堆叠层的第一开口、以及沿所述第二方向贯穿所述电容区域的所述堆叠层的第二开口，所述第一开口和所述第二开口在所述衬底的顶面上的投影均为矩形或者圆角矩形，在沿所述第一方向上，所述第一开口的宽度与所述第二开口的宽度相等；在沿所述第三方向上，所述第一开口与所述第二开口对齐排布；所述晶体管区域残留 的所述半导体层作为沟道层、以及沿所述第三方向位于所述沟道层两端的源极区和漏极区；
    于所述第一开口内形成栅极层；
    于所述第二开口内至少形成上电极层、以及环绕所述上电极层的外周分布的电介质层。
  21. 根据权利要求20所述的半导体结构的形成方法，其中，所述堆叠层包括沿所述第二方向交替堆叠的所述半导体层和牺牲层；形成沿所述第二方向贯穿所述晶体管区域的所述堆叠层的第一开口、以及沿所述第二方向贯穿所述电容区域的所述堆叠层的第二开口之后，还包括如下步骤：
    去除所述牺牲层，形成位于相邻所述半导体层之间、且暴露所述隔离墙的第二沟槽；
    沉积第二介质材料于所述第二沟槽内，形成隔离层。
  22. 根据权利要求20所述的半导体结构的形成方法，其中，所述晶体管区域残留的所述半导体层中的所述沟道层环绕所述第一开口的外周分布；或者，
    所述晶体管区域残留的所述半导体层中的所述沟道层沿所述第三方向贯穿所述第一开口。
  23. 根据权利要求21所述的半导体结构的形成方法，其中，于所述第一开口内形成栅极层的具体步骤包括：
    沿所述第一开口形成覆盖所述沟道层表面的栅极介质层；
    沿所述第一开口沉积第一导电材料，于所述第一开口内形成覆盖所述栅极介质层表面的所述栅极层、以及沿所述第二方向延伸且连接沿所述第二方向相邻的所述栅极层的字线。
  24. 根据权利要求21所述的半导体结构的形成方法，其中，于所述第二开口内至少形成上电极层、以及环绕所述上电极层的外周分布的电介质层的具体步骤包括：
    沿所述第二开口去除所述电容区域残留的所述半导体层，于所述电容区域的相邻所述隔离层之间的第三开口；
    形成覆盖所述第三开口内壁的下电极层；
    于所述第三开口内形成覆盖所述下电极层表面的电介质层；
    于所述第三开口内形成覆盖所述电介质层的上电极层，形成包括所述下电极层、所述电介质层和所述上电极层的电容结构。
  25. 根据权利要求21所述的半导体结构的形成方法，其中，于所述第二开口内至少形成上电极层、以及环绕所述上电极层的外周分布的电介质层的具体步骤包括：
    沿所述第二开口注入掺杂离子至所述电容区域残留的所述半导体层中，形成第一导电层；
    于所述第二开口内形成覆盖所述第一导电层表面的第二导电层；
    于所述第二开口内形成覆盖所述第二导电层的电介质层；
    于所述第二开口内形成覆盖所述电介质层的上电极层，形成包括所述第一导电层、所述第二导电层、所述电介质层和所述上电极层的电容结构。
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109285838A (zh) * 2018-08-28 2019-01-29 中国科学院微电子研究所 半导体存储设备及其制造方法及包括存储设备的电子设备
CN109616474A (zh) * 2017-09-29 2019-04-12 三星电子株式会社 半导体存储器件
CN110164867A (zh) * 2018-02-12 2019-08-23 三星电子株式会社 半导体存储器件
CN113644061A (zh) * 2020-04-27 2021-11-12 长鑫存储技术有限公司 半导体结构及其形成方法、存储器及其形成方法
US20210375938A1 (en) * 2020-05-29 2021-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional memory device and manufacturing method thereof
CN113745224A (zh) * 2020-05-28 2021-12-03 美光科技公司 包含堆叠水平电容器结构的设备以及相关方法、存储器装置和电子系统
CN114023744A (zh) * 2022-01-10 2022-02-08 长鑫存储技术有限公司 一种半导体结构、半导体结构的制备方法和半导体存储器

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109616474A (zh) * 2017-09-29 2019-04-12 三星电子株式会社 半导体存储器件
CN110164867A (zh) * 2018-02-12 2019-08-23 三星电子株式会社 半导体存储器件
CN109285838A (zh) * 2018-08-28 2019-01-29 中国科学院微电子研究所 半导体存储设备及其制造方法及包括存储设备的电子设备
CN113644061A (zh) * 2020-04-27 2021-11-12 长鑫存储技术有限公司 半导体结构及其形成方法、存储器及其形成方法
CN113745224A (zh) * 2020-05-28 2021-12-03 美光科技公司 包含堆叠水平电容器结构的设备以及相关方法、存储器装置和电子系统
US20210375938A1 (en) * 2020-05-29 2021-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional memory device and manufacturing method thereof
CN114023744A (zh) * 2022-01-10 2022-02-08 长鑫存储技术有限公司 一种半导体结构、半导体结构的制备方法和半导体存储器

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