WO2024036877A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2024036877A1
WO2024036877A1 PCT/CN2023/070465 CN2023070465W WO2024036877A1 WO 2024036877 A1 WO2024036877 A1 WO 2024036877A1 CN 2023070465 W CN2023070465 W CN 2023070465W WO 2024036877 A1 WO2024036877 A1 WO 2024036877A1
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Prior art keywords
along
bit line
active area
active
electrically connected
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PCT/CN2023/070465
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English (en)
French (fr)
Inventor
施志成
张瑞奇
刘欣然
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长鑫存储技术有限公司
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Priority to US18/451,011 priority Critical patent/US20240064971A1/en
Publication of WO2024036877A1 publication Critical patent/WO2024036877A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or writing data information into the capacitor.
  • the drain in semiconductor structures such as DRAM is electrically connected to the capacitor through the node contact (NC) and the landing pad (LP) in turn.
  • the contact area between the drain, node contact, and landing pad Smaller, which will increase the resistance inside the semiconductor structure, resulting in a reduction in the electrical performance of the semiconductor structure.
  • memory arrays in semiconductor structures such as DRAM mostly use a 6F2 array structure, which is less dense and is not conducive to improving the integration and storage capacity of the semiconductor structure.
  • Some embodiments of the present disclosure provide semiconductor structures and methods for forming the same, which are used to increase the density of the semiconductor structure and improve the electrical properties of the semiconductor structure.
  • the present disclosure provides a semiconductor structure including:
  • a memory array located on the substrate, includes a plurality of memory cells arranged in an array along a first direction and a second direction, the memory cells include a transistor structure, and the transistor structure includes a gate electrode and an active region, so The active area includes a first active area and a second active area distributed on opposite sides of the gate electrode along a first direction, wherein the first direction and the second direction are both in contact with the substrate.
  • the top surface is parallel, and the first direction is perpendicular to the second direction;
  • a word line extends along the second direction and is continuously electrically connected to the gate electrodes in a plurality of memory cells spaced apart along the second direction;
  • Bit lines extend along the first direction and are located outside the memory cells along the second direction.
  • the bit lines are continuously connected to the plurality of memory cells spaced apart along the first direction.
  • the first active area and the second active area are electrically connected.
  • the first active region includes a first channel region, and a first source region and a first drain region distributed on opposite sides of the first channel region along a third direction, Wherein, the third direction is perpendicular to the top surface of the substrate;
  • the second active region includes a second channel region, and a second source region and a second drain region distributed on opposite sides of the second channel region along the third direction, and the third A channel region and the second channel region are symmetrically distributed about the gate electrode.
  • it also includes:
  • a bit line contact array located below the memory array, includes a plurality of bit line contact structures arranged in an array along the first direction and the second direction;
  • the bit line contact structure is electrically connected to the active region in the transistor structure, and a plurality of the bit line contact structures spaced apart along the first direction is electrically connected to the same bit line.
  • bit line contact array and the memory array are arranged staggered
  • One bit line contact structure is electrically connected to two active area contacts adjacent along the first direction, and one active area is electrically connected to two bit line contacts adjacent along the first direction.
  • Line contact structures contact electrical connections.
  • one end of the bit line contact structure along the first direction is connected to one The first source region in the memory cell is electrically connected, and the other end of the bit line contact structure along the first direction is electrically connected to the second source region in another memory cell;
  • Two of the bit line contact structures electrically connected to one of the active area contacts are symmetrically distributed about an axis of the active area, the axis extending along the second direction.
  • the shape and size of the projection of the bit line contact structure on the top surface of the substrate are the same as the shape and size of the projection of the active region on the top surface of the substrate.
  • the distance between adjacent bit line contact structures is equal to the distance between adjacent active regions.
  • the storage unit further includes:
  • a capacitor structure located above the transistor structure, and the capacitor structure is electrically connected to the first drain region and the second drain region, and the projection of the capacitor structure on the top surface of the substrate is at least completely Covering the projection of the active area on the top surface of the substrate.
  • the memory unit structure further includes:
  • a node contact structure is located between the capacitor structure and the transistor. One end of the node contact structure is electrically connected to the first drain region and the second drain region, and the other end is electrically connected to the capacitor. structure.
  • a plurality of the word lines are arranged at intervals along the first direction, and a plurality of the bit lines are arranged at intervals along the second direction;
  • the distance between two adjacent word lines along the first direction, the distance between two adjacent bit lines along the second direction, and the distance between adjacent memory cells are all equal.
  • the present disclosure also provides a method for forming a semiconductor structure, including the following steps:
  • the active array includes a plurality of active areas arranged in an array along a first direction and a second direction, wherein the first direction and the The second directions are both parallel to the top surface of the substrate, and the first direction is perpendicular to the second direction;
  • a bit line is formed outside the active area along the second direction.
  • the bit line extends along the first direction and is continuous with a plurality of active areas arranged at intervals along the first direction. electrical connection;
  • the gate electrode separates the active area into a first active area and a second active area arranged along the first direction.
  • bit lines along the outside of the active area along the second direction are further included:
  • bit line contact array located below the active array
  • the bit line contact array includes a plurality of bit line contact structures arranged in an array along the first direction and the second direction, the bit line contact array A structure is in electrical contact with the active area.
  • the substrate further includes a first isolation layer located between adjacent active areas; the specific steps of forming a bit line contact array located below the active array include:
  • the bit line contact structure electrically connected to the active area contact is formed at the bottom of the first trench.
  • the specific steps of forming bit lines on the outside of the active area along the second direction include:
  • a bit line extending along the first direction is formed in the second trench, and the bit line is continuously and electrically connected to a plurality of bit line contact structures spaced apart along the first direction.
  • a gate electrode is formed extending through the active region along the second direction, and a plurality of gate electrode electrodes extending along the second direction and arranged continuously and spaced apart along the second direction are formed.
  • Specific steps for connecting word lines include:
  • Word line trenches are formed between adjacent active areas in the second direction;
  • the gate electrode is formed in the gate trench, and the word line is formed in the word line trench.
  • a gate electrode is formed extending through the active region along the second direction, and a plurality of gate electrode electrodes extending along the second direction and arranged continuously and spaced apart along the second direction are formed.
  • a capacitive structure is formed above the active area, the capacitive structure is electrically connected to the first active area and the second active area, and the projection of the capacitive structure on the top surface of the substrate is at least completely Covering the projection of the active area on the top surface of the substrate.
  • the memory unit includes a transistor.
  • the gate electrode in the transistor structure separates the active area into a first active area and a second active area, so that it can be formed in the transistor structure.
  • Two transistors sharing a gate electrode, and the same bit line is electrically connected to the first active region and the second active region in the memory cell, so that in a word electrically connected to the memory cell.
  • two parallel signal transmission channels can be formed in the memory unit, which can not only improve the signal transmission efficiency and improve the electrical performance of the semiconductor structure, but also form 4F2 (where F is characteristic size) memory array structure to achieve an increase in the density of memory cells in the semiconductor structure.
  • the projection of the capacitor structure on the top surface of the substrate at least completely covers the projection of the active area on the top surface of the substrate, thereby increasing the size of the capacitor structure and the transistor structure.
  • the contact area reduces the contact resistance inside the memory cell, thereby improving the electrical performance of the semiconductor structure.
  • the capacitor structure in some embodiments of the present disclosure is directly electrically connected to the node contact structure without forming a transfer pad (LP), thereby simplifying the manufacturing process of the semiconductor structure and reducing the manufacturing cost of the semiconductor structure.
  • LP transfer pad
  • FIG. 1 is a schematic top view of a semiconductor structure in a specific embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a memory unit in a specific embodiment of the present disclosure
  • FIG. 3 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure
  • 4 to 10 are structural schematic diagrams of main processes in forming a semiconductor structure according to specific embodiments of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure in a specific embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a memory unit in a specific embodiment of the present disclosure. As shown in Figures 1 and 2, the semiconductor structure includes:
  • the memory array is located on the substrate 20 and includes a plurality of memory cells arranged in an array along the first direction D1 and the second direction D2.
  • the memory cells include a transistor structure, and the transistor structure includes a gate electrode 12 and a
  • the active area includes a first active area 10 and a second active area 11 distributed on opposite sides of the gate electrode 12 along the first direction D1, wherein the first direction D1 and the The second directions D2 are both parallel to the top surface of the substrate 20, and the first direction D1 is perpendicular to the second direction D2;
  • the word line 13 extends along the second direction D2 and is continuously electrically connected to the gate electrodes 12 in a plurality of memory cells arranged at intervals along the second direction D2;
  • the bit line 14 extends along the first direction D1 and is located outside the memory cell along the second direction D2.
  • the bit line 14 is continuously connected to a plurality of spaced apart ones arranged along the first direction D1.
  • the first active area 10 and the second active area 11 in the memory cell are electrically connected.
  • the semiconductor structure described in this specific embodiment may be, but is not limited to, a DRAM.
  • the following description takes the semiconductor structure as a DRAM as an example.
  • the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment will be described by taking the substrate 20 as a silicon substrate as an example. In other embodiments, the substrate 20 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI.
  • the substrate 20 is used to support device structures thereon.
  • a plurality of the memory cells are arranged in a two-dimensional array on the top surface of the substrate 20 along the first direction D1 and the second direction D2 to form the memory array.
  • the memory cell includes the transistor structure, the transistor structure includes the gate electrode and the active area, and all the active areas in the memory array are also along the first direction D1 and the first direction D1.
  • the two directions D2 are arranged in an array to form an active array.
  • the gate electrode 12 in the transistor structure separates the active area into the first active area 10 and the second active area 10 distributed on opposite sides of the gate electrode 12 along the first direction D1.
  • two transistors with a common gate electrode and arranged along the first direction D1 can be formed in the transistor structure.
  • One of the bit lines 14 located outside the memory cell is electrically connected to the memory cell.
  • the first active area 10 and the second active area 11 inside.
  • the top surface of the substrate 20 refers to the surface of the substrate 20 facing the memory array.
  • the plurality mentioned in this specific embodiment refers to two or more.
  • the structure of the memory cell, the position of the word line 13 and the gate electrode 12, the position of the bit line 14, and the two of the bit line 14 and the memory cell are set.
  • the connection relationship between the transistors allows the memory array in this specific embodiment to have a 4F2 array structure, in which the density of the memory cells in the memory array is more than twice that of the 6F2 array structure, thus extremely This greatly increases the density of the memory cells within the memory array, which helps to increase the storage capacity of the semiconductor structure or reduce the size of the semiconductor structure.
  • one of the bit lines 14 and one of the word lines 13 electrically connected to the selected memory cell are turned on (i.e., to the selected memory cell
  • One of the bit lines 14 and one of the word lines 13 that are electrically connected to the cells transmit read and write signals), so that the two transistors in the selected memory cell are turned on at the same time, thereby switching on the selected memory cell.
  • Two parallel signal transmission channels are formed in the unit, and the two signal transmission channels transmit read and write signals at the same time to realize read and write operations, thereby improving the stability and stability of the read and write signal transmission inside the storage unit. The efficiency of transmission improves the electrical properties of the semiconductor structure.
  • the first active region 10 includes a first channel region 101, and a first source region 102 and a first source region 102 distributed on opposite sides of the first channel region 101 along the third direction D3. a drain region 103, wherein the third direction D3 is perpendicular to the top surface of the substrate 20;
  • the second active region 11 includes a second channel region 111, and a second source region 112 and a second drain region distributed on opposite sides of the second channel region 111 along the third direction D3. 113, and the first channel region 101 and the second channel region 111 are symmetrically distributed with respect to the gate electrode 12.
  • the two transistors in the transistor structure are vertical structure transistors. After one of the memory cells is selected, two parallel vertical transistors are simultaneously formed inside the memory cell and turned on. signal transmission channel.
  • the two transistors in the memory unit are symmetrically distributed along the first direction D1 with respect to an axis, which passes through the center of the active area and extends along the second direction D2, that is, the The first active region 10 and the second active region 11 are symmetrically distributed about the axis (including the first channel region 101 and the second channel region 111 are symmetrically distributed about the axis, the first channel region 101 and the second channel region 111 are symmetrically distributed about the axis, A source region 102 and the second source region 112 are symmetrically distributed about the axis, and the first drain region 103 and the second drain region 113 are symmetrically distributed about the axis), so that the The two transistors connected in parallel in the transistor structure have the same transmission current, thereby further improving the performance of the semiconductor structure.
  • the memory cell further includes a first gate dielectric layer located between the first channel region 101 and the gate electrode 12, and a first gate dielectric layer located between the second channel region 111 and the gate electrode 12.
  • a second gate dielectric layer between the electrodes 12 is the same, for example, both are oxide materials (such as silicon dioxide).
  • the semiconductor structure further includes:
  • a bit line contact array is located below the memory array and includes a plurality of bit line contact structures 15 arranged in an array along the first direction D1 and the second direction D2;
  • the bit line contact structure 15 is electrically connected to the active area in the transistor structure, and a plurality of the bit line contact structures arranged at intervals along the first direction D1 is the same bit line as 15 14 electrical connections.
  • the semiconductor structure also includes a plurality of bit line contact structures 15.
  • the bit line contact structures 15 are located under the active area and are used to electrically connect the bit lines 14 and the memory cells. In the active area, signals are transmitted between the bit line 14 and the memory cell through the bit line contact structure 15, so that the bit line 14 can be arranged along the memory cell. While forming a 4F2 array structure on the outside of the second direction D2, the connection line between the bit line 14 and the memory cell can also be simplified, thereby simplifying the manufacturing process of the semiconductor structure.
  • the material of the bit line contact structure 15 is a conductive material such as polysilicon.
  • bit line contact array and the memory array are staggered
  • One bit line contact structure 15 is electrically connected to two adjacent active area contacts along the first direction D1, and one active area is electrically connected to two adjacent active area contacts along the first direction D1.
  • the bit line contact structures 15 make electrical connections.
  • bit line contact structure 15 is along the first direction D1.
  • One end of the bit line contact structure 15 is electrically connected to the first source region 102 in one of the memory cells, and the other end of the bit line contact structure 15 along the first direction D1 is electrically connected to the first source region 102 of the other memory cell.
  • the two source regions 112 are electrically connected;
  • the two bit line contact structures 15 electrically connected to one of the active area contacts are symmetrically distributed about the axis of the active area, the axis extending along the second direction D2.
  • a plurality of bit line contact structures 15 are arranged in a two-dimensional array along the first direction D1 and the second direction D2 to form the bit line contact array.
  • the staggered arrangement of the bit line contact array and the memory array means that the projection of the bit line contact structure 15 in the bit line contact array on the top surface of the substrate 20 is different from that in the memory array.
  • the projections of the memory cells on the top surface of the substrate 20 are staggered along the first direction D1 and the second direction D2.
  • one bit line contact structure 15 is located between the active areas in two adjacent memory cells along the first direction D1, and the bit line contact structure 15 is connected to the active area along the first direction D1.
  • the active areas in the two adjacent memory cells in the first direction D1 are in contact and electrically connected.
  • the cross-section of the bit line contact structure 15 may be circular, elliptical, or any polygon. Taking the cross-section of the bit line contact structure 15 as a rectangle as an example, the two opposite ends of the bit line contact structure 15 along the first direction D1 are respectively adjacent to the two adjacent ends along the first direction D1.
  • the active area contact is electrically connected
  • the end of the bit line contact structure 15 along the second direction D2 is electrically connected to one of the bit lines 14
  • the first active area in one of the memory cells 10 and the second active area 11 are respectively in contact and electrically connected with the two bit line contact structures 15 spaced apart along the first direction D1, thereby further increasing the density inside the semiconductor structure.
  • the two bit line contact structures 15 electrically connected to one of the active area contacts are symmetrically distributed about an axis passing through the center of the active area and extending along the second direction D2, that is, with the same
  • the two bit line contact structures 15 of the first source region 102 and the second source region 112 in the memory cell are symmetrically distributed about the axis, so that the two bit line contact structures 15 are aligned with
  • the contact areas of the first source region 102 and the second source region 112 in the same memory cell are equal, thereby further ensuring that the transmission between the two transistors in the same memory cell is
  • the current signals are equal in magnitude to further improve the performance of the semiconductor structure.
  • the shape and size of the projection of the bit line contact structure 15 on the top surface of the substrate 20 is consistent with the formation and formation of the projection of the active area on the top surface of the substrate 20 . All sizes are the same;
  • the distance between adjacent bit line contact structures 15 is equal to the distance between adjacent active areas, so that the photomask for forming multiple active areas can be combined with the photomask for forming multiple bit line contacts.
  • the photomasks of the structures 15 are shared, which reduces the number of photomasks in the manufacturing process of the semiconductor structure and reduces the manufacturing cost of the semiconductor structure.
  • the storage unit further includes:
  • the capacitor structure 18 is located above the transistor structure, and the capacitor structure 18 is electrically connected to the first drain region 103 and the second drain region 113 .
  • the capacitor structure 18 is on the top of the substrate 20
  • the projection on the surface at least completely covers the projection of the active area on the top surface of the substrate 20 , so that the contact area between the capacitor structure 18 and the two transistors in the transistor structure is increased. , thereby reducing the contact resistance between the capacitor structure and the transistor structure.
  • the projection of the active area on the top surface of the substrate 20 is within the projection of the capacitive structure 18 on the top surface of the substrate 20 .
  • the memory unit structure further includes:
  • Node contact structure 17 is located between the capacitor structure 18 and the transistor. One end of the node contact structure 17 is electrically connected to the first drain region 103 and the second drain region 113, and the other end is in contact. The capacitive structure 18 is electrically connected.
  • the memory unit includes one capacitor structure 18, that is, two of the transistors in the transistor structure are electrically connected to the same capacitor structure 18, thereby forming the memory unit with a 2T1C structure.
  • the memory cell also includes the node contact structure 17 located above the transistor structure along the third direction D3, a capacitive isolation layer 16 located between the node contact structure 17 and the gate electrode 12, and a capacitive isolation layer 16 located between the node contact structure 17 and the gate electrode 12.
  • the node contact structure 17 faces away from the capacitor structure 18 on the side of the transistor structure.
  • the capacitive isolation layer 16 is used to electrically isolate the gate electrode 12 and the node contact structure 17 .
  • the material of the capacitive isolation layer 16 may be an insulating dielectric material such as an oxide material (such as silicon dioxide).
  • the node contact structure 17 covers at least completely the drain region 103 and the second drain region 113 in the transistor structure.
  • the capacitor structure 18 is directly in electrical contact with the node contact structure 17 , thereby eliminating the need to form a transfer pad (LP), simplifying the manufacturing process of the semiconductor structure, and reducing the manufacturing cost of the semiconductor structure.
  • the material of the node contact structure 17 is a conductive material such as polysilicon.
  • the node contact structure 17 is formed along the The dimensions of the first direction D1 and the second direction D2 are both larger than the size of the whole composed of the first active region 10 and the second active region 11 in the first direction D1 and the second direction. D2 size.
  • a plurality of the word lines 13 are arranged at intervals along the first direction D1, and a plurality of the bit lines 14 are arranged at intervals along the second direction D2;
  • the distance between two adjacent word lines 13 along the first direction D1, the distance between two adjacent bit lines 14 along the second direction D2, and the distance between adjacent memory are all equal.
  • the distance between two adjacent word lines 13 along the first direction D1 the distance between two adjacent bit lines 14 along the second direction D2
  • the distance between the memory cells, the distance between adjacent active areas, and the distance between adjacent bit line contact structures 15 are all equal, thereby further reducing the area occupied by the memory cells.
  • the density of the memory cells in the memory array is further increased.
  • FIGS. 1 and 2 Schematic diagrams of the semiconductor structure formed in this specific embodiment can be shown in FIGS. 1 and 2 .
  • the method for forming the semiconductor structure includes the following steps:
  • Step S31 Form a substrate 20 and an active array located on the substrate 20.
  • the active array includes a plurality of active regions 40 arranged in an array along the first direction D1 and the second direction D2, wherein , the first direction D1 and the second direction D2 are both parallel to the top surface of the substrate 20, and the first direction D1 is perpendicular to the second direction D2, as shown in Figure 4, where, (a) in Figure 4 is a schematic structural view from above, (b) in Figure 4 is a schematic cross-sectional view of (a) in Figure 4 at the position a-a, and (c) in Figure 4 is a schematic view of (a) in Figure 4 at the position a-a. Schematic cross-section at position b-b.
  • Step S32 Form bit lines 14 on the outside of the active area 40 along the second direction D2.
  • the bit lines 14 extend along the first direction D1 and are continuously arranged at intervals along the first direction D1.
  • a plurality of the active areas 40 of the cloth are electrically connected, as shown in Figure 7, where (a) in Figure 7 is a schematic top view of the structure, and (b) in Figure 7 is a-a between (a) in Figure 7 A schematic cross-sectional view of the position, (c) in Figure 7 is a schematic cross-sectional view of (a) in Figure 7 at the b-b position.
  • Step S33 Form the gate electrode 12 penetrating the active region 40 along the second direction D2, and form a plurality of gate electrodes 12 extending along the second direction D2 and continuously arranged at intervals along the second direction D2.
  • the electrode 12 is electrically connected to the word line 13, and the gate electrode 12 separates the active area 40 into a first active area 10 and a second active area 11 arranged along the first direction D1, as shown in Figure 9
  • (a) in Figure 9 is a schematic structural view from above
  • (b) in Figure 9 is a schematic cross-sectional view of (a) in Figure 9 at the position a-a
  • (c) in Figure 9 is a schematic view of the structure in Figure 9 (a) Schematic cross-section at position b-b.
  • bit line 14 before forming the bit line 14 along the outside of the active area 40 in the second direction D2, the following steps are also included:
  • a bit line contact array is formed below the active array.
  • the bit line contact array includes a plurality of bit line contact structures 15 arranged in an array along the first direction D1 and the second direction D2.
  • the bit line contact structure 15 is electrically connected to the active area 40 .
  • the substrate 20 further includes a first isolation layer 41 between adjacent active areas 40; the specific steps of forming a bit line contact array located below the active array include:
  • Part of the active region 40 and part of the first isolation layer 41 are etched to form a plurality of first trenches 50 arranged in an array along the first direction D1 and the second direction D2.
  • the first trench 50 overlaps two adjacent active areas 40 along the first direction D1, and one active area 40 overlaps two adjacent active areas 40 along the first direction D1.
  • the first grooves 50 overlap;
  • the bit line contact structure 15 electrically connected to the active area 40 is formed at the bottom of the first trench 50, as shown in Figure 5, where (a) in Figure 5 is a schematic top view of the structure, (b) in Figure 5 is a schematic cross-sectional view of (a) in Figure 5 at the position a-a, and (c) in Figure 5 is a schematic cross-sectional view of (a) in Figure 5 at the position b-b.
  • an initial substrate is first provided, and the initial substrate is etched along the first direction D1 and the second direction D2 to form a two-dimensional structure along the first direction D1 and the second direction D2.
  • a plurality of active areas 40 arranged in an array and active area isolation trenches located between adjacent active areas 40 form the active array, leaving the initial The substrate serves as the substrate 20 .
  • a photolithography process is used to etch part of the active region 40 and part of the first isolation layer 41 to form a plurality of first isolation layers arranged in an array along the first direction D1 and the second direction D2.
  • One trench 50 is used to etch part of the active region 40 and part of the first isolation layer 41 to form a plurality of first isolation layers arranged in an array along the first direction D1 and the second direction D2.
  • first trench 50 Fill the first trench 50 with conductive materials such as polysilicon, and form the bit line contact structure 15 electrically connected to the active area 40 at the bottom of the first trench 50, as shown in FIG. 5 .
  • conductive materials such as polysilicon
  • an alignment process may be used to make one first trench 50 overlap with two adjacent active areas 40 along the first direction D1, And one of the active regions 40 overlaps two adjacent first trenches 50 along the first direction D1, thereby further increasing the density of the semiconductor structure.
  • the specific steps of forming the bit line 14 on the outside of the active area 40 along the second direction D2 include:
  • FIG. 6 Form a second isolation layer 60 that fills the first trench 50, as shown in Figure 6, where (a) in Figure 6 is a schematic top view of the structure, and (b) in Figure 6 is (b) in Figure 6 a) A schematic cross-sectional view at position a-a. (c) in Figure 6 is a schematic cross-sectional view of (a) in Figure 6 at position b-b;
  • a bit line 14 extending along the first direction D1 is formed in the second trench 70 .
  • the bit line 14 is continuously connected to a plurality of bit line contact structures 15 arranged at intervals along the first direction D1 . Make the electrical connections as shown in Figure 7.
  • a gate electrode 12 is formed that penetrates the active region 40 along the second direction D2, and a plurality of gate electrodes 12 extending along the second direction D2 and continuously and spaced apart along the second direction D2 are formed.
  • the specific steps of electrically connecting the gate electrode 12 to the word line 13 include:
  • FIG. 8 Form a third isolation layer 80 that fills the second trench 70, as shown in Figure 8, where (a) in Figure 8 is a schematic top view of the structure, and (b) in Figure 8 is (b) in Figure 8 a) A schematic cross-sectional view at position a-a. (c) in Figure 8 is a schematic cross-sectional view of (a) in Figure 8 at position b-b;
  • the gate electrode 12 is formed in the gate trench, and the word line 13 is formed in the word line trench, as shown in FIG. 9 .
  • the gate trench separates the active area into the first active area 10 and the second active area 11 arranged along the first direction D1.
  • form the gate electrode 12 filling the gate trench and the word line 13 filling the word line trench, and etch back the portion.
  • the gate electrode 12 and part of the word line 13 are positioned so that the top surface of the gate electrode 12 is located below the top surface of the gate trench and the top surface of the word line 13 is located in the word line trench. under the top surface.
  • insulating dielectric materials such as oxide (such as silicon dioxide) are filled into the gate trench and the word line trench to form a capacitive isolation layer 16 covering the gate electrode 12 and the word line 13, as shown in FIG. 9 shown.
  • the materials of the gate electrode 12 and the word line 13 are conductive materials such as metallic tungsten or TiN.
  • the gate electrode 12 is formed through the active area along the second direction D2, and a plurality of the gate electrodes 12 are formed extending along the second direction D2 and arranged continuously and spaced apart along the second direction D2. After the gate electrode 12 is electrically connected to the word line 13, the following steps are also included:
  • a capacitor structure 18 is formed above the active area 40 .
  • the capacitor structure 18 is electrically connected to the first active area 10 and the second active area 11 .
  • the capacitor structure 18 is on the substrate 20
  • the projection on the top surface at least completely covers the projection of the active area 40 on the top surface of the substrate 20 .
  • the node contact structure 17 covering the first active area 10 , the second active area 11 and the capacitive isolation layer 16 is first formed above the active area, and then the Node contact structure 17 is above the capacitive structure 18 .
  • the capacitor structure includes a lower electrode layer covering the surface of the node contact structure 17 and electrically connected to the node contact structure 17 , a dielectric layer covering the surface of the lower electrode layer, and a dielectric layer covering the surface of the node contact structure 17 . surface of the upper electrode layer.
  • the memory unit includes a transistor.
  • the gate electrode in the transistor structure separates the active area into a first active area and a second active area, so that the transistor structure can be Two transistors with a common gate electrode are formed, and the same bit line is electrically connected to the first active region and the second active region in the memory cell, so that when the bit line is electrically connected to the memory cell
  • two parallel signal transmission channels can be formed in the memory cell, which can not only improve the signal transmission efficiency and improve the electrical performance of the semiconductor structure, but also form 4F2 (where, F is the characteristic size) of the memory array structure to achieve an increase in the density of memory cells in the semiconductor structure.
  • the projection of the capacitor structure on the top surface of the substrate at least completely covers the projection of the active area on the top surface of the substrate, thereby increasing the distance between the capacitor structure and the top surface of the substrate.
  • the contact area of the transistor structure reduces the contact resistance inside the memory cell, thereby improving the electrical performance of the semiconductor structure.
  • the capacitor structure in some embodiments of this embodiment is directly electrically connected to the node contact structure without forming a transfer pad (LP), thereby simplifying the manufacturing process of the semiconductor structure and reducing the manufacturing cost of the semiconductor structure. cost.

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Abstract

本公开涉及一种半导体结构及其形成方法。半导体结构包括：衬底；存储阵列，位于衬底上，包括沿第一方向和第二方向呈阵列排布的多个存储单元，存储单元包括晶体管结构，晶体管结构包括栅电极和有源区，有源区包括沿第一方向分布于栅电极相对两侧的第一有源区和第二有源区；字线，沿第二方向延伸，且连续与沿第二方向间隔排布的多个存储单元内的栅电极电连接；位线，沿第一方向延伸、且位于存储单元沿第二方向的外侧，位线连续与沿第一方向间隔排布的多个存储单元内的第一有源区和第二有源区电连接。本公开改善半导体结构的电性能，而且实现了对半导体结构中存储单元密集度的提高。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2022年08月19日递交的中国专利申请号202211003987.3、申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
DRAM等半导体结构中的漏极依次通过节点接触(Node Contact，NC)和转接垫(Landing Pad，LP)与电容器电连接，但是，漏极、节点接触、以及转接垫之间的接触面积较小，从而会增大半导体结构内部的电阻，导致半导体结构电性能的降低。另外，DRAM等半导体结构中的存储阵列多采用6F2阵列结构，密集度较低，不利于所述半导体结构集成度和存储容量的提高。
因此，如何提高半导体结构的密集度，并改善半导体结构的电性能，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体结构及其形成方法，用于提高所述半导体结构的密集度，并改善所述半导体结构的电性能。
根据一些实施例，本公开提供了一种半导体结构，包括：
衬底；
存储阵列，位于所述衬底上，包括沿第一方向和第二方向呈阵列排布的多个存储单元，所述存储单元包括晶体管结构，所述晶体管结构包括栅电极和有源区，所述有源区包括沿第一方向分布于所述栅电极相对两侧的第一有源区和第二有源区，其中，所述第一方向和所述第二方向均与所述衬底的顶面平行，且所述第一方向与所述第二方向垂直；
字线，沿所述第二方向延伸，且连续与沿所述第二方向间隔排布的多个所述存储单元内的所述栅电极电连接；
位线，沿所述第一方向延伸、且位于所述存储单元沿所述第二方向的外侧，所述位线连续与沿所述第一方向间隔排布的多个所述存储单元内的所述第一有源区和所述第二有源区电连接。
在一些实施例中，所述第一有源区包括第一沟道区、以及沿第三方向分布于所述第一沟道区相对两侧的第一源极区和第一漏极区，其中，所述第三方向与所述衬底的顶面垂直；
所述第二有源区包括第二沟道区、以及沿所述第三方向分布于所述第二沟道区相对两侧的第二源极区和第二漏极区，且所述第一沟道区和所述第二沟道区关于所述栅电极对称分布。
在一些实施例中，还包括：
位线接触阵列，位于所述存储阵列下方，包括沿所述第一方向和所述第二方向呈阵列排布的多个位线接触结构；
所述位线接触结构与所述晶体管结构中的所述有源区电连接，且沿所述第一方向间隔排布的多个所述位线接触结构与同一条所述位线电连接。
在一些实施例中，所述位线接触阵列与所述存储阵列错开排布；
一个所述位线接触结构与沿所述第一方向相邻的两个所述有源区接触电连接，且一个所述有源区与沿所述第一方向相邻的两个所述位线接触结构接触电连接。
在一些实施例中，对于位于沿所述第一方向相邻的两个所述存储单元之间的一个所述位线接触结构，所述位线接触结构沿所述第一方向的一端与一个所述存储单元中的所述第一源极区电连接、所述位线接触结构沿所述第一方向的另一端与另一个所述存储单元中的所述第二源极区电连接；
与一个所述有源区接触电连接的两个所述位线接触结构关于所述有源区的轴线对称分布，所述轴线沿所述第二方向延伸。
在一些实施例中，所述位线接触结构在所述衬底的顶面上的投影的形状和尺寸与所述有源区在所述衬底的顶面上的投影的形成和尺寸均相同；
相邻所述位线接触结构之间的距离与相邻所述有源区之间的距离相等。
在一些实施例中，所述存储单元还包括：
电容结构，位于所述晶体管结构上方，且所述电容结构电连接所述第一漏极区和所述第二漏极区，所述电容结构在所述衬底的顶面上的投影至少完全覆盖所述有源区在所述衬底的顶面上的投影。
在一些实施例中，所述存储单元结构还包括：
节点接触结构，位于所述电容结构和所述晶体管之间，所述节点接触结构的一端接触电连接所述第一漏极区和所述第二漏极区、另一端接触电连接所述电容结构。
在一些实施例中，多条所述字线沿所述第一方向间隔排布，多条所述位线沿所述第二方向间隔排布；
沿所述第一方向相邻的两条所述字线之间的距离、沿所述第二方向相邻的两条所述位线之间的距离、以及相邻所述存储单元之间的距离均相等。
根据另一些实施例，本公开还提供了一种半导体结构的形成方法，包括如下步骤：
形成衬底、以及位于所述衬底上的有源阵列，所述有源阵列包括沿第一方向和第二方向呈阵列排布的多个有源区，其中，所述第一方向和所述第二方向均与所述衬底的顶面平行，且所述第一方向与所述第二方向垂直；
于所述有源区沿所述第二方向的外侧形成位线，所述位线沿所述第一方向延伸、且连续与沿所述第一方向间隔排布的多个所述有源区电连接；
形成沿第二方向贯穿所述有源区的栅电极、并形成沿所述第二方向延伸且连续与沿所述第二方向间隔排布的多个所述栅电极电连接的字线，所述栅电极将所述有源区分隔为沿所述第一方向排布的第一有源区和第二有源区。
在一些实施例中，于所述有源区沿所述第二方向的外侧形成位线之前，还包括如下步骤：
形成位于所述有源阵列下方的位线接触阵列，所述位线接触阵列包括沿所述第一方向和所述第二方向呈阵列排布的多个位线接触结构，所述位线接触结构与所述有源区接触电连接。
在一些实施例中，所述衬底上还包括位于相邻所述有源区之间的第一隔离层；形成位于所述有源阵列下方的位线接触阵列的具体步骤包括：
刻蚀部分的所述有源区和部分的所述第一隔离层，形成沿所述第一方向和所述第二方向呈阵列排布的多个第一沟槽，一个所述第一沟槽与沿所述第一方向相邻的两个所述有源区交叠，且一个所述有源区与沿所述第一方向相邻的两个所述第一沟槽交叠；
于所述第一沟槽的底部形成与所述有源区接触电连接的所述位线接触结构。
在一些实施例中，于所述有源区沿所述第二方向的外侧形成位线的具体步骤包括：
形成填充满所述第一沟槽的第二隔离层；
刻蚀部分的所述第二隔离层和部分的所述第一隔离层，形成位于所述有源区沿所述第二方向的外侧、且暴露所述位线接触结构的第二沟槽；
于所述第二沟槽内形成沿所述第一方向延伸的位线，所述位线连续与沿所述第一方向间隔排布的多个所述位线接触结构接触电连接。
在一些实施例中，形成沿第二方向贯穿所述有源区的栅电极、并形成沿所述第二方向延伸且连续与沿所述第二方向间隔排布的多个所述栅电极电连接的字线的具体步骤包括：
形成填充满所述第二沟槽的第三隔离层；
刻蚀所述有源区、所述第一隔离层和所述第三隔离层，于所述有源区内形成沿所述第二方向贯穿所述有源区的栅极槽、并于沿所述第二方向相邻所述有源区之间形成字线槽；
于所述栅极槽内形成所述栅电极、并于所述字线槽内形成所述字线。
在一些实施例中，形成沿第二方向贯穿所述有源区的栅电极、并形成沿所述第二方向延伸且连续与沿所述第二方向间隔排布的多个所述栅电极电连接的字线之后，还包括如下步骤：
形成电容结构于所述有源区上方，所述电容结构电连接所述第一有源区和所述第二有源区，所述电容结构在所述衬底的顶面上的投影至少完全覆盖所述有源区在所述衬底的顶面上的投影。
本公开一些实施例提供的半导体结构及其形成方法，存储单元包括晶体管，晶体管结构中的栅电极将有源区分隔为第一有源区和第二有源区，从而可以在晶体管结构中形成共用栅电极的两个晶体管，且同一条位线与所述存储单元内的所述第一有源区和所述第二有源区电连接，使得在与所述存储单元电连接的一条字线和一条位线开启之后，可以在所述存储单元内形成了相互并联的两个信号传输通道，不仅能够提高信号传输效率，改善半导体结构的电性能，而且还能够形成4F2(其中，F为特征尺寸)的存储阵列结构，以实现对半导体结构中存储单元密集度的提高。本公开另一些实施例中，电容结构在所述衬底的顶面上的投影至少完全覆盖所述有源区在所述衬底的顶面上的投影，从而能够增大电容结构与晶体管结构的接触面积，降低所述存储单元内部的接触电阻，从而改善所述半导体结构的电性能。而且，本公开一些实施例中的电容结构直接与节点接触结构接触电连接，无需形成转接垫(LP)，从而简化了所述半导体结构的制程工艺，降低了所述半导体结构的制造成本。
附图说明
附图1是本公开具体实施方式中半导体结构的俯视结构示意图；
附图2是本公开具体实施方式中存储单元的结构示意图；
附图3是本公开具体实施方式中半导体结构的形成方法流程图；
附图4-附图10是本公开具体实施方式在形成半导体结构的过程中主要工艺的结构示意图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构，附图1是本公开具体实施方式中半导体结构的俯视结构示意图，附图2是本公开具体实施方式中存储单元的结构示意图。如图1和图2所示，所述半导体结构，包括：
衬底20；
存储阵列，位于所述衬底20上，包括沿第一方向D1和第二方向D2呈阵列排布的多个存储单元，所述存储单元包括晶体管结构，所述晶体管结构包括栅电极12和有源区，所述有源区包括沿第一方向D1分布于所述栅电极12相对两侧的第一有源区10和第二有源区11，其中，所述第一方向D1和所述第二方向D2均与所述衬底20的顶面平行，且所述第一方向D1与所述第二方向D2垂直；
字线13，沿所述第二方向D2延伸，且连续与沿所述第二方向D2间隔排布的多个所述存储单元内的所述栅电极12电连接；
位线14，沿所述第一方向D1延伸、且位于所述存储单元沿所述第二方向D2的外侧，所述位线14连续与沿所述第一方向D1间隔排布的多个所述存储单元内的所述第一有源区10和所述第二有源区11电连接。
本具体实施方式中所述的半导体结构可以是但不限于DRAM，以下以所述半导体结构为DRAM为例进行说明。所述衬底20可以是但不限于硅衬底，本具体实施方式以所述衬底20为硅衬底为例进行说明。在其他实施例中，所述衬底20还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底20用于支撑在其上的器件结构。多个所述存储单元在所述衬底20的顶面上沿所述第一方向D1和所述第二方向D2呈二维阵列排布，形成所述存储阵列。所述存储单元包括所述晶体管结构，所述晶体管结构包括所述栅电极和所述有源区，所述存储阵列中的所有所述有源区也沿所述第一方向D1和所述第二方向D2呈阵列排布，形成有源阵列。所述晶体管结构中的所述栅电极12将所述有源区分隔为沿所述第一方向D1分布于所述栅电极12相对两侧的所述第一有源区10和所述第二有源区11，从而可以在晶体管结构中形成共用栅电极、且沿所述第一方向D1排布的两个晶体管，位于所述存储单元外侧的一条所述位线14电连接所述存储单元内的所述第一有源区10和所述第二有源区11。本具体实施方式中所述衬底20的顶面是指所述衬底20朝向所述存储阵列的表面。本具体实施方式中所述的多个是指两个以上。
本具体实施方式通过设置所述存储单元的结构、所述字线13和所述栅电极12的位置、所述位线14的位置、以及所述位线14与所述存储单元中的两个所述晶体管之间的连接关系，使得本具体实施方式中的所述存储阵列可以具有4F2阵列结构，其所述存储阵列中所述存储单元的密集度是6F2阵列结构的2倍以上，从而极大的提高了所述存储阵列内部所述存储单元的密集度，有助于提高所述半导体结构的存储容量或者缩小所述半导体结构的尺寸。
在对一个选定的所述存储单元进行读写操作时，开启与选定的所述存储单元电连接的一条所述位线14和一条所述字线13(即向选定的所述存储单元电连接的一条所述位线14和一条所述字线13传输读写信号)，使得选定的所述存储单元内的两个所述晶体管同时导通，从而于选定的所述存储单元内形成两条并联的信号传输通道，两条所述信号传输通道同时进行读写信号的传输，实现读写操作，从而提高了所述读写信号在所述存储单元内部传输的稳定性和传输的效率，改善了所述半导体结构的电性能。
在一些实施例中，所述第一有源区10包括第一沟道区101、以及沿第三方向D3分布于所述第一沟道区101相对两侧的第一源极区102和第一漏极区103，其中，所述第三方向D3与所述衬底20的顶面垂直；
所述第二有源区11包括第二沟道区111、以及沿所述第三方向D3分布于所述第二沟道区111相对两侧的第二源极区112和第二漏极区113，且所述第一沟道区101和所述第二沟道区111关于所述栅电极12对称分布。
具体来说，所述晶体管结构中的两个所述晶体管均为垂直结构的晶体管，在一个所述存储单元被选定后，所述存储单元内部同时形成、并导通两个相互并联的垂直信号传输通道。而且，所述存储单元内的两个所述晶体管沿所述第一方向D1关于轴线对称分布，所述轴线穿过所述有源区的中心且沿所述第二方向D2延伸，即所述第一有源区10与所述第二有源区11关于所述轴线对称分布(包括所述第一沟道区101和所述第二沟道区111关于所述轴线对称分布、所述第一源极区102和所述第二源极区112关于所述轴线对称分布、以及所述第一漏极区103和所述第二漏极区113关于所述轴线对称分布)，从而使得所述晶体管结构中相互并联的两个所述晶体管中传输电流大小相同，从而进一步改善所述半导体结构的性能。
在一些实施例中，所述存储单元还包括位于所述第一沟道区101与所述栅电极12之间的第一栅介质层、以及位于所述第二沟道区111与所述栅电极12之间的第二栅介质层。在一示例中，所述第一栅介质层的材料和所述第二栅介质层的材料相同，例如均为氧化物材料(例如二氧化硅)。
在一些实施例中，所述半导体结构还包括：
位线接触阵列，位于所述存储阵列下方，包括沿所述第一方向D1和所述第二方向D2 呈阵列排布的多个位线接触结构15；
所述位线接触结构15与所述晶体管结构中的所述有源区电连接，且沿所述第一方向D1间隔排布的多个所述位线接触结构与15同一条所述位线14电连接。
具体来说，所述半导体结构中还包括多个所述位线接触结构15，所述位线接触结构15位于所述有源区下方，用于电连接所述位线14与所述存储单元中的所述有源区，所述位线14与所述存储单元之间通过所述位线接触结构15进行信号的传输，从而使得所述位线14能够布置在所述存储单元沿所述第二方向D2的外侧以形成4F2阵列结构的同时，也能简化所述位线14与所述存储单元之间的连接线路，从而简化所述半导体结构的制程工艺。在一示例中，所述位线接触结构15的材料为多晶硅等导电材料。
为了进一步提高所述半导体结构内的密集度，在一些实施例中，所述位线接触阵列与所述存储阵列错开排布；
一个所述位线接触结构15与沿所述第一方向D1相邻的两个所述有源区接触电连接，且一个所述有源区与沿所述第一方向D1相邻的两个所述位线接触结构15接触电连接。
在一些实施例中，对于位于沿所述第一方向D1相邻的两个所述存储单元之间的一个所述位线接触结构15，所述位线接触结构15沿所述第一方向D1的一端与一个所述存储单元中的所述第一源极区102电连接、所述位线接触结构15沿所述第一方向D1的另一端与另一个所述存储单元中的所述第二源极区112电连接；
与一个所述有源区接触电连接的两个所述位线接触结构15关于所述有源区的轴线对称分布，所述轴线沿所述第二方向D2延伸。
具体来说，如图1和图2所示，多个所述位线接触结构15沿所述第一方向D1和所述第二方向D2呈二维阵列排布，形成所述位线接触阵列。所述位线接触阵列与所述存储阵列错开排布是指，所述位线接触阵列中的所述位线接触结构15在所述衬底20的顶面上的投影与所述存储阵列中的所述存储单元在所述衬底20的顶面上的投影沿所述第一方向D1和所述第二方向D2错开。举例来说，一个所述位线接触结构15位于沿所述第一方向D1相邻的两个所述存储单元中的所述有源区之间，且所述位线接触结构15与沿所述第一方向D1相邻的两个所述存储单元中的所述有源区均接触电连接。
所述位线接触结构15的截面形成可以是圆形、椭圆形、或者任意多边形。以所述位线接触结构15的截面为矩形为例，所述位线接触结构15沿所述第一方向D1相对的两端部分别与沿所述第一方向D1相邻的两个所述有源区接触电连接，所述位线接触结构15沿所述第二方向D2的端部与一条所述位线14接触电连接，且一个所述存储单元内的所述第一有源区10和所述第二有源区11分别与沿所述第一方向D1间隔排布的两个所述位线接触结构15接触电连接，从而进一步提高所述半导体结构内部的密集度。
与一个所述有源区接触电连接的两个所述位线接触结构15关于穿过所述有源区的中心且沿所述第二方向D2延伸的轴线对称分布，即与同一个所述存储单元内的所述第一源极区102和所述第二源极区112的两个所述位线接触结构15关于所述轴线对称分布，从而使得两个所述位线接触结构15与同一个所述存储单元内的所述第一源极区102和所述第二源极区112的接触面积相等，从而进一步确保在同一个所述存储单元内的两个所述晶体管内传输的电流信号的大小相等，以进一步提高所述半导体结构的性能。
在一实施例中，所述栅电极12在所述衬底20的顶面上的投影与所述位线接触结构15在所述衬底20的顶面上的投影之间具有间隙，即所述栅电极12在所述衬底20的顶面上的投影与所述位线接触结构15在所述衬底20的顶面上的投影不接触，从而减小甚至是消除所述栅电极12与所述位线接触结构15之间的寄生电容效应。
在一些实施例中，所述位线接触结构15在所述衬底20的顶面上的投影的形状和尺寸与所述有源区在所述衬底20的顶面上的投影的形成和尺寸均相同；
相邻所述位线接触结构15之间的距离与相邻所述有源区之间的距离相等，从而可以将形成多个所述有源区的光罩与形成多个所述位线接触结构15的光罩共用，减少了所述半导 体结构制造过程中的光罩数量，降低了所述半导体结构的制造成本。
在一些实施例中，所述存储单元还包括：
电容结构18，位于所述晶体管结构上方，且所述电容结构18电连接所述第一漏极区103和所述第二漏极区113，所述电容结构18在所述衬底20的顶面上的投影至少完全覆盖所述有源区在所述衬底20的顶面上的投影，使得所述电容结构18与所述晶体管结构中的两个所述晶体管之间的接触面积增大，从而降低了所述电容结构与所述晶体管结构之间的接触电阻。在一示例中，所述有源区在所述衬底20的顶面上的投影位于所述电容结构18在所述衬底20的顶面上的投影内。
在一些实施例中，所述存储单元结构还包括：
节点接触结构17，位于所述电容结构18和所述晶体管之间，所述节点接触结构17的一端接触电连接所述第一漏极区103和所述第二漏极区113、另一端接触电连接所述电容结构18。
图1中未示出所述电容结构和所述节点接触结构。具体来说，所述存储单元内包括一个所述电容结构18，即所述晶体管结构中的两个所述晶体管与同一个所述电容结构18电连接，从而形成具有2T1C结构的所述存储单元。所述存储单元还包括沿所述第三方向D3位于所述晶体管结构上方的所述节点接触结构17、位于所述节点接触结构17与所述栅电极12之间的电容隔离层16、以及位于所述节点接触结构17背离所述晶体管结构一侧的所述电容结构18。所述电容隔离层16用于电性隔离所述栅电极12与所述节点接触结构17。在一实施例中，所述电容隔离层16的材料可以为氧化物材料(例如二氧化硅)等绝缘介质材料。所述节点接触结构17覆盖至少完全覆盖所述晶体管结构中的所述漏极区103和所述第二漏极区113。所述电容结构18直接与所述节点接触结构17接触电连接，从而无需形成转接垫(LP)，简化了所述半导体结构的制程工艺，降低了所述半导体结构的制造成本。在一示例中，所述节点接触结构17的材料为多晶硅等导电材料。
为了增大所述晶体管结构与所述电容结构18之间的接触面积，从而降低所述晶体管结构与所述电容结构18之间的接触电阻，在一示例中，所述节点接触结构17沿所述第一方向D1和所述第二方向D2的尺寸均大于由所述第一有源区10和所述第二有源区11构成的整体在所述第一方向D1和所述第二方向D2的尺寸。
在一些实施例中，多条所述字线13沿所述第一方向D1间隔排布，多条所述位线14沿所述第二方向D2间隔排布；
沿所述第一方向D1相邻的两条所述字线13之间的距离、沿所述第二方向D2相邻的两条所述位线14之间的距离、以及相邻所述存储单元之间的距离均相等。
举例来说，沿所述第一方向D1相邻的两条所述字线13之间的距离、沿所述第二方向D2相邻的两条所述位线14之间的距离、相邻所述存储单元之间的距离、相邻所述有源区之间的距离、相邻所述位线接触结构15之间的距离均相等，从而使得所述存储单元所占用的面积进一步缩小，所述存储阵列内所述存储单元的密集度进一步提高。
本具体实施方式还提供了一种半导体结构的形成方法，附图3是本公开具体实施方式中半导体结构的形成方法流程图，附图4-附图10是本公开具体实施方式在形成半导体结构的过程中主要工艺的结构示意图。本具体实施方式形成的所述半导体结构的示意图可以如图1和图2所示。如图3-图10所示，所述半导体结构的形成方法，包括如下步骤：
步骤S31，形成衬底20、以及位于所述衬底20上的有源阵列，所述有源阵列包括沿第一方向D1和第二方向D2呈阵列排布的多个有源区40，其中，所述第一方向D1和所述第二方向D2均与所述衬底20的顶面平行，且所述第一方向D1与所述第二方向D2垂直，如图4所示，其中，图4中的(a)为俯视结构示意图，图4中的(b)为图4中的(a)在a-a位置的截面示意图，图4中的(c)为图4中的(a)在b-b位置的截面示意图。
步骤S32，于所述有源区40沿所述第二方向D2的外侧形成位线14，所述位线14沿所述第一方向D1延伸、且连续与沿所述第一方向D1间隔排布的多个所述有源区40电连接， 如图7所示，其中，图7中的(a)为俯视结构示意图，图7中的(b)为图7中的(a)在a-a位置的截面示意图，图7中的(c)为图7中的(a)在b-b位置的截面示意图。
步骤S33，形成沿第二方向D2贯穿所述有源区40的栅电极12、并形成沿所述第二方向D2延伸且连续与沿所述第二方向D2间隔排布的多个所述栅电极12电连接的字线13，所述栅电极12将所述有源区40分隔为沿所述第一方向D1排布的第一有源区10和第二有源区11，如图9所示，其中，图9中的(a)为俯视结构示意图，图9中的(b)为图9中的(a)在a-a位置的截面示意图，图9中的(c)为图9中的(a)在b-b位置的截面示意图。
在一些实施例中，于所述有源区40沿所述第二方向D2的外侧形成位线14之前，还包括如下步骤：
形成位于所述有源阵列下方的位线接触阵列，所述位线接触阵列包括沿所述第一方向D1和所述第二方向D2呈阵列排布的多个位线接触结构15，所述位线接触结构15与所述有源区40接触电连接。
在一些实施例中，所述衬底20上还包括位于相邻所述有源区40之间的第一隔离层41；形成位于所述有源阵列下方的位线接触阵列的具体步骤包括：
刻蚀部分的所述有源区40和部分的所述第一隔离层41，形成沿所述第一方向D1和所述第二方向D2呈阵列排布的多个第一沟槽50，一个所述第一沟槽50与沿所述第一方向D1相邻的两个所述有源区40交叠，且一个所述有源区40与沿所述第一方向D1相邻的两个所述第一沟槽50交叠；
于所述第一沟槽50的底部形成与所述有源区40接触电连接的所述位线接触结构15，如图5所示，其中，图5中的(a)为俯视结构示意图，图5中的(b)为图5中的(a)在a-a位置的截面示意图，图5中的(c)为图5中的(a)在b-b位置的截面示意图。
具体来说，先提供初始衬底，沿所述第一方向D1和所述第二方向D2刻蚀所述初始衬底，形成沿所述第一方向D1和所述第二方向D2呈二维阵列排布的多个所述有源区40、以及位于相邻所述有源区40之间的有源区隔离槽，形成所述有源阵列，残留所述有源阵列下方的所述初始衬底作为所述衬底20。填充氧化物(例如二氧化硅)等绝缘介质材料于所述有源区隔离槽内，形成所述第一隔离层41，如图4所示。接着，采用光刻工艺刻蚀部分的所述有源区40和部分的所述第一隔离层41，形成沿所述第一方向D1和所述第二方向D2呈阵列排布的多个第一沟槽50。填充多晶硅等导电材料于所述第一沟槽50内，于所述第一沟槽50的底部形成与所述有源区40接触电连接的所述位线接触结构15，如图5所示。在刻蚀所述第一沟槽50的过程中，可以通过对准工艺使得一个所述第一沟槽50与沿所述第一方向D1相邻的两个所述有源区40交叠，且一个所述有源区40与沿所述第一方向D1相邻的两个所述第一沟槽50交叠，从而进一步提高所述半导体结构的密集度。
在一些实施例中，于所述有源区40沿所述第二方向D2的外侧形成位线14的具体步骤包括：
形成填充满所述第一沟槽50的第二隔离层60，如图6所示，其中，图6中的(a)为俯视结构示意图，图6中的(b)为图6中的(a)在a-a位置的截面示意图，图6中的(c)为图6中的(a)在b-b位置的截面示意图；
刻蚀部分的所述第二隔离层60和部分的所述第一隔离层41，形成位于所述有源区40沿所述第二方向D2的外侧、且暴露所述位线接触结构15的第二沟槽70；
于所述第二沟槽70内形成沿所述第一方向D1延伸的位线14，所述位线14连续与沿所述第一方向D1间隔排布的多个所述位线接触结构15接触电连接，如图7所示。
在一些实施例中，形成沿第二方向D2贯穿所述有源区40的栅电极12、并形成沿所述第二方向D2延伸且连续与沿所述第二方向D2间隔排布的多个所述栅电极12电连接的字线13的具体步骤包括：
形成填充满所述第二沟槽70的第三隔离层80，如图8所示，其中，图8中的(a)为 俯视结构示意图，图8中的(b)为图8中的(a)在a-a位置的截面示意图，图8中的(c)为图8中的(a)在b-b位置的截面示意图；
刻蚀所述有源区40、所述第一隔离层41和所述第三隔离层80，于所述有源区40内形成沿所述第二方向D2贯穿所述有源区40的栅极槽、并于沿所述第二方向D2相邻所述有源区40之间形成字线槽；
于所述栅极槽内形成所述栅电极12、并于所述字线槽内形成所述字线13，如图9所示。
具体来说，所述栅极槽将所述有源区分隔为沿所述第一方向D1排布的所述第一有源区10和所述第二有源区11。在形成所述栅极槽和所述字线槽之后，形成填充满所述栅极槽的所述栅电极12、以及填充满所述字线槽的所述字线13，并回刻蚀部分的所述栅电极12和部分的所述字线13，使得所述栅电极12的顶面位于所述栅极槽的顶面之下、所述字线13的顶面位于所述字线槽的顶面之下。之后，填充氧化物(例如二氧化硅)等绝缘介质材料于所述栅极槽和所述字线槽内，形成覆盖所述栅电极12和所述字线13的电容隔离层16，如图9所示。在一示例中，所述栅电极12和所述字线13的材料均为金属钨或者TiN等导电材料。
在一些实施例中，形成沿第二方向D2贯穿所述有源区的栅电极12、并形成沿所述第二方向D2延伸且连续与沿所述第二方向D2间隔排布的多个所述栅电极12电连接的字线13之后，还包括如下步骤：
形成电容结构18于所述有源区40上方，所述电容结构18电连接所述第一有源区10和所述第二有源区11，所述电容结构18在所述衬底20的顶面上的投影至少完全覆盖所述有源区40在所述衬底20的顶面上的投影。
具体来说，先于所述有源区上方形成覆盖所述第一有源区10、所述第二有源区11和所述电容隔离层16的所述节点接触结构17，再于所述节点接触结构17上方所述电容结构18。在一示例中，所述电容结构包括覆盖所述节点接触结构17表面且与所述节点接触结构17电连接的下电极层、覆盖所述下电极层表面的电介质层、以及覆盖所述电介质层表面的上电极层。
本具体实施方式一些实施例提供的半导体结构及其形成方法，存储单元包括晶体管，晶体管结构中的栅电极将有源区分隔为第一有源区和第二有源区，从而可以在晶体管结构中形成共用栅电极的两个晶体管，且同一条位线与所述存储单元内的所述第一有源区和所述第二有源区电连接，使得在与所述存储单元电连接的一条字线和一条位线开启之后，可以在所述存储单元内形成了相互并联的两个信号传输通道，不仅能够提高信号传输效率，改善半导体结构的电性能，而且还能够形成4F2(其中，F为特征尺寸)的存储阵列结构，以实现对半导体结构中存储单元密集度的提高。本具体实施方式另一些实施例中，电容结构在所述衬底的顶面上的投影至少完全覆盖所述有源区在所述衬底的顶面上的投影，从而能够增大电容结构与晶体管结构的接触面积，降低所述存储单元内部的接触电阻，从而改善所述半导体结构的电性能。而且，本具体实施方式一些实施例中的电容结构直接与节点接触结构接触电连接，无需形成转接垫(LP)，从而简化了所述半导体结构的制程工艺，降低了所述半导体结构的制造成本。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种半导体结构，包括：
    衬底；
    存储阵列，位于所述衬底上，包括沿第一方向和第二方向呈阵列排布的多个存储单元，所述存储单元包括晶体管结构，所述晶体管结构包括栅电极和有源区，所述有源区包括沿第一方向分布于所述栅电极相对两侧的第一有源区和第二有源区，其中，所述第一方向和所述第二方向均与所述衬底的顶面平行，且所述第一方向与所述第二方向垂直；
    字线，沿所述第二方向延伸，且连续与沿所述第二方向间隔排布的多个所述存储单元内的所述栅电极电连接；
    位线，沿所述第一方向延伸、且位于所述存储单元沿所述第二方向的外侧，所述位线连续与沿所述第一方向间隔排布的多个所述存储单元内的所述第一有源区和所述第二有源区电连接。
  2. 根据权利要求1所述的半导体结构，其中，所述第一有源区包括第一沟道区、以及沿第三方向分布于所述第一沟道区相对两侧的第一源极区和第一漏极区，其中，所述第三方向与所述衬底的顶面垂直；
    所述第二有源区包括第二沟道区、以及沿所述第三方向分布于所述第二沟道区相对两侧的第二源极区和第二漏极区，且所述第一沟道区和所述第二沟道区关于所述栅电极对称分布。
  3. 根据权利要求2所述的半导体结构，还包括：
    位线接触阵列，位于所述存储阵列下方，包括沿所述第一方向和所述第二方向呈阵列排布的多个位线接触结构；
    所述位线接触结构与所述晶体管结构中的所述有源区电连接，且沿所述第一方向间隔排布的多个所述位线接触结构与同一条所述位线电连接。
  4. 根据权利要求3所述的半导体结构，其中，所述位线接触阵列与所述存储阵列错开排布；一个所述位线接触结构与沿所述第一方向相邻的两个所述有源区接触电连接，且一个所述有源区与沿所述第一方向相邻的两个所述位线接触结构接触电连接。
  5. 根据权利要求4所述的半导体结构，其中，对于位于沿所述第一方向相邻的两个所述存储单元之间的一个所述位线接触结构，所述位线接触结构沿所述第一方向的一端与一个所述存储单元中的所述第一源极区电连接、所述位线接触结构沿所述第一方向的另一端与另一个所述存储单元中的所述第二源极区电连接；
    与一个所述有源区接触电连接的两个所述位线接触结构关于所述有源区的轴线对称分布，所述轴线沿所述第二方向延伸。
  6. 根据权利要求4所述的半导体结构，其中，所述位线接触结构在所述衬底的顶面上的投影的形状和尺寸与所述有源区在所述衬底的顶面上的投影的形成和尺寸均相同；
    相邻所述位线接触结构之间的距离与相邻所述有源区之间的距离相等。
  7. 根据权利要求2所述的半导体结构，其中，所述存储单元还包括：
    电容结构，位于所述晶体管结构上方，且所述电容结构电连接所述第一漏极区和所述第二漏极区，所述电容结构在所述衬底的顶面上的投影至少完全覆盖所述有源区在所述衬底的顶面上的投影。
  8. 根据权利要求7所述的半导体结构，其中，所述存储单元结构还包括：
    节点接触结构，位于所述电容结构和所述晶体管之间，所述节点接触结构的一端接触电连接所述第一漏极区和所述第二漏极区、另一端接触电连接所述电容结构。
  9. 根据权利要求1所述的半导体结构，其中，多条所述字线沿所述第一方向间隔排布，多条所述位线沿所述第二方向间隔排布；
    沿所述第一方向相邻的两条所述字线之间的距离、沿所述第二方向相邻的两条所述位线之间的距离、以及相邻所述存储单元之间的距离均相等。
  10. 一种半导体结构的形成方法，包括如下步骤：
    形成衬底、以及位于所述衬底上的有源阵列，所述有源阵列包括沿第一方向和第二方向呈阵列排布的多个有源区，其中，所述第一方向和所述第二方向均与所述衬底的顶面平行，且所述第一方向与所述第二方向垂直；
    于所述有源区沿所述第二方向的外侧形成位线，所述位线沿所述第一方向延伸、且连续与沿所述第一方向间隔排布的多个所述有源区电连接；
    形成沿第二方向贯穿所述有源区的栅电极、并形成沿所述第二方向延伸且连续与沿所述第二方向间隔排布的多个所述栅电极电连接的字线，所述栅电极将所述有源区分隔为沿所述第一方向排布的第一有源区和第二有源区。
  11. 根据权利要求10所述的半导体结构的形成方法，其中，于所述有源区沿所述第二方向的外侧形成位线之前，还包括如下步骤：
    形成位于所述有源阵列下方的位线接触阵列，所述位线接触阵列包括沿所述第一方向和所述第二方向呈阵列排布的多个位线接触结构，所述位线接触结构与所述有源区接触电连接。
  12. 根据权利要求11所述的半导体结构的形成方法，其中，所述衬底上还包括位于相邻所述有源区之间的第一隔离层；形成位于所述有源阵列下方的位线接触阵列的具体步骤包括：
    刻蚀部分的所述有源区和部分的所述第一隔离层，形成沿所述第一方向和所述第二方向呈阵列排布的多个第一沟槽，一个所述第一沟槽与沿所述第一方向相邻的两个所述有源区交叠，且一个所述有源区与沿所述第一方向相邻的两个所述第一沟槽交叠；
    于所述第一沟槽的底部形成与所述有源区接触电连接的所述位线接触结构。
  13. 根据权利要求12所述的半导体结构的形成方法，其中，于所述有源区沿所述第二方向的外侧形成位线的具体步骤包括：
    形成填充满所述第一沟槽的第二隔离层；
    刻蚀部分的所述第二隔离层和部分的所述第一隔离层，形成位于所述有源区沿所述第二方向的外侧、且暴露所述位线接触结构的第二沟槽；
    于所述第二沟槽内形成沿所述第一方向延伸的位线，所述位线连续与沿所述第一方向间隔排布的多个所述位线接触结构接触电连接。
  14. 根据权利要求13所述的半导体结构的形成方法，其中，形成沿第二方向贯穿所述有源区的栅电极、并形成沿所述第二方向延伸且连续与沿所述第二方向间隔排布的多个所述栅电极电连接的字线的具体步骤包括：
    形成填充满所述第二沟槽的第三隔离层；
    刻蚀所述有源区、所述第一隔离层和所述第三隔离层，于所述有源区内形成沿所述第二方向贯穿所述有源区的栅极槽、并于沿所述第二方向相邻所述有源区之间形成字线槽；
    于所述栅极槽内形成所述栅电极、并于所述字线槽内形成所述字线。
  15. 根据权利要求10所述的半导体结构的形成方法，其中，形成沿第二方向贯穿所述有源区的栅电极、并形成沿所述第二方向延伸且连续与沿所述第二方向间隔排布的多个所述栅电极电连接的字线之后，还包括如下步骤：
    形成电容结构于所述有源区上方，所述电容结构电连接所述第一有源区和所述第二有源区，所述电容结构在所述衬底的顶面上的投影至少完全覆盖所述有源区在所述衬底的顶面上的投影。
PCT/CN2023/070465 2022-08-19 2023-01-04 半导体结构及其形成方法 WO2024036877A1 (zh)

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CN102522407A (zh) * 2011-12-23 2012-06-27 清华大学 具有垂直晶体管的存储器阵列结构及其形成方法
CN114420644A (zh) * 2022-01-07 2022-04-29 长鑫存储技术有限公司 半导体结构及其制造方法
CN114784006A (zh) * 2022-04-26 2022-07-22 长鑫存储技术有限公司 半导体结构及其制造方法

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