WO2024055422A1 - 半导体结构及其形成方法、半导体结构的操作方法 - Google Patents

半导体结构及其形成方法、半导体结构的操作方法 Download PDF

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Publication number
WO2024055422A1
WO2024055422A1 PCT/CN2022/133651 CN2022133651W WO2024055422A1 WO 2024055422 A1 WO2024055422 A1 WO 2024055422A1 CN 2022133651 W CN2022133651 W CN 2022133651W WO 2024055422 A1 WO2024055422 A1 WO 2024055422A1
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Prior art keywords
source
substrate
drain region
semiconductor structure
active
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PCT/CN2022/133651
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English (en)
French (fr)
Inventor
安达隆郎
王晓光
肖德元
朴淳秉
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长鑫存储技术有限公司
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Priority to US18/511,808 priority Critical patent/US20240098975A1/en
Publication of WO2024055422A1 publication Critical patent/WO2024055422A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure, a method for forming the same, and an operating method of the semiconductor structure.
  • the semiconductor structure, its formation method, and the operating method of the semiconductor structure provided by some embodiments of the present disclosure are used to improve the space utilization inside the semiconductor structure, thereby helping to further reduce the size of the semiconductor structure, while simplifying the manufacturing process of the semiconductor structure and reducing the cost of the semiconductor structure. Manufacturing costs of semiconductor structures.
  • the present disclosure provides a semiconductor structure including:
  • a memory array located on the substrate, includes a plurality of memory cells arranged along a first direction and a second direction, the memory cells include active pillars, and the active pillars include a plurality of memory cells arranged at intervals along a third direction.
  • the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects the second direction, and the The third direction is perpendicular to the top surface of the substrate;
  • a word line structure located on the substrate, includes a first word line extending along the first direction and a second word line extending along the second direction, the first word line covering the first word line along the first direction.
  • a common bit line is located on the substrate and electrically connected to all the memory cells in the memory array.
  • the active pillar further includes:
  • a common source and drain region located between the first channel region and the second channel region
  • a first source and drain region located on a side of the first channel region away from the common source and drain region;
  • the second source and drain region is located on a side of the second channel region away from the common source and drain region.
  • the material of the active pillar is a semiconductor material including doped ions
  • the ion doping concentration of the common source and drain regions is respectively greater than the ion doping concentration of the first channel region and the ion doping concentration of the common source and drain regions.
  • the ion doping concentration of the second channel region is a semiconductor material including doped ions
  • the common bit line is flat-shaped, and the projection of the flat-shaped common bit line on the top surface of the substrate covers the projection of the memory array on the top surface of the substrate. projection.
  • the second source and drain region is located above the first source and drain region; the memory unit further includes:
  • a storage element is located above the second source and drain region and is electrically connected to the second source and drain region.
  • the common bit line is located above the storage array along the third direction; the storage elements include:
  • the first end is electrically connected to the second source and drain region
  • the second end is located above the first end along the third direction, and the second end is electrically connected to the common bit line.
  • the storage unit further includes:
  • a bottom contact electrode is located between the first end and the second source and drain region, the bottom contact electrode is electrically connected to the first end and the second source and drain region, and the bottom contact electrode covers the second source and drain region.
  • it also includes:
  • a common source line is located below the memory array along the third direction, and the first source and drain regions of all memory cells in the memory array are electrically connected to the common source line.
  • the common source line is flat, and the projection of the flat common source line on the top surface of the substrate covers the memory array on the top surface of the substrate. projection on.
  • the storage element is a capacitor
  • the common bit line is located below the storage array along the third direction; the capacitor includes:
  • the lower electrode layer is electrically connected to the second source and drain region
  • the upper electrode layer covers the surface of the dielectric layer.
  • a plurality of the first word lines are spaced apart along the second direction, and a plurality of the second word lines are spaced apart along the first direction.
  • the semiconductor structure further includes:
  • a sense amplifier is located outside the memory array and electrically connected to the common bit line.
  • the present disclosure also provides a method for forming a semiconductor structure, including:
  • Etching the initial substrate to form an active array and a substrate located under the active array where the active array includes a plurality of active pillars arranged along a first direction and a second direction,
  • the active pillar includes first channel regions and second channel regions spaced apart along a third direction, both the first direction and the second direction are parallel to the top surface of the substrate, and the third channel region is parallel to the top surface of the substrate.
  • One direction intersects the second direction, the third direction is perpendicular to the top surface of the substrate, and all active pillars in the active array are electrically connected to a common bit line;
  • a word line structure is formed on the substrate.
  • the word line structure includes a first word line extending along the first direction and a second word line extending along the second direction.
  • the first word line covers The first channel region of a plurality of active pillars spaced apart along the first direction, the second word line covering the plurality of active pillars spaced apart along the second direction of the second channel region.
  • forming an active array includes:
  • Second trenches arranged at intervals in the direction, a plurality of first trenches and a plurality of second trenches are defined on the initial substrate and arranged along the first direction and the second direction. A plurality of said active columns.
  • the active pillar includes a common source and drain region located between the first channel region and the second channel region, and the first channel region is located away from the common source and drain region.
  • the first source and drain region on one side of the region and the second source and drain region on the side of the second channel region away from the common source and drain region.
  • the second source and drain region The region is located above the first source and drain region; forming a word line structure on the substrate includes:
  • the third trenches are exposed along the first direction.
  • the first channel regions of the active pillars of a plurality of memory cells arranged at intervals;
  • a second gate dielectric layer covering the second channel region is formed along the fourth trench, and the second word line covering the second gate dielectric layer is formed.
  • the method further includes:
  • a storage element is formed above the second source and drain region, and the storage element is electrically connected to the second source and drain region.
  • forming a storage element above the second source and drain region includes:
  • a second end is formed above the first end to form the memory element including the first end and the second end, and the second end is used for electrical connection with a common bit line.
  • the method before forming a first end electrically connected to the second source and drain region above the second source and drain region, the method further includes:
  • a bottom contact electrode covering the second source and drain region is formed, and the bottom contact electrode covers the second source and drain region.
  • the method further includes:
  • the common bit line electrically connected to the second end of the storage element is formed above the storage element along the third direction.
  • forming the common bit line electrically connected to the second end of the storage element above the storage element along the third direction includes:
  • bit line contact plugs over the second end of each of the storage elements
  • it also includes:
  • a flat common source line is formed below the active array, the common source line is electrically connected to the first source and drain region, and the flat common source line is on the top surface of the substrate.
  • the projection on covers the projection of the active array on the top surface of the substrate.
  • forming an active array and a substrate underlying the active array includes:
  • the plurality of first trenches and the plurality of second trenches are formed on the initial substrate.
  • a plurality of active pillars arranged along the first direction and the second direction are defined on the bottom, and the remaining portion of the initial substrate below the active pillar serves as the common source line, and The remaining portion of the initial substrate below the common source line serves as the substrate.
  • the storage element is a capacitor; forming an active array and a substrate located under the active array further includes:
  • the initial substrate is etched to form a plurality of first trenches and a plurality of second trenches.
  • the plurality of first trenches and the plurality of second trenches are formed on the initial substrate.
  • a plurality of active pillars arranged along the first direction and the second direction are defined on the bottom, and the remaining portion of the initial substrate below the active pillars forms a flat common bit line.
  • the common bit line is electrically connected to the first source and drain region, and the flat common bit line is on the substrate
  • the projection on the top surface covers the projection of the active array on the top surface of the substrate.
  • the material of the active pillar is a semiconductor material including doped ions, and the ion doping concentration of the common source and drain region is greater than the ion doping concentration of the first channel region and the ion doping concentration of the second channel region.
  • the present disclosure also provides a method of operating a semiconductor structure, including the following steps:
  • the memory unit is positioned to perform a read operation or a write operation.
  • Some embodiments of the present disclosure provide a semiconductor structure, a method of forming the same, and an operating method of the semiconductor structure, by arranging first channel regions and second trenches spaced apart along the extension direction of the active pillar in the active pillar of the memory cell.
  • channel area, and a word line structure including a first word line and a second word line is provided, and each memory cell is connected to a first word line and a second word line, so that the first word line and the second word line can pass through
  • the bit line determines the position of the memory cell in the memory array. Therefore, only one common bit line is provided in the memory array, and all the memory cells in the memory array are electrically connected through the common bit line. On the one hand, the bit line is simplified.
  • the process technology increases the area of the bit line and reduces the resistance of the bit line, thereby improving the electrical performance of the semiconductor structure; on the other hand, since only one common bit line is provided, the number of sense amplifiers can be greatly reduced The number reduces the area occupied by the sensing amplifier, thereby improving the space utilization inside the semiconductor structure and helping to further reduce the size of the semiconductor structure.
  • a flat common source line can also be formed, thereby further simplifying the manufacturing process of the semiconductor structure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure in an embodiment of the present disclosure
  • FIG. 2 is a schematic circuit diagram of a semiconductor structure in an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a semiconductor structure in another embodiment of the present disclosure.
  • FIG. 4 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure
  • Figures 5 to 10 are schematic diagrams of the main process structures in the process of forming semiconductor structures according to specific embodiments of the present disclosure
  • FIG. 11 is a flowchart of a method of operating a semiconductor structure in an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of the semiconductor structure in an embodiment of the disclosure.
  • FIG. 2 is a schematic circuit diagram of the semiconductor structure in an embodiment of the disclosure. As shown in Figures 1 and 2, the semiconductor structure includes:
  • the memory array is located on the substrate 10 and includes a plurality of memory cells arranged along the first direction D1 and the second direction D2.
  • the memory cells include active pillars, and the active pillars include active pillars along the third direction.
  • the first channel region and the second channel region are spaced apart in the direction D3.
  • the first direction D1 and the second direction D2 are both parallel to the top surface of the substrate 10, and the first direction D1 Intersecting with the second direction D2, the third direction D3 is perpendicular to the top surface of the substrate 10;
  • the word line structure is located on the substrate 10 and includes a first word line 11 extending along the first direction D1 and a second word line 12 extending along the second direction D2.
  • the first word line 11 Covering the first channel region of the active pillars of a plurality of memory cells spaced along the first direction D1, the second word line 12 covers the spaced rows along the second direction D2. Distributing the second channel regions of the active pillars of a plurality of the memory cells;
  • the common bit line 19 is located on the substrate 10 and electrically connects all the memory cells in the memory array.
  • the semiconductor structure described in this specific embodiment can be, but is not limited to, DRAM, MRAM, RRAM (Resistive Random Access Memory, resistive random access memory), PCRAM (Phase-Change Random Access Memory, phase change random access memory) or FeRAM (Ferroelectric Random Access Memory, ferroelectric random access memory), etc.
  • the substrate 10 may be, but is not limited to, a silicon substrate.
  • the substrate 10 is a silicon substrate as an example for description.
  • the substrate 10 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI (Silicon On Insulator).
  • the substrate is used to form or support device structures such as the memory array thereon.
  • the top surface of the substrate 10 refers to the surface of the substrate 10 facing the memory array.
  • the plurality mentioned in this specific embodiment refers to two or more.
  • the memory array includes a plurality of memory cells arranged in a two-dimensional array along the first direction D1 and the second direction D2, and the memory cells include active pillars and memory elements.
  • the active pillar is located on the substrate 10 and extends along the third direction D3.
  • the channel structure in the active pillar includes the first channel region and the second channel region spaced apart along the third direction D3, and the first channel region and the The second channel region is electrically connected through part of the active pillars (ie, the common source and drain regions introduced later) located between them, so that the memory cell includes a first transistor and a second transistor connected in series, so The first transistor includes the first channel region, and the second transistor includes the second channel region.
  • the part of the first word line 11 covering the first channel region serves as the first gate of the first transistor, and the part of the second word line 12 covering the second channel region as the second gate of the second transistor.
  • a first turn-on signal is transmitted to the first transistor in the memory cell through the first word line 11 and simultaneously to the second transistor in the same memory cell through the second word line 12
  • the second turn-on signal is transmitted, the first transistor and the second transistor in the memory unit are turned on at the same time, so that the memory unit can be read and written.
  • the memory cells in the memory array are selected through the first word line 11 and the second word line 12.
  • bit line 19 only one common bit line 19 can be formed, and there is no need for Providing one bit line for each row of memory cells not only reduces the number of bit lines and the difficulty of the bit line manufacturing process, but also reduces the number of sense amplifiers used to amplify bit line signals in peripheral circuits. , thereby saving space inside the semiconductor structure, improving the integration level of the semiconductor structure, and helping to further reduce the size of the semiconductor structure.
  • the storage unit further includes:
  • Common source and drain region 13 is located between the first channel region and the second channel region;
  • the first source and drain region 14 is located on the side of the first channel region away from the common source and drain region 13;
  • the second source and drain region 15 is located on the side of the second channel region away from the common source and drain region 13 .
  • the material of the active pillar is a semiconductor material including doped ions
  • the ion doping concentration of the common source and drain regions 13 is respectively greater than the ion doping concentration of the first channel region and The ion doping concentration of the second channel region.
  • the active pillar may be a silicon pillar extending along the third direction D3, and the material of the silicon pillar is silicon material including the doped ions.
  • the doping ions may be N-type ions or P-type ions.
  • the silicon pillar includes the first source and drain region 14, the first channel region, the common source and drain region 13, the second channel region and the the second source-drain region 15.
  • the ion doping concentration of the common source and drain region 13 is greater than the ion doping concentration of the channel structure, thereby enhancing the conductivity of the common source and drain region 13 .
  • the ion doping concentration of the common source and drain region 13 may be equal to the ion doping concentration of the first source and drain region 14 and the ion doping concentration of the second source and drain region 15, To simplify the ion doping operation of the silicon pillar.
  • the length of the common source and drain region 13 along the third direction D3 should not be too short, otherwise there will be a gap between the first word line 11 and the second word line 12 that are electrically connected to the same memory cell. It has a strong parasitic capacitance effect, causing leakage; the length of the common source and drain region 13 along the third direction D3 should not be too long, otherwise the size of the memory cell will be too large. In one example, the length of the common source and drain region 13 along the third direction D3 is 10 nm to 30 nm, but is not limited thereto.
  • the material of the active pillar may also be an oxide semiconductor material.
  • the oxide semiconductor material is In 2 O 3 (indium oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), IZTO (indium tin zinc oxide), ZnON (Zinc Nitride Oxide) or a combination of two or more.
  • the material of the active region is IGZO.
  • the common bit line 19 is in the shape of a flat plate, and the projection of the flat common bit line 19 on the top surface of the substrate 10 covers the surface of the memory array on the substrate 10 The projection on the top surface.
  • Using the flat-shaped common bit line 19 not only simplifies the manufacturing process of the common bit line 19, but also eliminates the need to align the common bit line 19 with each memory cell, thereby further simplifying the semiconductor structure. manufacturing process.
  • the area of the common bit line 19 can be increased, thereby reducing the resistance of the common bit line 19 and improving the electrical performance of the semiconductor structure.
  • the memory unit further includes:
  • a storage element is located above the second source and drain region 15 and is electrically connected to the second source and drain region.
  • the common bit line 19 is located above the storage array along the third direction D3; the storage elements include:
  • the first end is electrically connected to the second source and drain region 15;
  • the second end is located above the first end along the third direction D3, and is electrically connected to the common bit line 19 .
  • the storage unit further includes:
  • the bottom contact electrode 16 is located between the first end and the second source and drain region 15.
  • the bottom contact electrode 16 is electrically connected to the first end and the second source and drain region 15, and the The bottom contact electrode 16 covers the second source and drain region 15 .
  • the semiconductor structure further includes:
  • the common source line 20 is located below the memory array along the third direction D3, and the first source and drain regions 14 of all the memory cells in the memory array are electrically connected to the common source line 20 .
  • the common source line 20 is flat, and the projection of the flat common source line 20 on the top surface of the substrate 10 covers the memory array on the substrate. The projection on the top surface of 10.
  • the storage element including the first end and the second end may be a storage element (eg, a magnetic tunnel junction) in MRAM, a storage element in RRAM, a storage element in PCRAM, or a storage element in FeRAM. storage element.
  • a storage element eg, a magnetic tunnel junction
  • the following description takes the semiconductor structure as an MRAM and the storage element in the memory unit as a magnetic tunnel junction element 17 as an example.
  • the magnetic tunnel junction element 17 includes the fixed layer (ie, the first end), the insulating layer and the free layer (ie, the second end) arranged in sequence along the third direction D3.
  • the fixed layer is electrically connected to the second source and drain region 15 through the bottom contact electrode 16 .
  • a bit line contact plug 18 is also provided above the magnetic tunnel junction element 17 along the third direction D3.
  • the bit line contact plug 18 extends along the third direction D3, and one end of the bit line contact plug 18 is electrically connected to the free layer contact in the magnetic tunnel junction element 17, and the other end is electrically connected to the free layer contact in the magnetic tunnel junction element 17.
  • the common bit line 19 is electrically connected.
  • the semiconductor structure also includes the common source line 20 underneath the memory array.
  • the flat-shaped common source line 20 not only simplifies the manufacturing process of the common source line 20, but also eliminates the need to align the common source line 20 with each memory cell, thus simplifying the process of manufacturing the common source line 20. Manufacturing processes for semiconductor structures.
  • the flat-shaped common source line 20 can also increase the area of the common source line 20 , thereby reducing the resistance of the common source line 20 .
  • planar common source line 20 and the planar common bit line 19 may have the same shape and size, so the same mask may be used to form the common source line 20 and all the common bit lines 19 .
  • the common bit lines 19 are thus further reduced in number of masks and the manufacturing cost of the semiconductor structure is reduced.
  • FIG. 3 is a schematic structural diagram of a semiconductor structure in another embodiment of the present disclosure.
  • the storage element is a capacitor 21, and the common bit line is located below the storage array along the third direction D3; the capacitor 21 includes:
  • the lower electrode layer is electrically connected to the second source and drain region 15;
  • the upper electrode layer covers the surface of the dielectric layer.
  • the semiconductor structure is a DRAM and the storage element in the memory unit is the capacitor 21 .
  • the flat common bit line 19 is located below the memory array along the third direction D3 and is connected with the first source in all the memory cells in the memory array.
  • the drain region 14 contacts are electrically connected.
  • the capacitor 21 in the memory unit is located above the transistor along the third direction D3, and is electrically connected to the second source-drain region 15 in the transistor.
  • a common electrode 22 is also included in the semiconductor structure.
  • the common electrode 22 is located above the memory array along the third direction D3 and is electrically connected to the upper electrode layers of all capacitors in the memory array.
  • the upper electrode layers of the capacitors 21 of all the memory cells in the memory array are integrated into the above-mentioned common electrode 22 .
  • a plurality of first word lines 11 are arranged at intervals along the second direction D2, and a plurality of second word lines 12 are arranged at intervals along the first direction D1.
  • the distance between adjacent first word lines 11 is equal to the distance between adjacent second word lines 12 , and the shape and size of the first word line 11 are the same as the distance between adjacent second word lines 12 .
  • the two word lines 12 have the same shape and size.
  • the same mask plate can be used to form multiple first word lines 11 and multiple second word lines 12, thereby further reducing the number of mask plates and reducing the manufacturing cost of the semiconductor structure.
  • the first channel region and the second channel region are made of the same material, and the first channel region and the second channel region are symmetrically distributed about the common source and drain region 13,
  • the first channel region and the second channel region are symmetrically distributed about an axis passing through the center of the common source and drain region 13 and extending along the first direction D1, so that the first channel region
  • the turn-on voltage of the region is the same as the turn-on voltage of the second channel region, which can not only simplify the manufacturing process of the semiconductor structure, but also simplify the control operation of the semiconductor structure.
  • the semiconductor structure further includes:
  • a sense amplifier is located outside the memory array and electrically connected to the common bit line 19 .
  • only one sense amplifier electrically connected to the common bit line 19 can be provided, thereby greatly saving the internal space of the semiconductor structure, thereby helping to further reduce the size of the semiconductor structure. .
  • FIG. 4 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure.
  • FIGS. 5 to 10 are a diagram of a method for forming a semiconductor structure in a specific embodiment of the present disclosure. Schematic diagram of the main process structure in the process. Schematic diagrams of the semiconductor structure formed in this specific embodiment can be seen in Figures 1-3. As shown in Figures 1-10, the method for forming the semiconductor structure includes the following steps:
  • Step S41 provide an initial substrate
  • Step S42 Etch the initial substrate to form an active array and the substrate 10 located under the active array.
  • the active array includes a plurality of arrays arranged along the first direction D1 and the second direction D2.
  • the active pillar 50 includes a first channel region 51 and a second channel region 52 spaced apart along the third direction D3. As shown in FIG. 5, the first direction D1 and the The second directions D2 are both parallel to the top surface of the substrate 10 , and the first direction D1 intersects the second direction D2 , and the third direction D3 is perpendicular to the top surface of the substrate 10 , so All the active pillars 50 in the active array are electrically connected to a common bit line 19;
  • Step S43 Form a word line structure on the substrate 10.
  • the word line structure includes a first word line 11 extending along the first direction D1 and a second word line 12 extending along the second direction D2.
  • the first word line 11 covers the first channel region of a plurality of active pillars 50 spaced along the first direction D1
  • the second word line 12 covers the first channel region along the second direction D1.
  • the second channel regions of the plurality of active pillars 50 are spaced apart in the direction D2, as shown in FIG. 10 .
  • forming an active array includes:
  • the initial substrate is etched to form a plurality of first trenches extending along the first direction D1 and spaced along the second direction D2, and a plurality of first trenches extending along the second direction D2 and arranged along the second direction D2.
  • Second trenches are spaced apart in the first direction D1, and a plurality of the first trenches and a plurality of the second trenches define on the original substrate along the first direction D1 and the A plurality of active pillars 50 are arranged in the second direction D2, as shown in FIG. 5 .
  • the active pillar 50 includes a common source and drain region 13 located between the first channel region 51 and the second channel region 52 , and a common source and drain region 13 located away from the first channel region 51 .
  • the first source and drain region 14 on the side of the common source and drain region 13 and the second source and drain region 15 on the side of the second channel region 52 away from the common source and drain region 13 are located along the first In one direction D1, the second source and drain region 15 is located above the first source and drain region 14; the steps of forming a word line structure on the substrate 10 include:
  • the first isolation layer is etched back to form a plurality of third trenches extending along the first direction D1 and spaced apart along the second direction D2.
  • the third trenches are exposed along the first direction D2.
  • the first channel regions of the active pillars of a plurality of memory cells spaced apart in one direction D1;
  • the second isolation layer is etched back to form a plurality of fourth trenches extending along the second direction D2 and arranged at intervals along the first direction D1.
  • the fourth trenches are exposed along the first direction D1.
  • the second channel regions 52 of the active pillars of a plurality of memory cells arranged at intervals in the two directions D2;
  • a third isolation layer covering the second word line 12 and filling the fourth trench is formed.
  • the following steps are also included:
  • a storage element is formed above the second source and drain region 15 , and the storage element is electrically connected to the second source and drain region 15 .
  • the step of forming a storage element above the second source and drain region 15 includes:
  • a second end is formed above the first end to form the memory element including the first end and the second end, and the second end is used for electrical connection with the common bit line 19 (see FIG. 10 ).
  • the method before forming a first end electrically connected to the second source and drain region 15 above the second source and drain region 15, the method further includes:
  • a bottom contact electrode 16 covering the second source and drain region 15 is formed, as shown in FIG. 8 , and the bottom contact electrode 16 covers the second source and drain region 15 .
  • the common bit line 19 electrically connected to the second end of the storage element is formed above the storage element along the third direction D3.
  • the step of forming the common bit line 19 electrically connected to the second end of the storage element above the storage element along the third direction D3 includes:
  • the common bit line 19 is formed in a flat shape and is continuously electrically connected to all the bit line plugs 18 , and the projection of the flat common bit line 19 on the top surface of the substrate 10 covers The projection of the active array on the top surface of the substrate 10 is shown in FIG. 10 .
  • the step of forming the memory array, word line structure and common bit line 19 on the substrate 10 further includes:
  • a flat common source line 20 is formed below the active array.
  • the common source line 20 is electrically connected to the first source and drain region 14 , and the flat common source line 20 is on the substrate.
  • the projection on the top surface of the base 10 covers the projection of the active array on the top surface of the substrate 10 .
  • forming an active array on, and on the substrate 10 underlying, the active array includes:
  • Etching the initial substrate, the plurality of first trenches, and the plurality of second trenches, the plurality of first trenches and the plurality of second trenches on the initial substrate A plurality of active pillars 50 arranged along the first direction D2 and the second direction D2 are defined, and the remaining portion of the initial substrate below the active pillars serves as the common source line. 20. And the remaining portion of the initial substrate below the common source line 20 is used as the substrate 10 .
  • the following description takes the semiconductor structure as MRAM and the storage element as a magnetic tunnel junction as an example.
  • the initial substrate may be etched using a photolithography process to form a plurality of first trenches extending along the first direction D1 and spaced along the second direction D2, and a plurality of first trenches extending along the second direction D2 and arranged along the second direction D2.
  • Second trenches are spaced in the first direction D1, and a plurality of first isolation trenches and a plurality of second isolation trenches define lines along the first direction D1 and the plurality of second isolation trenches on the original substrate.
  • a plurality of the active pillars 50 arranged in an array in the second direction D2 form an active array, as shown in FIG. 5 .
  • the first trench and the second trench have substantially the same depth along the third direction D3, and neither of them penetrates the original substrate. Therefore, the depths of the first trench and the first trench remain in the active array and the first trench.
  • the portion of the initial substrate below the trench and the second trench can be used as the common source line 20 after doping, and the remaining initial substrate below the common source line 20 can be used as the substrate. 10, as shown in Figure 5.
  • a first isolation material such as spin-on dielectric material (SOD) can be filled in the first trench and the second trench to form a structure that fills the first trench. and the first isolation layer of the second trench.
  • part of the first isolation layer is removed through an etch-back process to form a plurality of third trenches extending along the first direction D1 and spaced apart along the second direction D2.
  • the third trench exposes all of the first channel region 51 in the active pillar 50 , and the remaining isolation layer covers and fills the common source line 20 and the first source-drain region 14 part of the first trench and part of the second trench.
  • the width of the third trench along the second direction D2 is greater than the width of the first trench along the second direction D2, so that the third trench in the active pillar 50 One channel area 51 is completely exposed.
  • the remaining first isolation layer can be used to isolate the adjacent third trench, thereby simplifying the subsequent process of forming the first word line.
  • a deposition process or an in-situ growth process may be used to form a first gate dielectric material layer covering the exposed active pillar 50 .
  • the first gate dielectric material layer is made of an oxide material (such as silicon dioxide).
  • a selective atomic layer deposition process may be used to deposit a first word line material such as metal tungsten or TiN to form a first word line material layer.
  • part of the first word line material layer and part of the first gate dielectric material layer are removed through an etching back process, leaving only the first gate dielectric material layer located on the first channel region 51.
  • the top surface of the first word line material layer is located below the common source and drain region 13 to expose the common source and drain region 13, the second channel region 52 and the In the second source and drain region 15, as shown in FIG. 6, the remaining first gate dielectric material layer covering the first channel region 51 serves as the first gate dielectric layer, and the remaining first gate dielectric material layer covers the first channel region 51.
  • the first word line material layer serves as the first word line 11 .
  • the portion of the first word line 11 covering the surface of the first gate dielectric layer serves as the first gate electrode of the first transistor.
  • a second isolation layer covering the first word line 11 and filling the third trench is formed.
  • a portion of the second isolation layer is etched back to form a plurality of fourth trenches extending along the second direction D2 and spaced apart along the first direction D1.
  • the fourth trenches expose the second channel region 52.
  • the width of the fourth trench along the first direction D1 is greater than the width of the second trench along the first direction D1 , so that the third trench in the active pillar 50
  • the second channel area 52 is completely exposed.
  • a deposition process or an in-situ growth process may be used to form a second gate dielectric material layer covering the exposed active pillar 50 .
  • the second gate dielectric material layer is made of an oxide material (such as silicon dioxide).
  • a selective atomic layer deposition process may be used to deposit a second word line material such as metal tungsten or TiN to form the second word line material layer.
  • a second word line material such as metal tungsten or TiN
  • part of the second word line material layer and part of the second gate dielectric material layer are removed through an etching back process, leaving only the second gate dielectric material layer located on the second channel region 52.
  • the top surface of the second word line material layer is located below the second source and drain region 15 to expose the second source and drain region 15 in the active pillar 50.
  • the remaining The second gate dielectric material layer covering the second channel region 52 serves as the second gate dielectric layer
  • the remaining second word line material layer serves as the second word line 12 .
  • the portion of the second word line 12 covering the surface of the second gate dielectric layer serves as the second gate of the second transistor. Finally, a third isolation layer covering the second word line 12 and filling the fourth trench is formed.
  • the method of forming the word line structure is not limited to this.
  • a deposition process or an in-situ growth process may be used to form a gate dielectric layer covering the exposed active pillars 50; forming a gate dielectric layer that fills the first trench and the second trench.
  • the first isolation layer is etched back to form a third trench; a first word line material layer is formed in the third trench, and the first word line material layer is etched back to obtain a third trench.
  • the gate dielectric layer on the top surface of the active pillar 50 needs to be removed first.
  • the bottom contact electrode 16 , the magnetic tunnel junction element 17 located on the bottom contact electrode 16 , and the magnetic tunnel junction element 17 are formed above the second source and drain region 15 of the active pillar 50
  • the bit lines on 17 contact plug 18 as shown in Figures 8 and 9.
  • conductive materials such as metal tungsten or TiN are deposited above the bit line contact plugs 18 to form the flat common bit line 19, and the common bit line 19 is connected to all the bit line contact plugs at the same time. 18 contacts for electrical connections.
  • the storage element is a capacitor 21; the step of forming an active array and the substrate 10 located under the active array further includes:
  • the plurality of first trenches and the plurality of second trenches are formed on the initial substrate.
  • a plurality of active pillars arranged along the first direction and the second direction are defined on the bottom, and the remaining portion of the initial substrate below the active pillars forms a flat common bit line. 19.
  • the common bit line 19 is electrically connected to the first source and drain region 14.
  • the projection of the flat common bit line 19 on the top surface of the substrate 10 covers the active array on the substrate.
  • a photolithography process may be used to etch the initial substrate to form a plurality of first trenches extending along the first direction D1 and spaced apart along the second direction D2, and a plurality of first trenches extending along the second direction D2.
  • D2 extends and is arranged at intervals along the first direction D1.
  • a plurality of the first trenches and a plurality of the second trenches define lines on the original substrate along the first direction.
  • a plurality of the active pillars 50 arranged in an array in the direction D1 and the second direction D2 form an active array, as shown in FIG. 5 .
  • the first trench and the second trench have substantially the same depth along the third direction D3, and neither penetrates the initial substrate. Therefore, part of the initial trench remaining under the active array
  • the substrate serves as the common bit line 19
  • the initial substrate remaining under the common bit line 19 serves as the substrate 10 , as shown in FIG. 3 .
  • the first trench and the second trench have the same depth along the third direction D3.
  • the manufacturing process of the semiconductor structure can be simplified and the manufacturing difficulty of the semiconductor structure can be reduced. ; On the other hand, it can also ensure the consistency of performance in all directions of the active pillar to improve the electrical performance of the semiconductor structure.
  • the capacitor 21 is formed on the second source-drain region 15 .
  • the capacitor 21 includes a lower electrode layer electrically connected to the second source-drain region 15 , a dielectric layer covering the surface of the lower electrode layer, and an upper electrode layer covering the surface of the dielectric layer.
  • a flat common electrode 22 is formed above the capacitor 21 , and the common electrode 22 is electrically connected to the upper electrode layers in all the capacitors.
  • the material of the active pillar 50 is a silicon material including doped ions, and the ion doping concentration of the common source and drain regions 13 is greater than the ion doping concentration of the first channel region 51 and the ion doping concentration of the second channel region 52 .
  • the material of the active pillar 50 may also be an oxide semiconductor material.
  • the oxide semiconductor material is In 2 O 3 (indium oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), IZTO (indium tin zinc oxide), ZnON (Zinc Nitride Oxide) or a combination of two or more.
  • the material of the active region is IGZO.
  • This specific embodiment also provides a method of operating a semiconductor structure.
  • 11 is a flowchart of a method of operating a semiconductor structure in an embodiment of the present disclosure.
  • the semiconductor structures shown in FIGS. 1 to 3 can all be operated using the operating method of the semiconductor structure provided in this embodiment. As shown in Figures 1-2 and 11, the operating method of the semiconductor structure includes the following steps:
  • Step S111 provide a semiconductor structure; the semiconductor structure is as shown in Figures 1 and 2, or the semiconductor structure is as shown in Figure 3;
  • Step S112 applying a first enable signal to one of the first word lines 11 and a second enable signal to one of the second word lines 12, and connecting one of the first word lines 11 and one of the first word lines 11 through the common bit line 19
  • the memory cell positioned by one of the second word lines 12 performs a read operation or a write operation.
  • the following description takes the semiconductor structure as an MRAM as shown in FIGS. 1 and 2 as an example.
  • a first turn-on signal is applied to one of the first word lines 11 and a second turn-on signal is applied to one of the second word lines 12
  • a first turn-off signal is applied to the other first word lines 11
  • a second off signal is applied to the other second word lines 12, thereby being positioned to be connected to the first word line 11 that applies the first on signal, and at the same time connected to the first word line 11 that applies the second on signal.
  • the second word line 12 connects the memory cells, and performs a read operation or a write operation on the located memory cells.
  • Some embodiments of this specific embodiment provide a semiconductor structure, a method of forming the same, and an operating method of the semiconductor structure, by arranging first channel regions and a third channel region spaced apart along the extension direction of the active column in the active column of the memory cell.
  • a two-channel region is provided with a word line structure including a first word line and a second word line, and each memory cell is connected to a first word line and a second word line, so that the first word line and the second word line can pass through the first word line and the second word line.
  • the two word lines determine the location of the memory cells in the memory array. Therefore, only one common bit line is provided in the memory array, and all the memory cells in the memory array are electrically connected through the common bit line.
  • bit line increases the contact area between the bit line and the memory cell, thereby improving the electrical performance of the semiconductor structure; on the other hand, since only one common bit line is provided, the number of sense amplifiers can be greatly reduced , reducing the area occupied by the sensing amplifier, thereby improving the space utilization inside the semiconductor structure and helping to further reduce the size of the semiconductor structure.
  • a flat common source line may also be formed, thereby further simplifying the manufacturing process of the semiconductor structure.

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Abstract

本公开涉及半导体结构及其形成方法、半导体结构的操作方法。半导体结构包括：衬底；存储阵列，包括沿第一方向和第二方向排布的多个存储单元，存储单元包括有源柱，有源柱包括沿第三方向间隔排布的第一沟道区和第二沟道区；字线结构，包括沿第一方向延伸的第一字线和沿第二方向延伸的第二字线，第一字线覆盖沿第一方向间隔排布的多个存储单元的有源柱的第一沟道区，第二字线覆盖沿第二方向间隔排布的多个存储单元的有源柱的第二沟道区；公共位线，电连接存储阵列中全部存储单元。本公开简化了位线的制程工艺，改善了半导体结构的电性能，且有助于进一步缩小半导体结构的尺寸。

Description

半导体结构及其形成方法、半导体结构的操作方法
相关申请引用说明
本申请要求于2022年09月15日递交的中国专利申请号202211120748.6、申请名为“半导体结构及其形成方法、半导体结构的操作方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法、半导体结构的操作方法。
背景技术
在DRAM(Dynamic Random Access Memory，动态随机存储器)、MRAM(Magnetoresistive Random Access Memory，磁性随机存储器)等半导体结构中，需要依靠一条字线和一条位线来定位一个存储单元，因此，需要在半导体结构中设置排布密集的多条所述字线和多条所述位线。随着半导体结构尺寸的不断微缩，用于形成位线的空间不断缩小，在不断微缩的空间内形成多条位线的工艺难度不断增大。另外，在半导体结构中，通常两条位线共享一个感测放大器(Sense Amplifier，SA)，密集排布的多条位线需要设置多个感测放大器，从而增大了感测放大器的面积，制约了半导体结构尺寸的进一步缩小。
因此，如何提高半导体结构内部的空间利用率，减小感测放大器的占用面积，同时简化半导体结构的制造工艺，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体结构及其形成方法、半导体结构的操作方法，用于提高半导体结构内部的空间利用率，从而有助于半导体结构的进一步缩小，同时简化半导体结构的制造工艺，降低半导体结构的制造成本。
根据一些实施例，本公开提供了一种半导体结构，包括：
衬底；
存储阵列，位于所述衬底上，包括沿第一方向和第二方向排布的多个存储单元，所述存储单元包括有源柱，所述有源柱包括沿第三方向间隔排布的第一沟道区和第二沟道区，所述第一方向和所述第二方向均与所述衬底的顶面平行，且所述第一方向与所述第二方向相交，所述第三方向与所述衬底的顶面垂直；
字线结构，位于所述衬底上，包括沿所述第一方向延伸的第一字线和沿所述第二方向延伸的第二字线，所述第一字线覆盖沿所述第一方向间隔排布的多个所述存储单元的所述有源柱的所述第一沟道区，所述第二字线覆盖沿所述第二方向间隔排布的多个所述存储单元的所述有源柱的所述第二沟道区；
公共位线，位于所述衬底上，且电连接所述存储阵列中全部所述存储单元。
在一些实施例中，所述有源柱还包括：
公共源漏区，位于所述第一沟道区和所述第二沟道区之间；
第一源漏区，位于所述第一沟道区的远离所述公共源漏区的一侧；
第二源漏区，位于所述第二沟道区的远离所述公共源漏区的一侧。
在一些实施例中，所述有源柱的材料为包括掺杂离子的半导体材料，且所述公共源漏区的离子掺杂浓度分别大于所述第一沟道区的离子掺杂浓度和所述第二沟道区的离子掺杂浓度。
在一些实施例中，所述公共位线呈平板状，且平板状的所述公共位线在所述衬底的顶面上的投影覆盖所述存储阵列在所述衬底的顶面上的投影。
在一些实施例中，在沿所述第三方向上，所述第二源漏区位于所述第一源漏区上方；所述存储单元还包括：
存储元件，所述存储元件位于第二源漏区上方、且电连接所述第二源漏区。
在一些实施例中，所述公共位线沿所述第三方向位于所述存储阵列上方；所述存储元 件包括：
第一端，电连接所述第二源漏区；
第二端，沿所述第三方向位于所述第一端上方，且所述第二端电连接所述公共位线。
在一些实施例中，所述存储单元还包括：
底部接触电极，位于所述第一端与所述第二源漏区之间，所述底部接触电极接触电连接所述第一端和所述第二源漏区，且所述底部接触电极覆盖所述第二源漏区。
在一些实施例中，还包括：
公共源极线，沿所述第三方向位于所述存储阵列下方，且所述存储阵列中全部所述存储单元的所述第一源漏区均电连接所述公共源极线。
在一些实施例中，所述公共源极线呈平板状，且平板状的所述公共源极线在所述衬底的顶面上的投影覆盖所述存储阵列在所述衬底的顶面上的投影。
在一些实施例中，所述存储元件为电容器，所述公共位线沿所述第三方向位于所述存储阵列下方；所述电容器包括：
下电极层，电连接所述第二源漏区；
电介质层，覆盖于所述下电极层表面；
上电极层，覆盖于所述电介质层表面。
在一些实施例中，多条所述第一字线沿所述第二方向间隔排布，且多条所述第二字线沿所述第一方向间隔排布。
在一些实施例中，所述半导体结构还包括：
感测放大器，位于所述存储阵列的外部，且电连接所述公共位线。
根据另一些实施例，本公开还提供了一种半导体结构的形成方法，包括：
提供初始衬底；
刻蚀所述初始衬底，形成有源阵列、以及位于所述有源阵列下方的衬底，所述有源阵列包括沿第一方向和第二方向排布的多个有源柱，所述有源柱包括沿第三方向间隔排布的第一沟道区和第二沟道区，所述第一方向和所述第二方向均与所述衬底的顶面平行，且所述第一方向与所述第二方向相交，所述第三方向与所述衬底的顶面垂直，所述有源阵列中全部的所述有源柱均与一个公共位线电连接；
形成字线结构于所述衬底上，所述字线结构包括沿所述第一方向延伸的第一字线和沿所述第二方向延伸的第二字线，所述第一字线覆盖沿所述第一方向间隔排布的多个所述有源柱的所述第一沟道区，所述第二字线覆盖沿所述第二方向间隔排布的多个所述有源柱的所述第二沟道区。
在一些实施例中，形成有源阵列的步骤包括：
刻蚀所述初始衬底，形成多条沿所述第一方向延伸且沿所述第二方向间隔排布的第一沟槽、以及多条沿所述第二方向延伸且沿所述第一方向间隔排布的第二沟槽，多个所述第一沟槽和多个所述第二沟槽在所述初始衬底上定义出沿所述第一方向和所述第二方向排布的多个所述有源柱。
在一些实施例中，所述有源柱包括位于所述第一沟道区和所述第二沟道区之间的公共源漏区、位于所述第一沟道区远离所述公共源漏区一侧的第一源漏区、以及位于所述第二沟道区远离所述公共源漏区一侧的第二源漏区，在沿所述第一方向上，所述第二源漏区位于所述第一源漏区上方；形成字线结构于所述衬底上包括：
填充第一隔离材料于所述第一沟槽和所述第二沟槽内，形成填充满所述第一沟槽和所述第二沟槽的第一隔离层；
回刻蚀所述第一隔离层，形成多条沿所述第一方向延伸、且沿所述第二方向间隔排布的第三沟槽，所述第三沟槽暴露沿所述第一方向间隔排布的多个所述存储单元的所述有源柱的所述第一沟道区；
沿所述第三沟槽形成包覆所述第一沟道区的第一栅介质层、并形成覆盖所述第一栅介 质层的所述第一字线；
形成覆盖所述第一字线且填充满所述第三沟槽的第二隔离层；
回刻蚀所述第二隔离层，形成多条沿所述第二方向延伸、且沿所述第一方向间隔排布的第四沟槽，所述第四沟槽暴露沿所述第二方向间隔排布的多个所述存储单元的所述有源柱的所述第二沟道区；
沿所述第四沟槽形成包覆所述第二沟道区的第二栅介质层、并形成覆盖所述第二栅介质层的所述第二字线。
在一些实施例中，形成字线结构于所述衬底上之后，还包括：
于所述第二源漏区上方形成存储元件，所述存储元件电连接所述第二源漏区。
在一些实施例中，于所述第二源漏区上方形成存储元件包括：
于所述第二源漏区上方形成与所述第二源漏区电连接的第一端；
于所述第一端上方形成第二端，以形成包括所述第一端和所述第二端的所述存储元件，所述第二端用于与公共位线电连接。
在一些实施例中，于所述第二源漏区上方形成与所述第二源漏区电连接的第一端之前，还包括：
形成覆盖所述第二源漏区的底部接触电极，且所述底部接触电极覆盖所述第二源漏区。
在一些实施例中，于所述第二源漏区上方形成存储元件之后，还包括：
于所述存储元件沿所述第三方向的上方形成电连接所述存储元件的所述第二端的所述公共位线。
在一些实施例中，于所述存储元件沿所述第三方向的上方形成电连接所述存储元件的所述第二端的所述公共位线包括：
于每个所述存储元件的所述第二端上方形成位线接触插塞；
形成连续与全部所述位线插塞接触电连接、且呈平板状的所述公共位线，且平板状的所述公共位线在所述衬底的顶面上的投影覆盖所述有源阵列在所述衬底的顶面上的投影。
在一些实施例中，还包括：
形成平板状的公共源极线于所述有源阵列下方，所述公共源极线电连接所述第一源漏区，且平板状的所述公共源极线在所述衬底的顶面上的投影覆盖所述有源阵列在所述衬底的顶面上的投影。
在一些实施例中，形成有源阵列、以及位于所述有源阵列下方的衬底包括：
刻蚀所述初始衬底，形成多条所述第一沟槽、以及多条所述第二沟槽，多条所述第一沟槽和多条所述第二沟槽在所述初始衬底上定义出沿所述第一方向和所述第二方向排布的多个所述有源柱，所述有源柱下方残留的部分所述初始衬底作为所述公共源极线、且所述公共源极线下方残留的部分所述初始衬底作为所述衬底。
在一些实施例中，所述存储元件为电容器；形成有源阵列、以及位于所述有源阵列下方的衬底还包括：
刻蚀所述初始衬底，形成多条所述第一沟槽、以及多条所述第二沟槽，多个所述第一沟槽和多个所述第二沟槽在所述初始衬底上定义出沿所述第一方向和所述第二方向排布的多个所述有源柱，所述有源柱下方残留的部分所述初始衬底形成平板状的所述公共位线、且所述公共位线下方残留的部分所述初始衬底作为所述衬底，所述公共位线电连接所述第一源漏区，平板状的所述公共位线在所述衬底的顶面上的投影覆盖所述有源阵列在所述衬底的顶面上的投影。
在一些实施例中，所述有源柱的材料为包括掺杂离子的半导体材料，且所述公共源漏区的离子掺杂浓度大于所述第一沟道区的离子掺杂浓度和所述第二沟道区的离子掺杂浓度。
根据又一些实施例，本公开还提供了一种半导体结构的操作方法，包括如下步骤：
提供如上所述的半导体结构；
向一条所述第一字线施加第一开启信号、向一条所述第二字线施加第二开启信号，通过所述公共位线对一条所述第一字线和一条所述第二字线定位的所述存储单元进行读取操作或写入操作。
本公开一些实施例提供的半导体结构及其形成方法、半导体结构的操作方法，通过在存储单元的有源柱中设置沿有源柱的延伸方向间隔排布的第一沟道区和第二沟道区，并设置包括第一字线和第二字线的字线结构，且每个存储单元均连接一条第一字线和一条第二字线，使得能够通过第一字线和第二字线确定存储阵列中存储单元的位置，因而，在所述存储阵列中仅设置一条公共位线，通过所述公共位线电连接所述存储阵列中全部的存储单元，一方面，简化了位线的制程工艺，且增大了位线的面积，减小了位线的电阻，从而改善了半导体结构的电性能；另一方面，由于仅设置一条公共位线，因而可以大幅度减少感测放大器的数量，减少感测放大器占用面积，从而提高了半导体结构内部的空间利用率，有助于进一步缩小半导体结构的尺寸。本公开另一些实施例中，还可以形成平板状的公共源极线，从而进一步简化半导体结构的制程工艺。
附图说明
附图1是本公开具体实施方式一实施例中半导体结构的结构示意图；
附图2是本公开具体实施方式一实施例中半导体结构的电路示意图；
附图3是本公开具体实施方式另一实施例中半导体结构的结构示意图；
附图4是本公开具体实施方式中半导体结构的形成方法流程图；
附图5-附图10是本公开具体实施方式在形成半导体结构的过程中主要的工艺结构示意图；
附图11是本公开具体实施方式中半导体结构的操作方法流程图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其形成方法、半导体结构的操作方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构，附图1是本公开具体实施方式一实施例中半导体结构的结构示意图，附图2是本公开具体实施方式一实施例中半导体结构的电路示意图。如图1和图2所示，所述半导体结构，包括：
衬底10；
存储阵列，位于所述衬底10上，包括沿第一方向D1和第二方向D2排布的多个存储单元，所述存储单元包括有源柱，所述有源柱包括沿所述第三方向D3间隔排布的第一沟道区和第二沟道区，所述第一方向D1和所述第二方向D2均与所述衬底10的顶面平行，且所述第一方向D1与所述第二方向D2相交，所述第三方向D3与所述衬底10的顶面垂直；
字线结构，位于所述衬底10上，包括沿所述第一方向D1延伸的第一字线11和沿所述第二方向D2延伸的第二字线12，所述第一字线11覆盖沿所述第一方向D1间隔排布的多个所述存储单元的所述有源柱的所述第一沟道区，所述第二字线12覆盖沿所述第二方向D2间隔排布的多个所述存储单元的所述有源柱的所述第二沟道区；
公共位线19，位于所述衬底10上，且电连接所述存储阵列中全部所述存储单元。
本具体实施方式中所述的半导体结构可以是但不限于DRAM、MRAM、RRAM(Resistive Random Access Memory，阻变随机存储器)、PCRAM(Phase-Change Random Access Memory，相变随机存储器)或者FeRAM(Ferroelectric Random Access Memory，铁电随机存储器)等。具体来说，所述衬底10可以是但不限于硅衬底，本具体实施方式以所述衬底10为硅衬底为例进行说明。在其他实施例中，所述衬底10还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI(Silicon On Insulator，绝缘体上硅)等半导体衬底。所述衬底用于形成或支撑在其上的所述存储阵列等器件结构。本具体实施方式中所述衬底10的顶面是指所述衬底10朝向所述存储阵列的表面。本具体实施方式中所述的多个是指两个以上。
所述存储阵列中包括沿所述第一方向D1和所述第二方向D2呈二维阵列排布的多个所 述存储单元，所述存储单元包括有源柱和存储元件。所述有源柱位于所述衬底10上，且沿所述第三方向D3延伸。所述有源柱中的所述沟道结构包括沿所述第三方向D3间隔排布的所述第一沟道区和所述第二沟道区，且所述第一沟道区和所述第二沟道区通过位于两者之间的部分有源柱(即后续介绍的公共源漏区)电连接，从而使得所述存储单元中包括串联连接的第一晶体管和第二晶体管，所述第一晶体管包括所述第一沟道区，所述第二晶体管包括所述第二沟道区。所述第一字线11覆盖于所述第一沟道区上的部分作为所述第一晶体管的第一栅极，所述第二字线12覆盖于所述第二沟道区上的部分作为所述第二晶体管的第二栅极。当通过所述第一字线11向所述存储单元内的所述第一晶体管传输第一开启信号、且通过所述第二字线12同时向同一所述存储单元内的所述第二晶体管传输第二开启信号时，所述存储单元内的所述第一晶体管和所述第二晶体管同时导通，从而才能对所述存储单元进行读写操作。针对与同一个所述存储单元电连接的所述第一字线11和所述第二字线12，若仅所述第一字线11向所述存储单元内的所述第一晶体管传输所述第一开启信号或者若仅所述第二字线12向所述存储单元内的所述第二晶体管传输所述第二开启信号，则所述存储单元内仅所述第一晶体管导通或者仅所述第二晶体管导通，则不能对所述存储单元进行读写操作。本具体实施方式通过所述第一字线11和所述第二字线12来选定所述存储阵列中的所述存储单元，因而，可以仅形成一条所述公共位线19，不再需要对每一排所述存储单元设置一条位线，不仅减少了位线的数量、降低了位线制程工艺的难度，而且减少了外围电路中用于对位线信号进行放大的感测放大器的数量，从而节约了所述半导体结构内部的空间，提高了所述半导体结构的集成度，有助于进一步缩小所述半导体结构的尺寸。
在一些实施例中，所述存储单元还包括：
公共源漏区13，位于所述第一沟道区和所述第二沟道区之间；
第一源漏区14，位于所述第一沟道区远离所述公共源漏区13的一侧；
第二源漏区15，位于所述第二沟道区远离所述公共源漏区13的一侧。
在一些实施例中，所述有源柱的材料为包括掺杂离子的半导体材料，且所述公共源漏区13的离子掺杂浓度分别大于所述第一沟道区的离子掺杂浓度和所述第二沟道区的离子掺杂浓度。
举例来说，如图1所示，所述有源柱可以为沿所述第三方向D3延伸的硅柱，所述硅柱的材料为包括所述掺杂离子的硅材料。在一示例中，所述掺杂离子可以为N型离子，也可以为P型离子。所述硅柱包括沿所述第三方向D3依次排布的所述第一源漏区14、所述第一沟道区、所述公共源漏区13、所述第二沟道区和所述第二源漏区15。所述公共源漏区13的离子掺杂浓度大于所述沟道结构的离子掺杂浓度，从而增强所述公共源漏区13的导电性。在一示例中，所述公共源漏区13的离子掺杂浓度可以与所述第一源漏区14的离子掺杂浓度、以及所述第二源漏区15的离子掺杂浓度均相等，以简化所述硅柱的离子掺杂操作。
所述公共源漏区13沿所述第三方向D3的长度不宜过短，否则会使得与同一个所述存储单元电连接的所述第一字线11与所述第二字线12之间具有较强的寄生电容效应，导致漏电的发生；所述公共源漏区13沿所述第三方向D3的长度也不宜过长，否则会导致所述存储单元尺寸过大。在一示例中，所述公共源漏区13沿所述第三方向D3的长度为10nm～30nm，但不限于此。
在另一些实施例中，所述有源柱的材料还可以为氧化物半导体材料。其中，所述氧化物半导体材料为In 2O 3(氧化铟)、ZnO(氧化锌)、IZO(氧化铟锌)、IGZO(铟镓锌氧化物)、IZTO(铟锡锌氧化物)、ZnON(氮氧化锌)中的任一种或者两种以上的组合。优选的，所述有源区的材料为IGZO。
在一些实施例中，所述公共位线19呈平板状，且平板状的所述公共位线19在所述衬底10的顶面上的投影覆盖所述存储阵列在所述衬底10的顶面上的投影。采用平板状的所述公共位线19，不仅能够简化所述公共位线19的制程工艺，而且无需进行公共位线19与每个所述存储单元的对准，从而进一步简化了所述半导体结构的制造工艺。另外，能够增 大所述公共位线19的面积，从而降低公共位线19的电阻，实现对所述半导体结构电性能的改进。
在一些实施例中，在沿所述第三方向D3上，所述第二源漏区15位于所述第一源漏区14上方；所述存储单元还包括：
存储元件，所述存储元件位于第二源漏区15上方、且电连接所述第二源漏区。
在一些实施例中，所述公共位线19沿所述第三方向D3位于所述存储阵列上方；所述存储元件包括：
第一端，电连接所述第二源漏区15；
第二端，沿所述第三方向D3位于所述第一端上方，且所述第二端电连接所述公共位线19。
在一些实施例中，所述存储单元还包括：
底部接触电极16，位于所述第一端与所述第二源漏区15之间，所述底部接触电极16接触电连接所述第一端和所述第二源漏区15，且所述底部接触电极16覆盖所述第二源漏区15。
在一些实施例中，所述半导体结构还包括：
公共源极线20，沿所述第三方向D3位于所述存储阵列下方，且所述存储阵列中全部所述存储单元的所述第一源漏区14均电连接所述公共源极线20。
在一些实施例中，所述公共源极线20呈平板状，且平板状的所述公共源极线20在所述衬底10的顶面上的投影覆盖所述存储阵列在所述衬底10的顶面上的投影。
具体来说，包括所述第一端和所述第二端的所述存储元件可以是MRAM中的存储元件(例如，磁性隧道结)、RRAM中的存储元件、PCRAM中的存储元件或者FeRAM中的存储元件。以下以所述半导体结构为MRAM、所述存储单元中的所述存储元件为磁性隧道结元件17为例进行说明。例如，所述磁性隧道结元件17包括沿所述第三方向D3依次排布的所述固定层(即第一端)、绝缘层和自由层(即第二端)。其中，所述固定层通过所述底部接触电极16与所述第二源漏区15接触电连接。所述磁性隧道结元件17沿所述第三方向D3的上方还设置有位线接触插塞18。所述位线接触插塞18沿所述第三方向D3延伸，且所述位线接触插塞18的一端与所述磁性隧道结元件17中的所述自由层接触电连接、另一端与所述公共位线19接触电连接。
所述半导体结构还包括位于所述存储阵列下方的所述公共源极线20。平板状的所述公共源极线20不仅可以简化所述公共源极线20的制程工艺，而且无需进行所述公共源极线20与每个所述存储单元的对准，从而简化了所述半导体结构的制造工艺。另外，平板状的所述公共源极线20还能够增大所述公共源极线20的面积，从而降低所述公共源极线20的电阻。
在一示例中，平板状的所述公共源极线20与平板状的所述公共位线19的形状和尺寸可以均相同，因而可以采用同一掩模板来形成所述公共源极线20和所述公共位线19，从而进一步减少掩模板的数量，降低所述半导体结构的制造成本。
附图3是本公开具体实施方式另一实施例中半导体结构的结构示意图。在一些实施例中，如图3所示，所述存储元件为电容器21，所述公共位线沿所述第三方向D3位于所述存储阵列下方；所述电容器21包括：
下电极层，电连接所述第二源漏区15；
电介质层，覆盖于所述下电极层表面；
上电极层，覆盖于所述电介质层表面。
以下以所述半导体结构为DRAM、所述存储单元中的所述存储元件为所述电容器21为例进行说明。例如，如图3所示，平板状的所述公共位线19沿所述第三方向D3位于所述存储阵列下方，且与所述存储阵列中全部所述存储单元内的所述第一源漏区14接触电连接。所述存储单元中的所述电容器21沿所述第三方向D3位于所述晶体管上方，且与所述晶体 管中的所述第二源漏区15接触电连接。所述半导体结构中还包括公共电极22。所述公共电极22沿所述第三方向D3位于所述存储阵列上方，且与所述存储阵列中全部所述电容器中的所述上电极层电连接。当然，也可以说，所述存储阵列中的全部存储单元的电容器21的上电极层一体化形成为上述公共电极22。
在一些实施例中，多条所述第一字线11沿所述第二方向D2间隔排布，且多条所述第二字线12沿所述第一方向D1间隔排布。
在一示例中，相邻所述第一字线11之间的距离与相邻所述第二字线12之间的距离相等，且所述第一字线11的形状和尺寸与所述第二字线12的形状和尺寸均相同。此时，可以采用同一掩模板来形成多条所述第一字线11和多条所述第二字线12，从而进一步减少掩模板的数量，降低所述半导体结构的制造成本。
在一示例中，所述第一沟道区和所述第二沟道区的材料相同，所述第一沟道区和所述第二沟道区关于所述公共源漏区13对称分布，例如所述第一沟道区和所述第二沟道区关于穿过所述公共源漏区13的中心且沿所述第一方向D1延伸的轴线对称分布，从而使得所述第一沟道区的开启电压与所述第二沟道区的开启电压相同，不仅能够简化所述半导体结构的制造工艺，还能够简化所述半导体结构的控制操作。
在一些实施例中，所述半导体结构还包括：
感测放大器，位于所述存储阵列的外部，且电连接所述公共位线19。本具体实施方式可以仅设置一个与所述公共位线19电连接的所述感测放大器，从而极大的节省了所述半导体结构的内部空间，从而有助于进一步缩小所述半导体结构的尺寸。
本具体实施方式还提供了一种半导体结构的形成方法，附图4是本公开具体实施方式中半导体结构的形成方法流程图，附图5-附图10是本公开具体实施方式在形成半导体结构的过程中主要的工艺结构示意图。本具体实施方式形成的半导体结构的示意图可以参见图1-图3。如图1-图10所示，所述半导体结构的形成方法，包括如下步骤：
步骤S41，提供初始衬底；
步骤S42，刻蚀所述初始衬底，形成有源阵列、以及位于所述有源阵列下的衬底10，所述有源阵列包括沿第一方向D1和第二方向D2排布的多个有源柱50，所述有源柱50包括沿第三方向D3间隔排布的第一沟道区51和第二沟道区52，如图5所示，所述第一方向D1和所述第二方向D2均与所述衬底10的顶面平行，且所述第一方向D1与所述第二方向D2相交，所述第三方向D3与所述衬底10的顶面垂直，所述有源阵列中全部的所述有源柱50均与一个公共位线19电连接；
步骤S43，形成字线结构于所述衬底10上，所述字线结构包括沿所述第一方向D1延伸的第一字线11和沿所述第二方向D2延伸的第二字线12，所述第一字线11覆盖沿所述第一方向D1间隔排布的多个所述有源柱50的所述第一沟道区，所述第二字线12覆盖沿所述第二方向D2间隔排布的多个所述有源柱50的所述第二沟道区，如图10所示。
在一些实施例中，形成有源阵列的步骤包括：
刻蚀所述初始衬底，形成多条沿所述第一方向D1延伸且沿所述第二方向D2间隔排布的第一沟槽、以及多条沿所述第二方向D2延伸且沿所述第一方向D1间隔排布的第二沟槽，多个所述第一沟槽和多个所述第二沟槽在所述初始衬底上定义出沿所述第一方向D1和所述第二方向D2排布的多个所述有源柱50，如图5所示。
在一些实施例中，所述有源柱50包括位于所述第一沟道区51和所述第二沟道区52之间的公共源漏区13、位于所述第一沟道区51远离所述公共源漏区13一侧的第一源漏区14、以及位于所述第二沟道区52远离所述公共源漏区13一侧的第二源漏区15，在沿所述第一方向D1上，所述第二源漏区15位于所述第一源漏区14上方；形成字线结构于所述衬底10上的步骤包括：
填充第一隔离材料于所述第一沟槽和所述第二沟槽内，形成填充满所述第一沟槽和所述第二沟槽的第一隔离层；
回刻蚀所述第一隔离层，形成多条沿所述第一方向D1延伸、且沿所述第二方向D2间隔排布的第三沟槽，所述第三沟槽暴露沿所述第一方向D1间隔排布的多个所述存储单元的所述有源柱的所述第一沟道区；
沿所述第三沟槽形成包覆所述第一沟道区51的第一栅介质层、并形成覆盖所述第一栅介质层的所述第一字线11；
形成覆盖所述第一字线11并填充满所述第三沟槽的第二隔离层；
回刻蚀所述第二隔离层，形成多条沿所述第二方向D2延伸、且沿所述第一方向D1间隔排布的第四沟槽，所述第四沟槽暴露沿所述第二方向D2间隔排布的多个所述存储单元的所述有源柱的所述第二沟道区52；
沿所述第四沟槽形成包覆所述第二沟道区52的第二栅介质层、并形成覆盖所述第二栅介质层的所述第二字线12；以及
形成覆盖所述第二字线12并填充满所述第四沟槽的第三隔离层。
在一些实施例中，形成字线结构于所述衬底10上之后，还包括如下步骤：
于所述第二源漏区15上方形成存储元件，所述存储元件电连接所述第二源漏区15。
在一些实施例中，于所述第二源漏区15上方形成存储元件的步骤包括：
于所述第二源漏区15上方形成与所述第二源漏区15电连接的第一端；
于所述第一端上方形成第二端，以形成包括所述第一端和所述第二端的所述存储元件，所述第二端用于与公共位线19(参见图10)电连接。
在一些实施例中，于所述第二源漏区15上方形成与所述第二源漏区15电连接的第一端之前，还包括：
形成覆盖所述第二源漏区15的底部接触电极16，如图8所示，且所述底部接触电极16覆盖所述第二源漏区15。
在一些实施例中，于所述第二源漏区15上方形成存储元件之后，还包括如下步骤：
于所述存储元件沿所述第三方向D3的上方形成电连接所述存储元件的所述第二端的所述公共位线19。
在一些实施例中，于所述存储元件沿所述第三方向D3的上方形成电连接所述存储元件的所述第二端的所述公共位线19的步骤包括：
于每个所述存储元件的所述第二端上方形成位线接触插塞18，如图9所示；
形成连续与所有所述位线插塞18接触电连接、且呈平板状的所述公共位线19，且平板状的所述公共位线19在所述衬底10的顶面上的投影覆盖所述有源阵列在所述衬底10的顶面上的投影，如图10所示。
在一些实施例中，形成存储阵列、字线结构和公共位线19于所述衬底10上的步骤还包括：
形成平板状的公共源极线20于所述有源阵列下方，所述公共源极线20电连接所述第一源漏区14，且平板状的所述公共源极线20在所述衬底10的顶面上的投影覆盖所述有源阵列在所述衬底10的顶面上的投影。
在一些实施例中，形成有源阵列于、以及位于所述有源阵列下方的衬底10上的步骤包括：
刻蚀所述初始衬底，多条所述第一沟槽、以及多条所述第二沟槽，多条所述第一沟槽和多条所述第二沟槽在所述初始衬底上定义出沿所述第一方向D2和所述第二方向D2排布的多个所述有源柱50，所述有源柱下方残留的部分所述初始衬底作为所述公共源极线20、且所述公共源极线20下方残留的部分所述初始衬底作为所述衬底10。
以下以所述半导体结构为MRAM、所述存储元件为磁性隧道结为例进行说明。可以采用光刻工艺刻蚀所述初始衬底，形成多条沿第一方向D1延伸且沿所述第二方向D2间隔排布的第一沟槽、以及多条沿第二方向D2延伸且沿所述第一方向D1间隔排布的第二沟槽，多条所述第一隔离槽和多条所述第二隔离槽在所述初始衬底上定义出沿所述第一方向D1 和所述第二方向D2呈阵列排布的多个所述有源柱50，形成有源阵列，如图5所示。所述第一沟槽和所述第二沟槽沿所述第三方向D3的深度基本相同、且均未贯穿所述初始衬底，因此，残留于所述有源阵列、所述第一沟槽和所述第二沟槽下方的部分所述初始衬底在掺杂后可作为所述公共源极线20、所述公共源极线20下方残留的所述初始衬底作为所述衬底10，如图5所示。
在形成所述有源阵列之后，可以填充旋涂式介电材料(SOD)等第一隔离材料于所述第一沟槽和所述第二沟槽内，形成填充满所述第一沟槽和所述第二沟槽的第一隔离层。之后，通过回刻蚀工艺去除部分的所述第一隔离层，形成多条沿所述第一方向D1延伸、且沿所述第二方向D2间隔排布的所述第三沟槽，所述第三沟槽暴露所述有源柱50中全部的所述第一沟道区51，残留的所述一隔离层覆盖所述公共源极线20和所述第一源漏区14、并填充部分的所述第一沟槽和部分的所述第二沟槽。在一示例中，所述第三沟槽沿所述第二方向D2的宽度大于所述第一沟槽沿所述第二方向D2的宽度，从而使得所述有源柱50中的所述第一沟道区51全部暴露。残留的所述第一隔离层可以用于隔离相邻的所述第三沟槽，从而简化后续形成第一字线的工艺。之后，可以采用沉积工艺或者原位生长工艺形成包覆暴露的所述有源柱50的第一栅介质材料层。所述第一栅介质材料层的材料为氧化物材料(例如二氧化硅)。接着，可以采用选择性原子层沉积工艺沉积金属钨或者TiN等第一字线材料，形成第一字线材料层。之后，通过回刻蚀工艺去除部分的所述第一字线材料层和部分的所述第一栅介质材料层，仅保留位于所述第一沟道区51上的第一栅介质材料层、并使得所述第一字线材料层的顶面位于所述公共源漏区13下方，以暴露所述有源柱50中的所述公共源漏区13、所述第二沟道区52和所述第二源漏区15，如图6所示，残留的覆盖于所述第一沟道区51上的所述第一栅介质材料层作为所述第一栅介质层、残留的所述第一字线材料层作为所述第一字线11。其中，所述第一字线11覆盖于所述第一栅介质层表面的部分作为第一晶体管的第一栅极。接着，形成覆盖所述第一字线11并填充满所述第三沟槽的第二隔离层。回刻蚀部分的所述第二隔离层，形成多条沿所述第二方向D2延伸、且沿所述第一方向D1间隔排布的第四沟槽，所述第四沟槽暴露所述第二沟道区52。在一示例中，所述第四沟槽沿所述第一方向D1的宽度大于所述第二沟槽沿所述第一方向D1的宽度，从而使得所述有源柱50中的所述第二沟道区52全部暴露。之后，可以采用沉积工艺或者原位生长工艺形成包覆暴露的所述有源柱50的第二栅介质材料层。所述第二栅介质材料层的材料为氧化物材料(例如二氧化硅)。接着，可以采用选择性原子层沉积工艺沉积金属钨或者TiN等第二字线材料，形成所述第二字线材料层。之后，通过回刻蚀工艺去除部分的所述第二字线材料层和部分的所述第二栅介质材料层，仅保留位于所述第二沟道区52上的第二栅介质材料层、并使得所述第二字线材料层的顶面位于所述第二源漏区15下方，以暴露所述有源柱50中的所述第二源漏区15，如图7所示，残留的覆盖于所述第二沟道区52上的所述第二栅介质材料层作为所述第二栅介质层、残留的所述第二字线材料层作为所述第二字线12。其中，所述第二字线12覆盖于所述第二栅介质层表面的部分作为第二晶体管的第二栅极。最后，形成覆盖所述第二字线12并填充满所述第四沟槽的第三隔离层。需要说明的是，形成字线结构的方法不限于此。例如，在形成有源阵列之后，可以采用沉积工艺或者原位生长工艺形成包覆暴露的所述有源柱50的栅介质层；形成填充满所述第一沟槽和所述第二沟槽的第一隔离层，回刻蚀所述第一隔离层以形成第三沟槽；在第三沟槽中形成第一字线材料层，回刻蚀所述第一字线材料层以得到第一字线11；形成覆盖所述第一字线11并填充满所述第三沟槽的第二隔离层，回刻蚀所述第二隔离层以形成第四沟槽；在第四沟槽中形成第二字线材料层，回刻蚀所述第二字线材料层以得到第二字线12；形成覆盖所述第二字线12并填充满所述第四沟槽的第三隔离层。当然，在此情况下，于所述有源柱50的所述第二源漏区15上方形成所述底部接触电极16之前，需要先去出有源柱50顶面的栅介质层。
于所述有源柱50的所述第二源漏区15上方形成所述底部接触电极16、位于所述底部接触电极16上的所述磁性隧道结元件17、以及位于所述磁性隧道结元件17上的位线接触 插塞18，如图8和图9所示。之后，沉积金属钨或者TiN等导电材料于所述位线接触插塞18上方，形成平板状的所述公共位线19，且所述公共位线19同时与所有的所述位线接触插塞18接触电连接。
在一些实施例中，如图3所示，所述存储元件为电容器21；形成有源阵列、以及位于所述有源阵列下方的衬底10的步骤还包括：
刻蚀所述初始衬底，形成多条所述第一沟槽、以及多条所述第二沟槽，多条所述第一沟槽和多条所述第二沟槽在所述初始衬底上定义出沿所述第一方向和所述第二方向排布的多个所述有源柱，所述有源柱下方残留的部分所述初始衬底形成平板状的所述公共位线19，所述公共位线19电连接所述第一源漏区14，平板状的所述公共位线19在所述衬底10的顶面上的投影覆盖所述有源阵列在所述衬底10的顶面上的投影。
以下以所述半导体结构为DRAM为例进行说明。举例来说，可以采用光刻工艺刻蚀所述初始衬底，形成多条沿第一方向D1延伸且沿所述第二方向D2间隔排布的第一沟槽、以及多条沿第二方向D2延伸且沿所述第一方向D1间隔排布的第二沟槽，多条所述第一沟槽和多条所述第二沟槽在所述初始衬底上定义出沿所述第一方向D1和所述第二方向D2呈阵列排布的多个所述有源柱50，形成有源阵列，如图5所示。所述第一沟槽和所述第二沟槽沿所述第三方向D3的深度基本相同、且均未贯穿所述初始衬底，因此，残留于所述有源阵列下方的部分所述初始衬底作为所述公共位线19，所述公共位线19下方残留的所述初始衬底作为所述衬底10，如图3所示。在一示例中，所述第一沟槽和所述第二沟槽沿所述第三方向D3的深度相同，一方面，可以简化所述半导体结构的制造工艺，降低所述半导体结构的制造难度；另一方面，还能确保所述有源柱各方向性能的一致性，以改善所述半导体结构的电性能。
在形成所述第一字线11和所述第二字线12(形成所述第一字线11和所述第二字线12的方法可以与MRAM相同)之后，于所述有源结构20中的所述第二源漏区15上形成所述电容器21。所述电容器21包括与所说第二源漏区15接触电连接的下电极层、覆盖所述下电极层表面的电介质层、以及覆盖所述电介质层表面的上电极层。之后，于所述电容器21上方形成平板状的公共电极22，且所述公共电极22与所有所述电容器中的所述上电极层电连接。
在一些实施例中，所述有源柱50的材料为包括掺杂离子的硅材料，且所述公共源漏区13的离子掺杂浓度大于所述第一沟道区51的离子掺杂浓度和所述第二沟道区52的离子掺杂浓度。
在另一些实施例中，所述有源柱50的材料还可以为氧化物半导体材料。其中，所述氧化物半导体材料为In 2O 3(氧化铟)、ZnO(氧化锌)、IZO(氧化铟锌)、IGZO(铟镓锌氧化物)、IZTO(铟锡锌氧化物)、ZnON(氮氧化锌)中的任一种或者两种以上的组合。优选的，所述有源区的材料为IGZO。
本具体实施方式还提供了一种半导体结构的操作方法。附图11是本公开具体实施方式中半导体结构的操作方法流程图。图1-图3所示的半导体结构均可采用本具体实施方式提供的半导体结构的操作方法进行操作。如图1-图2、以及图11所示，所述半导体结构的操作方法，包括如下步骤：
步骤S111，提供半导体结构；所述半导体结构如图1和图2所示，或者，所述半导体结构如图3所示；
步骤S112，向一条所述第一字线11施加第一开启信号、向一条所述第二字线12施加第二开启信号，通过所述公共位线19对一条所述第一字线11和一条所述第二字线12定位的所述存储单元进行读取操作或写入操作。
以下以所述半导体结构为如图1和图2所示的MRAM为例进行说明。当向一条所述第一字线11施加第一开启信号、并向一条所述第二字线12施加第二开启信号，同时向其他的所述第一字线11施加第一关闭信号、以及向其他的所述第二字线12施加第二关闭信号， 从而定位到与施加所述第一开启信号的所述第一字线11连接、且同时与施加所述第二开启信号的所述第二字线12连接的所述存储单元，并对定位到的所述存储单元进行读取操作或者写入操作。
本具体实施方式一些实施例提供的半导体结构及其形成方法、半导体结构的操作方法，通过在存储单元的有源柱中设置沿有源柱的延伸方向间隔排布的第一沟道区和第二沟道区，并设置包括第一字线和第二字线的字线结构，且每个存储单元均连接一条第一字线和一条第二字线，使得能够通过第一字线和第二字线确定存储阵列中存储单元的位置，因而，在所述存储阵列中仅设置一条公共位线，通过所述公共位线电连接所述存储阵列中所有的存储单元，一方面，简化了位线的制程工艺，且增大了位线与存储单元的接触面积，从而改善了半导体结构的电性能；另一方面，由于仅设置一条公共位线，因而可以大幅度减少感测放大器的数量，减少感测放大器占用面积，从而提高了半导体结构内部的空间利用率，有助于进一步缩小半导体结构的尺寸。本具体实施方式另一些实施例中，还可以形成平板状的公共源极线，从而进一步简化半导体结构的制程工艺。
需要说明的是，在本公开中，为简化图示，附图中省略了部分结构和/或膜层(例如，第一隔离层、第二隔离层和第三隔离层等)。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (25)

  1. 一种半导体结构，包括：
    衬底；
    存储阵列，位于所述衬底上，包括沿第一方向和第二方向排布的多个存储单元，所述存储单元包括有源柱，所述有源柱包括沿第三方向间隔排布的第一沟道区和第二沟道区，所述第一方向和所述第二方向均与所述衬底的顶面平行，且所述第一方向与所述第二方向相交，所述第三方向与所述衬底的顶面垂直；
    字线结构，位于所述衬底上，包括沿所述第一方向延伸的第一字线和沿所述第二方向延伸的第二字线，所述第一字线覆盖沿所述第一方向间隔排布的多个所述存储单元的所述有源柱的所述第一沟道区，所述第二字线覆盖沿所述第二方向间隔排布的多个所述存储单元的所述有源柱的所述第二沟道区；
    公共位线，位于所述衬底上，且电连接所述存储阵列中全部所述存储单元。
  2. 根据权利要求1所述的半导体结构，其中，所述有源柱还包括：
    公共源漏区，位于所述第一沟道区和所述第二沟道区之间；
    第一源漏区，位于所述第一沟道区的远离所述公共源漏区的一侧；
    第二源漏区，位于所述第二沟道区的远离所述公共源漏区的一侧。
  3. 根据权利要求2所述的半导体结构，其中，所述有源柱的材料为包括掺杂离子的半导体材料，且所述公共源漏区的离子掺杂浓度分别大于所述第一沟道区的离子掺杂浓度和所述第二沟道区的离子掺杂浓度。
  4. 根据权利要求2所述的半导体结构，其中，所述公共位线呈平板状，且平板状的所述公共位线在所述衬底的顶面上的投影覆盖所述存储阵列在所述衬底的顶面上的投影。
  5. 根据权利要求2所述的半导体结构，其中，在沿所述第三方向上，所述第二源漏区位于所述第一源漏区上方；所述存储单元还包括：
    存储元件，所述存储元件位于第二源漏区上方、且电连接所述第二源漏区。
  6. 根据权利要求5所述的半导体结构，其中，所述公共位线沿所述第三方向位于所述存储阵列上方；所述存储元件包括：
    第一端，电连接所述第二源漏区；
    第二端，沿所述第三方向位于所述第一端上方，且所述第二端电连接所述公共位线。
  7. 根据权利要求6所述的半导体结构，其中，所述存储单元还包括：
    底部接触电极，位于所述第一端与所述第二源漏区之间，所述底部接触电极接触电连接所述第一端和所述第二源漏区，且所述底部接触电极覆盖所述第二源漏区。
  8. 根据权利要求6所述的半导体结构，还包括：
    公共源极线，沿所述第三方向位于所述存储阵列下方，且所述存储阵列中全部所述存储单元的所述第一源漏区均电连接所述公共源极线。
  9. 根据权利要求8所述的半导体结构，其中，所述公共源极线呈平板状，且平板状的所述公共源极线在所述衬底的顶面上的投影覆盖所述存储阵列在所述衬底的顶面上的投影。
  10. 根据权利要求5所述的半导体结构，其中，所述存储元件为电容器，所述公共位线沿所述第三方向位于所述存储阵列下方；所述电容器包括：
    下电极层，电连接所述第二源漏区；
    电介质层，覆盖于所述下电极层表面；
    上电极层，覆盖于所述电介质层表面。
  11. 根据权利要求1所述的半导体结构，其中，多条所述第一字线沿所述第二方向间隔排布，且多条所述第二字线沿所述第一方向间隔排布。
  12. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括：
    感测放大器，位于所述存储阵列的外部，且电连接所述公共位线。
  13. 一种半导体结构的形成方法，包括：
    提供初始衬底；
    刻蚀所述初始衬底，形成有源阵列、以及位于所述有源阵列下方的衬底，所述有源阵列包括沿第一方向和第二方向排布的多个有源柱，所述有源柱包括沿第三方向间隔排布的第一沟道区和第二沟道区，所述第一方向和所述第二方向均与所述衬底的顶面平行，且所述第一方向与所述第二方向相交，所述第三方向与所述衬底的顶面垂直，所述有源阵列中全部的所述有源柱均与一个公共位线电连接；
    形成字线结构于所述衬底上，所述字线结构包括沿所述第一方向延伸的第一字线和沿所述第二方向延伸的第二字线，所述第一字线覆盖沿所述第一方向间隔排布的多个所述有源柱的所述第一沟道区，所述第二字线覆盖沿所述第二方向间隔排布的多个所述有源柱的所述第二沟道区。
  14. 根据权利要求13所述的半导体结构的形成方法，其中，形成有源阵列的步骤包括：
    刻蚀所述初始衬底，形成多条沿所述第一方向延伸且沿所述第二方向间隔排布的第一沟槽、以及多条沿所述第二方向延伸且沿所述第一方向间隔排布的第二沟槽，多个所述第一沟槽和多个所述第二沟槽在所述初始衬底上定义出沿所述第一方向和所述第二方向排布的多个所述有源柱。
  15. 根据权利要求14所述的半导体结构的形成方法，其中，所述有源柱包括位于所述第一沟道区和所述第二沟道区之间的公共源漏区、位于所述第一沟道区远离所述公共源漏区一侧的第一源漏区、以及位于所述第二沟道区远离所述公共源漏区一侧的第二源漏区，在沿所述第一方向上，所述第二源漏区位于所述第一源漏区上方；形成字线结构于所述衬底上包括：
    填充第一隔离材料于所述第一沟槽和所述第二沟槽内，形成填充满所述第一沟槽和所述第二沟槽的第一隔离层；
    回刻蚀所述第一隔离层，形成多条沿所述第一方向延伸、且沿所述第二方向间隔排布的第三沟槽，所述第三沟槽暴露沿所述第一方向间隔排布的多个所述存储单元的所述有源柱的所述第一沟道区；
    沿所述第三沟槽形成包覆所述第一沟道区的第一栅介质层、并形成覆盖所述第一栅介质层的所述第一字线；
    形成覆盖所述第一字线且填充满所述第三沟槽的第二隔离层；
    回刻蚀所述第二隔离层，形成多条沿所述第二方向延伸、且沿所述第一方向间隔排布的第四沟槽，所述第四沟槽暴露沿所述第二方向间隔排布的多个所述存储单元的所述有源柱的所述第二沟道区；
    沿所述第四沟槽形成包覆所述第二沟道区的第二栅介质层、并形成覆盖所述第二栅介质层的所述第二字线。
  16. 根据权利要求15所述的半导体结构的形成方法，其中，形成字线结构于所述衬底上之后，还包括：
    于所述第二源漏区上方形成存储元件，所述存储元件电连接所述第二源漏区。
  17. 根据权利要求16所述的半导体结构的形成方法，其中，于所述第二源漏区上方形成存储元件包括：
    于所述第二源漏区上方形成与所述第二源漏区电连接的第一端；
    于所述第一端上方形成第二端，以形成包括所述第一端和所述第二端的所述存储元件，所述第二端用于与公共位线电连接。
  18. 根据权利要求17所述的半导体结构的形成方法，其中，于所述第二源漏区上方形成与所述第二源漏区电连接的第一端之前，还包括：
    形成覆盖所述第二源漏区的底部接触电极，且所述底部接触电极覆盖所述第二源漏区。
  19. 根据权利要求17所述的半导体结构的形成方法，其中，于所述第二源漏区上方形成存储元件之后，还包括：
    于所述存储元件沿所述第三方向的上方形成电连接所述存储元件的所述第二端的所述 公共位线。
  20. 根据权利要求19所述的半导体结构的形成方法，其中，于所述存储元件沿所述第三方向的上方形成电连接所述存储元件的所述第二端的所述公共位线包括：
    于每个所述存储元件的所述第二端上方形成位线接触插塞；
    形成连续与全部所述位线插塞接触电连接、且呈平板状的所述公共位线，且平板状的所述公共位线在所述衬底的顶面上的投影覆盖所述有源阵列在所述衬底的顶面上的投影。
  21. 根据权利要求20所述的半导体结构的形成方法，还包括：
    形成平板状的公共源极线于所述有源阵列下方，所述公共源极线电连接所述第一源漏区，且平板状的所述公共源极线在所述衬底的顶面上的投影覆盖所述有源阵列在所述衬底的顶面上的投影。
  22. 根据权利要求21所述的半导体结构的形成方法，其中，形成有源阵列、以及位于所述有源阵列下方的衬底包括：
    刻蚀所述初始衬底，形成多条所述第一沟槽、以及多条所述第二沟槽，多条所述第一沟槽和多条所述第二沟槽在所述初始衬底上定义出沿所述第一方向和所述第二方向排布的多个所述有源柱，所述有源柱下方残留的部分所述初始衬底作为所述公共源极线、且所述公共源极线下方残留的部分所述初始衬底作为所述衬底。
  23. 根据权利要求16所述的半导体结构的形成方法，其中，所述存储元件为电容器；形成有源阵列、以及位于所述有源阵列下方的衬底还包括：
    刻蚀所述初始衬底，形成多条所述第一沟槽、以及多条所述第二沟槽，多个所述第一沟槽和多个所述第二沟槽在所述初始衬底上定义出沿所述第一方向和所述第二方向排布的多个所述有源柱，所述有源柱下方残留的部分所述初始衬底形成平板状的所述公共位线、且所述公共位线下方残留的部分所述初始衬底作为所述衬底，所述公共位线电连接所述第一源漏区，平板状的所述公共位线在所述衬底的顶面上的投影覆盖所述有源阵列在所述衬底的顶面上的投影。
  24. 根据权利要求16所述的半导体结构的形成方法，其中，所述有源柱的材料为包括掺杂离子的半导体材料，且所述公共源漏区的离子掺杂浓度大于所述第一沟道区的离子掺杂浓度和所述第二沟道区的离子掺杂浓度。
  25. 一种半导体结构的操作方法，包括如下步骤：
    提供如权利要求1所述的半导体结构；
    向一条所述第一字线施加第一开启信号、向一条所述第二字线施加第二开启信号，通过所述公共位线对一条所述第一字线和一条所述第二字线定位的所述存储单元进行读取操作或写入操作。
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