WO2023245816A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

Info

Publication number
WO2023245816A1
WO2023245816A1 PCT/CN2022/109461 CN2022109461W WO2023245816A1 WO 2023245816 A1 WO2023245816 A1 WO 2023245816A1 CN 2022109461 W CN2022109461 W CN 2022109461W WO 2023245816 A1 WO2023245816 A1 WO 2023245816A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electrode layer
sub
lower electrode
forming
Prior art date
Application number
PCT/CN2022/109461
Other languages
English (en)
French (fr)
Inventor
邵光速
肖德元
邱云松
白卫平
苏星松
郁梦康
黄娟娟
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP22839611.5A priority Critical patent/EP4329454A1/en
Priority to US18/170,631 priority patent/US20230413523A1/en
Publication of WO2023245816A1 publication Critical patent/WO2023245816A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate electrode of the transistor is electrically connected to the word line
  • the source electrode is electrically connected to the bit line
  • the drain electrode is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line.
  • the semiconductor structure and its formation method provided by some embodiments of the present disclosure are used to solve the problem of low capacitance of the semiconductor structure and improve the storage capacity of the semiconductor structure.
  • the present disclosure provides a semiconductor structure including a plurality of memory cells located on a substrate, each of the memory cells including: a transistor; a capacitor electrically connected to the transistor, the capacitor including a body portion, and an extension portion located on the side of the main body and electrically connected to the main body.
  • the number of the extension portions in the capacitor is multiple, and the plurality of extension portions are distributed at least on one side of the main body portion.
  • the number of the extension portions in the capacitor is multiple, and the plurality of extension portions are distributed on opposite sides of the main body portion at least along a first direction, and the first direction is direction parallel to the top surface of the substrate.
  • the transistor includes: a source electrode/drain electrode, one of the source electrode/drain electrode being electrically connected to the capacitor; a channel layer, a source electrode located in the source electrode/drain electrode and between the drain electrodes; the gate electrode, and the channel layer surrounds at least part of the gate electrode.
  • the width of the projection of the extension portion on the substrate along the first direction is greater than the width of the projection of the main body portion on the substrate along the first direction, and the The main body is electrically connected to the transistor.
  • the capacitor includes: a lower electrode layer, including a first sub-lower electrode layer and a second sub-lower electrode layer intersecting the first sub-lower electrode layer, the lower electrode layer and the The transistor is electrically connected through contact; a dielectric layer covers the inner surface of the lower electrode layer; an upper electrode layer covers the surface of the dielectric layer; wherein the first sub-lower electrode layer defines the position of the main body, so The second sub-lower electrode layer defines the position of the extension portion.
  • the capacitor includes: a lower electrode layer, including a first sub-lower electrode layer and a second sub-lower electrode layer intersecting the first sub-lower electrode layer, the lower electrode layer and the The transistor is electrically connected through contact; a dielectric layer is continuously coated on the surface of the lower electrode layer; an upper electrode layer is continuously coated on the surface of the dielectric layer; wherein the first sub-lower electrode layer defines the main body The second sub-lower electrode layer defines the position of the extension portion.
  • the transistor is located below the capacitor with a first isolation layer between them, wherein the main body portion of the capacitor penetrates the first isolation layer to electrically connect the transistor.
  • a plurality of the memory cells are arranged in an array along a first direction and a second direction, and both the first direction and the second direction are directions parallel to the top surface of the substrate, And the first direction intersects the second direction;
  • the semiconductor structure further includes: a plurality of word lines extending along the second direction, the word lines are electrically connected to the word lines arranged along the second direction.
  • a plurality of memory cells; a plurality of bit lines extending along the first direction, the bit lines are located below the word lines and are electrically connected to the plurality of memory cells arranged along the first direction.
  • a plurality of the memory units are also stacked and arranged along a third direction, and the third direction is a direction perpendicular to the top surface of the substrate.
  • the present disclosure also provides a method for forming a semiconductor structure, including the following steps: providing a substrate; forming a plurality of memory cells on the substrate, and the steps of forming a plurality of the memory cells include: A transistor is formed on the substrate; a capacitor is formed, the capacitor is electrically connected to the transistor, and the capacitor includes a main body part and an extension part located on the side of the main body part and electrically connected to the main body part.
  • the method before forming a transistor on the substrate, the method further includes the following steps: forming a plurality of bit lines spaced apart along the second direction, each of the bit lines extending along the first direction, and the first bit line extending along the first direction. Both the first direction and the second direction are directions parallel to the top surface of the substrate, and the first direction intersects the second direction; forming a third isolation layer covering the bit line.
  • the specific steps of forming transistors on the substrate include: defining a plurality of transistor regions spaced apart along the second direction above the substrate; forming a gate electrode on each of the transistors.
  • a word line is formed in the region and extends along the second direction and continuously connects a plurality of the gate electrodes; a word line is formed above the word line extending along the second direction and continuously covering a plurality of the transistor regions.
  • Channel layer forming a source electrode and a drain electrode that at least cover the surface of the channel layer in each of the transistor regions, and the channel layer is at least between the source electrode and the drain electrode.
  • forming a capacitor includes: forming a first isolation layer covering the transistor; forming a second isolation layer over the first isolation layer; defining a capacitor along the second direction over the substrate.
  • a plurality of capacitance regions arranged at intervals, and the plurality of capacitance regions are used to form a plurality of the capacitors respectively; a sub-trough penetrating the second isolation layer along the third direction is formed in the capacitance region, and a sub-trough is formed along the third direction.
  • the third direction penetrates the communication grooves of the second isolation layer and the first isolation layer, and the communication grooves in the capacitance area connects multiple sub-slots in the same capacitance area.
  • Three directions are directions perpendicular to the top surface of the substrate; the extension portion is formed in the sub-groove, and the main body portion is formed in the communication groove.
  • the specific steps of forming the extension portion in the sub-groove and forming the main body portion in the communication groove include: forming an inner wall that continuously covers the inner wall of the sub-groove and the communication groove. a lower electrode layer; forming a dielectric layer covering the surface of the lower electrode layer and the top surface of the second isolation layer; forming an upper electrode layer covering the surface of the dielectric layer, the extension including The lower electrode layer, the dielectric layer and the upper electrode layer are provided, and the main body part includes the lower electrode layer, the dielectric layer and the upper electrode layer located in the communication groove.
  • the specific steps of forming the extension portion in the sub-groove and forming the main body portion in the communication groove include: forming an inner wall that continuously covers the inner wall of the sub-groove and the communication groove. a lower electrode layer; removing the second isolation layer; forming a dielectric layer covering the surface of the lower electrode layer; forming an upper electrode layer covering the surface of the dielectric layer, wherein the lower electrode located in the sub-trough
  • the lower electrode layer, the dielectric layer and the upper electrode layer located in the communication groove together form the main body part.
  • the method further includes: sequentially forming a plurality of the memory cells stacked and arranged along a third direction above the substrate, where the third direction is a direction perpendicular to the top surface of the substrate.
  • Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.
  • a capacitor structure is provided above the transistor structure, and the capacitor structure includes a transistor and a capacitor electrically connected to the transistor.
  • Each of the capacitors includes a main body portion. , and an extension portion located on the side of the main body and electrically connected to the main body to increase the size of the capacitor, thereby increasing the capacitance of the capacitor, thereby increasing the storage capacity of the semiconductor structure.
  • the capacitor including the main body part and the extension part is located above the transistor structure, thereby making full use of the three-dimensional space above the substrate, reducing the occupation of the substrate surface area, and improving the semiconductor structure.
  • the internal space utilization rate helps further control the size of the semiconductor structure and expands the application field of the semiconductor structure.
  • the size of a single layer be increased, but multi-layer stacking of a three-dimensional semiconductor structure can also be realized, thereby reducing process difficulty and improving the storage density of the semiconductor structure.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor structure in a specific embodiment of the present disclosure
  • FIG. 2 is a partial top structural schematic diagram of a capacitor structure in an embodiment of the present disclosure
  • FIG. 3 is a partial top structural schematic diagram of a capacitor structure in another embodiment of the present disclosure.
  • FIG. 4 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure
  • 5A-5N are schematic diagrams of the main process structures in the process of forming semiconductor structures according to specific embodiments of the present disclosure.
  • 6A-6G are schematic structural diagrams of various capacitors in specific embodiments of the present disclosure.
  • FIG. 1 is a schematic cross-sectional view of the semiconductor structure in the specific implementation of the present disclosure.
  • FIG. 2 is a partial top structural schematic diagram of the capacitor structure in an example of the specific implementation of the present disclosure.
  • the semiconductor structure described in this specific embodiment may be, but is not limited to, DRAM.
  • the semiconductor structure includes a plurality of memory units 28 located on the substrate 10; the memory units 28 include:
  • a capacitor is electrically connected to the transistor.
  • the capacitor includes a main body part 32 and an extension part 31 located on the side of the main body part 32 and electrically connected to the main body part.
  • the substrate 10 may be, but is not limited to, a silicon substrate.
  • the substrate 10 is a silicon substrate as an example for description.
  • the substrate 10 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI.
  • the memory unit 28 includes a transistor structure, the transistor structure is located above the substrate 10 , and the transistor structure at least includes a plurality of the transistors spaced apart along the first direction D1, wherein , the first direction D1 is a direction parallel to the top surface of the substrate 10 .
  • the memory unit 28 also includes a capacitor structure, and the capacitor structure includes a plurality of capacitors arranged at intervals along the first direction D1.
  • the capacitor structure is located above the transistor structure along a third direction D3, which is a direction perpendicular to the top surface of the substrate 10.
  • a third direction D3 which is a direction perpendicular to the top surface of the substrate 10.
  • embodiments of the present disclosure can be Arranging a plurality of the memory cells 28 in the first direction D1 and the second direction D2, increasing the size of a single layer, and performing multi-layer stacking in the third direction D3 can realize a three-dimensional semiconductor structure and reduce process difficulty. Improving the storage density of semiconductor structures.
  • the top surface of the substrate 10 refers to the surface of the substrate 10 facing the memory unit.
  • the capacitor structure includes a plurality of capacitors arranged at intervals along the first direction D1, and the plurality of capacitors are electrically connected to a plurality of transistors one by one to form a 1T1C structure.
  • Each capacitor includes a main body portion 32 and an extension portion 31 located on the side of the main body portion 32 .
  • the main body portion 32 and the extension portion 31 intersect to form a corner structure to increase the size of the capacitor. , thereby increasing the capacitance of the capacitor, thereby achieving the effect of increasing the storage capacity of the semiconductor structure.
  • the extension portion 31 includes a first sub-lower electrode layer, a first sub-dielectric layer covering the surface of the first sub-lower electrode layer, and a first sub-dielectric layer covering the surface of the first sub-dielectric layer.
  • the upper electrode layer, the main body part includes a second sub-lower electrode layer, a second sub-dielectric layer covering the surface of the second sub-lower electrode layer, and a second sub-upper layer covering the surface of the second sub-lower electrode layer.
  • electrode layer, the first sub-lower electrode layer and the second sub-lower electrode layer intersect and are electrically connected, and the first sub-upper electrode layer intersects and is electrically connected to the second sub-upper electrode layer.
  • the first sub-lower electrode layer and the second sub-lower electrode layer jointly serve as the lower electrode layer of the capacitor, and the first sub-dielectric layer and the second sub-dielectric layer jointly serve as the dielectric layer of the capacitor.
  • the first sub-upper electrode layer and the second sub-upper electrode layer together serve as the upper electrode layer of the capacitor.
  • the number of the extension portions 31 in the capacitor is multiple, and the plurality of extension portions 31 are distributed at least on one side of the main body portion 32 .
  • the number of the extension portions 31 in the capacitor is multiple, and the plurality of extension portions 31 are distributed on opposite sides of the main body portion 32 at least along the first direction D1.
  • the first direction D1 is a direction parallel to the top surface of the substrate 10 .
  • FIGS. 6A-6G are schematic structural diagrams of various capacitors in specific embodiments of the present disclosure.
  • the number of the extension parts 31 may be one or more, and all the extension parts 31 are located on the same side of the main body part 32 .
  • the lengths of the multiple extension portions 31 along the first direction D1 may be the same, or they may be different, so that the capacitance of the capacitor can be flexibly set.
  • the plurality mentioned in this specific embodiment refers to two or more.
  • the number of the extension parts 31 is multiple, and the multiple extension parts 31 are distributed on opposite sides of the main body part 32 along the first direction D1 .
  • the lengths of the extension portions 31 located on opposite sides of the main body portion 32 along the first direction D1 may be the same or different to meet different capacitance requirements of the capacitor.
  • the extension portions 31 located on opposite sides of the main body 32 can be distributed symmetrically or asymmetrically with respect to the main body 32 to fully utilize the space inside the semiconductor structure.
  • the extension part 31 may further include a first sub-part 311 and a second sub-part 312 located on the side of the first sub-part 311 and electrically connected to the first sub-part 311.
  • the first sub-section 311 is located on the side of the main body part 32 and is electrically connected to the main body part 32, thereby further increasing the surface area of the capacitor.
  • the first sub-lower electrode layer includes at least one corner.
  • the first sub-lower electrode layer is in the shape of a surrounding frame.
  • the extension part 31 and the main part 32 are electrically connected, so that the extension part 31 and the main part 32 in the capacitor are electrically connected to the same transistor.
  • This specific embodiment does not limit the extension direction of the extension portion 31 and the extension direction of the main body portion 32, as long as the extension portion 31 and the main body portion 32 intersect and are electrically connected, thereby increasing the capacitor size.
  • the surface area is enough.
  • the intersection in this specific embodiment may be a vertical intersection or an oblique intersection.
  • the extension portion 31 is in direct contact and electrical connection with the main body portion 32 to simplify the structure of the capacitor and reduce the manufacturing cost of the capacitor.
  • a plurality in this specific embodiment means two or more.
  • the transistor structure further includes:
  • Source electrode/drain electrode one of the source electrode/drain electrode is electrically connected to the capacitor;
  • Channel layer 29 is located between the source electrode 22 and the drain electrode 21 in the source electrode/drain electrode;
  • Gate electrode 18 the channel layer 29 surrounds at least part of the gate electrode 18.
  • a plurality of the memory units 28 may be arranged at intervals along a first direction D1 and a second direction D2, wherein the first direction D1 and the second direction D2 are parallel to the top of the substrate 10
  • the second direction D2 intersects the first direction D1.
  • the transistor includes the gate electrode 18, a diffusion barrier layer 19 located above the gate electrode 18, a gate dielectric layer 20 covering the surface of the diffusion barrier layer 19 and the sidewalls of the gate electrode 18, and a gate dielectric layer 20 located above the gate electrode 18.
  • the channel layer 29 is continuously distributed over the plurality of gate electrodes 18 spaced apart along the second direction D2, so that the plurality of transistors spaced apart along the second direction D2 share the channel.
  • the channel layer 29 thus helps to simplify the manufacturing process of the semiconductor structure and the driving operation of the semiconductor structure.
  • the material of the channel layer 29 may be an amorphous material.
  • the amorphous material may be IGZO (indium gallium zinc oxide), polysilicon, SnO 2 , WO 3 , In 2 O 3 , ZnO, TiO 2 , Fe 2 O 3 , MoO 3 , CuO, NiO, Co 3 O 4 and Cr 2 O 3 and other oxide semiconductor materials, any one or a combination of two or more.
  • Each of the transistors includes the source electrode 22 and the drain electrode 21 arranged at intervals along the first direction D1, and the source electrodes 22 of a plurality of the transistors are arranged at intervals along the second direction D2. , and the drain electrodes 21 of the plurality of transistors are also arranged at intervals along the second direction D2.
  • the source electrode/drain electrode mentioned in this specific embodiment refers to the two electrodes, the source electrode and the drain electrode.
  • the width of the projection of the extension portion 31 on the substrate 10 along the first direction D1 is greater than the width of the main body portion 32 on the substrate 10
  • the projection on is along the width of the first direction D1
  • the main body portion 32 is electrically connected to the transistor.
  • the projection of the main body 32 on the top surface of the substrate 10 and the projection of the drain electrode 21 on the top surface of the substrate 10 at least partially overlap, so that the main body 32 and The drain electrode 21 is in direct contact and electrically connected, thereby simplifying the manufacturing process of the semiconductor structure.
  • the depth of the main body part 32 along the third direction D3 is greater than the depth of the extension part 31 along the third direction D3.
  • the width of the projection of the extension portion 31 on the substrate 10 along the first direction D1 is greater than the width of the projection of the main body portion 32 on the substrate 10 along the first direction D1.
  • the capacitor includes:
  • the lower electrode layer 23 includes a first sub-lower electrode layer and a second sub-lower electrode layer intersecting the first sub-lower electrode layer.
  • the lower electrode layer 23 is electrically connected to the transistor contact;
  • Dielectric layer 24 covers the inner surface of the lower electrode layer 23;
  • the upper electrode layer 25 covers the surface of the dielectric layer 24;
  • the first sub-lower electrode layer defines the position of the main body part
  • the second sub-lower electrode layer defines the position of the extension part
  • the transistor is located below the capacitor, with a first isolation layer 33 between them, wherein the main body portion 32 of the capacitor passes through the The first isolation layer 33 is used to electrically connect the transistor.
  • the first isolation layer 33 covers the transistor structure, the extension portion 31 is located above the first isolation layer 33 , and the main body portion 31 extends along the first isolation layer 33 .
  • Three directions D3 penetrate the first isolation layer 33 , and the top end of the main body part 31 is in contact and electrical connection with the extension part 31 , and the bottom end is in contact and electrical connection with the drain electrode 21 of the transistor.
  • the material of the first isolation layer 33 may be an oxide material (such as silicon dioxide).
  • the capacitor structure further includes:
  • the second isolation layer 55 is located above the first isolation layer 33 and distributed between the two adjacent capacitors.
  • the main body portion 32 continuously penetrates the first isolation layer along the third direction D3. 33 and the second isolation layer 55;
  • the third isolation layer 26 is located above the first isolation layer 33 and distributed around the periphery of all the capacitors.
  • the capacitor structure further includes a fourth isolation layer 27 located between the second isolation layer 55 and the first isolation layer 33 .
  • the third isolation layer 26 is located on the surface of the fourth isolation layer 27 and distributed around the periphery of all the capacitors.
  • the third isolation layer 26 is used to isolate the adjacent memory cells; on the other hand, it is also used to support the capacitor structure and improve the structural stability of the capacitor structure.
  • the extension part 31 may include a first sub-lower electrode layer, a first sub-dielectric layer covering the surface of the first sub-lower electrode layer and the top surface of the second isolation layer 55 , and a first sub-dielectric layer covering the first sub-lower electrode layer.
  • the main body part 32 may include a second sub-lower electrode layer, a second sub-dielectric layer covering the surface of the second sub-lower electrode layer, and a second sub-upper electrode layer covering the surface of the second sub-dielectric layer. .
  • the first sub-lower electrode layer and the second sub-lower electrode layer are in contact and electrically connected, and together form the lower electrode layer 23 of the capacitor.
  • the second sub-lower electrode layer is electrically connected to the drain electrode 21 of the transistor.
  • the first sub-dielectric layer and the second sub-dielectric layer together constitute the dielectric layer 24 of the capacitor.
  • the first sub-upper electrode layer and the second sub-upper electrode layer together constitute the upper electrode layer 25 of the capacitor.
  • FIG. 3 is a partial top structural schematic diagram of a capacitor structure in another embodiment of the present disclosure.
  • the semiconductor structure may not include the second isolation layer 55 (as shown in FIG. 3 ), that is, the dielectric layer 24 covers the lower electrode layer 23 , and the upper electrode layer 25 covers the entire surface of the dielectric layer 24 to further increase the capacitance of the capacitor.
  • the capacitor includes:
  • the lower electrode layer 23 includes a first sub-lower electrode layer and a second sub-lower electrode layer that intersects the first sub-lower electrode layer.
  • the lower electrode layer 23 is electrically connected to the transistor contact;
  • the dielectric layer 24 continuously covers the surface of the lower electrode layer 23;
  • the upper electrode layer 25 continuously covers the surface of the dielectric layer 24;
  • the first sub-lower electrode layer defines the position of the main body portion 32
  • the second sub-lower electrode layer 31 defines the position of the extension portion.
  • a plurality of the memory cells 28 may be arranged in an array along the first direction D1 and the second direction D2 .
  • D2 are both directions parallel to the top surface of the substrate 10, and the first direction D1 intersects the second direction D2; the semiconductor structure also includes:
  • a plurality of bit lines 12 extending along the first direction D1 are located below the word lines and are electrically connected to a plurality of memory cells 28 arranged along the first direction.
  • the semiconductor structure includes a plurality of memory cells 28 arranged at intervals along the second direction D2, and a plurality of transistors are located in the memory cells 28 one by one.
  • the transistor includes a gate electrode 18, a source electrode and a drain electrode.
  • the word line extends along the second direction D2 and is continuously electrically connected to the gate electrodes 18 of the transistors in the plurality of memory cells 28 .
  • the bit line 12 is located below the word line and extends along the first direction D1 intersecting the second direction D2. In an embodiment, both the first direction D1 and the second direction D2 are directions parallel to the top surface of the substrate 10 .
  • the bit line 12 may be located within the substrate 10 , that is, forming a buried bit line structure. As shown in FIG. 1 , in another embodiment, the bit line 12 may be located above the substrate 10 , thereby simplifying the manufacturing process of the bit line 12 . Taking the bit line 12 above the substrate 10 as an example, a substrate isolation layer 11 may be provided between the bit line 12 and the substrate 10 to isolate the substrate 10 from the bit line 12 . Line 12. A fifth isolation layer may also be included between the bit line 12 and the word line. The fifth isolation layer may have a single-layer structure or a multi-layer structure.
  • the memory cell further includes a bit line contact plug 17 that penetrates the fifth isolation layer along the third direction D3, and one end of the bit line contact plug 17 is connected to the The source electrode of the transistor is electrically connected to the source electrode, and the other end is electrically connected to the bit line 12 .
  • the fifth isolation layer includes a first dielectric layer 13 covering the surface of the bit line 12 and a second dielectric layer 14 covering the surface of the first dielectric layer 13 .
  • the third dielectric layer 15 covering the surface of the second dielectric layer 14
  • the fourth dielectric layer 16 covering the surface of the third dielectric layer 15 .
  • the material of the first dielectric layer 13 may be an oxide material (such as silicon dioxide)
  • the material of the second dielectric layer 14 may be a nitride material (such as silicon nitride).
  • the material of the third dielectric layer 15 may be polyimide
  • the material of the fourth dielectric layer 16 may be a nitride material (such as silicon nitride).
  • a plurality of memory units 28 are stacked and arranged along a third direction D3 , which is a direction perpendicular to the top surface of the substrate 10 , thereby forming
  • the semiconductor structure has a three-dimensional structure to further improve the integration level and storage capacity of the semiconductor structure.
  • FIG. 4 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure.
  • Figures 5A-5N are a process of forming a semiconductor structure in a specific embodiment of the present disclosure. Schematic diagram of the main process structure. Schematic diagrams of the semiconductor structure formed in this specific embodiment can be seen in Figures 1-3. As shown in Figures 1-4 and 5A-5N, the method for forming a semiconductor structure includes the following steps: step S11, providing a substrate 10;
  • a plurality of memory cells are formed above the substrate.
  • the steps of forming the plurality of memory cells include: step S12, forming transistors on the substrate 10; step S13, forming a capacitor, and the capacitor is electrically connected to the transistor. connected, and the capacitor includes a main body part 32 and an extension part 31 located on the side of the main body part 32 and electrically connected to the main body part 32 .
  • a plurality of bit lines 12 are formed at intervals along the second direction D2. Each of the bit lines 12 extends along the first direction D1.
  • the first direction D1 and the second direction D2 are both parallel to the first direction D1.
  • the direction of the top surface of the substrate 10, and the first direction D1 intersects the second direction D2;
  • a fifth isolation layer covering the bit line 12 is formed.
  • an insulating dielectric material such as oxide (such as silicon dioxide) is deposited on the top surface of the substrate 10 , and a planarization process such as chemical mechanical polishing is performed to form the substrate isolation layer 11 .
  • the substrate isolation layer 11 is patterned, and a plurality of bit line trenches extending along the first direction D1 are formed in the substrate isolation layer 11, and the plurality of bit line trenches are formed along the first direction D1.
  • the second direction D2 is arranged at intervals.
  • the bit line trench does not penetrate the substrate isolation layer 11 along the third direction D3 , which is a direction perpendicular to the top surface of the substrate 10 .
  • the fifth isolation layer covering the bit line 12 is formed.
  • the fifth isolation layer may include a single layer or a multi-layer structure.
  • the fifth isolation layer includes a first dielectric layer 13 covering the surface of the bit line 12, and a first dielectric layer 13 covering the surface of the bit line 12.
  • the second dielectric layer 14 on the surface, the third dielectric layer 15 covering the surface of the second dielectric layer 14 , and the fourth dielectric layer 16 covering the surface of the third dielectric layer 15 .
  • specific steps of forming transistors on the substrate 10 include:
  • a gate electrode 18 is formed in each of the transistor regions, and a word line extending along the second direction D2 and continuously connecting a plurality of the gate electrodes 18 is formed, as shown in FIG. 5A , wherein ( in FIG. 5A a) is a schematic cross-sectional view, and (b) in Figure 5A is a top view;
  • a channel layer 29 extending along the second direction D1 and continuously covering a plurality of the transistor regions is formed above the word line;
  • a source electrode 22 and a drain electrode 21 covering at least the surface of the channel layer 29 are formed in each of the transistor regions, and the channel layer 29 is at least between the source electrode 22 and the drain electrode 21, As shown in Figure 5B, (a) in Figure 5B is a schematic cross-sectional view, and (b) in Figure 5B is a top view.
  • the specific steps of forming a channel layer 29 extending along the second direction D1 and continuously covering a plurality of the transistor regions above the word line include:
  • Amorphous material is deposited above the word line to form the channel layer 29 .
  • word line material such as metal tungsten
  • word line material may be deposited above the fifth isolation layer, wherein the word line material located in the transistor region forms the gate electrode 18 of the transistor, located in the phase
  • the word line material adjacent the gate electrode 18 forms the word line.
  • materials such as TiN are deposited on the word lines and the gate electrode 18 to form a diffusion barrier layer 19 , as shown in FIG. 5A , to prevent the conductive particles in the gate electrode 18 from diffusing outward.
  • oxide such as silicon dioxide, aluminum oxide and other dielectric materials
  • oxide is deposited on the surface of the diffusion barrier layer 19, the sidewalls of the gate electrode 18, the sidewalls of the word lines and the surface of the fifth isolation layer to form the gate dielectric layer 20 .
  • Amorphous materials such as IGZO are deposited on the surface of the gate dielectric layer 20 to form the channel layer 29 .
  • Source and drain metal materials such as metal tungsten are deposited on the surface of the channel layer 29 and the surface of the gate dielectric layer 20 to form the source electrode 22 and the drain electrode 21, as shown in FIG. 5B.
  • the following steps are further included:
  • a bit line contact plug 17 is formed that at least penetrates the fifth isolation layer. One end of the bit line contact plug 17 is electrically connected to the bit line 12 and the other end is electrically connected to the source electrode 22 , as shown in FIG. 5C shown.
  • forming the capacitor includes:
  • a second isolation layer 55 is formed above the first isolation layer 33, as shown in Figure 5E, where (a) in Figure 5E is a schematic cross-sectional view, and (b) in Figure 5E is a top view;
  • a sub-trench 51 penetrating the second isolation layer 55 along the third direction D3 is formed in each of the capacitor regions (as shown in FIG. 5F , where (a) in FIG. 5F is a schematic cross-sectional view, and (a) in FIG. 5F is a schematic cross-sectional view. (b) is a top view), and a communication groove 53 penetrating the second isolation layer 55 and the first isolation layer 33 along the third direction D3. The communication groove 53 in the capacitor area communicates with the same place.
  • the plurality of sub-grooves 51 in the capacitor area are as shown in Figure 5H, where (a) in Figure 5H is a schematic cross-sectional view, (b) in Figure 5H is a top view, and the third direction D3 is vertical In the direction of the top surface of the substrate 10;
  • the extension portion 31 is formed in the sub-groove 51 , and the main body portion 32 is formed in the communication groove 53 .
  • the specific steps of forming the second isolation layer 55 above the first isolation layer 33 include:
  • the initial second isolation layer 50 is etched back to form an isolation trench exposing the fourth isolation layer 27 at the end of the initial second isolation layer 50 , and the remaining initial second isolation layer 50 serves as the The second isolation layer 55 is as shown in Figure 5E;
  • a third isolation layer 26 is formed in the isolation trench, as shown in FIG. 5E.
  • a sub-groove 51 penetrating the second isolation layer 55 along the third direction D3 is formed, and a sub-groove 51 penetrating the second isolation layer 55 and the first isolation layer 33 along the third direction D3 is formed.
  • Connecting slot 53, specific steps include:
  • the remaining second isolation layer 55 is selectively etched along the second direction D2 to form a plurality of communication grooves 53.
  • Each communication groove 53 connects at least two sub-grooves 51; at this time, there is still a third sub-groove 51 between adjacent sub-grooves 51.
  • Second isolation layer 55 is selectively etched along the second direction D2 to form a plurality of communication grooves 53.
  • each capacitor hole can expose the drain electrode 21 of a single transistor, so that the surface area of the lower electrode subsequently deposited in the capacitor hole can be A further increase also allows the lower electrode to be directly connected to the transistor.
  • a photolithography process may be used to pattern the second isolation layer 55 to form a plurality of sub-grooves 51 penetrating the second isolation layer 55 along the third direction D3, as shown in FIG. 5F.
  • Each of the capacitive regions includes at least two sub-slots 51 .
  • a sacrificial layer 52 filled with the sub-trench 51 is formed, as shown in FIG. 5G , where (a) in FIG. 5G is a schematic cross-sectional view, and (b) in FIG. 5G is a top view.
  • the sacrificial layer 52 and the partially remaining second isolation layer 55 are etched to form a plurality of communication grooves 53 penetrating the sacrificial layer 52 and the second isolation layer 55 .
  • the fourth isolation layer 27 and the first isolation layer 33 are etched downward along the communication groove 53 , and the communication groove 53 is extended to the surface of the drain electrode 51 of the transistor.
  • the communication groove 53 in the capacitance area intersects at least two of the sub-grooves 51 in the same capacitance area to form one capacitance hole, as shown in FIG. 5H.
  • the bottom of the communication groove 53 exposes the drain electrode 21 , as shown in FIG. 5I , which is a top view.
  • the bottom of the communication groove 53 exposing the drain electrode 21 means that the projection of the communication groove 53 on the top surface of the substrate 10 is the same as the projection of the drain electrode 21 of the transistor on the substrate 10 The projections on the top surface at least partially overlap.
  • the extension portion 31 is formed in the sub-groove 51, and the main body portion 32 is formed in the communication groove 53. Steps include:
  • the lower electrode layer 23 is formed to continuously cover the inner wall of the sub-trough 51 and the inner wall of the communication groove 53, as shown in Figure 5J, wherein (a) in Figure 5J is a schematic cross-sectional view, and (b) in Figure 5J is a top view. ;
  • a dielectric layer 24 covering the surface of the lower electrode layer 23 and the top surface of the second isolation layer 55 is formed, as shown in FIG. 5K , where (a) in FIG. 5K is a schematic cross-sectional view, ((a) in FIG. 5K b) is a top view;
  • the extension part 31 includes the lower electrode layer 23 located in the sub-groove 51 , the dielectric layer 24 and the upper electrode layer 25 .
  • Electrode layer 25 , the main body portion 32 includes the lower electrode layer 23 , the dielectric layer 54 and the upper electrode layer 25 located in the communication groove 53 .
  • at least two sub-grooves 51 and a single communication groove 53 form a single capacitor hole.
  • the lower electrode layer 23 is deposited in the capacitor hole.
  • the adjacent lower electrode layers are independent of each other.
  • a dielectric is formed on the surface of the lower electrode layer 23.
  • the adjacent dielectric layers 24 are connected to each other, that is, the dielectric layers 24 in the capacitor are shared.
  • the electrode layer 25 is on the surface of the dielectric layer 24, the adjacent upper electrode layers 25 are connected to each other, and the upper electrode layer 25 in the capacitor is It is also shared.
  • the sacrificial layer 52 is removed, and a lower electrode material is deposited that continuously covers the inner wall of the sub-groove 51 and the communication groove 53 .
  • the lower electrode material located on the inner wall of the sub-trough 51 serves as the first sub-lower electrode layer
  • the lower electrode material located on the inner wall of the communication groove 53 serves as the second sub-lower electrode layer.
  • the first sub-lower electrode layer The electrode layer and the second sub-lower electrode layer together serve as the lower electrode layer 23 .
  • the extension portion 31 includes the lower electrode layer 23 , the dielectric layer 24 and the upper electrode layer 25 located in the sub-trough 51 , and the main body portion 32 includes the lower electrode layer 23 located in the communication groove 53 .
  • the extension portion 31 is formed in the sub-groove 51, and the main body portion 32 is formed in the communication groove 53.
  • the specific steps include:
  • An upper electrode layer 25 is formed covering the surface of the dielectric layer 24 , wherein the lower electrode layer 23 located in the sub-trough 51 , the dielectric layer 24 and the upper electrode layer 25 together constitute the extension portion 31 , located in the communication
  • the second isolation layer 55 can be removed, so that the subsequently formed dielectric layer 24 covers the lower electrode layer 23 , thereby further increasing the capacitor's resistance. surface area, increasing the capacitance of the capacitor.
  • the method of forming the semiconductor structure further includes:
  • a plurality of the memory cells 28 are sequentially formed in a stacked arrangement above the substrate 10 along a third direction D3, which is a direction perpendicular to the top surface of the substrate 10, as shown in FIG. 5N Show.
  • a capacitance structure is provided above the transistor structure, and the capacitance structure includes a plurality of capacitors.
  • each of the capacitors By arranging each of the capacitors to include an intersecting extension part and a main part, To increase the size of the capacitor, thereby increasing the capacitance of the capacitor, thereby increasing the storage capacity of the semiconductor structure.
  • the capacitor including the extension part and the main body part is located above the transistor structure, thereby making full use of the three-dimensional space above the substrate, reducing the occupation of the substrate surface area, and improving the efficiency of the substrate.
  • the space utilization inside the semiconductor structure helps to further control the size of the semiconductor structure and expand the application field of the semiconductor structure. In the embodiments of this specific implementation mode, not only can the size of a single layer be increased, but also multi-layer stacking of three-dimensional semiconductor structures can be realized, which reduces process difficulty and improves the storage density of the semiconductor structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

本公开涉及一种半导体结构及其形成方法。所述半导体结构包括位于衬底上的多个存储单元，每个所述存储单元包括：晶体管；电容器，电连接所述晶体管，所述电容器包括主体部、以及位于所述主体部的侧面且与所述主体部电连接的延伸部。本公开增大了电容器的电容量，提高了半导体结构的存储容量。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2022年06月21日递交的中国专利申请号202210704100.7、申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅电极与字线电连接、源电极与位线电连接、漏电极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。随着半导体制造技术的不断发展，各领域对DRAM等半导体结构的存储容量的要求越来越高。但是，传统的DRAM等半导体结构由于其结构的限制，导致电容器的电容量较低，从而限制了半导体结构存储容量的提高。因此，如何增大半导体结构中的电容量，从而提高半导体结构的存储容量，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体结构及其形成方法，用于解决半导体结构的电容量较低的问题，以提高半导体结构的存储容量。
根据一些实施例，本公开提供了一种半导体结构，包括位于衬底上的多个存储单元，每个所述存储单元包括：晶体管；电容器，电连接所述晶体管，所述电容器包括主体部、以及位于所述主体部的侧面且与所述主体部电连接的延伸部。
在一些实施例中，所述电容器中的所述延伸部的数量为多个，且多个所述延伸部至少分布于所述主体部的一侧。
在一些实施例中，所述电容器中的所述延伸部的数量为多个，且多个所述延伸部至少沿第一方向分布于所述主体部的相对两侧，所述第一方向为平行于所述衬底的顶面的方向。
在一些实施例中，所述晶体管包括：源电极/漏电极，所述源电极/漏电极中之一电连接所述电容器；沟道层，位于所述源电极/漏电极中的源电极和漏电极之间；栅电极，所述沟道层至少包围部分所述栅电极。
在一些实施例中，所述延伸部在所述衬底上的投影沿第一方向的宽度大于所述主体部在所述衬底的上的投影沿所述第一方向的宽度，且所述主体部与所述晶体管电连接。
在一些实施例中，所述电容器包括：下电极层，包括第一子下电极层、以及与所述第一子下电极层相交的第二子下电极层，所述下电极层与所述晶体管接触电连接；电介质层，覆盖所述下电极层的内表面；上电极层，覆盖所述电介质层的表面；其中，所述第一子下电极层定义出所述主体部的位置，所述第二子下电极层定义出所述延伸部的位置。
在一些实施例中，所述电容器包括：下电极层，包括第一子下电极层、以及与所述第一子下电极层相交的第二子下电极层，所述下电极层与所述晶体管接触电连接；电介质层，连续包覆在所述下电极层的表面；上电极层，连续包覆在所述电介质层的表面；其中，所述第一子下电极层定义出所述主体部的位置，所述第二子下电极层定义出所述延伸部的位置。
在一些实施例中，所述晶体管位于所述电容器的下方，且二者之间具有第一隔离层，其中，所述电容器的所述主体部贯穿所述第一隔离层，以电连接所述晶体管。
在一些实施例中，多个所述存储单元沿第一方向和第二方向呈阵列排布，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；所述半导体结构还包括：多条沿所述第二方向延伸的字线，所述字线电连接沿所述第二方向上排布的多个存储单元；多条沿所述第一方向延伸的位线，所述位线位于所述字线下方，且电连接沿所述第一方向上排布的多个存储单元。
在一些实施例中，多个所述存储单元还沿第三方向堆叠排布，所述第三方向为垂直于所述衬底的顶面的方向。
根据另一些实施例，本公开还提供了一种半导体结构的形成方法，包括如下步骤：提供衬底；形成 多个存储单元于所述衬底上，多个所述存储单元的形成步骤包括：形成晶体管于所述衬底上；形成电容器，所述电容器与所述晶体管电连接，且所述电容器包括主体部、以及位于所述主体部的侧面且与所述主体部电连接的延伸部。
在一些实施例中，形成晶体管于所述衬底上之前，还包括如下步骤：形成多条沿第二方向间隔排布的位线，每条所述位线沿第一方向延伸，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；形成覆盖所述位线的第三隔离层。
在一些实施例中，形成晶体管于所述衬底上的具体步骤包括：于所述衬底上方定义沿所述第二方向间隔排布的多个晶体管区域；形成栅电极于每个所述晶体管区域内、并形成沿所述第二方向延伸且连续连接多个所述栅电极的字线；于所述字线上方形成沿所述第二方向延伸、且连续覆盖多个所述晶体管区域的沟道层；于每一个所述晶体管区域内形成至少覆盖于所述沟道层表面的源电极和漏电极，所述沟道层至少位于所述源电极和所述漏电极之间。
在一些实施例中，形成电容器的步骤包括：形成覆盖所述晶体管的第一隔离层；于所述第一隔离层上方形成第二隔离层；于所述衬底上方定义沿所述第二方向间隔排布的多个电容区域，多个所述电容区域用于分别形成多个所述电容器；于所述电容区域内形成沿第三方向贯穿所述第二隔离层的子槽、以及沿所述第三方向贯穿所述第二隔离层和所述第一隔离层的连通槽，所述电容区域内的所述连通槽连通同一所述电容区域内的多个所述子槽，所述第三方向为垂直于所述衬底的顶面的方向；形成所述延伸部于所述子槽内、并形成所述主体部于所述连通槽内。
在一些实施例中，形成所述延伸部于所述子槽内、并形成所述主体部于所述连通槽内的具体步骤包括：形成连续覆盖所述子槽内壁和所述连通槽内壁的下电极层；形成覆盖所述下电极层的表面和所述第二隔离层的顶面的电介质层；形成覆盖所述电介质层表面的上电极层，所述延伸部包括位于所述子槽内的所述下电极层、所述电介质层和所述上电极层，所述主体部包括位于所述连通槽内的所述下电极层、所述电介质层和所述上电极层。
在一些实施例中，形成所述延伸部于所述子槽内、并形成所述主体部于所述连通槽内的具体步骤包括：形成连续覆盖所述子槽内壁和所述连通槽内壁的下电极层；去除所述第二隔离层；形成覆盖所述下电极层表面的电介质层；形成覆盖所述电介质层的表面的上电极层，其中，位于所述子槽中的所述下电极层、所述电介质层和所述上电极层共同构成所述延伸部，位于所述连通槽中的所述下电极层、所述电介质层和所述上电极层共同构成所述主体部。
在一些实施例中，还包括：依次形成沿第三方向堆叠排布的多个所述存储单元于所述衬底上方，所述第三方向为与所述衬底的顶面垂直的方向。
本公开一些实施例提供的半导体结构及其形成方法，在晶体管结构上方设置电容结构，且所述电容结构包括晶体管、以及与所述晶体管电连接的电容器，通过设置每个所述电容器包括主体部、以及位于所述主体部的侧面且与所述主体部电连接的延伸部，来增大所述电容器的尺寸，进而达到增大电容器的电容量的效果，以提高半导体结构的存储容量。另外，本公开中包括所述主体部和所述延伸部的所述电容器是位于晶体管结构的上方的，从而能够充分利用衬底上方的三维空间，减少对衬底表面积的占用，提高了半导体结构内部的空间利用率，从而有助于进一步控制所述半导体结构的尺寸，扩大所述半导体结构的应用领域。本公开实施例中,不仅可以增加单层的尺寸，还可以实现三维半导体结构的多层堆叠，减少工艺难度，提高半导体结构的存储密度。
附图说明
附图1是本公开具体实施方式中半导体结构的截面示意图；
附图2是本公开具体实施方式的一实施例中电容结构的部分俯视结构示意图；
附图3是本公开具体实施方式的另一实施例中电容结构的部分俯视结构示意图；
附图4是本公开具体实施方式中半导体结构的形成方法流程图；
附图5A-5N是本公开具体实施方式在形成半导体结构的过程中主要的工艺结构示意图；
附图6A-6G是本公开具体实施方式中多种电容器的结构示意图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构，附图1是本公开具体实施方式中半导体结构的截面示意图，附图2是本公开具体实施方式的一实施例中电容结构的部分俯视结构示意图。本具体实施方式中所述的半导体结构可以是但不限于DRAM。如图1和图2所示，所述半导体结构，包括位于衬底10上的多个存储单元28；所述存储单元28包括：
晶体管；
电容器，电连接所述晶体管，所述电容器包括主体部32、以及位于所述主体部32的侧面且与所述主体部电连接的延伸部31。
具体来说，所述衬底10可以是但不限于硅衬底，本具体实施方式以所述衬底10为硅衬底为例进行说明。在其他示例中，所述衬底10可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。在一实施例中，所述存储单元28包括晶体管结构，所述晶体管结构位于所述衬底10上方，且所述晶体管结构至少包括沿第一方向D1间隔排布的多个所述晶体管，其中，所述第一方向D1为平行于所述衬底10的顶面的方向。所述存储单元28中还包括电容结构，所述电容结构包括沿所述第一方向D1间隔排布的多个所述电容器。所述电容结构沿第三方向D3位于所述晶体管结构上方，所述第三方向D3为垂直于所述衬底10的顶面的方向，在一些实施例中，本公开实施例可以在所述第一方向D1、以及所述第二方向D2排布多个所述存储单元28，增加单层的尺寸，并在第三方向D3上进行多层堆叠，可以实现三维半导体结构，减少工艺难度，提高半导体结构的存储密度。所述衬底10的顶面是指所述衬底10朝向所述存储单元的表面。所述电容结构中包括沿所述第一方向D1间隔排布的多个所述电容器，且多个所述电容器与多个所述晶体管一一电连接，形成1T1C结构。每个所述电容器包括所述主体部32和位于所述主体部32的侧面的所述延伸部31，通过所述主体部32与所述延伸部31相交形成拐角结构来增加所述电容器的尺寸，从而使得所述电容器的电容量增大，进而达到增大所述半导体结构的存储容量的效果。
具体来说，所述延伸部31包括第一子下电极层、覆盖于所述第一子下电极层表面的第一子电介质层、以及覆盖于所述第一子电介质层表面的第一子上电极层，所述主体部包括第二子下电极层、覆盖于所述第二子下电极层表面的第二子电介质层、以及覆盖于所述第二子电介质层表面的第二子上电极层，所述第一子下电极层和所述第二子下电极层相交且电连接，所述第一子上电极层与所述第二子上电极层相交且电连接。所述第一子下电极层和所述第二子下电极层共同作为所述电容器的下电极层，所述第一子电介质层和所述第二子电介质层共同作为所述电容器的电介质层，所述第一子上电极层和所述第二子上电极层共同作为所述电容器的上电极层。通过形成弯折的下电极层和上电极层结构，来增大所述下电极层和上电极层的表面积，进而增大所述电容器的表面积，最终达到增大所述电容器的电容量的技术效果。
在一些实施例中，所述电容器中的所述延伸部31的数量为多个，且多个所述延伸部31至少分布于所述主体部32的一侧。
在一些实施例中，所述电容器中的所述延伸部31的数量为多个，且多个所述延伸部31至少沿第一方向D1分布于所述主体部32的相对两侧，所述第一方向D1为平行于所述衬底10的顶面的方向。
附图6A-6G是本公开具体实施方式中多种电容器的结构示意图。举例来说，如图6A-图6C所示，所述延伸部31的数量可以为一个或者多个，且所有的所述延伸部31均位于所述主体部32的同一侧。当所述延伸部31的数量为多个且均位于所述主体部32沿第一方向D1的同一侧时，多个所述延伸部31沿所述第一方向D1的长度可以相同，也可以不同，从而可以灵活设置所述电容器的电容量。本具体实施方式中所述的多个是指两个以上。再例如，如图6D-图6G所示，所述延伸部31的数量为多个，且多个所述延伸部31沿所述第一方向D1分布于所述主体部32的相对两侧。在一实施例中，位于所述主体部32相对两侧的所述延伸部31沿所述第一方向D1的长度可以相同，也可以不同，以满足不同的电容器电容量要求。在一实施例中，位于所述主体部32相对两侧的所述延伸部31可以关于所述主体部对称分布、也可以不对称分布，以充分利用所述半导体结构内部的空间。
在一实施例中，所述延伸部31还可以包括第一子部311、以及位于所述第一子部311侧面且与所述第一子部311电连接的第二子部312，所述第一子部311位于所述主体部32侧面且与所述主体部32电连接，从而进一步增大所述电容器的表面积。
为了进一步增大所述电容器的表面积，在一实施例中，所述第一子下电极层包括至少一个拐角。举例来说，所述第一子下电极层呈围框状。
所述延伸部31和所述主体部32电连接，从而使得所述电容器中的所述延伸部31和所述主体部32电连接至同一个所述晶体管。本具体实施方式对所述延伸部31的延伸方向、以及所述主体部32的延伸方向不作限定，只要使得所述延伸部31和所述主体部32相交且电连接，从而增大所述电容器的表面积即可。本具体实施方式中的相交可以是垂直相交，也可以是倾斜相交。在一实施例中，所述延伸部31与所述主体部32直接接触电连接，以简化所述电容器的结构，降低所述电容器的制造成本。本具体实施方式中的多个是指两个以上。
如图1所示，在一些实施例中，晶体管结构还包括：
源电极/漏电极，所述源电极/漏电极中之一电连接所述电容器；
沟道层29，位于所述源电极/漏电极中的源电极22和漏电极21之间；
栅电极18，所述沟道层29至少包围部分所述栅电极18。
具体来说，多个所述存储单元28可以沿第一方向D1、沿第二方向D2间隔排布，其中，所述第一方向D1、第二方向D2为平行于所述衬底10的顶面的方向，且所述第二方向D2与所述第一方向D1相交。所述晶体管包括所述栅电极18、位于所述栅电极18上方的扩散阻挡层19、覆盖所述扩散阻挡层19的表面和所述栅电极18的侧壁的栅极介质层20、位于所述栅极介质层20表面的所述沟道层29、以及位于所述沟道层29表面的所述源电极22和所述漏电极21。所述沟道层29连续分布于沿所述第二方向D2间隔排布的多个所述栅电极18上方，使得沿所述第二方向D2间隔排布的多个所述晶体管共用所述沟道层29，从而有助于简化所述半导体结构的制造工艺和所述半导体结构的驱动操作。其中，所述沟道层29的材料可以为非晶材料，例如，所述非晶材料可以是IGZO(氧化铟镓锌)、多晶硅、SnO 2、WO 3、In 2O 3、ZnO、TiO 2、Fe 2O 3、MoO 3、CuO、NiO、Co 3O 4和Cr 2O 3等氧化物半导体材料中的任一种或者两种以上的组合。每个所述晶体管包括沿所述第一方向D1间隔排布的所述源电极22和所述漏电极21，多个所述晶体管的所述源电极22沿所述第二方向D2间隔排布，且多个所述晶体管的所述漏电极21也沿所述第二方向D2间隔排布。本具体实施方式中所述的源电极/漏电极是指源电极和漏电极这两个电极。
如图1和图2所示，在一些实施例中，所述延伸部31在所述衬底10上的投影沿所述第一方向D1的宽度大于所述主体部32在所述衬底10上的投影沿所述第一方向D1的宽度，且所述主体部32与所述晶体管电连接。举例来说，所述主体部32在所述衬底10的顶面上的投影与所述漏电极21在所述衬底10的顶面上的投影至少部分重叠，使得所述主体部32与所述漏电极21直接接触电连接，从而简化所述半导体结构的制造工艺。由于所述主体部32与所述晶体管的漏电极21直接接触电连接，因此，所述主体部32沿第三方向D3的深度大于所述延伸部31沿所述第三方向D3的深度，通过将所述延伸部31在所述衬底10上的投影沿所述第一方向D1的宽度大于所述主体部32在所述衬底10上的投影沿所述第一方向D1的宽度，可以简化所述主体部32的刻蚀工艺(例如减小刻蚀时间)。
在一些实施例中，如图1和图2所示，所述电容器包括：
下电极层23，包括第一子下电极层、以及与所述第一子下电极层相交的第二子下电极层，所述下电极层23与所述晶体管接触电连接；
电介质层24，覆盖所述下电极层23的内表面；
上电极层25，覆盖所述电介质层24的表面；
其中，所述第一子下电极层定义出所述主体部的位置，所述第二子下电极层定义出所述延伸部的位置。
图1和图2所示，在一些实施例中，所述晶体管位于所述电容器的下方，且二者之间具有第一隔离层33，其中，所述电容器的所述主体部32贯穿所述第一隔离层33，以电连接所述晶体管。
具体来说，如图1和图2所示，所述第一隔离层33覆盖所述晶体管结构，所述延伸部31位于所述第一隔离层33上方，所述主体部31沿所述第三方向D3贯穿所述第一隔离层33，且所述主体部31的顶端与所述延伸部31接触电连接、底端与所述晶体管的所述漏电极21接触电连接。其中，所述第一隔离层33的材料可以为氧化物材料(例如二氧化硅)。
在一些实施例中，如图1和图2所示，所述电容结构还包括：
第二隔离层55，位于所述第一隔离层33上方、且分布于相邻的两个所述电容器之间，所述主体部32沿所述第三方向D3连续贯穿所述第一隔离层33和所述第二隔离层55；
第三隔离层26位于所述第一隔离层33上方，且环绕所有所述电容器的外周分布。
具体来说，如图1和图2所示，所述电容结构还包括位于所述第二隔离层55与所述第一隔离层33之间的第四隔离层27。所述第三隔离层26位于所述第四隔离层27的表面、且环绕所有所述电容器的外周分布。所述第三隔离层26一方面用于隔离相邻的所述存储单元；另一方面还用于支撑所述电容结构，提高所述电容结构的结构稳定性。所述延伸部31可以包括第一子下电极层、覆盖于所述第一子下电极层表面和所述第二隔离层55的顶面的第一子电介质层、以及覆盖于所述第一子电介质层表面的第一子上电极层。所述主体部32可以包括第二子下电极层、覆盖于所述第二子下电极层表面的第二子电介质层、以及覆盖于所述第二子电介质层表面的第二子上电极层。所述第一子下电极层和所述第二子下电极层接触电连接，且共同构成所述电容器的所述下电极层23。所述第二子下电极层与所述晶体管的所述漏电极21接触电连接。所述第一子电介质层和所述第二子电介质层共同构成所述电容器的所述电介质层24。所述第一子上电极层和所述第二子上电极层共同构成所述电容器的所述上电极层25。
图3是本公开具体实施方式的另一实施例中电容结构的部分俯视结构示意图。在另一实施例中，所述半导体结构中也可以不包括所述第二隔离层55(如图3所示)即所述电介质层24包覆所述下电极层23，所述上电极层25覆盖整个所述电介质层24的表面，以进一步增大所述电容器的电容量。具体地，如图1和图3所示，所述电容器包括：
下电极层23，包括第一子下电极层、以及与所述第一子下电极层相交的第二子下电极层，所述下电极层23与所述晶体管接触电连接；
电介质层24，连续包覆所述下电极层23的表面；
上电极层25，连续包覆所述电介质层24的表面；
其中，所述第一子下电极层定义出所述主体部32的位置，所述第二子下电极层31定义出所述延伸部的位置。如图1至图3所示，在一些实施例中，多个所述存储单元28可以沿第一方向D1和第二方向D2呈阵列排布，所述第一方向D1和所述第二方向D2均为平行于所述衬底10的顶面的方向，且所述第一方向D1与所述第二方向D2相交；所述半导体结构还包括：
多条沿第二方向D2延伸的字线，所述字线电连接沿所述第二方向D2上排布的多个所述存储单元28；
多条沿第一方向D1延伸的位线12，所述位线12位于所述字线下方，且电连沿所述第一方向上排布的多个存储单元28。
具体来说，所述半导体结构包括沿所述第二方向D2间隔排布的多个所述存储单元28，多个所述晶体管一一位于多个所述存储单元28内。所述晶体管包括栅电极18、源电极和漏电极。所述字线沿所述第二方向D2延伸，且连续与多个所述存储单元28内的所述晶体管的栅电极18接触电连接。所述位线12位于所述字线下方、且沿与所述第二方向D2相交的所述第一方向D1延伸。在一实施例中，所述第一方向D1和所述第二方向D2均为平行于所述衬底10的顶面的方向。
在一实施例中，所述位线12可以是位于所述衬底10内，即形成埋入式位线结构。如图1所示，在另一实施例中，所述位线12可以位于所述衬底10上方，从而可以简化所述位线12的制程工艺。以所述位线12位于所述衬底10上方为例，所述位线12与所述衬底10之间还可以设置衬底隔离层11，用于隔离所述衬底10与所述位线12。所述位线12与所述字线之间还可以包括第五隔离层。所述第五隔离层可以为单层结构，也可以为多层结构。所述存储单元还包括位线接触插塞17，所述位线接触插塞17沿所述第三方向D3贯穿所述第五隔离层，且所述位线接触插塞17的一端与所述晶体管的源电极接触电连接、另一端与所述位线12接触电连接。
如图1所示，在一实施例中，所述第五隔离层包括覆盖于所述位线12表面的第一介质层13、覆盖于所述第一介质层13表面的第二介质层14、覆盖于所述第二介质层14表面的第三介质层15、以及覆盖于所述第三介质层15表面的第四介质层16。在一实施例中，所述第一介质层13的材料可以为氧化物材料(例如二氧化硅)，所述第二介质层14的材料可以为氮化物材料(例如氮化硅)，所述第三介质层15的材料可以为聚酰亚胺，所述第四介质层16的材料可以为氮化物材料(例如氮化硅)。通过设置多层结构的所述第五隔离层，在增强所述位线12与所述字线电性隔离效果的同时，还有助于进一步降低所述位线12与所述字线之间的电容寄生效应。
如图1所示，在一些实施例中，多个所述存储单元28沿第三方向D3堆叠排布，所述第三方向D3为垂直于所述衬底10的顶面的方向，从而形成具有三维结构的所述半导体结构，以进一步提高所述半导体结构的集成度和存储容量。
本具体实施方式还提供了一种半导体结构的形成方法，附图4是本公开具体实施方式中半导体结构的形成方法流程图，附图5A-5N是本公开具体实施方式在形成半导体结构的过程中主要的工艺结构示意图。本具体实施方式形成的半导体结构的示意图可以参见图1-图3。如图1-图4、图5A-图5N所示，所述半导体结构的形成方法，包括如下步骤：步骤S11，提供衬底10；
形成多个存储单元于所述衬底上方，多个所述存储单元的形成步骤包括：步骤S12，形成晶体管于所述衬底10上；步骤S13，形成电容器，所述电容器与所述晶体管电连接，且所述电容器包括主体部32、以及位于所述主体部32的侧面且与所述主体部32电连接的延伸部31。
在一些实施例中，形成晶体管于所述衬底10上之前，还包括如下步骤：
形成多条沿所述第二方向D2间隔排布的位线12，每条所述位线12沿第一方向D1延伸，所述第一方向D1和所述第二方向D2均为平行于所述衬底10的顶面的方向，且所述第一方向D1与所述第二方向D2相交；
形成覆盖所述位线12的第五隔离层。
具体来说，如图5A所示，沉积氧化物(例如二氧化硅)等绝缘介质材料于所述衬底10的顶面、并进行化学机械研磨等平坦化工艺处理，形成衬底隔离层11。之后，图案化所述衬底隔离层11，于所述衬底隔离层11中形成多个沿所述第一方向D1延伸的位线沟槽，且多个所述位线沟槽沿所述第二方向D2间隔排布。所述位线沟槽沿所述第三方向D3未贯穿所述衬底隔离层11，所述第三方向D3为垂直于所述衬底10的顶面的方向。沉积金属钨等导电材料于所述位线沟槽内，形成所述位线12。接着，形成覆盖所述位线12的所述第五隔离层。第五隔离层可以包括单层或者多层结构，在一实施例中，所述第五隔离层包括覆盖于所述位线12表面的第一介质层13、覆盖于所述第一介质层13表面的第二介质层14、覆盖于所述第二介质层14表面的第三介质层15、以及覆盖于所述第三介质层15表面的第四介质层16。
在一些实施例中于，形成晶体管于所述衬底10上的具体步骤包括：
于所述衬底10上方定义沿所述第二方向D2间隔排布的多个晶体管区域；
形成栅电极18于每个所述晶体管区域内、并形成沿所述第二方向D2延伸且连续连接多个所述栅电极18的字线，如图5A所示，其中，图5A中的(a)为截面示意图，图5A中的(b)为俯视图；
于所述字线上方形成沿所述第二方向D1延伸、且连续覆盖多个所述晶体管区域的沟道层29；
于每一个所述晶体管区域内形成至少覆盖于所述沟道层29表面的源电极22和漏电极21，所述沟道层29至少位于所述源电极22和所述漏电极21之间，如图5B所示，其中，图5B中的(a)为截面示意图，图5B中的(b)为俯视图。
在一些实施例中，于所述字线上方形成沿所述第二方向D1延伸、且连续覆盖多个所述晶体管区域的沟道层29的具体步骤包括：
沉积非晶材料于所述字线上方，形成所述沟道层29。
具体来说，可以沉积字线材料(例如金属钨)于所述第五隔离层上方，其中，位于所述晶体管区域内的所述字线材料形成所述晶体管的所述栅电极18，位于相邻所述栅电极18的所述字线材料形成所述字线。之后，沉积TiN等材料于所述字线和所述栅电极18上方，形成扩散阻挡层19，如图5A所示，以阻挡所述栅电极18中的导电粒子向外扩散。之后，沉积氧化物(例如二氧化硅、氧化铝等介质材料)于所述扩散阻挡层19表面、所述栅电极18侧壁、所述字线侧壁和所述第五隔离层表面，形成所述栅极介质层20。沉积IGZO等非晶材料于所述栅极介质层20表面，形成所述沟道层29。沉积金属钨等源漏金属材料于所述沟道层29的表面和所述栅极介质层20的表面，形成所述源电极22和所述漏电极21，如图5B所示。
在一些实施例中，于每一个所述晶体管区域内形成至少覆盖于所述沟道层29表面的源电极22和漏电极21之后，还包括如下步骤：
形成至少贯穿所述第五隔离层的位线接触插塞17，所述位线接触插塞17的一端与所述位线12电连接、另一端与所述源电极22电连接，如图5C所示。
在一些实施例中，形成电容器的步骤包括：
形成覆盖所述晶体管的第一隔离层33；
于所述第一隔离层33上方形成第二隔离层55，如图5E所示，其中，图5E中的(a)为截面示意图，图5E中的(b)为俯视图；
于所述衬底10上方定义沿所述第二方向D2间隔排布的多个电容区域，多个所述电容区域用于分别形成多个所述电容器；
于每个所述电容区域内形成沿第三方向D3贯穿所述第二隔离层55的子槽51(如图5F所示，其中，图5F中的(a)为截面示意图，图5F中的(b)为俯视图)、以及沿所述第三方向D3贯穿所述第二隔离层55和所述第一隔离层33的连通槽53，所述电容区域内的所述连通槽53连通同一所述电容区域内的多个所述子槽51，如图5H所示，其中，图5H中的(a)为截面示意图，图5H中的(b)为俯视图，所述第三方向D3为垂直于所述衬底10的顶面的方向；
形成所述延伸部31于所述子槽51内、并形成所述主体部32于所述连通槽53内。
在一些实施例中，于所述第一隔离层33上方形成第二隔离层55的具体步骤包括：
形成覆盖所述第一隔离层33的第四隔离层27；
形成覆盖所述第四隔离层27的初始第二隔离层50，如图5D所示；
回刻蚀所述初始第二隔离层50，于所述初始第二隔离层50的端部形成暴露所述第四隔离层27的隔离沟槽，残留的所述初始第二隔离层50作为所述第二隔离层55，如图5E所示；
于所述隔离沟槽内形成第三隔离层26，如图5E所示。
在一些实施例中，形成沿第三方向D3贯穿所述第二隔离层55的子槽51、以及沿所述第三方向D3贯穿所述第二隔离层55和所述第一隔离层33的连通槽53，具体步骤包括：
沿第一方向D1刻蚀第二隔离层55，形成多个子槽51，多个子槽51沿第二方向D2将剩余的第二隔离层55彼此间隔；
沿第二方向D2选择性地刻蚀剩余的第二隔离层55，形成多个连通槽53，每个连通槽53将至少两个子槽51连通；此时相邻子槽51之间仍然具有第二隔离层55。
沿连通槽53继续刻蚀第四隔离层27和第一隔离层33，至暴露晶体管的漏电极21，形成电容孔。在本公开实施例中，至少两个子槽51和单个连通槽53形成单个电容孔，每个电容孔可以暴露单个晶体管的漏电极21，以使得后续的在电容孔内沉积的下电极的表面积可以进一步增加，同时也使得下电极直接连接晶体管。当然在另外的一些实施例中，也可以不沿连通槽53继续刻蚀第四隔离层27和第一隔离层33至暴露晶体管漏电极21，可以通过电容接触插塞结构，将电容下电极连接晶体管的漏电极21。
具体来说，可以采用光刻工艺图案化所述第二隔离层55，形成多个沿所述第三方向D3贯穿所述第二隔离层55的所述子槽51，如图5F所示。其中，每个所述电容区域至少包括两条所述子槽51。接着，形成填充满所述子槽51的牺牲层52，如图5G所示，其中，图5G中的(a)为截面示意图，图5G中的(b)为俯视图。之后，刻蚀所述牺牲层52和部分残留的所述第二隔离层55，形成多个贯穿所述牺牲层52和所述第二隔离层55的所述连通槽53。之后，沿所述连通槽53继续向下刻蚀所述第四隔离层27和所述第一隔离层33，延伸所述连通槽53至所述晶体管的所述漏电极51表面。所述电容区域内的所述连通槽53至少与位于同一所述电容区域内的两个所述子槽51相交，形成一个所述电容孔，如图5H所示。在一实施例中，所述连通槽53的底部暴露所述漏电极21，如图5I所示，图5I为俯视图。所述连通槽53的底部暴露所述漏电极21是指，所述连通槽53在所述衬底10的顶面上的投影与所述晶体管的所述漏电极21在所述衬底10的顶面上的投影至少部分重叠。
在一些实施例中，如图5K、5M，和图1-2所示，形成所述延伸部31于所述子槽51内、并形成所述主体部32于所述连通槽53内的具体步骤包括：
形成连续覆盖所述子槽51内壁和所述连通槽53内壁的下电极层23，如图5J所示，其中，图5J中的(a)为截面示意图，图5J中的(b)为俯视图；
形成覆盖所述下电极层23的表面和所述第二隔离层55的顶面的电介质层24，如图5K所示，其中，图5K中的(a)为截面示意图，图5K中的(b)为俯视图；
形成覆盖所述电介质层24表面的上电极层25，如图5M所示，所述延伸部31包括位于所述子槽51 内的所述下电极层23、所述电介质层24和所述上电极层25，所述主体部32包括位于所述连通槽53内的所述下电极层23、所述电介质层54和所述上电极层25。该实施例中，至少2个子槽51和单个连通槽53形成单个电容孔，在电容孔内沉积形成的下电极层23，相邻下电极层之间彼此独立，在下电极层23表面形成电介层24时，相邻电介质层24彼此连接，即电容器中的电介质层24共用，之后，在电介质层24表面上电极层25时，相邻上电极层25彼此连接，电容器中的上电极层25也是共用的。
具体来说，在形成所述子槽51和所述连通槽53之后，去除所述牺牲层52，并沉积连续覆盖所述子槽51内壁和所述连通槽53内壁的下电极材料。其中，位于所述子槽51内壁的所述下电极材料作为第一子下电极层，位于所述连通槽53内壁的所述下电极材料作为第二子下电极层，所述第一子下电极层和所述第二子下电极层共同作为所述下电极层23。之后，沉积连续覆盖所述下电极层23的表面和所述第二隔离层55的顶面的所述电介质层24，并沉积覆盖所述电介质层24表面的所述上电极层25。所述延伸部31包括位于所述子槽51内的所述下电极层23、所述电介质层24和所述上电极层25，所述主体部32包括位于所述连通槽53内的所述下电极层23、所述电介质层54和所述上电极层25，且所述延伸部31中的各层(包括所述下电极层23、所述电介质层24和所述上电极层25)与所述主体部32中的各层(包括所述下电极层23、所述电介质层24和所述上电极层25)同步沉积形成，在简化所述半导体结构的制造工艺的同时，还能降低所述电容器内部的电阻。
在另一些实施例中，如图5L-M，和图1、图3所示，形成所述延伸部31于所述子槽51内、并形成所述主体部32于所述连通槽53内的具体步骤包括：
形成连续覆盖所述子槽51内壁和所述连通槽53内壁的下电极层23；
去除所述第二隔离层55；
形成覆盖所述下电极层23表面的电介质层24，如图5L所示；
形成覆盖所述电介质层24的表面的上电极层25，其中，位于子槽51中的下电极层23、所述电介质层24和所述上电极层25共同构成所述延伸部31，位于连通槽53中的所述下电极层23、所述电介质层24和所述上电极层25共同构成所述主体部32。
具体来说，在形成所述下电极层23之后，可以去除所述第二隔离层55，使得后续形成的所述电介质层24包覆所述下电极层23，从而进一步增大所述电容器的表面积，提高电容器的电容量。
在一些实施例中，所述半导体结构的形成方法还包括：
依次形成沿第三方向D3堆叠排布的多个所述存储单元28于所述衬底10上方，所述第三方向D3为与所述衬底10的顶面垂直的方向，如图5N所示。
本具体实施方式一些实施例提供的半导体结构及其形成方法，在晶体管结构上方设置电容结构，且所述电容结构包括多个电容器，通过设置每个所述电容器包括相交的延伸部和主体部，来增大所述电容器的尺寸，进而达到增大电容器的电容量，以提高半导体结构的存储容量。另外，本具体实施方式中包括所述延伸部和所述主体部的所述电容器是位于晶体管结构的上方的，从而能够充分利用衬底上方的三维空间，减少对衬底表面积的占用，提高了半导体结构内部的空间利用率，从而有助于进一步控制所述半导体结构的尺寸，扩大所述半导体结构的应用领域。本具体实施方式的实施例中,不仅可以增加单层的尺寸，还可以实现三维半导体结构的多层堆叠，减少工艺难度，提高半导体结构的存储密度。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (17)

  1. 一种半导体结构，包括位于衬底上的多个存储单元，每个所述存储单元包括：
    晶体管；
    电容器，电连接所述晶体管，所述电容器包括主体部、以及位于所述主体部的侧面且与所述主体部电连接的延伸部。
  2. 根据权利要求1所述的半导体结构，其中，所述电容器中的所述延伸部的数量为多个，且多个所述延伸部至少分布于所述主体部的一侧。
  3. 根据权利要求1所述的半导体结构，其中，所述电容器中的所述延伸部的数量为多个，且多个所述延伸部至少沿第一方向分布于所述主体部的相对两侧，所述第一方向为平行于所述衬底的顶面的方向。
  4. 根据权利要求1所述的半导体结构，其中，所述晶体管包括：
    源电极/漏电极，所述源电极/漏电极中之一电连接所述电容器；
    沟道层，位于所述源电极/漏电极中的源电极和漏电极之间；
    栅电极，所述沟道层至少包围部分所述栅电极。
  5. 根据权利要求1～4任意一项所述的半导体结构，其中，所述延伸部在所述衬底上的投影沿第一方向的宽度大于所述主体部在所述衬底的上的投影沿所述第一方向的宽度，且所述主体部与所述晶体管电连接。
  6. 根据权利要求1或5所述的半导体结构，其中，所述电容器包括：
    下电极层，包括第一子下电极层、以及与所述第一子下电极层相交的第二子下电极层，所述下电极层与所述晶体管接触电连接；
    电介质层，覆盖所述下电极层的内表面；
    上电极层，覆盖所述电介质层的表面；
    其中，所述第一子下电极层定义出所述主体部的位置，所述第二子下电极层定义出所述延伸部的位置。
  7. 根据权利要求1或5所述的半导体结构，其中，所述电容器包括：
    下电极层，包括第一子下电极层、以及与所述第一子下电极层相交的第二子下电极层，所述下电极层与所述晶体管接触电连接；
    电介质层，连续包覆在所述下电极层的表面；
    上电极层，连续包覆在所述电介质层的表面；
    其中，所述第一子下电极层定义出所述主体部的位置，所述第二子下电极层定义出所述延伸部的位置。
  8. 根据权利要求1所述的半导体结构，其中，所述晶体管位于所述电容器的下方，且二者之间具有第一隔离层，其中，所述电容器的所述主体部贯穿所述第一隔离层，以电连接所述晶体管。
  9. 根据权利要求1所述的半导体结构，其中，多个所述存储单元沿第一方向和第二方向呈阵列排布，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；所述半导体结构还包括：
    多条沿所述第二方向延伸的字线，所述字线电连接沿所述第二方向上排布的多个存储单元；
    多条沿所述第一方向延伸的位线，所述位线位于所述字线下方，且电连接沿所述第一方向上排布的多个存储单元。
  10. 根据权利要求1或9所述的半导体结构，其中，多个所述存储单元还沿第三方向堆叠排布，所述第三方向为垂直于所述衬底的顶面的方向。
  11. 一种半导体结构的形成方法，包括如下步骤：
    提供衬底；
    形成多个存储单元于所述衬底上，多个所述存储单元的形成步骤包括：
    形成晶体管于所述衬底上；
    形成电容器，所述电容器与所述晶体管电连接，且所述电容器包括主体部、以及位于所述主体部的侧面且与所述主体部电连接的延伸部。
  12. 根据权利要求11所述的半导体结构的形成方法，其中，形成晶体管于所述衬底上之前，还包括如下步骤：
    形成多条沿第二方向间隔排布的位线，每条所述位线沿第一方向延伸，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；
    形成覆盖所述位线的第三隔离层。
  13. 根据权利要求12所述的半导体结构的形成方法，其中，形成晶体管于所述衬底上的具体步骤包括：
    于所述衬底上方定义沿所述第二方向间隔排布的多个晶体管区域；
    形成栅电极于每个所述晶体管区域内、并形成沿所述第二方向延伸且连续连接多个所述栅电极的字线；
    于所述字线上方形成沿所述第二方向延伸、且连续覆盖多个所述晶体管区域的沟道层；
    于每一个所述晶体管区域内形成至少覆盖于所述沟道层表面的源电极和漏电极，所述沟道层至少位于所述源电极和所述漏电极之间。
  14. 根据权利要求12或13所述的半导体结构的形成方法，其中，形成电容器的步骤包括：
    形成覆盖所述晶体管的第一隔离层；
    于所述第一隔离层上方形成第二隔离层；
    于所述衬底上方定义沿所述第二方向间隔排布的多个电容区域，多个所述电容区域用于分别形成多个所述电容器；
    于所述电容区域内形成沿第三方向贯穿所述第二隔离层的子槽、以及沿所述第三方向贯穿所述第二隔离层和所述第一隔离层的连通槽，所述电容区域内的所述连通槽连通同一所述电容区域内的多个所述子槽，所述第三方向为垂直于所述衬底的顶面的方向；
    形成所述延伸部于所述子槽内、并形成所述主体部于所述连通槽内。
  15. 根据权利要求14所述的半导体结构的形成方法，其中，形成所述延伸部于所述子槽内、并形成所述主体部于所述连通槽内的具体步骤包括：
    形成连续覆盖所述子槽内壁和所述连通槽内壁的下电极层；
    形成覆盖所述下电极层的表面和所述第二隔离层的顶面的电介质层；
    形成覆盖所述电介质层表面的上电极层，所述延伸部包括位于所述子槽内的所述下电极层、所述电介质层和所述上电极层，所述主体部包括位于所述连通槽内的所述下电极层、所述电介质层和所述上电极层。
  16. 根据权利要求14所述的半导体结构的形成方法，其中，形成所述延伸部于所述子槽内、并形成所述主体部于所述连通槽内的具体步骤包括：
    形成连续覆盖所述子槽内壁和所述连通槽内壁的下电极层；
    去除所述第二隔离层；
    形成覆盖所述下电极层表面的电介质层；
    形成覆盖所述电介质层的表面的上电极层，其中，位于所述子槽中的所述下电极层、所述电介质层和所述上电极层共同构成所述延伸部，位于所述连通槽中的所述下电极层、所述电介质层和所述上电极层共同构成所述主体部。
  17. 根据权利要求11～16任意一项所述的半导体结构的形成方法，还包括：
    依次形成沿第三方向堆叠排布的多个所述存储单元于所述衬底上方，所述第三方向为与所述衬底的顶面垂直的方向。
PCT/CN2022/109461 2022-06-21 2022-08-01 半导体结构及其形成方法 WO2023245816A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP22839611.5A EP4329454A1 (en) 2022-06-21 2022-08-01 Semiconductor structure and forming method therefor
US18/170,631 US20230413523A1 (en) 2022-06-21 2023-02-17 Semiconductor structure and method for forming semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210704100.7A CN117337023A (zh) 2022-06-21 2022-06-21 半导体结构及其形成方法
CN202210704100.7 2022-06-21

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/170,631 Continuation US20230413523A1 (en) 2022-06-21 2023-02-17 Semiconductor structure and method for forming semiconductor structure

Publications (1)

Publication Number Publication Date
WO2023245816A1 true WO2023245816A1 (zh) 2023-12-28

Family

ID=85382997

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/109461 WO2023245816A1 (zh) 2022-06-21 2022-08-01 半导体结构及其形成方法

Country Status (2)

Country Link
CN (1) CN117337023A (zh)
WO (1) WO2023245816A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001036027A (ja) * 1999-05-14 2001-02-09 Matsushita Electronics Industry Corp 半導体装置及びその製造方法
CN108428702A (zh) * 2017-04-27 2018-08-21 睿力集成电路有限公司 动态随机存取存储器的制造方法
CN110957303A (zh) * 2018-09-26 2020-04-03 长鑫存储技术有限公司 电容器及其形成方法、半导体器件及其形成方法
CN111435661A (zh) * 2019-01-14 2020-07-21 英特尔公司 3d 1t1c堆叠dram结构及制造方法
CN112185961A (zh) * 2019-07-03 2021-01-05 美光科技公司 集成式组合件以及形成集成式组合件的方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001036027A (ja) * 1999-05-14 2001-02-09 Matsushita Electronics Industry Corp 半導体装置及びその製造方法
CN108428702A (zh) * 2017-04-27 2018-08-21 睿力集成电路有限公司 动态随机存取存储器的制造方法
CN110957303A (zh) * 2018-09-26 2020-04-03 长鑫存储技术有限公司 电容器及其形成方法、半导体器件及其形成方法
CN111435661A (zh) * 2019-01-14 2020-07-21 英特尔公司 3d 1t1c堆叠dram结构及制造方法
CN112185961A (zh) * 2019-07-03 2021-01-05 美光科技公司 集成式组合件以及形成集成式组合件的方法

Also Published As

Publication number Publication date
CN117337023A (zh) 2024-01-02

Similar Documents

Publication Publication Date Title
WO2022213534A1 (zh) 动态随机存取存储器及其形成方法
KR102581399B1 (ko) 반도체 메모리 소자
CN112951769B (zh) 半导体存储器及其形成方法
US20240081041A1 (en) Semiconductor structure and method for forming same
US20090114970A1 (en) Embedded dram with increased capacitance and method of manufacturing same
WO2023245816A1 (zh) 半导体结构及其形成方法
WO2022052628A1 (zh) 半导体结构和半导体结构的制造方法
WO2014126214A1 (ja) 半導体装置
US20220102206A1 (en) Semiconductor device, manufacturing method of semiconductor device, and storage device
WO2022077919A1 (zh) 半导体器件及其制造方法
US20230413523A1 (en) Semiconductor structure and method for forming semiconductor structure
US20230013060A1 (en) Semiconductor device and method for forming same
TWI827230B (zh) 半導體結構及其製造方法、記憶體晶片、電子設備
WO2024036877A1 (zh) 半导体结构及其形成方法
WO2024045328A1 (zh) 半导体结构及其形成方法
WO2023201849A1 (zh) 半导体结构及其形成方法
CN117529103B (zh) 半导体结构及其形成方法
US20110057240A1 (en) Semiconductor device and method of manufacturing the same
WO2023231196A1 (zh) 半导体结构及其形成方法
WO2024060676A1 (zh) 半导体结构和半导体结构的制造方法
US20240324182A1 (en) Semiconductor memory devices
WO2023245799A1 (zh) 半导体结构及其形成方法
US20230345712A1 (en) Semiconductor structure and method for forming semiconductor structure
WO2024051062A1 (zh) 半导体结构及其形成方法
US20230413508A1 (en) Semiconductor structure and method for manufacturing semiconductor structure

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2022839611

Country of ref document: EP

Effective date: 20230118