WO2024060676A1 - 半导体结构和半导体结构的制造方法 - Google Patents

半导体结构和半导体结构的制造方法 Download PDF

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Publication number
WO2024060676A1
WO2024060676A1 PCT/CN2023/098114 CN2023098114W WO2024060676A1 WO 2024060676 A1 WO2024060676 A1 WO 2024060676A1 CN 2023098114 W CN2023098114 W CN 2023098114W WO 2024060676 A1 WO2024060676 A1 WO 2024060676A1
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WIPO (PCT)
Prior art keywords
trench
sub
layer
source
electrode
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PCT/CN2023/098114
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English (en)
French (fr)
Inventor
韩清华
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from CN202211153790.8A external-priority patent/CN117794236A/zh
Priority claimed from CN202211153972.5A external-priority patent/CN117794238A/zh
Priority claimed from CN202211154217.9A external-priority patent/CN117794239A/zh
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to KR1020237026952A priority Critical patent/KR20240041857A/ko
Priority to EP23809952.7A priority patent/EP4369881A1/en
Priority to US18/450,509 priority patent/US20240098980A1/en
Publication of WO2024060676A1 publication Critical patent/WO2024060676A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • Embodiments of the present disclosure belong to the field of semiconductors, and specifically relate to a manufacturing method of a semiconductor structure and a semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • 3D DRAM is a structure that stacks multiple layers of memory cells. It has a higher degree of integration and a larger capacity per unit area, which helps reduce the cost per unit area. However, the performance of 3D DRAM still needs to be improved.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method of the semiconductor structure, which are at least beneficial to improving the performance of the semiconductor structure.
  • embodiments of the present disclosure provide a method of manufacturing a semiconductor structure, wherein the method of manufacturing a semiconductor structure includes: providing a substrate, forming a first trench and a second trench in the substrate.
  • the depth direction of both grooves is the first direction;
  • the first groove includes a plurality of first sub-grooves arranged in the first direction, and
  • the second groove includes a plurality of first sub-grooves arranged in the first direction.
  • the second sub-trench is arranged in the first direction, and the side walls of the first sub-trench and the second sub-trench are convex; at the junction of the adjacent first sub-trench Forming a word line protruding away from the first trench; forming a first source and drain layer on the sidewall of the first sub-trench; forming a word line at the junction of the adjacent second sub-trench facing away from the first trench.
  • the second source-drain layer protrudes from the second trench; the second source-drain layer and the word line are located between the first trench and the second trench, and the second source-drain layer
  • the drain layer is arranged opposite to the word line.
  • another aspect of the present disclosure further provides a semiconductor structure.
  • the semiconductor structure includes: a substrate having a first trench and a second trench in the substrate, and the depth direction of the two trenches is are all in the first direction; the first trench includes a plurality of first sub-trenches arranged in the first direction, and the second trench includes a plurality of second sub-trenches arranged in the first direction.
  • sub-trench, and the side walls of the first sub-trench and the second sub-trench are both convex; the junction of the adjacent first sub-trench has a surface facing away from the first trench.
  • a protruding word line; the sidewall of the first sub-trench has a first source-drain layer; the junction adjacent to the second sub-trench has a second source protruding away from the second trench. Drain layer; the second source and drain layer and the word line are located on the third Between a trench and the second trench, the second source and drain layer is arranged opposite to the word line.
  • a first trench and a second trench are formed in the substrate, the first trench includes a plurality of first sub-trenches, the second trench includes a plurality of second sub-trenches, the first sub-trench and the second sub-trench
  • the side walls of the grooves are all convex.
  • a word line protruding away from the first trench is formed at the junction of adjacent first sub-trench; a first source and drain layer is formed on the sidewall of the first sub-trench; and at the junction of adjacent second sub-trench A second source and drain layer protruding away from the second trench is formed.
  • a transistor is formed in the substrate based on the wavy sidewalls of the first trench and the second trench, thereby avoiding the use of indium gallium zinc oxide (IGZO) materials and superlattice (Superlattice) technology to form transistors. , thus helping to reduce defects in the semiconductor structure and improve the performance of the semiconductor structure.
  • IGZO indium gallium zinc oxide
  • Superlattice superlattice
  • Figure 44(a) is a partial enlarged view of Figure 43(a).
  • Figure 44(b) is a partial enlarged view of Figure 43(b).
  • Figure 44(c) is an enlarged partial cross-sectional view of the semiconductor structure.
  • 45 to 46, 48 to 49, and 51 to 52 show different top views of the semiconductor structure provided by an embodiment of the present disclosure in the back-end process.
  • Figure 47 shows a schematic diagram of a step region in a semiconductor structure provided by yet another embodiment of the present disclosure.
  • FIG. 50 shows a partial cross-sectional view of a bit line connection line in a semiconductor structure provided by yet another embodiment of the present disclosure.
  • 3D DRAM mainly includes two types. The first one is based on indium gallium zinc oxide (IGZO) material, forming a vertical annular channel device structure (CAA, Channel-All-Around). ) 3D DRAM, however, the uniformity of the IGZO material is difficult to control and there are many defects; the second one is based on superlattice technology, forming a structure composed of alternating layers of different materials, that is, silicon and germanium silicon. Alternating layers, however depositing multiple layers of silicon and germanium will cause more interface defects.
  • IGZO indium gallium zinc oxide
  • CAA Vertical annular channel device structure
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including: forming a first trench in a substrate A groove and a second groove, the first groove includes a plurality of first sub-grooves, the second groove includes a plurality of second sub-grooves, the side walls of the first sub-grooves and the second sub-grooves are both outwardly Convex shape.
  • a word line protruding away from the first trench is formed at the junction of adjacent first sub-trench; a first source and drain layer is formed on the side wall of the first sub-trench; and at the junction of adjacent second sub-trench A second source and drain layer protruding away from the second trench is formed.
  • a transistor is formed in the substrate based on the wavy sidewalls of the first trench and the second trench, thereby avoiding the use of IGZO and Superlattice technologies to form transistors, thereby reducing defects in the semiconductor structure and improving the performance of the semiconductor structure.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
  • the following will be implemented in conjunction with the accompanying drawings.
  • the manufacturing method of the semiconductor structure provided by the example is described in detail. It should be noted that, in order to facilitate the description and clearly illustrate the steps of the semiconductor structure manufacturing method, Figure 1(a), Figure 1(b) to Figure 27(a), and Figure 27(b) are all partial structures of the semiconductor structure. Schematic diagram.
  • Figure 1(b) is a top view of the semiconductor structure shown in Figure 1(a).
  • a substrate 1 is provided, and a first trench 2 is formed in the substrate 1.
  • the depth direction of the first trench 2 is the first direction X; the first trench 2 includes a plurality of first sub-trenches 20 arranged in the first direction shape. That is, the side walls of the first trench 2 have a wavy shape.
  • white filling blocks are used to illustrate the first trench 2 in FIG. 1(b) and subsequent top views.
  • the first trench 2 is formed using the Bosch process.
  • the Bosch process consists of two alternating steps of etching and passivation. First, use isotropic etching to form a first sub-trench 20; form a passivation layer on the inner wall of the first sub-trench 20; remove the passivation layer at the bottom of the first sub-trench 20; use isotropic etching.
  • Another first sub-trench 20 is formed. That is, the etching and passivation processes are repeated to form a plurality of first sub-trenches 20 to form the first trench 2 .
  • the material of substrate 1 may be single crystal silicon.
  • the etching gas used in the Bosch process can be sulfur hexafluoride, and the passivation gas can be octafluorocyclobutane.
  • doped ions in the substrate 1 there may be doped ions in the substrate 1, and the type of doped ions in the substrate 1 may be different from those in the subsequently formed first source and drain layers 61 and second source and drain layers 62 (refer to FIG. 27(a)).
  • the doping ions are of the opposite type.
  • the depth h of the first sub-trench 20 in the first direction The size s of the first sub-trench 20 protruding toward the substrate 1 is about tens of nanometers, thereby facilitating the subsequent formation of the hole 24 (refer to FIG. 5 ).
  • Figure 2(b) is a top view of the semiconductor structure shown in Figure 2(a).
  • a first isolation film 21 is formed on the side wall of the first trench 2.
  • the first isolation film 21 adjacent to the junction of the first sub-trench 20 is protruding toward the inside of the first sub-trench 20 . That is, since the side walls of the first trench 2 have a wavy shape, the first isolation film 21 formed on the side walls of the first trench 2 also has a wavy shape.
  • the thickness of the first isolation film 21 may be 20 nm to 50 nm. It should be noted that when the thickness of the first isolation film 21 is within the above range, it can be convenient to retain the first isolation film 21 on the side of the first sub-trench 20 when the first isolation film 21 at the junction of adjacent first sub-trench 20 is subsequently removed.
  • the first isolation membrane 21 of the wall is a first isolation membrane 21 of the wall.
  • the thickness of the first isolation film 21 is too large, it is difficult to expose the substrate 1 located at the intersection of adjacent first sub-trenches 20; if the thickness of the first isolation film 21 is too small, it is possible to remove all the third sub-trenches 20 at the same time.
  • An isolation film 21 is provided.
  • part of the first isolation film 21 may also cover the upper surface of the substrate 1 , and this part of the first isolation film 21 will be removed later.
  • Figure 3(b) is a top view of the semiconductor structure shown in Figure 3(a).
  • the substrate 1 is etched along the first direction A portion of the first isolation film 21 adjacent to the junction of the first sub-trench 20 . That is, an anisotropic etching process is used to cut flat the protruding first isolation film 21 at the junction of adjacent first sub-trenches 20, thereby making the first isolation film 21 there thin.
  • an isotropic etching process is used to remove the remaining first isolation film 21 located at the junction of adjacent first sub-trenches 20 to expose the liner located at the junction of adjacent first sub-trench 20 .
  • Bottom 1. The top view of the semiconductor structure in this step has not changed, and you can refer to Figure 3(b).
  • the first isolation film 21 at the junction of adjacent first sub-trench 20 is thinner than the first isolation film 21 on the side wall of the first sub-trench 20; in isotropic etching During the etching process, the first isolation film 21 at the junction of adjacent first sub-trenches 20 will be removed faster, thereby exposing a certain width of the substrate 1 .
  • the width L of the exposed substrate 1 at the junction of adjacent first sub-trenches 20 is 20 nm ⁇ 50 nm. It should be noted that when the width of the exposed substrate 1 is within the above range, it is beneficial to the subsequent formation of holes 24 of appropriate size, that is, to avoid the inner diameter of the holes 24 being too small or the interconnection of adjacent holes 24.
  • the first isolation film 21 located at the junction of adjacent first sub-trenches 20 can be removed to expose the adjacent first sub-trench 20 .
  • Trench 20 interfaces with substrate 1 .
  • the substrate 1 exposed by the first isolation film 21 is etched to form a hole 24 .
  • the top view of the semiconductor structure in this step has not changed, and you can refer to Figure 3(b).
  • the exposed substrate 1 is isotropically etched, so that the substrate 1 is further opened to form the hole 24 .
  • the depth of the hole 24 may be 100 nm ⁇ 200 nm. It should be noted that if the depth of the hole 24 is too small, it may be difficult for the hole 24 to provide sufficient filling position for the word line 32, thereby increasing the resistance of the word line 32; Defects such as voids occur in the line 32. When the depth of the hole 24 is within the above range, subsequent filling of the word line 32 can be facilitated, ensuring that the word line 32 has an appropriate size, and reducing defects in the word line 32, thereby improving the performance of the semiconductor structure.
  • a hole protruding away from the first trench 2 can be formed at the junction of adjacent first sub-trenches 20 twenty four. That is, the first isolation film 21 can be used as a mask layer for forming the holes 24 to control the position and size of the holes 24 .
  • a gate dielectric layer 31 is formed on the inner wall of the hole 24 .
  • the top view of the semiconductor structure in this step has not changed, and you can refer to Figure 3(b).
  • a thermal oxidation process is used to form silicon oxide on the inner wall of the hole 24 as the gate dielectric layer 31 of the transistor.
  • an atomic layer deposition process may be used to deposit a high dielectric constant material on the inner wall of the hole 24 as the gate dielectric layer 31 .
  • Figure 7(b) is a top view of the semiconductor structure shown in Figure 7(a).
  • An initial word line 321 is formed on the sidewall of the first trench 2 and in the hole 24.
  • an isotropic deposition process is used to deposit tungsten and titanium nitride as the initial word line 321 .
  • Figure 8(b) is a top view of the semiconductor structure shown in Figure 8(a).
  • An isotropic etching process is used to remove the sidewalls and Part of the initial word line 321 in the hole 24 and the remaining initial word line 321 in the hole 24 serve as the word line 32 .
  • the word line 32 serves as the gate of the transistor, and the gate dielectric layer 31 also covers the word line 32 .
  • the gate dielectric layer 31 covers the side of the word line 32 away from the inside of the first trench 2 .
  • a back-facing first trench can be formed at the interface of adjacent first sub-trenches 20
  • the word line 32 protrudes from the groove 2, and the word line 32 extends along the third direction Z.
  • Figure 9(b) is a top view of the semiconductor structure shown in Figure 9(a).
  • An initial insulating layer is formed in the hole 24 and on the sidewall of the first sub-trench 20. 331.
  • an isotropic deposition process is used to deposit silicon nitride as the initial insulating layer 331 to close the hole 24 .
  • the material of the initial insulating layer 331 may be different from the material of the first isolation film 21 , thereby avoiding the removal of the insulating layer 33 during the subsequent removal of the first isolation film 21 .
  • Figure 10(b) is a top view of the semiconductor structure shown in Figure 10(a) to illustrate
  • the bottom 1 itself is a mask, and the initial insulating layer 331 located on the sidewall of the first sub-trench 20 is etched along the first direction X, and the remaining initial insulating layer 331 serves as the insulating layer 33 .
  • the side walls of the insulating layer 33 are flush with the opening of the hole 24 .
  • the gate dielectric layer 31 also covers the surface of the insulating layer 33 .
  • the insulating layer 33 can be formed in the hole 24 , and the insulating layer 33 is located on the word line 32 toward the third One side of trench 2.
  • the purpose of forming the insulating layer 33 mainly includes two aspects: first, to isolate the word line 32 from the subsequently formed capacitor plate 72 (refer to FIG. 26(a) ) to avoid short circuit; second, The insulating layer 33 may face the subsequently formed first source and drain layer 61 (refer to FIG. 24 ) in the first direction risk.
  • Figure 11(b) is a top view of the semiconductor structure shown in Figure 11(a).
  • the word line 32 After forming the word line 32, it also includes: filling the first trench 2 with sacrificial material. Layer 22.
  • the sacrificial layer 22 can protect the first trench 2 from contamination in the subsequent steps of forming the second trench 5, the second source and drain layer 62, the second metal silicide layer 63 and the bit line 64, thereby ensuring the performance of the semiconductor structure. .
  • silicon oxide is deposited in the first trench 2 as the sacrificial layer 22 .
  • a planarization process may also be performed to smooth the upper surface of the substrate 1 and the upper surface of the sacrificial layer 22 .
  • the material of the sacrificial layer 22 can be the same as the material of the first isolation film 21. In this way, the sacrificial layer 22 and the first isolation film 21 can be subsequently removed using the same process step, thereby simplifying the production process.
  • Figure 12 is a top view. Part of the substrate 1 and part of the sacrificial layer 22 are removed to form a plurality of isolation trenches 4 arranged at intervals. The plurality of isolation trenches 4 extend in the second direction Y and extend in the third direction Z. arranged on top.
  • a mask is formed on the substrate 1 and the sacrificial layer 22, and the substrate 1 and the sacrificial layer 22 are etched using the mask. It should be noted that the word line 32 cannot be cut off during the etching process.
  • Figure 13 is a top view, forming a plurality of first isolation structures 41 arranged at intervals; the plurality of first isolation structures 41 extend along the second direction Y and are arranged in the third direction Z.
  • the first isolation structure 41 covers a plurality of word lines 32 , that is, the first isolation structure 41 does not cut off the word lines 32 .
  • the first isolation structure 41 also divides the sacrificial layer 22 into multiple pieces.
  • silicon nitride is filled in the isolation trench 4 as the first isolation structure 41 , and thereafter, a planarization process is performed to smooth the upper surfaces of the substrate 1 , the sacrificial layer 22 and the first isolation structure 41 .
  • the material of the first isolation structure 41 may be different from the material of the sacrificial layer 22 , thereby avoiding consumption of the first isolation structure 41 during subsequent removal of the sacrificial layer 22 .
  • Figure 14(b) is a top view of the semiconductor structure shown in Figure 14(a).
  • a second trench is formed in the substrate 1 5.
  • the depth direction of the second trench 5 is the first direction X; the second trench 5 includes a plurality of second sub-grooves 50 arranged in the first direction shape. That is, the second groove 5 also has wavy side walls.
  • the first isolation structure 41 also spans the first trench 2 and the second trench 5 .
  • white filling blocks are used to illustrate the second trench 5 in Figure 14(b) and subsequent top views.
  • the second trench 5 is formed using the Bosch process.
  • the specific formation process of the second trench 5 please refer to the detailed description of the first trench 2.
  • first isolation structure 41 and the substrate 1 may be made of different materials, so the first isolation structure 41 may not be removed during the process of etching the substrate 1 to form the second trench 5 .
  • the second trench 5 extending along the third direction Z may be formed first, and then the first isolation structure 41 extending along the second direction Y may be formed to divide the second trench 5 into Multiple.
  • the first trench 2 and the second trench 5 are first formed in the same process step; thereafter, the second trench 5 is filled with sacrificial material; thereafter, the first isolation film 21, word line 32, insulation layer 33 and other structures; thereafter, a first isolation structure 41 is formed to span the first trench 2 and the second trench 5. Since the first trench 2 and the second trench 5 can be integrated in the same process step, the production process is simplified.
  • FIG. 15(b) is a top view of the semiconductor structure shown in FIG. 15(a), and an initial second isolation film 511 is formed on the sidewall of the second trench 5, and the initial second isolation film 511 located at the junction of adjacent second sub-trench 50 is protruded toward the inside of the second sub-trench 50. That is, since the sidewall of the second trench 5 has a wavy shape, the initial second isolation film 511 formed on the sidewall of the second trench 5 also has a wavy shape.
  • an isotropic deposition process is used to form a silicon nitride film as the initial second isolation film 511.
  • Figure 16(b) is a top view of the semiconductor structure shown in Figure 16(a).
  • the substrate 1 itself is used as a mask, and the phase is etched along the first direction X.
  • the portion adjacent to the junction of the second sub-trench 50 is the initial second isolation film 511 . That is, an anisotropic etching process is used to cut flat the protruding initial second isolation film 511 at the junction of adjacent second sub-trenches 50, thereby making the initial second isolation film 511 there thin.
  • an isotropic etching process is used to remove the remaining initial second isolation film 511 located at the junction of adjacent second sub-trench 50 to expose the remaining initial second isolation film 511 located at the junction of adjacent second sub-trench 50 .
  • the remaining initial second isolation film 511 serves as the second isolation film 51. That is to say, in the isotropic etching process, the thin initial second isolation film 511 at the junction of adjacent second sub-trenches 50 will be removed faster, thereby exposing a certain width of the substrate 1 .
  • the top view of the semiconductor structure in this step has not changed, and you can refer to Figure 16(b).
  • the initial second isolation film 511 located at the junction of adjacent second sub-trenches 50 can be removed to expose the adjacent second isolation film 511 .
  • the substrate 1 at the junction of the sub-trenches 50 can be removed to expose the adjacent second isolation film 511 .
  • the substrate 1 exposed by the second isolation film 51 is doped to form a second source and drain layer 62 .
  • a plasma doping process is used to inject n-type doping ions into the substrate 1 to form the second source and drain layer 62 .
  • the top view of the semiconductor structure in this step has not changed, and you can refer to Figure 16(b).
  • the second source and drain layer 62 and the word line 32 are both located between the first trench 2 and the second trench 5 , and the second source and drain layer 62 is opposite to the word line 32 .
  • the second source and drain layer 62 is also in contact with the gate dielectric layer 31 .
  • the second source and drain layers 62 arranged adjacently in the third direction Z are separated by the first isolation structure 41 to avoid mutual interference.
  • the second source and drain layers 62 arranged in the first direction X are separated by the second isolation film 51 to avoid interconnection.
  • the second sub-trench 50 protruding away from the second trench 5 can be formed at the junction of the adjacent second sub-trench 50 .
  • a portion of the second source-drain layer 62 near the inside of the second trench 5 is removed to form a contact port 52.
  • an isotropic etching is used to remove a portion of the second source-drain layer 62 exposed by the second isolation film 51 to increase the exposed area of the second source-drain layer 62.
  • the top view of the semiconductor structure in this step does not change, and reference may be made to FIG16( b ).
  • a second metal suicide layer 63 is formed in the contact opening 52 . That is, the second metal silicide layer 63 is formed in contact with the second source and drain layer 62 , and the second metal silicide layer 63 is located on the side of the second source and drain layer 62 close to the inside of the second trench 5 .
  • a metal layer is first deposited in the contact opening 52 , and the metal layer is annealed so that the metal layer reacts with the second source and drain layer 62 to form the second metal silicide layer 63 .
  • the second metal silicide layer 63 can reduce the contact resistance between the subsequently formed bit line 64 and the second source/drain layer 62, thereby improving the electrical performance of the semiconductor structure. In other embodiments, the second metal silicide layer 63 may not be formed.
  • the contact opening 52 can increase the contact area between the second metal silicide layer 63 and the second source and drain layer 62, thereby reducing the contact resistance.
  • the second metal silicide layer 63 may only be attached to the inner wall of the contact port 52 without filling the contact port 52 . That is, the subsequently formed bit line 64 may also fill the contact port 52 , thereby facilitating the increase of the contact port 52 .
  • the filling space of the bit line 64 is large, and the connection between the bit line 64 and the second metal silicide is increased.
  • the second metal silicide layer 63 may also fill the contact opening 52 .
  • bit lines 64 are formed to fill the second trench 5, the bit lines 64 extend along the first direction X, and the bit lines 64 are electrically connected to the second source-drain layer 62, that is, each bit line 64 is electrically connected to the plurality of second source-drain layers 62 in the first direction X.
  • Two bit lines 64 arranged adjacent to each other in the third direction Z are separated by the isolation structure 41. The bit lines 64 are also in contact with the second metal silicide layer 63.
  • metals such as tungsten and titanium nitride are deposited in the second trench 5 to serve as the bit line 64. After the metal is deposited, the metal is polished and leveled.
  • a portion of the bit line 64 is etched back, and a third isolation film 57 is formed to close the top of the second trench 5 .
  • the third isolation film 57 can protect the bit line 64 from being polluted and oxidized.
  • the sacrificial layer 22 is removed.
  • the first isolation film 21 located on the sidewall of the first sub-trench 20 is also removed, thereby exposing the sidewall of the first sub-trench 20 .
  • a wet etching process is used to remove the sacrificial layer 22 and the first isolation film 21 .
  • a first source-drain layer 61 is formed on the sidewall of the first sub-groove 20.
  • the first source-drain layer 61 is also in contact with the gate dielectric layer 31.
  • the sidewall of the first sub-groove 20 is doped to form the first source-drain layer 61.
  • a plasma doping process is used to implant n-type doping ions into the substrate 1 exposed in the first groove 2.
  • the doping depth of the first source and drain layer 61 in the second direction Y is shallow, so that the first source and drain layer 61 and the word line 32 can be staggered in the first direction Create an overlapping area between the two, or reduce the overlapping area between the two, thereby avoiding the problem of leakage between the first source and drain layer 61 and the word line 32.
  • first source and drain layers 61 arranged adjacently in the third direction Z are separated by the first isolation structure 41 to avoid mutual interference between the adjacent first source and drain layers 61 .
  • an initial dielectric layer 811 is formed on the sidewalls of the first trench 2 and the upper surface of the substrate 1 .
  • the initial dielectric layer 811 also covers the first source and drain layer 61 .
  • a high dielectric constant material is deposited as the initial dielectric layer 811. High dielectric constant materials are beneficial to improving capacitance capacity.
  • the initial dielectric layer 811 on the upper surface of the substrate 1 is removed, and the initial dielectric layer 811 on the sidewall of the first trench 2 serves as the dielectric layer 71 .
  • a plurality of capacitor plates 82 filling the first trench 2 are formed.
  • the capacitor plates 82 also cover the dielectric layer 81; the plurality of capacitor plates 82 are in the third direction Z. arranged on and extending in the first direction X.
  • the capacitor plates 82 arranged adjacently in the third direction Z are separated by the first isolation structure 41 .
  • the first source-drain layer 61, the capacitor plate 82, and the dielectric layer 81 form a capacitor, which is connected to the transistor formed by the first source-drain layer 61, the second source-drain layer 62, and the word line 32. It can be understood that since the first source-drain layer 61 also serves as a plate of the capacitor, it is advantageous to omit the electrical connection structure between the first source-drain layer 61 and the capacitor, thus making the production process simpler.
  • the first trench 2 is filled with metals such as tungsten and titanium nitride as the capacitor plate 82 , and then the capacitor plate 82 and the upper surface of the substrate 1 are polished.
  • part of the capacitor plate 82 is etched back, and a fourth isolation film 23 is deposited to seal the top of the first trench 2.
  • the fourth isolation film 23 can act on the capacitor plate 82. to a protective effect.
  • the material of the fourth isolation film 23 may be silicon nitride.
  • the front-end manufacturing of the 3D DRAM can be completed. It is worth noting that performing each process step in the aforementioned order is conducive to reducing the contamination of the semiconductor structure and reducing impurity residues. In other embodiments, the order of each process step can also be adjusted. For example, the second trench 5 is first formed, and the second source and drain layer 62, the second metal silicide layer 63, and the bit line 64 are formed based on the wavy second trench 5; thereafter, the first trench 2 is formed, and the second source and drain layer 62, the second metal silicide layer 63, and the bit line 64 are formed based on the wavy first trench 5.
  • the trench 2 forms structures such as the word line 32, the dielectric layer 81, and the capacitor plate 82.
  • the first trench 2 the word line 32, the first source and drain layer 61, the dielectric layer 81, and the capacitor plate 82 are formed first, and then the second trench 5, the second source and drain layer 62, and the bit line 64 are formed.
  • the Bosch process is used to form the first trench 2 and the second trench 5 with a wavy shape, and the word line 32 and the first source and drain layer 61 are formed based on the wavy shape of the first trench 2. Based on the wavy shape, The second trench 5 forms a second source and drain layer 62 .
  • transistors can be formed within a silicon substrate without using IGZO and Superlattice technologies, thereby reducing defects within the semiconductor structure and improving the performance of the semiconductor structure.
  • Another embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure.
  • the manufacturing method is substantially the same as the method for manufacturing the semiconductor structure of the previous embodiment.
  • the main difference is that the manufacturing method also forms an electrode layer 7 , and the electrode layer 7 It is spaced apart from the bit line 64 in the third direction Z.
  • This manufacturing method will be described in detail below. For parts of this manufacturing method that are the same or similar to those of the previous embodiments, please refer to the previous detailed description and will not be repeated here.
  • the first trench 2 , word line 32 , insulating layer 33 , gate dielectric layer 31 , first isolation structure 41 , sacrificial layer 22 and other structures are formed.
  • word line 32 word line
  • insulating layer 33 gate dielectric layer 31
  • first isolation structure 41 sacrificial layer 22 and other structures
  • Figure 28(b) is a top view
  • Figure 28(a) is a cross-sectional view of Figure 28(b) in the A-A1 direction.
  • a second trench 5 is formed in the substrate 1 , the depth direction of the second trench 5 is the first direction X; the first trench 2 and the second trench 5 are arranged in the second direction Y; the second trench 5 It includes a plurality of second sub-grooves 50 arranged in the first direction X, and the side walls of the second sub-grooves 50 are convex. That is, the second groove 5 also has wavy side walls.
  • the first isolation structure 41 also spans the first trench 2 and the second trench 5 .
  • the first isolation structure 41 divides the second trench 5 into a plurality of bit line electrode trenches 54 arranged at intervals. It should be noted that, in order to be more intuitive, white filling blocks are used to illustrate the second trench 5 in FIG. 28(b) and subsequent top views.
  • the second trench 5 is formed using the Bosch process.
  • the specific formation process of the second trench 5 please refer to the detailed description of the first trench 2.
  • Figure 29(b) is a top view
  • Figure 29(a) is a cross-sectional view of Figure 29(b) in the A-A1 direction.
  • the initial second isolation structure 531 that is, the initial second isolation structure 531 fills the bit line electrode trench 54 .
  • the initial second isolation structures 531 and the first isolation structures 41 are arranged alternately.
  • silicon nitride is deposited in the second trench 5 as the initial second isolation structure 531 , that is, the material of the initial second isolation structure 531 may be the same as the material of the first isolation structure 41 .
  • Figure 30(b) is a top view
  • Figure 30(a) is a cross-sectional view of Figure 30(b) in the A-A1 and B-B1 directions.
  • the isolation structure 531 is patterned to form the second isolation structure 53 .
  • the second isolation structure 53 extends along the second direction Y and divides the bit line electrode groove 54 into a bit line groove 541 and an electrode groove 542 . That is to say, the second trench 5 includes bit line trenches 541 and electrode trenches 542 spaced apart in the third direction Z.
  • the bit line trench 541 includes a plurality of sub-bit line trenches 5410 arranged in the first direction X
  • the electrode trench 542 includes a plurality of sub-electrode trenches 5420 arranged in the first direction X.
  • the side walls of the sub-electrode slot 5420 and the sub-bit line slot 5410 are both convex.
  • the second sub-trench 50 includes a sub-electrode trench 5420 and a sub-bit line trench 5410.
  • Figure 31(b) is a top view
  • Figure 31(a) is a cross-sectional view of Figure 31(b) in the A-A1 and B-B1 directions, with the wire trough in place.
  • 541 and the side walls of the electrode trench 542 form an initial second isolation film 511; the initial second isolation film 511 located at the junction of adjacent sub-bit line trenches 5410 protrudes toward the inside of the bit line trench 541; located at the adjacent sub-electrode trench 5410
  • the initial second isolation film 511 at the junction of 5420 is disposed protruding toward the inside of the electrode groove 542 . That is, since the side walls of the bit line trench 541 and the electrode trench 542 have a wavy shape, the initial second isolation film 511 formed on the side walls of the bit line trench 541 and the electrode trench 542 also has a wavy shape.
  • an isotropic deposition process is used to form a silicon nitride film as the initial second isolation film 511.
  • Figure 32(b) is a top view
  • Figure 32(a) is Figure 32(b) at A-A1 and A cross-sectional view in the B-B1 direction
  • the portion at the junction of the electrode groove 5420 initializes the second isolation film 511 . That is, an anisotropic etching process is used to cut off the protruding initial second isolation film 511 at the junction of adjacent sub-bit line trenches 5410 and the junction of adjacent sub-electrode trenches 5420.
  • an isotropic etching process is used to remove the remaining initial second isolation film 511 at the junction of adjacent sub-bit line trenches 5410 to expose the substrate at the junction of adjacent sub-bit line trenches 5410 1; and remove the remaining initial second isolation film 511 located at the junction of adjacent sub-electrode trenches 5420 to expose the substrate 1 located at the junction of adjacent sub-electrode trenches 5420.
  • the initial second isolation film 511 on the side wall of the sub-electrode trench 5420 and the side wall of the sub-bit line trench 5410 serves as the second isolation film 51 .
  • the side walls of the sub-bit line trench 5410 and the side of the sub-electrode trench 5420 can be formed.
  • the second isolation film 51 of the wall exposes the substrate 1 at the junction of adjacent sub-bit line trenches 5410 and exposes the substrate 1 at the junction of adjacent sub-electrode trenches 5420.
  • Figure 34(c) is a top view
  • Figure 34(a) is a cross-sectional view of Figure 34(c) in the A-A1 direction
  • Figure 34(b) is a cross-sectional view of Figure 34(c) in the A-A1 direction.
  • (c) Cross-sectional view in the B-B1 direction.
  • a first mask layer 55 filling the electrode trench 542 is formed, and the first mask layer 55 exposes the bit line trench 541 .
  • photoresist is filled in the electrode trench 542 and the bit line trench 541 as an initial first mask layer, and a photolithography process is performed on the initial first mask layer to remove the initial first mask layer in the bit line trench 541. film layer, and the remaining initial first mask layer serves as the first mask layer 55 .
  • Part of the first mask layer 55 is also located on the upper surface of the substrate 1 .
  • a second source-drain layer 62 protruding away from the second trench 5 is formed at the junction of adjacent sub-bit line trenches 5410.
  • the second source and drain layer 62 is also in contact with the gate dielectric layer 31 .
  • the substrate 1 at the junction of adjacent sub-bit line trenches 5410 is subjected to a plasma doping process to form the second source and drain layer 62 .
  • the second isolation film 51 can be a mask for forming the second source and drain layer 62, used to control the position and size of the second source and drain layer 62, and to avoid adjacent second source and drain layers in the first direction X. 62 generates interconnection.
  • the doped ions of the second source and drain layer 62 may be n-type ions.
  • the second source and drain layer 62 and the word line 32 are both located between the first trench 2 and the second trench 5 , and the second source and drain layer 62 is opposite to the word line 32 .
  • a first isolation structure 41 is provided between the second source-drain layers 62 adjacent to each other in the third direction Z. Therefore, the second source-drain layers 62 adjacent to each other in the third direction Z are isolated from each other.
  • a second isolation film 51 is provided between the second source-drain layers 62 adjacent to each other in the first direction X. Therefore, the second source-drain layers 62 adjacent to each other in the first direction X are also isolated from each other.
  • a portion of the second source-drain layer 62 near the inside of the second trench 5 is removed to form a contact port 52.
  • the first mask layer 55 and the second isolation film 51 are used as masks, and an isotropic etching is used to remove a portion of the second source-drain layer 62 exposed by the second isolation film 51 to increase the exposed area of the second source-drain layer 62.
  • the top view of the semiconductor structure in this step and the cross-sectional view in the B-B1 direction do not change, and reference may be made to FIG34(c) and FIG34(b).
  • Figure 36(c) is a top view
  • Figure 36(a) is a cross-sectional view of Figure 36(c) in the A-A1 direction
  • Figure 36(b) is a cross-sectional view of Figure 36(c) in the A-A1 direction.
  • (c) Cross-sectional view in the B-B1 direction.
  • the first mask layer 55 is removed to form a second mask layer 56 filling the bit line trench 541
  • the second mask layer 56 exposes the electrode trench 542 .
  • the old photoresist is cleaned, new photoresist is filled in the bit line trench 541 and the electrode trench 542 as an initial second mask layer, and photolithography is performed on the initial second mask layer to The initial second mask layer located in the electrode groove 542 is removed, and the remaining initial second mask layer serves as the second mask layer 56 .
  • Part of the second mask layer 56 is also located on the substrate 1 the upper surface.
  • the substrate 1 at the junction of adjacent sub-electrode grooves 5420 is heavily doped to form a heavily doped layer 71.
  • plasma doping is used to inject p-type doping ions into the substrate 1 to serve as the heavily doped layer 71. That is, the type of doping ions in the heavily doped layer 71 can be the same as the type of doping ions in the substrate 1. In this way, a fast outflow channel can be provided for the charges in the substrate 1 to avoid the accumulation of charges in the substrate 1.
  • the doping depth of the heavily doped layer 71 is smaller than the doping depth of the second source and drain layer 62 . That is, the smaller doping depth of the heavily doped layer 71 can prevent the second source and drain layer 62 from contacting the heavily doped layer 71, and prevent the heavily doped layer 71 from contacting the gate dielectric layer 31, thereby avoiding leakage. or short circuit problem.
  • the second isolation film 51 on the sidewalls of the sub-bit line trench 5410 and the sub-electrode trench 5420 are formed in the same process step, the production process is simpler.
  • the second isolation film 51 may be formed only on the sidewalls of the sub-bit line trench 5410 and not on the sidewalls of the sub-electrode trench 5420, thereby exposing the entire sidewall of the electrode trench 542. Therefore, the heavily doped layer 71 can be formed on the entire sidewall of the electrode groove 542 , thereby increasing the contact area between the heavily doped layer 71 and the substrate 1 , thereby increasing the outflow speed of charges in the substrate 1 .
  • Figure 37(c) is a top view
  • Figure 37(a) is a cross-sectional view of Figure 37(c) in the A-A1 direction
  • Figure 37(b) is a cross-sectional view of Figure 37(c) in the A-A1 direction.
  • (c) Cross-sectional view in the B-B1 direction.
  • the second mask layer 56 is removed to expose the bit line trench 541 .
  • a second metal silicide layer 63 is formed on the side of the second source-drain layer 62 facing the inside of the bit line trench 541.
  • the second metal suicide layer 63 is also located within the contact opening 52 .
  • a metal layer is first deposited in the contact opening 52 , and the metal layer is annealed so that the metal layer reacts with the second source and drain layer 62 to form the second metal silicide layer 63 .
  • the contact opening 52 can increase the contact area between the second metal silicide layer 63 and the second source and drain layer 62, thereby reducing the contact resistance.
  • the second metal silicide layer 63 may only be attached to the inner wall of the contact port 52 without filling the contact port 52 . That is, the subsequently formed bit line 64 may also fill the contact port 52 , thereby facilitating the increase of the contact port 52 .
  • the filling space of the bit line 64 is enlarged, and the contact area between the bit line 64 and the second metal silicide layer 63 is increased.
  • the second metal silicide layer 63 may also fill the contact opening 52 .
  • a first metal silicide layer 72 is formed on the side of the heavily doped layer 71 facing the inside of the electrode trench 542 .
  • a metal layer is formed on the sidewall of the heavily doped layer 71 , and a high-temperature annealing process is performed to react the metal layer with the heavily doped layer 71 to generate the first metal silicide layer 72 .
  • the first metal silicide layer 72 and the second metal silicide layer 63 can be formed simultaneously, thereby simplifying the production process and reducing production costs.
  • the first metal silicide layer 72 may be located between the heavily doped layer 71 and the subsequently formed conductive layer 73 , thereby reducing the contact resistance between the subsequently formed conductive layer 73 and the heavily doped layer 71 ;
  • the second metal silicide layer 63 may It is located between the subsequently formed bit line 64 and the second source and drain layer 62, thereby reducing the contact resistance between the formed bit line 64 and the second source and drain layer 62, thereby improving the electrical performance of the semiconductor structure.
  • the first metal silicide layer 72 and the second metal silicide layer 63 may not be formed.
  • Figure 38(c) is a top view
  • Figure 38(a) is a cross-sectional view of Figure 38(c) in the A-A1 direction
  • Figure 38(b) is a cross-sectional view of Figure 38(c) in the A-A1 direction.
  • (c) Cross-sectional view in the B-B1 direction.
  • a bit line 64 filling the bit line trench 541 is formed, the bit line 64 is connected to the second metal silicide layer 63 , and the bit line 64 is electrically connected to the second source and drain layer 62 .
  • a conductive layer 73 filling the electrode trench 542 is formed, and the conductive layer 73 is electrically connected to the heavily doped layer 71 .
  • metal material layers such as tungsten and titanium nitride are simultaneously deposited in the bit line trench 541 and the electrode trench 542.
  • the metal material layer located in the bit line trench 541 serves as the bit line 64
  • the metal material layer located in the electrode trench 542 serves as Conductive layer 73. Since the bit line 64 and the conductive layer 73 can be formed in the same process step, the production process is more streamlined. Add simplicity. After depositing the metal material layer, the metal material layer can be polished and smoothed.
  • the bit lines 64 extend along the first direction X, and each bit line 64 is electrically connected to the plurality of second source and drain layers 62 in the first direction X.
  • the conductive layer 73 extends along the first direction X, and there is a first isolation structure 41 and a second isolation structure 53 between two adjacent conductive layers 73 in the third direction Z. That is, the bit lines 64 may be parallel to the conductive layer 73 , and the two may be alternately arranged in the third direction Z.
  • Electrode layer 7 the electrode layer 7 is electrically connected to the substrate 1 .
  • the electrode layer 7 includes a first metal silicide layer 72 , a conductive layer 73 and a heavily doped layer 71 .
  • the electrode layer 7 may include the conductive layer 73 and the heavily doped layer 71 , or the electrode layer 7 may only consist of the conductive layer 73 .
  • Figure 39(c) is a top view
  • Figure 39(a) is a cross-sectional view of Figure 39(c) in the A-A1 direction
  • Figure 39(b) is a cross-sectional view of Figure 39(c) in the A-A1 direction.
  • (c) Cross-sectional view in the B-B1 direction.
  • Part of the bit line 64 and part of the conductive layer 73 are etched back, and a third isolation film 57 is formed to close the tops of the bit line trench 541 and the electrode trench 542 .
  • the third isolation film 57 can protect the bit line 64 and the conductive layer 73 from being contaminated and oxidized.
  • Figure 40(b) is a top view
  • Figure 40(a) is a cross-sectional view of Figure 40(b) in the A-A1 direction.
  • the sacrificial layer 22 and the first isolation film 21 located on the sidewalls of the first sub-trench 20 are removed, thereby exposing the sidewalls of the first sub-trench 20 .
  • a wet etching process is used to remove the sacrificial layer 22 and the first isolation film 21 .
  • a first source and drain layer 61 is formed on the sidewall of the first sub-trench 20 .
  • the top view of the semiconductor structure in this step has not changed, and you can refer to Figure 40(b).
  • Figure 41(a) is a cross-sectional view of Figure 40(b) in the A-A1 direction
  • Figure 41(b) is a cross-sectional view of Figure 40(b) in the B-B1 direction.
  • the first source and drain layer 61 is also in contact with the gate dielectric layer 31 .
  • a first isolation structure 41 is provided between adjacent first source and drain layers 61 in the third direction Z to avoid mutual interference between adjacent first source and drain layers 61 .
  • the sidewalls of the first sub-trench 20 are doped to form the first source-drain layer 61 .
  • a plasma doping process is used to implant n-type doping ions into the substrate 1 exposed in the first trench 2 .
  • Figure 42(b) is a top view
  • Figure 42(a) is a cross-sectional view of Figure 42(b) in the A-A1 direction.
  • a dielectric layer 81 is formed on the sidewall of the first trench 2 , and the dielectric layer 81 also covers the first source and drain layer 61 .
  • a plurality of capacitor plates 82 arranged at intervals are formed in the first trench 2, and the capacitor plates 82 also cover the dielectric layer 81; the plurality of capacitor plates 82 are in the first trench 2. arranged in three directions Z and extending in the first direction X. The capacitor plates 82 arranged adjacently in the third direction Z are separated by the first isolation structure 41 .
  • Figure 43(d) is a top view
  • Figure 43(a) is a cross-sectional view of Figure 43(d) in the A-A1 direction
  • Figure 43(b) is a cross-sectional view of Figure 43(d) in the A-A1 direction
  • (d) is a cross-sectional view in the B-B1 direction
  • Figure 43(c) is a cross-sectional view of Figure 43(d) in the C-C1 direction.
  • a portion of the capacitor plate 82 is etched back, and a fourth isolation film 23 is deposited to close the top of the first trench 2 .
  • the front-end manufacturing of 3D DRAM can be completed. It is worth noting that performing each process step in the aforementioned order is beneficial to reducing contamination to the semiconductor structure and reducing impurity residues. In other embodiments, the order of each process step can also be adjusted.
  • the second trench 5 is first formed and divided into a bit line trench 541 and an electrode trench 542. After that, the second source and drain layer 62 and the second metal silicide are formed based on the wavy bit line trench 541.
  • Structures such as the object layer 63 and the bit line 64 are formed, and the electrode layer 7 is formed in the electrode groove 542; thereafter, the first trench 2 is formed, and the word line 32, dielectric layer 81, Capacitor plate 82 and other structures.
  • structures such as the first trench 2, word line 32, first source and drain layer 61, dielectric layer 81 and capacitor plate 82 are formed first, and then the second trench 5, second source and drain layer 62 and bits are formed. Line 64 and other structures.
  • the manufacturing method of this embodiment is based on the manufacturing method of the previous embodiment, forming an electrode layer 7 electrically connected to the substrate 1 , and the electrode layer 7 can be connected to the power supply in the peripheral area.
  • the electrode layer 7 may also include a heavily doped layer 71 and a first metal silicide layer 72 to guide charges to flow out quickly.
  • Another embodiment of the present disclosure also provides a semiconductor structure.
  • This semiconductor structure can be manufactured using the manufacturing method of the semiconductor structure described in the previous two embodiments.
  • This semiconductor structure please refer to the foregoing detailed description. This will not be described again.
  • the semiconductor structure will be described in detail below with reference to the accompanying drawings.
  • Example 1 as shown in Figures 27(a) to 27(b), the semiconductor structure includes: a substrate 1. There are a first trench 2 and a second trench 5 in the substrate 1, and the depth directions of both are equal. is the first direction X; the first trench 2 includes a plurality of first sub-trenches 20 arranged in the first direction 50, and the sidewalls of the first sub-trench 20 and the second sub-trench 50 are both convex; the junction of adjacent first sub-trenches 20 has a word line 32 protruding away from the first trench 2 ; The sidewall of the first sub-trench 20 has a first source-drain layer 61; the junction of the adjacent second sub-trench 50 has a second source-drain layer 62 protruding away from the second trench 5; the second source The drain layer 62 and the word line 32 are both located between the first trench 2 and the second trench 5 , and the second source and drain layer 62 is opposite to the word line 32 .
  • the semiconductor structure may be a dynamic random access memory (Dynamic Random Access Memory, DRAM).
  • the semiconductor structure also includes: a gate dielectric layer 31 that covers the side of the word line 32 away from the inside of the first trench 2 .
  • the gate dielectric layer 31 is also connected with the first source-drain layer 61 and the second source-drain layer 62 contact. That is, the first source and drain layer 61, the second source and drain layer 62, the word line 32 and the gate dielectric layer 31 can be used to form the transistor T (refer to FIG. 44(a)).
  • the semiconductor structure also includes: a plurality of capacitor plates 82 filling the first trench 2; the plurality of capacitor plates 82 are arranged at intervals in the third direction Z and extend along the first direction X, and the capacitor plates 82 are also filled in the third direction Z.
  • the semiconductor structure also includes: a dielectric layer 81 located on the sidewalls of the first trench 2.
  • the dielectric layer 81 is located on the two opposite sidewalls of the first trench 2.
  • the dielectric layer 81 is also located on the first source and drain layer 61 and the capacitor plate. between 82. That is, the first source and drain layer 61, the dielectric layer 81 and the capacitor plate 82 form a capacitor.
  • Capacitor and transistor T can form the basic memory unit.
  • Fig. 44(a) a partial enlarged view of Fig. 27(a) is shown.
  • a turn-on voltage is provided to the word line 32
  • two channels can be formed, that is, current flows between the first source-drain layer 61 and the second source-drain layer 62 on the upper and lower sides of the word line 32.
  • transistor T When transistor T is turned on, the capacitor can store or release charge.
  • the first groove 2 and the second groove 5 are arranged in the second direction Y, and both extend along the third direction Z.
  • there are multiple first trenches 2 and multiple second trenches 5 and the first trenches 2 and the second trenches 5 are alternately arranged in the second direction Y, which is conducive to increasing the number of The number of transistors T and capacitors increases the storage capacity.
  • a plurality of first source and drain layers 61 are arranged at intervals in the third direction Z; a plurality of second source and drain layers 62 are arranged in the third direction Z. Arranged at intervals; the word lines 32 extend along the third direction Z. That is, a plurality of transistors may be arranged in the third direction Z, and the word line 32 may serve as a gate electrode of the plurality of transistors arranged in the third direction Z.
  • both the first source and drain layer 61 and the second source and drain layer 62 may extend in the third direction Z, that is, both may have a columnar structure in the third direction Z.
  • the semiconductor structure also includes a plurality of bit lines 64 filled in the second trench 5.
  • the plurality of bit lines 64 are spaced apart in the third direction Z and along the first Extending in the direction X; the bit line 64 is electrically connected to the second source and drain layer 62 . That is to say, the bit line 64 is electrically connected to the plurality of second source and drain layers 62 arranged in the first direction X. connect.
  • the bit line 64 is electrically connected to the peripheral circuit, and the bit line 64 is used to read the stored data of the memory unit or write data to the memory unit.
  • the semiconductor structure also includes a first isolation structure 41, a plurality of first isolation structures 41 extending along the second direction Y and arranged in the third direction Z; the first isolation structure 41 spans the first trench 2 and the second Groove 5. That is to say, the first isolation structure 41 is used to isolate a plurality of transistors arranged in the third direction Z, but does not cut off the word line 32 .
  • the first source and drain layers 61 arranged adjacently in the third direction Z are separated by the first isolation structure 41
  • the second source and drain layers 62 arranged adjacently in the third direction Z are separated by the first isolation structure 41 . Structure 41 separated.
  • the first isolation structure 41 is provided between the adjacent first source and drain layers 61 in the third direction Z, and the first isolation structure 41 is provided between the adjacent second source and drain layers 62 in the third direction Z.
  • the first isolation structure 41 is also used to isolate the adjacent bit lines 64 in the third direction Z and the adjacent capacitor plates 72 in the third direction Z.
  • Example 1 the second trenches 5 between adjacent first isolation structures 41 are in a continuous state. Therefore, the bit line 64 is also in contact with the first isolation structure 41 on opposite sides in the third direction Z, and the second source and drain layer 62 is also in contact with the first isolation structure 41 on opposite sides in the third direction Z. .
  • Example 2 refer to Figures 43(a) to 43(d), and Figures 44(a) to 44(c).
  • Figure 44(a) is a partial enlarged view of Figure 43(a)
  • Figure 44(b) is a partial enlarged view of Figure 43(b)
  • Figure 44(c) is an enlarged partial cross-sectional view of the semiconductor structure, and the cross-section is vertical in the first direction X.
  • the semiconductor structure includes: a substrate 1. There are a first trench 2 and a second trench 5 in the substrate 1, and the depth direction of both trenches is the first direction X, and the arrangement direction of the two trenches is the second direction Y.
  • the extension direction of both is the third direction Z;
  • the second trench 5 includes bit line trenches 541 and electrode trenches 542 arranged at intervals in the third direction Z;
  • the first trench 2 includes a plurality of trenches arranged in the first direction X.
  • the bit line trench 541 includes a plurality of sub-bit line trenches 5410 arranged in the first direction
  • the sidewall of the first sub-trench 20 has a first source-drain layer 61;
  • the junction of adjacent sub-bit line trenches 5410 has a second source-drain layer 62 protruding away from the second trench 5;
  • the electrode groove 542 has an electrode layer 7 inside, and the electrode layer 7 is electrically connected to the substrate 1 .
  • Example 1 is substantially the same as the semiconductor structure shown in Example 2.
  • the main difference between them is that the second trench 5 and its internal structure are different.
  • the first trench 2 and its internal structure of the two can be the same, for example, the word line 32, the gate dielectric layer 31, the insulating layer 33, the first source and drain layer 61, the capacitor plate 82, and the dielectric layer 81 of the two.
  • the structures can be the same.
  • the electrode groove 542 includes a plurality of sub-electrode grooves 5420 arranged in the first direction X, and the sub-electrode grooves 5420 are convex.
  • the electrode layer 7 includes a heavily doped layer 71 and a conductive layer 73 that are electrically connected, the heavily doped layer 71 is at least located in the substrate 1 at the junction of adjacent sub-electrode grooves 5420, and the conductive layer 73 is filled in the electrode groove 542.
  • the heavily doped layer 71 may also cover the entire side wall of the electrode groove 542.
  • the electrode layer 7 may also include a first metal silicide layer 72, and the first metal silicide layer 72 is located between the conductive layer 73 and the heavily doped layer 71.
  • the semiconductor structure further includes a second isolation structure 53 extending along the second direction Y.
  • the first isolation structure 41 divides the second trench 5 into a plurality of bit line electrode grooves 54 arranged in the third direction Z
  • the second isolation structure 53 divides the bit line electrode groove 54 into a bit line groove 541 and an electrode groove 542 . Thereby, isolation between the bit line 64 and the electrode layer 7 can be achieved.
  • Example 2 since the semiconductor structure also includes an electrode layer 7 electrically connected to the substrate 1, the floating body effect can be avoided.
  • the electrode layer 7 and the bit line 64 are arranged in parallel, and they are alternately arranged in the third direction Z and separated by the second isolation structure 53 .
  • Example 1 Comparing Example 1 and Example 2, it can be seen that in Example 1, the second trenches 5 between adjacent first isolation structures 41 are in a continuous state, while in Example 2, the second trenches 5 between adjacent first isolation structures 41 are separated by the third The second isolation structure 53 is cut off. Therefore, in the first example, the length of the bit line 64 in the third direction Z is equal to the length of the first source and drain layer 62 in the third direction Z, and is equal to the distance between adjacent first isolation structures 41 .
  • Example 2 Median line 64 is in the third The length in the direction Z is less than the length of the first source and drain layer 61 in the third direction Z, and is also less than the distance between adjacent first isolation structures 41 .
  • the semiconductor structure includes an array area AR and a peripheral area P.
  • the substrate 1 of the array area AR has a transistor group T0.
  • the transistor group T0 It includes a multi-layer transistor T arranged in the first direction Y arrangement, two first source and drain layers 61 are arranged in the first direction X and are located on opposite sides of the word line 32; in the first direction X, two adjacent transistors T share a first source and drain layer 61;
  • the word line 32 is electrically connected to the sub-word line driver SWD.
  • the sub-word line driver SWD does not provide turn-on signals to two adjacent word lines 32 in the first direction X at the same time.
  • Example 1 and Example 2 show the array region AR of the semiconductor structure
  • Example 3 will be described in detail below with reference to the accompanying drawings.
  • the multiple transistor groups T0 are arranged in an array within the substrate 1 . That is, the plurality of transistor groups T0 are arranged in the second direction Y, and the plurality of transistor groups T0 are also arranged in the third direction Z. In other words, the plurality of transistor groups T0 arranged in the third direction Z constitute the transistor unit T1, and the plurality of transistor units T1 are arranged in the second direction Y. As a result, the number of transistor groups T0 can be increased, thereby increasing the storage capacity of the semiconductor structure. It should be noted that the dotted box in FIG. 43(d) shows the position of the orthographic projection of one transistor unit T1 on the substrate 1.
  • the word line 32 extends along the third direction Z, and one word line 32 is shared by multiple transistors T in the same layer of the transistor unit T1.
  • the word lines 32 are arranged in an array within the substrate 1 , that is, the plurality of word lines 32 are arranged in the first direction X, and the plurality of word lines 32 are also arranged in the second direction Y.
  • the bit lines 64 are filled in the second trench 5, and each bit line 64 is connected to a plurality of second source and drain layers 62 of the same transistor group T0.
  • FIG. 45 shows a top view of the semiconductor structure in the back-end process.
  • FIG. 45 only shows part of the structure.
  • the capacitor plug 83 is formed on the upper surface of the capacitor plate 82
  • the bit line contact layer BLC is formed on the upper surface of the bit line 64
  • the electrode contact layer 74 is formed on the upper surface of the electrode layer 7 .
  • the capacitor plug 83, the bit line contact layer BLC, and the electrode contact layer 74 may all extend in the first direction X.
  • the dotted box in FIG. 45 shows the position of the orthographic projection of one transistor group T1 on the substrate 1 .
  • the connection structure and connection relationship between the array area AR and the peripheral area P will be described in detail below.
  • the sub-word line driver SWD is electrically connected to the word line 32 and is used to provide an on signal or a turn off signal to the word line 32 .
  • the connection relationship between the sub-word line driver SWD and the word line 32 is as follows:
  • the sub-word line driver SWD and the word line 32 may be electrically connected through the lead posts 36 .
  • the array area AR includes a storage area AR1 and a step area AR2, and the step area AR2 and the storage area AR1 are arranged in the third direction Z.
  • the word lines 32 extend from the storage area AR1 to the step area AR2, and in the direction from the upper surface of the substrate 1 to the lower surface of the substrate 1, the lengths of the plurality of word lines 32 increase sequentially, that is, the word lines 32 on the lower layer are longer. long.
  • the plurality of lead posts 36 are connected to the plurality of word lines 32 in one-to-one correspondence, and the lead posts 36 are electrically connected to the sub-word line driver SWD. That is, through layered etching, the orthographic projections of the word lines 32 of each layer on the substrate 1 are staggered, and are connected through the lead posts 36 .
  • step areas AR2 there are two step areas AR2 , and the two step areas AR2 are arranged in the third direction Z and located on opposite sides of the storage area AR1 . Therefore, more sufficient space can be provided for the lead posts 36 , thereby increasing the distance between the lead posts 36 to reduce the parasitic capacitance between adjacent lead posts 36 .
  • multiple sub-word line drivers SWD are respectively located in the array area AR in the third direction. Opposite sides of the Z arrangement. That is, multiple sub-word line drivers SWD are respectively arranged opposite to the step area AR2. In this way, the distance between the sub-word line drivers SWD and the step area AR2 can be reduced, which is beneficial to reducing the wiring length and reducing the wiring resistance.
  • the lead posts 36 are arranged in the step area AR2, which is beneficial to providing a more sufficient space for the sub-word line driver SWD.
  • a plurality of word lines 32 of the same transistor unit T1 may extend from the same side of the array area AR to the same step area AR2, and the lead posts 36 connected to the word lines 32 of the same transistor unit T1 are located on the same side of the array area AR. Therefore, a plurality of sub-word line drivers SWD electrically connected to the same transistor unit T1 may be located on the same side of the array area AR, thereby facilitating the electrical connection of the sub-word line drivers SWD to the lead posts 36, thereby facilitating the reduction of the wiring length and the wiring resistance.
  • the word lines 32 of adjacent transistor units T1 may respectively extend from both sides of the array area AR into the two step areas AR2. This alternating arrangement is beneficial to improving the uniformity of the structure, and can also increase the spacing between the plurality of lead posts 36, thereby reducing parasitic capacitance.
  • multiple sub-word line drivers SWD electrically connected to the adjacent transistor unit T1 are located on different sides of the array area AR, so that the multiple sub-word line drivers SWD are evenly distributed in the peripheral area P, and can also provide the sub-word line drivers SWD with More ample space and less space waste.
  • the two adjacent upper and lower transistors T may not be turned on at the same time. That is, the sub-word line driver SWD does not provide enable signals to two adjacent word lines 32 in the first direction X at the same time.
  • the transistor T includes an isolation transistor and an active transistor, and the isolation transistor and the active transistor are alternately arranged in the first direction X.
  • the isolation transistor is supplied with a normally-off voltage so that it isolates the two active transistors.
  • an isolation transistor is provided between two effective transistors, thereby increasing the distance between the effective transistors, and the isolation transistor is in a normally off state, thereby isolating the two effective transistors and preventing two adjacent effective transistors from Interference between transistors.
  • the word line 32 of the active transistor is the first word line 321 and the word line 32 of the isolation transistor is the second word line 322 . That is, the word line 32 includes first word lines 321 and second word lines 322 that are alternately arranged in the first direction X, wherein the plurality of first word lines 321 are electrically connected to different sub-word line drivers SWD respectively.
  • the second word line 322 is connected to the same normally-off signal source. Specifically, the plurality of first word lines 321 are connected to different sub-word line drivers SWD through first conductive lines 34 respectively.
  • the plurality of second word lines 322 may be connected together through the second conductive line 35, and the normally-off signal source applies a normally-off signal to the second conductive line 35.
  • the second wire 35 may be directly connected to the normally-off signal source.
  • the second conductive line 35 may be connected to the sub-word line driver SWD that provides a normally-off signal. Therefore, the number of sub-word line drivers SWD can be reduced, thereby reducing the volume of the semiconductor structure.
  • first conductor 34 and the second conductor 35 can be connected to the lead post 36 from opposite sides, thereby avoiding intersection and thereby reducing interference.
  • first wire 34 is connected to the right side of the lead post 36
  • second wire 35 is connected to the left side of the lead post 36 .
  • different word lines 32 can also be electrically connected to different sub-word line drivers SWD. Therefore, the active transistor and the isolation transistor can be switched to each other according to the signal provided by the sub-word line driver SWD. Therefore, it can be more flexible. Ground utilizes transistor T.
  • the sense amplifier SA is electrically connected to the bit line 64 and is used to detect the signal on the bit line 64 and amplify the signal on the bit line 64 .
  • the connection structure and connection relationship between the sense amplifier SA and the bit line 64 are as follows:
  • the method further includes: forming a first contact layer 84 on the upper surface of the capacitor plug 83, forming a second contact layer BL2 on the upper surface of the bit line contact layer BLC, and forming a third contact layer 75 on the upper surface of the electrode contact layer 74.
  • the first contact layer 84, the second contact layer BL2 and the third contact layer 75 of the array area AR are shared by the other first contact layers 84, the second contact layers BL2 and the third contact layers 75 located in the middle of the array area AR, and are shared by two adjacent transistor groups T0 arranged in the second direction Y.
  • the capacitor plate 82 is shared by the transistor groups T0 on both sides thereof, the bit line 64 is shared by the transistor groups T0 on both sides thereof, and the electrode layer 7 is shared by the transistor groups T0 on both sides thereof.
  • it is beneficial to improve the utilization efficiency of the area of the substrate 1.
  • the plurality of first contact layers 84 and the plurality of third contact layers 75 are arranged on the same straight line in the second direction Y, and the plurality of second contact layers BL2 are arranged on a straight line in another second direction Y. superior. This arrangement can facilitate the subsequent setting of connecting lines.
  • the sense amplifier SA and the bit line 64 may be electrically connected through the bit line connection line BL1 .
  • bit line connection lines BL1 extend in the second direction Y and are arranged in the third direction Z; the bit line connection line BL1 is electrically connected to a plurality of bit lines 64, that is, the bit line connection line BL1 is connected to a row of second contact layers BL2 arranged in the second direction Y, thereby electrically connecting a row of bit lines 64.
  • the bit line connection line BL1 is arranged to cross the word line 32, and the intersection of the two may correspond to a transistor T.
  • a plurality of sense amplifiers SA are respectively located on opposite sides of the array area AR arranged in the second direction Y. Therefore, a more sufficient spatial location can be provided for the sense amplifier SA.
  • a fourth contact layer BL3 is provided at an end of the bit line connection line BL1, and the fourth contact layer BL3 is used to electrically connect with the sense amplifier SA.
  • the plurality of fourth contact layers BL3 are also located on two opposite edges of the array area AR. This is beneficial to increasing the distance between the fourth contact layers BL3. spacing, thereby reducing the parasitic capacitance between the fourth contact layer BL3.
  • multiple sense amplifiers SA may also be located on the same side of the array area AR.
  • the adjacent bit line connection lines BL1 are respectively connected to the sense amplifiers SA on different sides of the array area AR. Therefore, the arrangement of the plurality of sense amplifiers SA is more uniform, and the production process is simpler; in addition, the spacing between the plurality of fourth contact layers BL3 located on the same side is the same, which is beneficial to balancing the parasitic capacitance.
  • Figure 50 is a partial cross-sectional view of the bit line connection line BL1, and the cross section is perpendicular to the second direction Y.
  • the top and side walls of the bit line connection line BL1 have a fifth isolation film 65 to protect the bit line connection. line BL1, and isolates the bit line connection line BL1 from the word line 32.
  • the material of the fifth isolation layer 65 may be silicon nitride or silicon oxide.
  • the electrode layer 7 is electrically connected to the bias signal source.
  • the bias signal source provides a bias signal to the electrode layer 7 to fix the potential of the substrate 1. Accumulation of charges within the substrate 1 is avoided.
  • the connection structure and connection relationship between the electrode layer 7 and the bias signal source are as follows:
  • the semiconductor structure also It includes: electrode connection lines 76, the electrode connection lines 76 are electrically connected to the plurality of electrode layers 7, and the electrode connection lines 76 are connected to the bias signal source.
  • the electrode connection lines 76 include connected first electrode connection lines 77 and a plurality of second electrode connection lines 78, wherein the first electrode connection lines 77 extend in the second direction Y, and the second electrode connection lines 77 extend in the second direction Y.
  • the second electrode connection line 78 extends in the third direction Z; the second electrode connection line 78 is electrically connected to the plurality of electrode layers 7, that is, the second electrode connection line 78 is connected to the third contact layer 75 (refer to FIG. 49), and then is electrically connected to the electrode layer 7. connect.
  • the second electrode connection line 78 is electrically connected to the plurality of electrode layers 7, that is, the second electrode connection line 78 is connected to the third contact layer 75 (refer to FIG. 49), and then is electrically connected to the electrode layer 7. connect.
  • the peripheral area P also has a capacitive signal source (not shown in the figure), and the capacitive plate 82 is electrically connected to the capacitive signal source.
  • the capacitance signal source provides the capacitance signal to the capacitance plate 82.
  • the connection structure and connection relationship between the capacitance plate 82 and the capacitance signal source are as follows:
  • the semiconductor structure also includes: plate connection lines 85 , the plate connection lines 85 are electrically connected to a plurality of capacitor plates 82 , and the plate connection lines 85 are electrically connected to the capacitance signal source.
  • the plates connect The line 85 includes a connected first plate connection line 86 and a plurality of second plate connection lines 87, wherein the first plate connection line 86 extends in the second direction Y, and the second plate connection line 87 extends in the third direction Y. Extending in the direction Z; the second plate connection line 87 is electrically connected to the plurality of capacitor plates 82 .
  • the capacitance signal can be the ground voltage.
  • the first plate connection line 86 and the first electrode connection line 77 are respectively located on opposite sides of the array area AR; the second plate connection line 87 and the second electrode connection line 78 are in the second direction Y. Arrange alternately.
  • the arrangement of the plate connection lines 85 and the electrode connection lines 76 is simpler, and can avoid cross-relationships between them, thereby helping to reduce signal interference. This arrangement is also beneficial to shortening the lengths of the plate connecting lines 85 and the electrode connecting lines 76 .
  • the plate connection lines 85 and the electrode connection lines 76 can be arranged on the same layer, that is, they can be formed through the same process step, which is beneficial to reducing production costs.
  • a third isolation structure 79 may be provided between the plate connection line 85 and the electrode connection line 76, and the material of the third isolation structure 79 may be silicon nitride.
  • FIG. 52 shows a complete semiconductor structure.
  • the semiconductor structure provided by the embodiment of the present disclosure has a 3D stack of transistors T and capacitors, and the transistors T and capacitors constitute a memory unit.
  • the word line 32 includes first word lines 321 and second word lines 322 that are alternately arranged in the first direction X.
  • Multiple first word lines 321 can be connected to different sub-word line drivers SWD.
  • the signal can be a normally-off signal.
  • adjacent memory cells are separated by the first isolation structure 41 .
  • bit lines 64 are electrically connected together through a bit line connection line BL1 and connected to the sense amplifier SA. All electrode layers 7 can be electrically connected together, and all capacitor plates 82 can be electrically connected together.
  • the aforementioned layout method is conducive to reducing signal interference and avoiding waste of space, thereby conducive to improving the performance of the semiconductor structure.

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Abstract

公开了一种半导体结构的制造方法和半导体结构，该制造方法包括提供衬底，在衬底内形成第一沟槽和第二沟槽，且二者的深度方向均为第一方向。第一沟槽包括多个在第一方向排布的第一子沟槽，第二沟槽包括多个在第一方向排布的第二子沟槽，且第一子沟槽和第二子沟槽的侧壁均呈外凸形；在相邻第一子沟槽的交界处形成背向第一沟槽凸出的字线，在第一子沟槽的侧壁形成第一源漏层，在相邻第二子沟槽的交界处形成背向第二沟槽凸出的第二源漏层。

Description

半导体结构和半导体结构的制造方法
交叉引用
本申请引用于2022年9月21日递交的名称为“半导体结构的制造方法和半导体结构”的第202211153790.8号中国专利申请、名称为“半导体结构和半导体结构的制造方法”的第202211154217.9号中国专利申请以及名称为“半导体结构和半导体结构的制造方法”的第202211153972.5号中国专利申请，其通过引用被全部并入本申请。
技术领域
本公开实施例属于半导体领域，具体涉及一种半导体结构的制造方法和半导体结构。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是一种半导体存储器，主要的作用原理是利用电容内存储电荷的多寡来代表其存储的一个二进制比特是1还是0。
3D DRAM是一种堆叠多层存储单元的一种结构，其集成度较高，单位面积上的容量更大，从而有利于降低单位面积的成本。然而3D DRAM的性能还有待提升。
发明内容
本公开实施例提供一种半导体结构和半导体结构的制造方法，至少有利于提高半导体结构的性能。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构的制造方法，其中，半导体结构的制造方法包括：提供衬底，在所述衬底内形成第一沟槽和第二沟槽，且二者的深度方向均为第一方向；所述第一沟槽包括多个在所述第一方向排布的第一子沟槽，所述第二沟槽包括多个在所述第一方向排布的第二子沟槽，且所述第一子沟槽和所述第二子沟槽的侧壁均呈外凸形；在相邻所述第一子沟槽的交界处形成背向所述第一沟槽凸出的字线；在所述第一子沟槽的侧壁形成第一源漏层；在相邻所述第二子沟槽的交界处形成背向所述第二沟槽凸出的第二源漏层；所述第二源漏层和所述字线均位于所述第一沟槽与所述第二沟槽之间，且所述第二源漏层与所述字线相对设置。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构，半导体结构包括：衬底，所述衬底内具有第一沟槽和第二沟槽，且二者的深度方向均为第一方向；所述第一沟槽包括多个在所述第一方向排布的第一子沟槽，所述第二沟槽包括多个在所述第一方向排布的第二子沟槽，且所述第一子沟槽和所述第二子沟槽的侧壁均呈外凸形；相邻所述第一子沟槽的交界处具有背向所述第一沟槽凸出的字线；所述第一子沟槽的侧壁具有第一源漏层；相邻所述第二子沟槽的交界处具有背向所述第二沟槽凸出的第二源漏层；所述第二源漏层和所述字线均位于所述第 一沟槽与所述第二沟槽之间，且所述第二源漏层与所述字线相对设置。
本公开实施例提供的技术方案至少具有以下优点：
在衬底内形成第一沟槽和第二沟槽，第一沟槽包括多个第一子沟槽，第二沟槽包括多个第二子沟槽，第一子沟槽和第二子沟槽的侧壁均呈外凸形。在相邻第一子沟槽的交界处形成背向第一沟槽凸出的字线；在第一子沟槽的侧壁形成第一源漏层；在相邻第二子沟槽的交界处形成背向第二沟槽凸出的第二源漏层。即基于第一沟槽和第二沟槽的波浪形状的侧壁在衬底内形成晶体管，从而避免采用氧化铟镓锌(indium gallium zinc oxide，IGZO)材料以及超晶格(Superlattice)技术形成晶体管，从而有利于减少半导体结构的缺陷，提高半导体结构的性能。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1(a)、图1(b)、图2(a)、图2(b)、图3(a)、图3(b)、图4、图5、图6、图7(a)、图7(b)、图8(a)、图8(b)、图9(a)、图9(b)、图10(a)、图10(b)、图11(a)、图11(b)、图12、图13、图14(a)、图14(b)、图15(a)、图15(b)、图16(a)、图16(b)、图17、图18、图19、图20、图21(a)、图21(b)、图22(a)、图22(b)、图23(a)、图23(b)、图24、图25(a)、图25(b)、图26(a)、图26(b)、图27(a)、图27(b)分别示出了本公开一实施例提供的半导体结构的制造方法中各步骤对应的不同结构示意图。
图28(a)、图28(b)、图29(a)、图29(b)、图30(a)、图30(b)、图31(a)、图31(b)、图32(a)、图32(b)、图33、图34(a)、图34(b)、图34(c)、图35、图36(a)、图36(b)、图36(c)、图37(a)、图37(b)、图37(c)、图38(a)、图38(b)、图38(c)、图39(a)、图39(b)、图39(c)、图40(a)、图40(b)、图41(a)、图41(b)、图42(a)、图42(b)、图43(a)、图43(b)、图43(c)、图43(d)分别示出了本公开另一实施例提供的半导体结构的制造方法中各步骤对应的不同结构示意图。
图44(a)为图43(a)的局部放大图。
图44(b)为图43(b)的局部放大图。
图44(c)为半导体结构的局部剖面放大图。
图45～图46、图48～图49以及图51～图52示出了本公开一实施例提供的半导体结构的在后段制程中的不同俯视图。
图47示出了本公开又一实施例提供的半导体结构中的台阶区的示意图；
图50示出了本公开又一实施例提供的半导体结构中的位线连接线的局部剖面图。
具体实施方式
由背景技术可知，3D DRAM的性能还有待提升。经分析发现，主要原因在于：3D DRAM主要包括两种，第一种是基于氧化铟镓锌(indium gallium zinc oxide，IGZO)材料，形成具有垂直环形沟道器件结构(CAA，Channel-All-Around)的3D DRAM，然而IGZO材料的均匀一致性难以控制，缺陷较多；第二种是基于超晶格(Superlattice)技术，形成由不同材料的交替层组成的结构，即形成硅和锗硅的交替层，然而沉积多层硅和锗硅会造成较多的界面缺陷。
本公开实施例提供一种半导体结构的制造方法，包括：在衬底内形成第一沟 槽和第二沟槽，第一沟槽包括多个第一子沟槽，第二沟槽包括多个第二子沟槽，第一子沟槽和第二子沟槽的侧壁均呈外凸形。在相邻第一子沟槽的交界处形成背向第一沟槽凸出的字线；在第一子沟槽的侧壁形成第一源漏层；在相邻第二子沟槽的交界处形成背向第二沟槽凸出的第二源漏层。即基于第一沟槽和第二沟槽的波浪形状的侧壁在衬底内形成晶体管，从而避免采用IGZO以及Superlattice技术形成晶体管，以减少半导体结构的缺陷，提高半导体结构的性能。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
如图1(a)、图1(b)～图27(a)、图27(b)所示，本公开一实施例提供一种半导体结构的制造方法，以下将结合附图对本申请一实施例提供的半导体结构的制造方法进行详细说明。需要说明的是，为了便于描述以及清晰地示意出半导体结构制作方法的步骤，图1(a)、图1(b)～图27(a)、图27(b)均为半导体结构的局部结构示意图。
参考图1(a)～图1(b)，图1(b)为图1(a)所示的半导体结构的俯视图，提供衬底1，在衬底1内形成第一沟槽2。第一沟槽2的深度方向为第一方向X；第一沟槽2包括多个在第一方向X排布的第一子沟槽20，第一子沟槽20的侧壁均呈外凸形。即，第一沟槽2的侧壁为波浪形状。为了更加直观，图1(b)以及后续的俯视图中均采用白色填充块示意第一沟槽2。
具体地，采用博世(Bosch)工艺形成第一沟槽2。博世工艺包括刻蚀和钝化两步交替进行的工艺。首先，采用各向同性刻蚀形成一个第一子沟槽20；在第一子沟槽20的内壁形成钝化层；去除第一子沟槽20底部的钝化层；采用各向同性刻蚀形成另一个第一子沟槽20。即重复进行刻蚀和钝化的工艺，从而形成多个第一子沟槽20以构成第一沟槽2。
在一些实施例中，衬底1的材料可以为单晶硅。单晶硅的材料稳定性，且相比于IGZO层以及硅和锗硅的交替层，单晶硅的缺陷易于控制，从而有利于保证半导体结构的性能。另外，基于单晶硅材料，博世工艺所采用的刻蚀气体可以为六氟化硫，钝化气体可以为八氟环丁烷。
此外，衬底1内可以具有掺杂离子，且衬底1内掺杂离子的类型可以与后续形成的第一源漏层61和第二源漏层62(参考图27(a))中的掺杂离子的类型相反。
在一些实施例中，第一子沟槽20的在第一方向X上的深度h为1um～2um，此深度h能够便于后续形成合适尺寸的第一源漏层61(参考图24)。第一子沟槽20朝向衬底1凸出的尺寸s约为几十纳米，从而便于后续形成孔洞24(参考图5)。
参考图2(a)～图2(b)，图2(b)为图2(a)所示的半导体结构的俯视图，在第一沟槽2的侧壁形成第一隔离膜21，位于相邻第一子沟槽20交界处的第一隔离膜21朝向第一子沟槽20的内部凸出设置。即，由于第一沟槽2的侧壁具有波浪形状，因而，形成于第一沟槽2侧壁的第一隔离膜21也具有波浪形状。
示例地，采用各向同性沉积工艺或利用热氧化法形成氧化硅膜以作为第一隔离膜21。在第二方向Y上，第一隔离膜21的厚度可以为厚度20nm～50nm。需要说明的是，在第一隔离膜21的厚度处于上述范围时，能够便于后续在去除相邻第一子沟槽20交界处的第一隔离膜21时，保留位于第一子沟槽20侧壁的第一隔离膜21。即，若第一隔离膜21的厚度过大，则不易露出位于相邻第一子沟槽20交界处的衬底1；若第一隔离膜21的厚度过小，则可能同时去除所有的第一隔离膜21。
此外，部分第一隔离膜21还可以覆盖衬底1的上表面，后续将去除该部分的第一隔离膜21。
参考图3(a)～图3(b)，图3(b)为图3(a)所示的半导体结构的俯视图，以衬底1自身为掩膜，沿第一方向X刻蚀位于相邻第一子沟槽20的交界处的部分第一隔离膜21。即，采用各向异性刻蚀工艺将相邻第一子沟槽20交界处凸出的第一隔离膜21切平，从而使得此处的第一隔离膜21变薄。
参考图4，采用各向同性刻蚀工艺，去除位于相邻第一子沟槽20的交界处的剩余的第一隔离膜21，以露出位于相邻第一子沟槽20的交界处的衬底1。此步骤的半导体结构的俯视图未发生变化，可以参考图3(b)。
也就是说，经过各向异性刻蚀后，相邻第一子沟槽20交界处的第一隔离膜21比第一子沟槽20侧壁的第一隔离膜21更薄；在各向同性刻蚀工艺中，相邻第一子沟槽20交界处的第一隔离膜21会更快地被去除，从而暴露了一定宽度的衬底1。
在第一方向X上，相邻第一子沟槽20交界处的暴露的衬底1的宽度L为20nm～50nm。需要说明的是，暴露的衬底1的宽度在上述范围时，有利于后续形成合适尺寸的孔洞24，即避免孔洞24的内径过小或相邻孔洞24发生互连。
至此，基于图3(a)～图3(b)以及图4所示的步骤，可以去除位于相邻第一子沟槽20交界处的第一隔离膜21，以露出位于相邻第一子沟槽20的交界处的衬底1。
参考图5，对被第一隔离膜21露出衬底1进行刻蚀，以形成孔洞24。此步骤的半导体结构的俯视图未发生变化，可以参考图3(b)。
示例地，对暴露的衬底1进行各向同性刻蚀，使得衬底1被进一步打开从而形成孔洞24。在第二方向Y上，孔洞24的深度可以为100nm～200nm。需要说明的是，若孔洞24的深度过小，则孔洞24可能难以为字线32提供充足的填充位置，从而提高字线32的电阻；当孔洞24的深度过大时，则可能会在字线32中产生孔隙等缺陷。当孔洞24的深度处于上述范围时，能够便于后续进行字线32填充，保证字线32具有合适的尺寸，并减少字线32内的缺陷，从而提高半导体结构的性能。
至此，基于图3(a)～图3(b)、图4以及图5所示的步骤，可以在相邻第一子沟槽20的交界处形成背向第一沟槽2凸出的孔洞24。即，第一隔离膜21可以作为形成孔洞24的掩膜层，用于控制形成孔洞24的位置以及尺寸。
参考图6，在孔洞24的内壁形成栅介电层31。此步骤的半导体结构的俯视图未发生变化，可以参考图3(b)。示例地，采用热氧化工艺在孔洞24的内壁形成氧化硅以作为晶体管的栅介电层31。在另一些实施例中，可以采用原子层沉积工艺在孔洞24的内壁沉积高介电常数材料以作为栅介电层31。
参考图7(a)～图7(b)，图7(b)为图7(a)所示的半导体结构的俯视图，在第一沟槽2的侧壁以及孔洞24内形成初始字线321。示例地，采用各向同性沉积工艺沉积钨和氮化钛作为初始字线321。
参考图8(a)～图8(b)，图8(b)为图8(a)所示的半导体结构的俯视图，采用各向同性刻蚀工艺以去除位于第一沟槽2侧壁和孔洞24内的部分初始字线321，孔洞24内剩余的初始字线321作为字线32。字线32作为晶体管的栅极，栅介电层31还覆盖字线32。具体地，栅介电层31覆盖字线32远离第一沟槽2内部的侧面。
至此，基于图7(a)～图7(b)以及图8(a)～图8(b)所示的步骤，可以在相邻第一子沟槽20的交界处形成背向第一沟槽2凸出的字线32，字线32沿第三方向Z延伸。
参考图9(a)～图9(b)，图9(b)为图9(a)所示的半导体结构的俯视图，在孔洞24内和第一子沟槽20的侧壁形成初始绝缘层331。示例地，采用各向同性沉积工艺沉积氮化硅以作为初始绝缘层331，从而封闭孔洞24。初始绝缘层331的材料可以与第一隔离膜21的材料不同，从而避免在后续去除第一隔离膜21的过程中将绝缘层33去除。
参考图10(a)～图10(b)，图10(b)为图10(a)所示的半导体结构的俯视图，以衬 底1本身为掩膜，沿第一方向X刻蚀位于第一子沟槽20侧壁的初始绝缘层331，剩余的初始绝缘层331作为绝缘层33。绝缘层33的侧壁与孔洞24开口齐平。栅介电层31还覆盖绝缘层33的表面。
至此，基于图9(a)～图9(b)以及图10(a)～图10(b)所示的步骤，可以在孔洞24内形成绝缘层33，绝缘层33位于字线32朝向第一沟槽2的一侧。需要说明的是，形成绝缘层33的目的主要包括两方面：第一，将字线32与后续形成的电容极板72(参考图26(a))相隔离，以避免发生短路；第二，绝缘层33可以在第一方向X上与后续形成的第一源漏层61(参考图24)正对，即，减少字线32与第一源漏层61的正对面积，从而降低漏电的风险。
参考图11(a)～图11(b)，图11(b)为图11(a)所示的半导体结构的俯视图，形成字线32后，还包括：在第一沟槽2中填充牺牲层22。牺牲层22可以在后续形成第二沟槽5、第二源漏层62、第二金属硅化物层63以及位线64等步骤中保护第一沟槽2不受到污染，从而保证半导体结构的性能。
示例地，在第一沟槽2中沉积氧化硅以作为牺牲层22。沉积氧化硅后还可以进行平坦化处理，以磨平衬底1的上表面和牺牲层22的上表面。在一些实施例中，牺牲层22的材料可以与第一隔离膜21的材料相同，如此，后续可以利用同一工艺步骤去除牺牲层22和第一隔离膜21，从而简化生产工艺。
参考图12，图12为俯视图，去除部分衬底1、部分牺牲层22以形成多个间隔设置的隔离沟槽4，多个隔离沟槽4在第二方向Y上延伸并在第三方向Z上排列。
示例地，在衬底1和牺牲层22上形成掩膜，利用掩膜刻蚀衬底1和牺牲层22。需要注意的是，在刻蚀过程中，字线32不能够被切断。
参考图13，图13为俯视图，形成多个间隔设置的第一隔离结构41；多个第一隔离结构41沿第二方向Y延伸且在第三方向Z上排布。第一隔离结构41包覆多条字线32，即第一隔离结构41未将字线32截断。此外，第一隔离结构41还将牺牲层22分割为多个。
示例地，在隔离沟槽4中填充氮化硅以作为第一隔离结构41，此后，进行平坦化处理以磨平衬底1、牺牲层22和第一隔离结构41的上表面。在一些实施例中，第一隔离结构41的材料可以与牺牲层22的材料不同，从而可以避免在后续去除牺牲层22的过程中消耗第一隔离结构41。
参考图14(a)～图14(b)，图14(b)为图14(a)所示的半导体结构的俯视图，形成第一隔离结构41后，在衬底1内形成第二沟槽5，第二沟槽5深度方向为第一方向X；第二沟槽5包括多个在第一方向X排布的第二子沟槽50，第二子沟槽50的侧壁呈外凸形。即第二沟槽5也具有波浪状的侧壁。第一隔离结构41还横跨第一沟槽2和第二沟槽5。为了更加直观，图14(b)以及后续的俯视图中均采用白色填充块示意第二沟槽5。
具体地，采用博世工艺形成第二沟槽5，有关第二沟槽5具体的形成工艺可参考第一沟槽2的详细说明。
需要说明的是，第一隔离结构41与衬底1的材料可以不同，因而在刻蚀衬底1以形成第二沟槽5的过程中，第一隔离结构41可以不被去除。
在另一些实施例中，也可以先形成沿第三方向Z延伸的第二沟槽5，此后，再形成沿第二方向Y延伸的第一隔离结构41，以将第二沟槽5分割为多个。比如，先在同一工艺步骤中形成第一沟槽2和第二沟槽5；此后，在第二沟槽5中填充牺牲材料；此后，在第一沟槽2中形成第一隔离膜21、字线32、绝缘层33等结构；此后，形成第一隔离结构41以横跨第一沟槽2和第二沟槽5。由于第一沟槽2和第二沟槽5可以集成在同一工艺步骤，因而简化生产工艺。
参考图15(a)～图15(b)，图15(b)为图15(a)所示的半导体结构的俯视图，在第二沟槽5的侧壁形成初始第二隔离膜511，位于相邻第二子沟槽50交界处的初始第二隔离膜511朝向第二子沟槽50的内部凸出设置。即，由于第二沟槽5的侧壁具有波浪形状，因而，形成于第二沟槽5侧壁的初始第二隔离膜511也具有波浪形状。
示例地，采用各向同性沉积工艺形成氮化硅膜以作为初始第二隔离膜511。
参考图16(a)～图16(b)，图16(b)为图16(a)所示的半导体结构的俯视图，以衬底1自身为掩膜，沿第一方向X刻蚀位于相邻第二子沟槽50的交界处的部分初始第二隔离膜511。即，采用各向异性刻蚀工艺将相邻第二子沟槽50交界处凸出的初始第二隔离膜511切平，从而使得此处的初始第二隔离膜511变薄。
参考图17，采用各向同性刻蚀工艺，去除位于相邻第二子沟槽50的交界处的剩余的初始第二隔离膜511，以露出位于相邻第二子沟槽50的交界处的衬底1，剩余的初始第二隔离膜511作为第二隔离膜51。也就是说，在各向同性刻蚀工艺中，相邻第二子沟槽50交界处较薄的初始第二隔离膜511会更快地被去除，从而暴露了一定宽度的衬底1。此步骤的半导体结构的俯视图未发生变化，可以参考图16(b)。
至此，基于图16(a)～图16(b)以及图17所示的步骤，可以去除位于相邻第二子沟槽50交界处的初始第二隔离膜511，以露出位于相邻第二子沟槽50的交界处的衬底1。
参考图18，对被第二隔离膜51露出衬底1进行掺杂处理以形成第二源漏层62。示例地，利用等离子体掺杂处理向衬底1内注入n型掺杂离子从而形成第二源漏层62。此步骤的半导体结构的俯视图未发生变化，可以参考图16(b)。
第二源漏层62和字线32均位于第一沟槽2与第二沟槽5之间，且第二源漏层62与字线32相对设置。第二源漏层62还与栅介电层31相接触。
另外，在第三方向Z上相邻排布的第二源漏层62被第一隔离结构41隔开，从而避免发生相互干扰。在第一方向X上排布的第二源漏层62被第二隔离膜51隔开，从而避免发生互联。
至此，基于图16(a)～图16(b)、图17以及图18所示的步骤，可以在相邻第二子沟槽50的交界处形成背向第二沟槽5凸出的第二源漏层62。也就是说，第二隔离膜51可以作为形成第二源漏层62的掩膜，从而避免相邻第二源漏层62在第一方向X上产生互联。
参考图19，去除靠近第二沟槽5内部的部分第二源漏层62，以形成接触口52。示例地，采用各向同性刻蚀去除被第二隔离膜51露出的部分第二源漏层62，以增大第二源漏层62被露出的面积。此步骤的半导体结构的俯视图未发生变化，可以参考图16(b)。
参考图20，在接触口52中形成第二金属硅化物层63。即，形成与第二源漏层62相接触的第二金属硅化物层63，且第二金属硅化物层63位于第二源漏层62靠近第二沟槽5内部的一侧。示例地，先在接触口52内沉积一层金属层，对金属层进行退火处理，以使金属层与第二源漏层62发生反应从而生成第二金属硅化物层63。
第二金属硅化物层63能够减少后续形成的位线64与第二源漏层62的接触电阻，从而提高半导体结构的电性能。在另一些实施例中，也可以不形成第二金属硅化物层63。
需要说明的是，接触口52能够增大第二金属硅化物层63与第二源漏层62的接触面积，从而降低接触电阻。在一些实施例中，第二金属硅化物层63可以只附着于接触口52的内壁，而不填充满接触口52，即后续形成的位线64还可以填充于接触口52，从而有利于增大位线64的填充空间，并且增大位线64与第二金属硅化 物层63的接触面积。在另一些实施例中，第二金属硅化物层63也可以填充满接触口52。
参考图21(a)～图21(b)，形成填充第二沟槽5的多条位线64，位线64沿第一方向X延伸，位线64与第二源漏层62电连接，即每条位线64在第一方向X上与多个第二源漏层62电连接。在第三方向Z上相邻排布的两条位线64被隔离结构41隔开。位线64还与第二金属硅化物层63相接触。
示例地，在第二沟槽5中沉积钨和氮化钛等金属以作为位线64。沉积金属后，对金属进行抛光磨平。
参考图22(a)～图22(b)，回刻部分位线64，并形成第三隔离膜57以封闭第二沟槽5的顶部。第三隔离膜57能够对位线64起到保护作用，避免其受到污染、氧化。
参考图23(a)～图23(b)，形成位线64后，去除牺牲层22。另外，还去除位于第一子沟槽20侧壁的第一隔离膜21，从而露出第一子沟槽20的侧壁。
示例地，采用湿法刻蚀工艺去除牺牲层22和第一隔离膜21。
参考图24，去除牺牲层22后，在第一子沟槽20的侧壁形成第一源漏层61。第一源漏层61还与栅介电层31相接触。具体地，对第一子沟槽20的侧壁进行掺杂处理，以形成第一源漏层61。示例地，采用等离子体掺杂工艺在第一沟槽2内暴露的衬底1中注入n型掺杂离子。
需要注意的是，第一源漏层61在第二方向Y上的掺杂深度较浅，从而能够使得第一源漏层61与字线32在第一方向上X上错开，避免二者之间产生交叠区，或者减小二者的交叠面积，进而避免第一源漏层61与字线32之间发生漏电的问题。
另外，在第三方向Z上相邻排布的第一源漏层61被第一隔离结构41隔开，以避免相邻第一源漏层61之间发生相互干扰。
参考图25(a)～图25(b)，在第一沟槽2的侧壁以及衬底1的上表面形成初始介质层811，初始介质层811还覆盖第一源漏层61。示例地，沉积高介电常数材料以作为初始介质层811。高介电常数材料有利于提高电容容量。
参考图26(a)～图26(b)，去除位于衬底1上表面的初始介质层811，第一沟槽2侧壁的初始介质层811作为介质层71。
继续参考图26(a)～图26(b)，形成填充第一沟槽2的多个电容极板82，电容极板82还覆盖介质层81；多个电容极板82在第三方向Z上排列并在第一方向X上延伸。在第三方向Z上相邻排布的电容极板82被第一隔离结构41隔开。
也就是说，第一源漏层61、电容极板82、介质层81构成了电容，此电容与第一源漏层61、第二源漏层62和字线32所构成的晶体管相连。可以理解的是，由于第一源漏层61还作为电容的一个极板，因而有利于省去第一源漏层61与电容之间的电连接结构，如此，生产工艺更加简单。
示例地，在第一沟槽2中填充钨和氮化钛等金属作为电容极板82，此后，对电容极板82以及衬底1的上表面进行抛光处理。
参考图27(a)～图27(b)，回刻部分电容极板82，并沉积第四隔离膜23以封闭第一沟槽2的顶部，第四隔离膜23可以对电容极板82起到保护作用。示例地，第四隔离膜23的材料可以为氮化硅。
至此，基于图1(a)～图27(b)所示的步骤，可以完成3D DRAM的前段制造。值得注意的是，按照前述顺序进行各工艺步骤有利于减少对半导体结构的污染，减少杂质残留。在另一些实施例中，也可以对各工艺步骤的顺序可以进行调整。比如，先形成第二沟槽5，并基于波浪形状的第二沟槽5形成第二源漏层62、第二金属硅化物层63以及位线64等结构；此后，再形成第一沟槽2，并基于波浪形状的第一 沟槽2形成字线32、介质层81、电容极板82等结构。再比如，先形成第一沟槽2、字线32、第一源漏层61、介质层81和电容极板82等结构，此后再形成第二沟槽5、第二源漏层62和位线64等结构。
综上所述，采用博世工艺形成具有波浪形状的第一沟槽2和第二沟槽5，并基于波浪形状的第一沟槽2形成字线32和第一源漏层61，基于波浪形状的第二沟槽5形成第二源漏层62。由此，可以在硅衬底内形成晶体管，且避免使用IGZO和Superlattice这两种技术，从而可以减少半导体结构内的缺陷，提高半导体结构的性能。
本公开另一实施例还提供一种半导体结构的制造方法，该制造方法与前述实施例半导体结构的制造方法大致相同，主要的区别在于：该制造方法还形成了电极层7，且电极层7与位线64在第三方向Z上间隔设置。下面将对该制造方法进行详细说明。该制造方法与前述实施例的制造方法相同或相似的部分可以参考前面的详细说明，在此不再赘述。
参考图1～图13，形成第一沟槽2、字线32、绝缘层33、栅介电层31、第一隔离结构41、牺牲层22等结构。有关上述结构制造步骤的详细说明可以参考前述实施例的制造方法，在此不再赘述。
参考图28(a)～图28(b)，图28(b)为俯视图，图28(a)为图28(b)在A-A1方向上的剖面图，形成第一隔离结构41后，在衬底1内形成第二沟槽5，第二沟槽5深度方向为第一方向X；第一沟槽2与第二沟槽5在第二方向Y上排布；第二沟槽5包括多个在第一方向X排布的第二子沟槽50，第二子沟槽50的侧壁呈外凸形。即第二沟槽5也具有波浪状的侧壁。第一隔离结构41还横跨第一沟槽2和第二沟槽5。第一隔离结构41将第二沟槽5分割为多个间隔设置的位线电极槽54。需要说明的是，为了更加直观，图28(b)以及后续的俯视图中均采用白色填充块示意第二沟槽5。
具体地，采用博世工艺形成第二沟槽5，有关第二沟槽5具体的形成工艺可参考第一沟槽2的详细说明。
参考图29(a)～图29(b)，图29(b)为俯视图，图29(a)为图29(b)在A-A1方向上的剖面图，形成填充第二沟槽5的初始第二隔离结构531，即初始第二隔离结构531填充于位线电极槽54。在第三方向Z上，初始第二隔离结构531与第一隔离结构41交替设置。示例地，在第二沟槽5中沉积氮化硅以作为初始第二隔离结构531，即初始第二隔离结构531的材料可以与第一隔离结构41的材料相同。
参考图30(a)～图30(b)，图30(b)为俯视图，图30(a)为图30(b)在A-A1以及B-B1方向上的剖面图，对初始第二隔离结构531进行图形化处理，以形成第二隔离结构53。第二隔离结构53沿第二方向Y延伸，并将位线电极槽54分割为位线槽541和电极槽542。也就是说，第二沟槽5包括在第三方向Z间隔设置的位线槽541和电极槽542。位线槽541包括多个在第一方向X排布的子位线槽5410，电极槽542包括多个在第一方向X排布的子电极槽5420。子电极槽5420和子位线槽5410的侧壁均呈外凸形。在第三方向Z上，第二子沟槽50包括子电极槽5420和子位线槽5410。
参考图31(a)～图31(b)，图31(b)为俯视图，图31(a)为图31(b)在A-A1以及B-B1方向上的剖面图，在位线槽541和电极槽542的侧壁形成初始第二隔离膜511；位于相邻子位线槽5410交界处的初始第二隔离膜511朝向位线槽541的内部凸出设置；位于相邻子电极槽5420交界处的初始第二隔离膜511朝向电极槽542的内部凸出设置。即，由于位线槽541和电极槽542的侧壁具有波浪形状，因而，形成于位线槽541和电极槽542侧壁的初始第二隔离膜511也具有波浪形状。
示例地，采用各向同性沉积工艺形成氮化硅膜以作为初始第二隔离膜511。
参考图32(a)～图32(b)，图32(b)为俯视图，图32(a)为图32(b)在A-A1以及 B-B1方向上的剖面图，以衬底1自身为掩膜，沿第一方向X刻蚀位于相邻子位线槽5410的交界处的部分初始第二隔离膜511，以及位于相邻子电极槽5420的交界处的部分初始第二隔离膜511。即，采用各向异性刻蚀工艺将相邻子位线槽5410交界处以及相邻子电极槽5420交界处凸出的初始第二隔离膜511切平。
参考图33，采用各向同性刻蚀工艺，去除位于相邻子位线槽5410的交界处的剩余的初始第二隔离膜511，以露出位于相邻子位线槽5410的交界处的衬底1；并去除位于相邻子电极槽5420的交界处的剩余的初始第二隔离膜511，以露出位于相邻子电极槽5420的交界处的衬底1。子电极槽5420侧壁以及子位线槽5410侧壁的初始第二隔离膜511作为第二隔离膜51。也就是说，在各向同性刻蚀工艺中，相邻子位线槽5410交界处以及相邻子电极槽5420交界处较薄的初始第二隔离膜511会更快地被去除，从而暴露了一定宽度的衬底1。此步骤的半导体结构的俯视图未发生变化，可以参考图32(b)。
至此，基于图31(a)～图31(b)、图32(a)～图32(b)以及图33所示的步骤，可以形成位于子位线槽5410侧壁以及子电极槽5420侧壁的第二隔离膜51，第二隔离膜51露出相邻子位线槽5410的交界处的衬底1，并露出相邻子电极槽5420交界处的衬底1。
参考图34(a)～图34(c)，图34(c)为俯视图，图34(a)为图34(c)在A-A1方向上的剖面图，图34(b)为图34(c)在B-B1方向上的剖面图。形成填充电极槽542的第一掩膜层55，第一掩膜层55露出位线槽541。示例地，在电极槽542和位线槽541内填充光刻胶以作为初始第一掩膜层，对初始第一掩膜层进行光刻处理，以去除位线槽541内的初始第一掩膜层，剩余的初始第一掩膜层作为第一掩膜层55。部分第一掩膜层55还位于衬底1的上表面。
继续参考图34(a)，在相邻子位线槽5410的交界处形成背向第二沟槽5凸出的第二源漏层62。第二源漏层62还与栅介电层31相接触。示例地，形成第二隔离膜51后，对相邻子位线槽5410交界处的衬底1进行等离子体掺杂处理以形成第二源漏层62。即，第二隔离膜51可以为形成第二源漏层62的掩膜，用于控制第二源漏层62的位置和尺寸，且避免在第一方向X上相邻的第二源漏层62产生互联。第二源漏层62的掺杂离子可以为n型离子。
第二源漏层62和字线32均位于第一沟槽2与第二沟槽5之间，且第二源漏层62与字线32相对设置。
在第三方向Z上相邻的第二源漏层62之间具有第一隔离结构41。因此，在第三方向Z上相邻的第二源漏层62之间是相互隔离的。在第一方向X上相邻的第二源漏层62之间具有第二隔离膜51，因此，在第一方向X上相邻的第二源漏层62之间也是相互隔离的。
参考图35，去除靠近第二沟槽5内部的部分第二源漏层62，以形成接触口52。示例地，以第一掩膜层55和第二隔离膜51为掩膜，采用各向同性刻蚀去除被第二隔离膜51露出的部分第二源漏层62，以增大第二源漏层62被露出的面积。此步骤的半导体结构的俯视图以及B-B1方向上的剖面图未发生变化，可以参考图34(c)和图34(b)。
参考图36(a)～图36(c)，图36(c)为俯视图，图36(a)为图36(c)在A-A1方向上的剖面图，图36(b)为图36(c)在B-B1方向上的剖面图。去除第一掩膜层55，形成填充位线槽541的第二掩膜层56，第二掩膜层56露出电极槽542。示例地，将旧的光刻胶清洗完毕，在位线槽541和电极槽542内填充新的光刻胶以作为初始第二掩膜层，对初始第二掩膜层进行光刻处理，以去除位于电极槽542内的初始第二掩膜层，剩余的初始第二掩膜层作为第二掩膜层56。部分第二掩膜层56还位于衬底1 的上表面。
继续参考图36(b)，对相邻子电极槽5420的交界处的衬底1进行重掺杂处理，以形成重掺杂层71。示例地，采用等离子体掺杂处理在衬底1内注入p形掺杂离子以作为重掺杂层71。也就是说，重掺杂层71内的掺杂离子的类型可以与衬底1内的掺杂离子的类型相同。如此，可以为衬底1内的电荷提供快速流出通道，避免电荷在衬底1内累积。
在第二方向Y上，重掺杂层71的掺杂深度小于第二源漏层62的掺杂深度。即，重掺杂层71较小的掺杂深度能够避免第二源漏层62与重掺杂层71相接触，且避免重掺杂层71与栅介电层31相接触，进而避免发生漏电或短路的问题。
需要说明的是，由于子位线槽5410和子电极槽5420侧壁的第二隔离膜51在同一工艺步骤中形成，因而生产工艺更为简单。在另一些实施例中，第二隔离膜51可以只形成于子位线槽5410的侧壁，而不形成于子电极槽5420的侧壁，由此，可以露出整个电极槽542的侧壁，从而可以在整个电极槽542的侧壁形成重掺杂层71，由此，可以增大重掺杂层71与衬底1的接触面积，从而提高衬底1内电荷的流出速度。
参考图37(a)～图37(c)，图37(c)为俯视图，图37(a)为图37(c)在A-A1方向上的剖面图，图37(b)为图37(c)在B-B1方向上的剖面图。去除第二掩膜层56，露出位线槽541。
继续参考图37(a)，在第二源漏层62朝向位线槽541内部的一侧形成第二金属硅化物层63。第二金属硅化物层63还位于接触口52内。示例地，先在接触口52内沉积一层金属层，对金属层进行退火处理，以使金属层与第二源漏层62发生反应从而生成第二金属硅化物层63。
需要说明的是，接触口52能够增大第二金属硅化物层63与第二源漏层62的接触面积，从而降低接触电阻。在一些实施例中，第二金属硅化物层63可以只附着于接触口52的内壁，而不填充满接触口52，即后续形成的位线64还可以填充于接触口52，从而有利于增大位线64的填充空间，并且增大位线64与第二金属硅化物层63的接触面积。在另一些实施例中，第二金属硅化物层63也可以填充满接触口52。
参考图37(b)，在重掺杂层71朝向电极槽542内部的一侧形成第一金属硅化物层72。示例地，在重掺杂层71的侧壁形成金属层，进行高温退火处理以使金属层与重掺杂层71进行反应，从而生成第一金属硅化物层72。
在一些实施例中，可以同时形成第一金属硅化物层72和第二金属硅化物层63，从而简化生产工艺，降低生产成本。第一金属硅化物层72可以位于重掺杂层71与后续形成的导电层73之间，从而减少后续形成的导电层73与重掺杂层71的接触电阻；第二金属硅化物层63可以位于后续形成的位线64与第二源漏层62之间，从而减少形成的位线64与第二源漏层62的接触电阻，进而提高半导体结构的电性能。在另一些实施例中，也可以不形成第一金属硅化物层72和第二金属硅化物层63。
参考图38(a)～图38(c)，图38(c)为俯视图，图38(a)为图38(c)在A-A1方向上的剖面图，图38(b)为图38(c)在B-B1方向上的剖面图。形成填充位线槽541的位线64，位线64与第二金属硅化物层63相连，且位线64与第二源漏层62电连接。形成填充电极槽542的导电层73，导电层73与重掺杂层71电连接。
示例地，在位线槽541和电极槽542中同时沉积钨和氮化钛等金属材料层，位于位线槽541中的金属材料层作为位线64，位于电极槽542中的金属材料层作为导电层73。由于位线64和导电层73可以在同一工艺步骤中形成，因而生产工艺更 加简单。沉积金属材料层后，可以对金属材料层进行抛光磨平。
由图38(a)～图38(c)可知，位线64沿第一方向X延伸，且每条位线64在第一方向X上与多个第二源漏层62电连接。在第三方向Z上相邻的两条位线64之间具有第一隔离结构41和第二隔离结构53。导电层73沿第一方向X延伸，在第三方向Z上相邻的两条导电层73之间具有第一隔离结构41和第二隔离结构53。即，位线64可以与导电层73平行，且二者在第三方向Z上交替设置。
至此，基于图36(a)～图36(c)、图37(a)～图37(c)和图38(a)～图38(c)所示的步骤，可以在电极槽542内形成电极层7，电极层7与衬底1电连接。电极层7包括第一金属硅化物层72、导电层73和重掺杂层71。在另一些实施例中，电极层7可以包括导电层73和重掺杂层71，或者电极层7可以只由导电层73构成。
参考图39(a)～图39(c)，图39(c)为俯视图，图39(a)为图39(c)在A-A1方向上的剖面图，图39(b)为图39(c)在B-B1方向上的剖面图。回刻部分位线64和部分导电层73，并形成第三隔离膜57以封闭位线槽541和电极槽542的顶部。第三隔离膜57能够对位线64和导电层73起到保护作用，避免其受到污染、氧化。
参考图40(a)～图40(b)，图40(b)为俯视图，图40(a)为图40(b)在A-A1方向上的剖面图。去除牺牲层22以及位于第一子沟槽20侧壁的第一隔离膜21，从而露出第一子沟槽20的侧壁。示例地，采用湿法刻蚀工艺去除牺牲层22和第一隔离膜21。
参考图41(a)～图41(b)，在第一子沟槽20的侧壁形成第一源漏层61。此步骤的半导体结构的俯视图未发生变化，可以参考图40(b)。图41(a)为图40(b)在A-A1方向上的剖面图，图41(b)为图40(b)在B-B1方向上的剖面图。第一源漏层61还与栅介电层31相接触。另外，在第三方向Z上相邻的第一源漏层61之间具有第一隔离结构41，以避免相邻第一源漏层61之间发生相互干扰。另外，在第一方向X上相邻的第一源漏层61之间还具有绝缘层33。
具体地，对第一子沟槽20的侧壁进行掺杂处理，以形成第一源漏层61。示例地，采用等离子体掺杂工艺在第一沟槽2内暴露的衬底1中注入n型掺杂离子。
[0077]参考图42(a)～图42(b)，图42(b)为俯视图，图42(a)为图42(b)在A-A1方向上的剖面图。在第一沟槽2的侧壁形成介质层81，介质层81还覆盖第一源漏层61。
继续参考图42(a)～图42(b)，在第一沟槽2内形成多个间隔设置的电容极板82，电容极板82还覆盖介质层81；多个电容极板82在第三方向Z上排列并在第一方向X上延伸。在第三方向Z上相邻排布的电容极板82被第一隔离结构41隔开。
参考图43(a)～图43(d)，图43(d)为俯视图，图43(a)为图43(d)在A-A1方向上的剖面图，图43(b)为图43(d)在B-B1方向上的剖面图，图43(c)为图43(d)在C-C1方向上的剖面图。回刻部分电容极板82，并沉积第四隔离膜23以封闭第一沟槽2的顶部。
至此，基于图1(a)～图13以及图28(a)～图43(c)所示的步骤，可以完成3D DRAM的前段制造。值得注意的是，按照前述顺序进行各工艺步骤有利于减少对半导体结构的污染，减少杂质残留。在另一些实施例中，也可以对各工艺步骤的顺序可以进行调整。比如，先形成第二沟槽5，并将第二沟槽5分割为位线槽541和电极槽542，此后，基于波浪形状的位线槽541形成第二源漏层62、第二金属硅化物层63以及位线64等结构，并在电极槽542内形成电极层7；此后，再形成第一沟槽2，并基于波浪形的第一沟槽2形成字线32、介质层81、电容极板82等结构。再比如，先形成第一沟槽2、字线32、第一源漏层61、介质层81和电容极板82等结构，此后再形成第二沟槽5、第二源漏层62和位线64等结构。
综上，本实施例的制造方法在前一实施例的制造方法的基础上，形成了与衬底1电连接的电极层7，电极层7可以与外围区中的电源相连。由此，可以避免电荷在衬底1内积累，从而避免浮体效应，进而提高半导体结构的性能。另外，电极层7还可以包括重掺杂层71和第一金属硅化物层72，以引导电荷快速流出。
本公开又一实施例还提供了一种半导体结构，此半导体结构可以采用前面两个实施例所述的半导体结构的制造方法进行制造，有关此半导体结构的详细说明可以参考前述的详细说明，在此不再赘述。下面将结合附图对半导体结构进行详细说明。
示例一，如图27(a)～图27(b)所示，半导体结构包括：衬底1，衬底1内具有第一沟槽2和第二沟槽5，且二者的深度方向均为第一方向X；第一沟槽2包括多个在第一方向X排布的第一子沟槽20，第二沟槽5包括多个在第一方向X排布的第二子沟槽50，且第一子沟槽20和第二子沟槽50的侧壁均呈外凸形；相邻第一子沟槽20的交界处具有背向第一沟槽2凸出的字线32；第一子沟槽20的侧壁具有第一源漏层61；相邻第二子沟槽50的交界处具有背向第二沟槽5凸出的第二源漏层62；第二源漏层62和字线32均位于第一沟槽2与第二沟槽5之间，且第二源漏层62与字线32相对设置。
下面将对半导体结构进行具体说明。
首先需要说明的是，半导体结构内具有第一方向X、第二方向Y和第三方向Z，这三个方向不相同。示例地，第一方向X垂直于第二方向Y和第三方向Z，且第二方向Y与第三方向Z垂直。在一些实施例中，半导体结构可以为动态随机存取存储器(Dynamic Random Access Memory，DRAM)。半导体结构还包括：栅介电层31，栅介电层31覆盖字线32远离第一沟槽2内部的侧面，栅介电层31还与第一源漏层61和第二源漏层62相接触。即第一源漏层61、第二源漏层62、字线32和栅介电层31可以用于构成晶体管T(参考图44(a))。
半导体结构还包括：填充第一沟槽2的多个电容极板82；多个电容极板82在第三方向Z上间隔排布且沿第一方向X延伸，电容极板82还填充于第一沟槽2内。半导体结构还包括：位于第一沟槽2侧壁的介质层81，例如介质层81位于第一沟槽2相对的两个侧壁，介质层81还位于第一源漏层61与电容极板82之间。即第一源漏层61、介质层81和电容极板82构成电容。电容与晶体管T可构成基本的存储单元。
参考图44(a)，图44(a)示出了图27(a)的局部放大图。在向字线32提供开启电压时，可形成两个沟道，即字线32上下两侧的第一源漏层61与第二源漏层62之间均有电流流动。在晶体管T导通时，电容可以存储电荷或释放电荷。
继续参考图27(b)，第一沟槽2和第二沟槽5在第二方向Y上排列，且二者均沿第三方向Z延伸。在一些实施例中，第一沟槽2为多个，第二沟槽5为多个，且第一沟槽2和第二沟槽5在第二方向Y上交替排布，从而有利于增多晶体管T和电容的数量，进而提高存储容量。
在一些实施例中，参考图27(a)～图27(b)，多个第一源漏层61在第三方向Z上间隔排列；多个第二源漏层62在第三方向Z上间隔排列；字线32沿第三方向Z延伸。也就是说，多个晶体管可以在第三方向Z上排列，且字线32可以作为在第三方向Z上排列的多个晶体管的栅极。此外，第一源漏层61和第二源漏层62均可以在第三方向Z上延伸，即二者在第三方向Z上可以均可以为柱状结构。
继续参考图27(a)～图27(b)，半导体结构还包括填充于第二沟槽5的多条位线64，多条位线64在第三方向Z上间隔排布且沿第一方向X延伸；位线64与第二源漏层62电连接。也就是说，位线64与第一方向X排布的多个第二源漏层62电 连接。位线64与外围电路电连接，位线64用于读取存储单元的存储数据或者向存储单元写入数据。
此外，半导体结构还包括第一隔离结构41，多个第一隔离结构41沿第二方向Y延伸且在第三方向Z上排布；第一隔离结构41横跨第一沟槽2和第二沟槽5。也就是说，第一隔离结构41用于隔离在第三方向Z上排列的多个晶体管，但并未截断字线32。具体地，在第三方向Z上相邻排布的第一源漏层61被第一隔离结构41隔开，在第三方向Z上相邻排布的第二源漏层62被第一隔离结构41隔开。即，在第三方向Z上相邻的第一源漏层61之间具有第一隔离结构41，在第三方向Z上相邻的第二源漏层62之间具有第一隔离结构41。此外，第一隔离结构41还用于隔离在第三方向Z上相邻的位线64，以及在第三方向Z上相邻的电容极板72。
值得注意的是，在示例一中，在相邻第一隔离结构41之间的第二沟槽5呈连续状态。因此，位线64在第三方向Z相对的两侧还与第一隔离结构41相接触，第二源漏层62在所述第三方向Z相对的两侧还与第一隔离结构41相接触。
示例二，参考图43(a)～图43(d)，以及图44(a)～图44(c)。图44(a)为图43(a)的局部放大图，图44(b)为图43(b)的局部放大图，图44(c)为半导体结构的局部剖面放大图，且该剖面垂直于第一方向X。半导体结构包括：衬底1，衬底1内具有第一沟槽2和第二沟槽5，且二者的深度方向均为第一方向X，二者的排布方向为第二方向Y，二者的延伸方向均为第三方向Z；第二沟槽5包括在第三方向Z间隔设置的位线槽541和电极槽542；第一沟槽2包括多个在第一方向X排布的第一子沟槽20，位线槽541包括多个在第一方向X排布的子位线槽5410；相邻第一子沟槽20的交界处具有背向第一沟槽2凸出的字线32；第一子沟槽20的侧壁具有第一源漏层61；相邻子位线槽5410的交界处具有背向第二沟槽5凸出的第二源漏层62；电极槽542内具有电极层7，且电极层7与衬底1电连接。
由此可知，示例一所示的半导体结构与示例二所示的半导体结构大致相同，主要区别在于，二者的第二沟槽5及其内部的结构不同。二者的第一沟槽2及其内部的结构可以相同，例如，二者的字线32、栅介电层31、绝缘层33、第一源漏层61、电容极板82、介质层81等结构可以相同。二者相同或相似的部分可以参考示例一的详细说明，下面将结合附图对二者的区别进行详细说明。
参考图43(b)，电极槽542包括多个在第一方向X排布的子电极槽5420，子电极槽5420呈外凸形。参考图43(b)和图44(b)，电极层7包括电连接的重掺杂层71和导电层73，重掺杂层71至少位于相邻子电极槽5420的交界处的衬底1内，导电层73填充于电极槽542内。在另一些实施例中，重掺杂层71还可以覆盖电极槽542的整个侧壁。另外，电极层7还可以包括第一金属硅化物层72，第一金属硅化物层72位于导电层73与重掺杂层71之间。
在一些实施例中，半导体结构还包括沿第二方向Y延伸的第二隔离结构53。第一隔离结构41将第二沟槽5分割为多个在第三方向Z排列的位线电极槽54，第二隔离结构53将位线电极槽54分割为位线槽541和电极槽542。由此，可以实现位线64与电极层7之间的隔离。
在示例二中，由于半导体结构还包括与衬底1电连接的电极层7，从而可以避免浮体效应。电极层7与位线64平行设置，且二者在第三方向Z上交替排列，并被第二隔离结构53隔开。
对比示例一和示例二可知，示例一中相邻第一隔离结构41之间的第二沟槽5呈连续状态，示例二中相邻第一隔离结构41之间的第二沟槽5被第二隔离结构53截断。因此，示例一中位线64在第三方向Z上的长度等于第一源漏层62在第三方向Z上的长度，并等于相邻第一隔离结构41之间的距离。示例二中位线64在第三 方向Z上的长度小于第一源漏层61在第三方向Z上的长度，还小于相邻第一隔离结构41之间的距离。
示例三，参考图43(a)～图44(c)，以及图45-图52，半导体结构包括阵列区AR和外围区P，阵列区AR的衬底1内具有晶体管组T0，晶体管组T0包括在第一方向X排列的多层晶体管T；晶体管T包括字线32、第二源漏层62和两个第一源漏层61，字线32与第二源漏层62在第二方向Y排布，两个第一源漏层61在第一方向X上排列，并位于字线32的相对两侧；在第一方向X上，相邻两个晶体管T共用一个第一源漏层61；外围区P内具有子字线驱动器SWD，字线32与子字线驱动器SWD电连接，子字线驱动器SWD不同时为第一方向X上相邻两条字线32提供开启信号。
也就是说，示例一和示例二示出了半导体结构的阵列区AR，示例三在示例一和示例二的基础之上，还示出了半导体结构的外围区P，以及外围区P和阵列区AR之间的各结构的连接关系。下面将结合附图对示例三进行详细说明。
在一些实施例中，参考图45，晶体管组T0(参考图43(a))为多个，且多个晶体管组T0在衬底1内阵列排布。即多个晶体管组T0在第二方向Y上排布，且多个晶体管组T0还在第三方向Z上排布。换言之，在第三方向Z排列的多个晶体管组T0构成晶体管单元T1，且多个晶体管单元T1在第二方向Y上排列。由此，可以增加晶体管组T0的数量，从而提高半导体结构的存储容量。需要说明的是，图43(d)中的虚线框示出了一个晶体管单元T1在衬底1上的正投影的位置。
参考图43(a)～图44(c)，字线32沿第三方向Z延伸，且一条字线32被晶体管单元T1同一层的多个晶体管T共用。在一些实施例中，字线32在衬底1内为阵列排布，即，多条字线32在第一方向X上排布，且多条字线32还在第二方向Y上排布。此外，位线64填充于第二沟槽5内，且每一位线64连接同一晶体管组T0的多个第二源漏层62。
参考图45，图45示出了半导体结构在后段制程中的一种俯视图，为了更加直观，图45仅示出了部分结构。在前段制程完成后，在电容极板82的上表面形成电容插塞83，在位线64的上表面形成位线接触层BLC，在电极层7的上表面形成电极接触层74。电容插塞83、位线接触层BLC以及电极接触层74可以均在第一方向X上延伸。图45中虚线框示出了一个晶体管组T1在衬底1上的正投影的位置。以下将对阵列区AR与外围区P的连接结构以及连接关系进行详细说明。
参考图46，外围区P内具有子字线驱动器SWD，子字线驱动器SWD与字线32电连接，用于向字线32提供开启信号或关闭信号。子字线驱动器SWD与字线32之间的连接关系如下：
参考图46-图47，子字线驱动器SWD与字线32可通过引线柱36电连接。具体地，阵列区AR包括存储区AR1和台阶区AR2，台阶区AR2与存储区AR1在第三方向Z上排布。字线32从存储区AR1延伸至台阶区AR2内，且在衬底1上表面指向衬底1下表面的方向上，多条字线32的长度依次增大，即越底层的字线32越长。台阶区AR2内具有多个在第一方向X延伸的引线柱36，多个引线柱36与多个字线32一一对应相连，且引线柱36与子字线驱动器SWD电连接。即，通过层次刻蚀的方式，使得各层字线32在衬底1上的正投影错开，并通过引线柱36连出。
在一些实施例中，参考图46，台阶区AR2为两个，两个台阶区AR2在第三方向Z上排布且位于存储区AR1的相对两侧。由此，可以为引线柱36提供更加充足的空间位置，从而增大多个引线柱36之间距离，以降低相邻引线柱36之间的寄生电容。
在一些实施例中，多个子字线驱动器SWD分别位于阵列区AR在第三方向 Z排列的相对两侧。即多个子字线驱动器SWD分别与台阶区AR2相对设置，如此，可以减小子字线驱动器SWD与台阶区AR2之间的距离，从而有利于减小走线长度，降低走线电阻。另外，由于子字线驱动器SWD需要在衬底1上占据较大的面积，而引线柱36在台阶区AR2层次排开，有利于为子字线驱动器SWD提供更加充足的空间位置。
在一些实施例中，参考图46，同一晶体管单元T1的多条字线32可以从阵列区AR的同一侧延伸至同一台阶区AR2内，与同一晶体管单元T1的字线32相连的引线柱36位于阵列区AR的同一侧。因此，与同一晶体管单元T1电连接的多个子字线驱动器SWD可以位于阵列区AR的同一侧，从而便于将子字线驱动器SWD与引线柱36电连接，从而有利于减小走线长度，降低走线电阻。
另外，相邻晶体管单元T1的字线32可以分别从阵列区AR的两侧延伸至两个台阶区AR2内。这种交替排列的方式有利于提高结构的均一性，还能够增大多个引线柱36之间的间距，从而降低寄生电容。此外，与相邻晶体管单元T1电连接的多个子字线驱动器SWD分别位于阵列区AR的不同两侧，使得多个子字线驱动器SWD均匀分布于外围区P，还能够为子字线驱动器SWD提供更充足的空间位置，且减少空间浪费。
需要说明的是，由于上下两个晶体管T共用一个第一源漏层61，因此，为了防止发生读写错误，可以不同时开启上下相邻的两个晶体管T。即，子字线驱动器SWD不同时为第一方向X上相邻两条字线32提供开启信号。
在一些实施例中，晶体管T包括隔离晶体管和有效晶体管，隔离晶体管和有效晶体管在第一方向X上交替排列。向隔离晶体管提供常关的电压，以使其隔离两个有效晶体管。换言之，两个有效晶体管之间设有一个隔离晶体管，从而增大了有效晶体管之间的距离，且隔离晶体管处于常关状态，从而对两个有效晶体管起到隔离作用，避免相邻两个有效晶体管之间的相互干扰。
在一些实施例中，结合参考图46和图57，有效晶体管的字线32为第一字线321，隔离晶体管的字线32为第二字线322。即，字线32包括在第一方向X上交替排列的第一字线321和第二字线322，其中，多条第一字线321分别与不同的子字线驱动器SWD电连接，多条第二字线322连接同一常关信号源。具体地，多条第一字线321分别通过第一导线34与不同的子字线驱动器SWD相连。多条第二字线322可以通过第二导线35连接在一起，常关信号源向第二导线35施加常关信号。在一些实施例中，第二导线35可以直接与常关信号源相连。在另一些实施例中，第二导线35可以与提供常关信号的子字线驱动器SWD相连。由此，可以减少子字线驱动器SWD的数量，从而减少半导体结构的体积。
需要说明的是，第一导线34与第二导线35可以从相对两侧与引线柱36相连，从而避免产生交叉，进而降低干扰。示例地，参考图46，第一导线34与引线柱36的右侧相连，第二导线35与引线柱36的左侧相连。
在另一些实施例中，不同字线32也可与不同的子字线驱动器SWD电连接，因而，有效晶体管和隔离晶体管可以根据子字线驱动器SWD提供的信号而互相切换，因而，可以更加灵活地利用晶体管T。
参考图48-图50，外围区P内还具有感测放大器SA，感测放大器SA与位线64电连接，用于检测位线64上的信号，并对位线64的信号进行放大。感测放大器SA与位线64之间的连接结构及连接关系如下：
参考图48，形成电容插塞83、位线接触层BLC和电极接触层74后，还包括：在电容插塞83的上表面形成第一接触层84，在位线接触层BLC的上表面形成第二接触层BL2，在电极接触层74的上表面形成第三接触层75。除了在边缘位置 的第一接触层84、第二接触层BL2和第三接触层75，其余位于阵列区AR中间位置的第一接触层84、第二接触层BL2和第三接触层75均被第二方向Y排列的相邻两个晶体管组T0所共享。也就是说，电容极板82被其两侧的晶体管组T0共享，位线64被其两侧的晶体管组T0共享，电极层7被其两侧的晶体管组T0共享。由此，有利于提高衬底1面积的利用效率。
在一些实施例中，多个第一接触层84与多个第三接触层75排列在第二方向Y上的同一直线上，多个第二接触层BL2排列在另一第二方向Y的直线上。这样的排列方式能够便于后续设置连接线。
结合参考图48和图49，感测放大器SA与位线64可以通过位线连接线BL1电连接。
具体地，多条位线连接线BL1在第二方向Y延伸且在第三方向Z排列；位线连接线BL1与多条位线64电连接，即位线连接线BL1连接一行在第二方向Y排列的第二接触层BL2，从而电连接一行位线64。位线连接线BL1与字线32交叉设置，二者的交叉点可以对应一个晶体管T。
在一些实施例中，参考图49，多个感测放大器SA分别位于阵列区AR在第二方向Y排列的相对两侧。由此，可以为感测放大器SA提供更加充足的空间位置。另外，位线连接线BL1的端部还设有第四接触层BL3，第四接触层BL3用于与感测放大器SA电连接。在多个感测放大器SA分别位于阵列区AR的相对两侧时，多个第四接触层BL3也分别位于阵列区AR相对的两个边缘，如此，有利于增加第四接触层BL3之间的间距，从而降低第四接触层BL3之间的寄生电容。在另一些实施例中，多个感测放大器SA也可以位于阵列区AR的同一侧。
相邻位线连接线BL1分别连接阵列区AR不同两侧的感测放大器SA。因此，多个感测放大器SA的排布方式更为均一，生产工艺更简单；另外，位于同一侧的多个第四接触层BL3之间的间距相同，有利于均衡寄生电容。
参考图50，图50为位线连接线BL1的局部剖面图，且该剖面垂直于第二方向Y，位线连接线BL1的顶部和侧壁具有第五隔离膜65，以便于保护位线连接线BL1，并将位线连接线BL1与字线32相隔离。第五隔离层65的材料可以为氮化硅或氧化硅。
外围区P内还具有偏压信号源(图中未示出)，电极层7与偏压信号源电连接，偏压信号源为电极层7提供偏压信号，以固定衬底1的电位，避免电荷在衬底1内累积。电极层7与偏压信号源的连接结构和连接关系如下所述：
参考图51，在第二沟槽5包括在第三方向Z间隔设置的位线槽541和电极槽542，且电极槽542具有与衬底1电连接的电极层7的情况下：半导体结构还包括：电极连接线76，电极连接线76与多个电极层7电连接，电极连接线76与偏压信号源连接。在一些实施例中，电极连接线76包括相连的第一电极连接线77和多条第二电极连接线78，其中，第一电极连接线77在第二方向Y上延伸，第二电极连接线78在第三方向Z上延伸；第二电极连接线78与多个电极层7电连接，即第二电极连接线78与第三接触层75(参考图49)相连，进而与电极层7电连接。通过上述连接方式，多个电极层7能够获取同一偏压信号，从而有利于简化结构。
在另一些实施例中，在不设置电极层7的情况下，则无需设置电极连接线76。外围区P内还具有电容信号源(图中未示出)，电容极板82与电容信号源的电连接。电容信号源为电容极板82提供电容信号，电容极板82与电容信号源的连接结构和连接关系如下所述：
参考图51，半导体结构还包括：极板连接线85，极板连接线85与多个电容极板82电连接，极板连接线85与电容信号源电连接。在一些实施例中，极板连接 线85包括相连的第一极板连接线86和多条第二极板连接线87，其中，第一极板连接线86在第二方向Y上延伸，第二极板连接线87在第三方向Z上延伸；第二极板连接线87与多个电容极板82电连接。通过上述连接方式，多个电容极板82能够获取同一电容信号，从而有利于简化结构。示例的，电容信号可以为接地电压。
在一些实施例中，第一极板连接线86与第一电极连接线77分别位于阵列区AR的相对两侧；第二极板连接线87与第二电极连接线78在第二方向Y上交替排列。由此，极板连接线85与电极连接线76的排列方式更简单，且能够避免二者之间产生交叉关系，从而有利于降低信号干扰。这种排列方式还有利于缩短极板连接线85和电极连接线76的长度。另外，极板连接线85与电极连接线76可以同层设置，即二者可以通过同一工艺步骤形成，从而有利于降低生产成本。另外，极板连接线85和电极连接线76之间可以设置第三隔离结构79，第三隔离结构79的材料可以为氮化硅。
参考图52，图52示出了完整的半导体结构，综上所述，本公开实施例所提供的半导体结构具有3D堆叠的晶体管T和电容，晶体管T和电容构成存储单元。在第一方向X，可以通过不同时开启相邻存储单元的方式，以避免相邻存储单元的干扰。即字线32包括在第一方向X上交替设置的第一字线321和第二字线322，多个第一字线321可以连接不同的子字线驱动器SWD，第二字线322上的信号可以为常关信号。在第三方向Z，相邻存储单元被第一隔离结构41隔开。另外，位线64通过一条位线连接线BL1电连接在一起，并连接至感测放大器SA。所有电极层7可以电连接在一起，所有电容极板82可以电连接在一起。前述布局方式有利于降低信号干扰，且避免空间浪费，从而有利于提高半导体结构的性能。

Claims (37)

  1. 一种半导体结构的制造方法，其特征在于，包括：
    提供衬底(1)，在所述衬底(1)内形成第一沟槽(2)和第二沟槽(5)，且二者的深度方向均为第一方向(X)；
    所述第一沟槽(2)包括多个在所述第一方向(X)排布的第一子沟槽(20)，所述第二沟槽(5)包括多个在所述第一方向(X)排布的第二子沟槽(50)，且所述第一子沟槽(20)和所述第二子沟槽(50)侧壁均呈外凸形；
    在相邻所述第一子沟槽(20)的交界处形成背向所述第一沟槽(2)凸出的字线(32)；
    在所述第一子沟槽(20)的侧壁形成第一源漏层(61)；
    在相邻所述第二子沟槽(50)的交界处形成背向所述第二沟槽(5)凸出的第二源漏层(62)；所述第二源漏层(62)和所述字线(32)均位于所述第一沟槽(2)与所述第二沟槽(5)之间，且所述第二源漏层(62)与所述字线(32)相对设置。
  2. 根据权利要求1所述的半导体结构的制造方法，其特征在于，在形成所述字线(32)前，还包括：
    在相邻所述第一子沟槽(20)的交界处形成背向所述第一沟槽(2)凸出的孔洞(24)；
    在所述孔洞(24)的内壁形成栅介电层(31)，所述栅介电层(31)覆盖所述字线(32)，并与所述第一源漏层(61)和所述第二源漏层(62)相接触。
  3. 根据权利要求2所述的半导体结构的制造方法，其特征在于，形成所述孔洞(24)的步骤包括：
    在所述第一沟槽(2)的侧壁形成第一隔离膜(21)，位于相邻所述第一子沟槽(20)交界处的所述第一隔离膜(21)朝向所述第一子沟槽(20)的内部凸出设置；
    去除位于相邻所述第一子沟槽(20)交界处的所述第一隔离膜(21)，以露出位于所述相邻所述第一子沟槽(20)的交界处的所述衬底(1)；
    对被所述第一隔离膜(21)露出所述衬底(1)进行刻蚀，以形成所述孔洞(24)。
  4. 根据权利要求3所述的半导体结构的制造方法，其特征在于，去除位于相邻所述第一子沟槽(20)交界处的所述第一隔离膜(21)，以露出位于所述相邻所述第一子沟槽(20)的交界处的所述衬底(1)；包括：
    以所述衬底(1)自身为掩膜，沿所述第一方向(X)刻蚀位于相邻所述第一子沟槽(20)的交界处的部分所述第一隔离膜(21)；
    采用各向同性刻蚀工艺，去除位于相邻所述第一子沟槽(20)的交界处的剩余的所述第一隔离膜(21)，以露出位于所述相邻所述第一子沟槽(20)的交界处的所述衬底(1)。
  5. 根据权利要求2-4中任一项所述的半导体结构的制造方法，其特征在于，还包括：在所述孔洞(24)内形成绝缘层(33)，所述绝缘层(33)位于所述字线(32)朝向所述第一沟槽(2)的一侧；
    所述栅介电层(31)还覆盖所述绝缘层(33)的表面。
  6. 根据权利要求2-5中任一项所述的半导体结构的制造方法，其特征在于，形成所述字线(32)的步骤包括：
    在所述第一沟槽(2)的侧壁以及所述孔洞(24)内形成初始字线(321)；
    采用各向同性刻蚀工艺以去除位于所述第一沟槽(2)侧壁和所述孔洞(24)内的部分所述初始字线(321)，所述孔洞(24)内剩余的所述初始字线(321)作为所述字线(32)。
  7. 根据权利要求1-6中任一项所述的半导体结构的制造方法，其特征在于，形成填充所述第二沟槽(5)的多条位线(64)，所述位线(64)沿所述第一方向(X)延伸；所述位线(64)与所述第二源漏层(62)电连接。
  8. 根据权利要求7所述的半导体结构的制造方法，其特征在于，所述第一沟 槽(2)和所述第二沟槽(5)在第二方向(Y)上排列，且二者均沿第三方向(Z)延伸；所述第二方向(Y)垂直于所述第三方向(Z)，且二者均垂直于所述第一方向(X)；
    所述字线(32)沿所述第三方向(Z)延伸；
    所述制造方法还包括：形成多个间隔设置的第一隔离结构(41)；多个所述第一隔离结构(41)沿第二方向(Y)延伸且在所述第三方向(Z)上排布；
    所述第一隔离结构(41)横跨所述第一沟槽(2)和所述第二沟槽(5)；所述第一隔离结构(41)包覆多条所述字线(32)；
    在所述第三方向(Z)上相邻排布的所述第一源漏层(61)之间具有所述第一隔离结构(41)；
    在所述第三方向(Z)上相邻排布的所述第二源漏层(62)之间具有所述第一隔离结构(41)；
    在所述第三方向(Z)上相邻排布的所述位线(64)之间具有所述第一隔离结构(41)。
  9. 根据权利要求8所述的半导体结构的制造方法，其特征在于，在相邻所述第一隔离结构(41)之间的所述第二沟槽(5)呈连续状态；
    所述位线(64)在所述第三方向(Z)相对的两侧还与所述第一隔离结构(41)相接触，所述第二源漏层(62)在所述第三方向(Z)相对的两侧还与第一隔离结构(41)相接触。
  10. 根据权利要求9所述的半导体结构的制造方法，其特征在于，形成所述第二源漏层(62)的步骤包括：
    在所述第二沟槽(5)的侧壁形成初始第二隔离膜(511)，位于相邻所述第二子沟槽(50)交界处的初始所述第二隔离膜(511)朝向所述第二子沟槽(50)的内部凸出设置；
    去除位于相邻所述第二子沟槽(50)交界处的所述初始第二隔离膜(511)，以露出位于所述相邻所述第二子沟槽(50)的交界处的所述衬底(1)；剩余的所述初始第二隔离膜(511)作为第二隔离膜(51)；
    对被所述第二隔离膜(51)露出所述衬底(1)进行掺杂处理以至少形成所述第二源漏层(62)。
  11. 根据权利要求8所述的半导体结构的制造方法，其特征在于，所述第二沟槽(5)包括在第三方向(Z)间隔设置的位线槽(541)和电极槽(542)；所述位线槽(541)包括多个在所述第一方向(X)排布的子位线槽(5410)，所述电极槽(542)包括多个在所述第一方向(X)排布的子电极槽(5420)，所述子位线槽(5410)和所述子电极槽(5420)侧壁均呈外凸形；所述第二子沟槽(50)包括所述子位线槽(5410)和所述子电极槽(5420)；
    在所述电极槽(542)内形成电极层(7)，所述电极层(7)与所述衬底(1)电连接；
    在相邻所述子位线槽(5410)的交界处形成背向所述第二沟槽(5)凸出的第二源漏层(62)；
    在所述位线槽(541)内形成所述位线(64)。
  12. 根据权利要求11所述的半导体结构的制造方法，其特征在于，形成所述电极层(7)的步骤包括：
    至少对相邻所述子电极槽(5420)的交界处的所述衬底(1)进行重掺杂处理，以形成重掺杂层(71)；
    形成填充所述电极槽(542)的导电层(73)，所述导电层(73)与所述重掺杂层(71)电连接，所述电极层(7)包括所述导电层(73)和所述重掺杂层(71)。
  13. 根据权利要求12所述的半导体结构的制造方法，其特征在于，在形成所述电极层(7)以及所述第二源漏层(62)前，还包括：形成位于所述子位线槽(5410)侧壁以及所述子电极槽(5420)侧壁的第二隔离膜(51)，所述第二隔离膜(51)露出相邻所述子位线槽(5410)的交界处的所述衬底(1)，并露出相邻所述子电极槽(5420)的交界处的所述衬底(1)；
    形成所述第二隔离膜(51)后，对相邻所述子位线槽(5410)的交界处的所述衬底(1)进行掺杂处理，以形成所述第二源漏层(62)。
  14. 根据权利要求12或13所述的半导体结构的制造方法，其特征在于，所述重掺杂层(71)的掺杂深度小于所述第二源漏层(62)的掺杂深度。
  15. 根据权利要求12-14中任一项所述的半导体结构的制造方法，其特征在于，还包括：在所述导电层(73)和所述重掺杂层(71)之间形成第一金属硅化物层(72)；所述电极层(7)包括所述第一金属硅化物层(72)、所述导电层(73)和所述重掺杂层(71)。
  16. 根据权利要求11-15中任一项所述的半导体结构的制造方法，其特征在于，形成所述第一沟槽(2)、所述位线槽(541)和所述电极槽(542)的步骤包括：
    采用博世工艺形成所述第一沟槽(2)和所述第二沟槽(5)；
    所述第一隔离结构(41)横跨所述第一沟槽(2)和所述第二沟槽(5)；所述第一隔离结构(41)将所述第二沟槽(5)分割为多个间隔设置的位线电极槽(54)；
    形成沿所述第二方向(Y)延伸的第二隔离结构(53)，所述第二隔离结构(53)将所述位线电极槽(54)分割为所述位线槽(541)和所述电极槽(542)。
  17. 根据权利要求8-16中任一项所述的半导体结构的制造方法，其特征在于，形成所述第一隔离结构(41)后，还包括：
    在所第一沟槽(2)的侧壁形成介质层(71)，所述介质层(71)还覆盖所述第一源漏层(61)；
    形成填充所述第一沟槽(2)的多个电容极板(72)，所述电容极板(72)还覆盖所述介质层(71)；在所述第三方向(Z)上相邻排布的所述电容极板(72)被所述第一隔离结构(41)隔开。
  18. 根据权利要求1-17中任一项所述的半导体结构的制造方法，其特征在于，还包括：形成与所述第二源漏层(62)相接触的第二金属硅化物层(63)，且所述第二金属硅化物层(63)位于所述第二源漏层(62)靠近所述第二沟槽(5)内部的一侧。
  19. 根据权利要求18所述的半导体结构的制造方法，其特征在于，在形成所述第二金属硅化物层(63)前，还包括：
    去除靠近所述第二沟槽(5)内部的部分所述第二源漏层(62)，以形成接触口(52)；
    在所述接触口(52)中形成所述第二金属硅化物层(63)。
  20. 根据权利要求1-19中任一项所述的半导体结构的制造方法，其特征在于，形成所述第一源漏层(61)的步骤包括：对所述第一子沟槽(20)侧壁的所述衬底(1)进行掺杂处理，以形成所述第一源漏层(61)。
  21. 一种半导体结构，其特征在于，包括：
    衬底(1)，所述衬底(1)内具有第一沟槽(2)和第二沟槽(5)，且二者的深度方向均为第一方向(X)；所述第一沟槽(2)包括多个在所述第一方向(X)排布的第一子沟槽(20)，所述第二沟槽(5)包括多个在所述第一方向(X)排布的第二子沟槽(50)，且所述第一子沟槽(20)和所述第二子沟槽(50)的侧壁呈外凸形；
    相邻所述第一子沟槽(20)的交界处具有背向所述第一沟槽(2)凸出的字线(32)；
    所述第一子沟槽(20)的侧壁具有第一源漏层(61)；
    相邻所述第二子沟槽(50)的交界处具有背向所述第二沟槽(5)凸出的第二源漏层(62)；所述第二源漏层(62)和所述字线(32)均位于所述第一沟槽(2)与所述第二沟槽(5)之间，且所述第二源漏层(62)与所述字线(32)相对设置。
  22. 根据权利要求21所述的半导体结构，其特征在于，还包括：栅介电层(31)，所述栅介电层(31)覆盖所述字线(32)远离所述第一沟槽(2)内部的侧面，所述栅介电层(31)还与所述第一源漏层(61)和所述第二源漏层(62)相接触。
  23. 根据权利要求21或22所述的半导体结构，其特征在于，还包括：填充所 述第一沟槽(2)的多个电容极板(72)；多个所述电容极板(72)在第三方向(Z)上间隔排布且沿所述第一方向(X)延伸；所述第三方向(Z)垂直于所述第一方向(X)；
    所述半导体结构还包括：位于所述第一沟槽(2)侧壁的介质层(71)，所述介质层(71)还位于所述第一源漏层(61)与所述电容极板(72)之间。
  24. 根据权利要求21-23中任一项所述的半导体结构，其特征在于，还包括：填充于所述第二沟槽(5)的多条位线(64)，多条所述位线(64)在第三方向(Z)上间隔排布且沿所述第一方向(X)延伸；所述第三方向(Z)垂直于所述第一方向(X)；所述位线(64)与所述第二源漏层(62)电连接；
    所述字线(32)沿所述第三方向(Z)延伸；
    多个所述第一源漏层(61)在所述第三方向(Z)上间隔排列；多个所述第二源漏层(62)在所述第三方向(Z)上间隔排列。
  25. 根据权利要求24所述的半导体结构，其特征在于，所述位线(64)在所述第三方向(Z)上的长度等于所述第一源漏层(61)在所述第三方向(Z)的长度。
  26. 根据权利要求24所述的半导体结构，其特征在于，
    所述第二沟槽(5)包括在第三方向(Z)间隔设置的位线槽(541)和电极槽(542)；所述第一沟槽(2)包括多个在所述第一方向(X)排布的第一子沟槽(20)，所述位线槽(541)包括多个在所述第一方向(X)排布的子位线槽(5410)，所述电极槽(542)包括多个在所述第一方向(X)排布的子电极槽(5420)，所述子位线槽(5410)和所述子电极槽(5420)侧壁均呈外凸形；所述第二子沟槽(50)包括所述子电极槽(5420)和所述子位线槽(5410)；
    所述位线(64)填充于所述位线槽(541)内；
    所述第二源漏层(62)位于相邻所述子位线槽(5410)的交界处；
    所述电极槽(542)内具有电极层(7)，且所述电极层(7)与所述衬底(1)电连接。
  27. 根据权利要求26所述的半导体结构，其特征在于
    所述电极层(7)包括电连接第一金属硅化物层(72)、重掺杂层(71)和导电层(73)，所述重掺杂层(71)至少位于相邻所述子电极槽(5420)的交界处的所述衬底(1)内，所述导电层(73)填充于所述电极槽(542)内；第一金属硅化物层(72)位于所述导电层(73)和所述重掺杂层(71)之间。
  28. 根据权利要求21-27中任一项所述的半导体结构，其特征在于，所述半导体结构包括阵列区(AR)和外围区(P)，所述阵列区(AR)的所述衬底内具有晶体管组(T0)，所述晶体管组(T0)包括在第一方向(X)排列的多层晶体管(T)；所述晶体管(T)包括一条所述字线(32)、一个所述第二源漏层(62)和两个所述第一源漏层(61)，所述字线(32)与所述第二源漏层(62)在第二方向(Y)排布，两个第一源漏层(61)在所述第一方向(X)上排列，并位于所述字线(32)的相对两侧；在所述第一方向(X)上，相邻两个所述晶体管(T)共用一个所述第一源漏层(61)；
    所述外围区(P)内具有子字线驱动器(SWD)，所述字线(32)与所述子字线驱动器(SWD)电连接，所述子字线驱动器(SWD)不同时为所述第一方向(X)上相邻两条所述字线(32)提供开启信号。
  29. 根据权利要求28所述的半导体结构，其特征在于，所述字线(32)包括在所述第一方向(X)上交替排列的第一字线(321)和第二字线(332)，其中，多条所述第一字线(321)分别与不同的所述子字线驱动器(SWD)电连接，多条所述第二字线(332)连接同一常关信号源。
  30. 根据权利要求28或29所述的半导体结构，其特征在于，所述晶体管组(T0)为多个，在第三方向(Z)排列的多个所述晶体管组(T0)构成晶体管单元(T1)，且多个所述晶体管单元(T1)在所述第二方向(Y)上排列；所述第三方向(Z)与所述第二方向(Y) 垂直，且二者均与所述第一方向(X)垂直；
    所述字线(32)沿所述第三方向(Z)延伸，且一条所述字线(32)被所述晶体管单元(T1)同一层的多个所述晶体管(T)共用。
  31. 根据权利要求30所述的半导体结构，其特征在于，多个所述子字线驱动器(SWD)分别位于所述阵列区(AR)第三方向(Z)排列的相对两侧；
    与同一所述晶体管单元(T1)电连接的多个所述子字线驱动器(SWD)位于所述阵列区(AR)的同一侧；与相邻所述晶体管单元(T1)电连接的多个所述子字线驱动器(SWD)分别位于所述阵列区(AR)的不同两侧。
  32. 根据权利要求31所述的半导体结构，其特征在于，所述阵列区(AR)包括存储区(AR1)和两个台阶区(AR2)，两个所述台阶区(AR2)在所述第三方向(Z)上排布且位于所述存储区(AR1)的相对两侧；
    所述字线(32)从所述存储区(AR1)延伸至所述台阶区(AR2)内，且在所述衬底(1)上表面指向所述衬底(1)下表面的方向上，多条所述字线(32)的长度依次增大；
    所述台阶区(AR2)内具有多个在所述第一方向(X)延伸的引线柱(36)，多个所述引线柱(36)与多个所述字线(32)一一对应相连，且所述引线柱(36)与子字线驱动器(SWD)电连接。
  33. 根据权利要求28-32中任一项所述的半导体结构，其特征在于，所述晶体管组(T0)为多个，且多个所述晶体管组(T0)在所述衬底(1)内阵列排布；
    所述半导体结构还包括：填充于所述第二沟槽(5)内的位线(64)，且每一所述位线(64)连接同一所述晶体管组(T0)的多个所述第二源漏层(62)；多条在所述第二方向(Y)延伸且在第三方向(Z)排列的位线连接线(BL1)；所述位线连接线(BL1)与多条所述位线(64)(BL)电连接；
    所述外围区(P)内还具有感测放大器(SA)，所述位线连接线(BL1)与所述感测放大器(SA)电连接。
  34. 根据权利要求33所述的半导体结构，其特征在于，多个所述感测放大器(SA)分别位于所述阵列区(AR)在所述第二方向(Y)排列的相对两侧；
    相邻所述位线连接线(BL1)分别连接所述阵列区(AR)不同两侧的所述感测放大器(SA)。
  35. 根据权利要求28-32中任一项所述的半导体结构，其特征在于，所述第二沟槽(5)包括在第三方向(Z)间隔设置的位线槽(541)和电极槽(542)；所述电极槽(542)具有电极层(7)，所述电极层(7)与所述衬底(1)电连接；
    所述半导体结构还包括：电极连接线(76)，所述电极连接线(76)与多个所述电极层(7)电连接，所述电极连接线(76)与偏压信号源电连接。
  36. 根据权利要求35所述的半导体结构，其特征在于，还包括：介质层(81)和电容极板(82)，所述介质层(81)位于所述第一沟槽(2)相对的两个侧壁；
    所述电容极板(82)填充于所述第一沟槽(2)内，所述介质层(81)还位于所述第一源漏层(61)与所述电容极板(82)之间；
    所述半导体结构还包括：极板连接线(85)，所述极板连接线(85)与多个所述电容极板(82)电连接，所述极板连接线(85)与电容信号源电连接。
  37. 根据权利要求36所述的半导体结构，其特征在于，所述极板连接线(85)包括相连的第一极板连接线(86)和多条第二极板连接线(87)，其中，所述第一极板连接线(86)在所述第二方向(Y)上延伸，所述第二极板连接线(87)在所述第三方向(Z)上延伸；所述第二极板连接线(87)与多个所述电容极板(82)电连接；
    所述电极连接线(76)包括相连的第一电极连接线(77)和多条第二电极连接线(78)，其中，所述第一电极连接线(77)在所述第二方向(Y)上延伸，所述第二电极连 接线(78)在所述第三方向(Z)上延伸；所述第二电极连接线(78)与多个所述电极层(7)电连接；
    所述第一极板连接线(86)与所述第一电极连接线(77)分别位于所述阵列区(AR)的相对两侧；所述第二极板连接线(87)与所述第二电极连接线(78)在所述第二方向(Y)上交替排列。
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