Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/11—Printed elements for providing electric connections to or between printed circuits
  • H05K1/115—Via connections; Lands around holes or via connections
  • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/11—Printed elements for providing electric connections to or between printed circuits
  • H05K1/115—Via connections; Lands around holes or via connections
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
  • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
  • G01R31/2815—Functional tests, e.g. boundary scans, using the normal I/O contacts
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
  • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
  • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
  • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0237—High frequency adaptations
  • H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0266—Marks, test patterns or identification means
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
  • H05K1/0298—Multilayer circuits
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/14—Structural association of two or more printed circuits
  • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/18—Printed circuits structurally associated with non-printed electric components
  • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
  • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
  • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0237—High frequency adaptations
  • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
  • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/09372—Pads and lands
  • H05K2201/0939—Curved pads, e.g. semi-circular or elliptical pads or lands
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/09372—Pads and lands
  • H05K2201/09454—Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/095—Conductive through-holes or vias
  • H05K2201/09509—Blind vias, i.e. vias having one side closed
  • H05K2201/09527—Inverse blind vias, i.e. bottoms outwards in multilayer PCB; Blind vias in centre of PCB having opposed bottoms
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/095—Conductive through-holes or vias
  • H05K2201/09618—Via fence, i.e. one-dimensional array of vias
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/65—Shapes or dispositions of interconnections
  • H10W70/654—Top-view layouts
  • H10W70/655—Fan-out layouts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/69—Insulating materials thereof
  • H10W70/695—Organic materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

• the present invention relates to a wiring board and a mounting structure using the same.
• the wiring board according to the present disclosure has a laminated structure in which a plurality of insulating layers and a plurality of conductor layers are alternately laminated.
• the plurality of insulating layers include at least a first insulating layer located at the bottom layer, a second insulating layer located one layer above the first insulating layer, and a third insulating layer located at the top layer and having a mounting area.
• the plurality of conductor layers include first signal wiring.
• the first signal wiring includes a first electrode and a second electrode located on the lower surface of the first insulating layer, a protruding portion located on the lower surface of the first insulating layer so as to be in contact with the first electrode, and a first insulating layer.
• a linear conductor located between the layer and the second insulating layer, having a first end and a second end, a third electrode located on the upper surface of the third insulating layer, and penetrating the upper and lower surfaces of the first insulating layer.
• a first via hole conductor, a second via hole conductor, and a third via hole conductor are positioned so as to be.
• the first electrode and the third electrode are connected by a first wiring pattern including a first via hole conductor.
• the protruding portion and the first end of the linear conductor are connected by a second via hole conductor.
• the second end of the linear conductor and the second electrode are connected by a third via hole conductor.
• a mounting structure includes the above wiring board and an electronic component located in a mounting area of the wiring board.
• FIG. 2 is an explanatory diagram for explaining main parts of a wiring board according to an embodiment of the present disclosure.
• 2 is a plan view showing an example when viewed from arrow A shown in FIG. 1.
• FIG. 2 is a plan view showing another example when viewed from arrow A shown in FIG. 1.
• FIG. 6 is an explanatory diagram for explaining the shortest distance between the first electrode and the grounding conductor, the shortest distance between the protruding portion and the grounding conductor, and the shortest distance between the protruding portions of the pair electrodes.
• measurement pads are formed at the ends of the wiring board, and the pattern of the measurement wiring path is significantly different from the actual product pattern. Further, although it is desired to measure electrical characteristics in a state where a signal pad is surrounded by a ground conductor layer, conventional testing results in a portion of the signal pad not being surrounded by a ground conductor layer. In this way, when a portion of the signal pad is not surrounded by the ground conductor, the electrical characteristics deteriorate. Therefore, there is a need for a wiring board in which the pattern of wiring paths for measurement is close to the actual product pattern and on which accurate electrical characteristics can be measured.
• the wiring board according to the present disclosure has the configuration described in the column of means for solving the problems, so that the pattern of the wiring route for measurement is close to the actual product pattern, and accurate electrical characteristics can be measured. I can do it. Further, in the mounting structure according to the present disclosure, electronic components are mounted on a wiring board whose electrical characteristics have been accurately measured. Therefore, the mounting structure according to the present disclosure has excellent electrical reliability and can reduce defects such as malfunction of electronic components.
• FIG. 1 is an explanatory diagram for explaining main parts of a wiring board 10 according to an embodiment of the present disclosure. Specifically, FIG. 1 shows the vicinity of an area to be connected to a measuring device in order to test (measuring electrical characteristics) whether a signal is transmitted as designed.
• the wiring board 10 has a laminated structure in which a plurality of insulating layers 1 and a plurality of conductor layers 2 are alternately laminated.
• the insulating layer 1 includes, for example, a build-up insulating layer laminated on the main surface of at least one of the core insulating layer 11 and the core insulating layer 11.
• a wiring board 10 according to one embodiment is connected to a motherboard 20 via solder 6, for example, as shown in FIG.
• the insulating layer 1 is made of, for example, a resin such as epoxy resin, bismaleimide-triazine resin, polyimide resin, polyphenylene ether resin, or liquid crystal polymer. These resins may be used alone or in combination of two or more. Insulating particles may be dispersed in the insulating layer 1.
• the insulating particles are not limited, and examples include inorganic insulating fillers such as silica, alumina, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide.
• the core insulating layer 11 and the buildup insulating layer may be formed of the same resin or different resins. Further, the layers constituting the build-up insulating layer may be made of the same resin, or may be made of different resins.
• the insulating layer 1 may contain a reinforcing material.
• the reinforcing material include insulating cloth materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more reinforcing materials may be used in combination.
• inorganic insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide may be dispersed in the insulating layer 1.
• the core insulating layer 11 When the insulating layer 1 is the core insulating layer 11, the core insulating layer 11 has a thickness of, for example, 200 ⁇ m or more and 1400 ⁇ m or less.
• the core insulating layer 11 has through-hole conductors for electrically connecting the conductor layers 2 located on the upper and lower surfaces of the core insulating layer 11.
• the through-hole conductor is located in a through-hole that penetrates the upper and lower surfaces of the core insulating layer 11.
• the through-hole conductor is formed of a conductor made of metal plating such as copper plating, for example.
• the through-hole conductor is connected to the conductor layers 2 on both sides of the core insulating layer 11.
• the through-hole conductor may be formed only on the inner wall surface of the through-hole, or may be filled within the through-hole.
• the build-up insulating layer has a thickness of, for example, 5 ⁇ m or more and 100 ⁇ m or less.
• the layers constituting the build-up insulating layer may be made of the same resin, or may be made of different resins.
• the build-up insulating layer has a via hole conductor for electrically connecting the conductor layers 2 located above and below each other via the build-up insulating layer.
• the via hole conductor is obtained by depositing, for example, copper plating on a via hole that passes through the upper and lower surfaces of the buildup insulating layer.
• the via hole conductor may be positioned so as to fill the inside of the via hole as shown in FIG. It doesn't matter if you stay there.
• the conductor layer 2 is located on the main surface of the insulating layer 1, that is, on the main surface of the core insulating layer 11 and the main surface of the build-up insulating layer.
• the conductor layer 2 is made of copper such as copper foil or copper plating.
• the thickness of the conductor layer 2 is not particularly limited, and is, for example, 3 ⁇ m or more and 30 ⁇ m or less.
• a solder resist 5 is located on a portion of the upper and lower surfaces of the wiring board 10.
• the solder resist 5 is made of, for example, an acrylic modified epoxy resin.
• the solder resist 5 has a function of, for example, protecting the conductor layer 2 from adhering to the solder 6 when electronic components are mounted.
• the solder resist 5 has an opening. The conductor layer 2 exposed through this opening functions as an electrode.
• the insulating layer 1 includes a first insulating layer 1a located at the bottom layer, a second insulating layer 1b located one layer above the first insulating layer 1a, and a second insulating layer 1b located at the top layer. It includes at least a third insulating layer 1c having a cage mounting area.
• the outermost build-up insulating layer corresponds to the first insulating layer 1a.
• the build-up insulating layer located one layer inside the first insulating layer 1a (on the core insulating layer 11 side) corresponds to the second insulating layer 1b.
• the outermost buildup insulating layer corresponds to the third insulating layer 1c.
• the conductor layer 2 includes a first signal wiring 21 for electrical measurement.
• the first signal wiring 21 includes a first electrode 31, a second electrode 32, a third electrode 33, a protruding portion 3a, a linear conductor 3b, a first via hole conductor 41, a second via hole conductor 42, and a third via hole conductor 43. . That is, the first signal wiring 21 is a series of wiring paths from the second electrode 32 to the third electrode 33 shown in FIG.
• the first electrode 31 and the second electrode 32 are located on the lower surface of the first insulating layer 1a.
• the first electrode 31 and the second electrode 32 are exposed through the opening of the solder resist 5.
• the first electrode 31 and the second electrode 32 are connected via a linear conductor 3b, as shown in FIG.
• the linear conductor 3b is located between the first insulating layer 1a and the second insulating layer 1b.
• the linear conductor 3b and the first electrode 31 are connected via the protruding portion 3a and the second via hole conductor 42, which are positioned so as to be in contact with the first electrode 31.
• the second via hole conductor 42 is connected to the vicinity of the first end 3b1 of the linear conductor 3b.
• the linear conductor 3b and the second electrode 32 are connected via a third via hole conductor 43.
• the third via hole conductor 43 is connected to the vicinity of the second end 3b2 of the linear conductor 3b.
• the first electrode 31 and the third electrode 33 located on the upper surface of the third insulating layer 1c are connected by a first wiring pattern P1 including a first via hole conductor 41. That is, the first wiring pattern P1 refers to a series of wiring paths from the first via hole conductor 41 shown in FIG. 1 to the via hole conductor connected to the third electrode 33.
• the conductor layer 2 may further include a grounding conductor 23.
• FIG. 2 is a plan view showing an example when viewed from arrow A shown in FIG. FIG. 2(A) shows the conductor layer 2 on the bottom surface, and FIG. 2(B) shows the one layer inside (the core insulating layer 11 side) from the bottom conductor layer 2, and the first electrode 31 and the second electrode 32 neighborhood is shown.
• the grounding conductor 23 is located, for example, on the lower surface of the first insulating layer 1a and between the first insulating layer 1a and the second insulating layer 1b. As shown in FIGS. 2(A) and 2(B), the grounding conductor 23 is located so as to surround both sides of the linear conductor 3b and the first electrode 31 in plan view. "Grounding conductors 23 located on both sides of the linear conductor 3b" means, for example, the grounding conductors 23 located in the left and right directions along the longitudinal direction of the linear conductor 3b in FIG. 2(B). In this way, when the grounding conductor 23 is located so as to surround both sides of the linear conductor 3b and the first electrode 31, the electrical characteristics can be measured more accurately.
• the first electrode 31 may be one electrode, as shown in FIG. 2, or may be a pair electrode having two electrodes located adjacent to each other, as shown in FIG.
• the protruding portion 3a may be in contact with.
• FIG. 3 is a plan view showing another example when viewed from arrow A shown in FIG. 3(A) shows the conductor layer 2 on the bottom surface, and FIG. 3(B) shows the one layer inside (the core insulating layer 11 side) from the bottom conductor layer 2, and the first electrode 31 and the second electrode 32 neighborhood is shown.
• the first electrode 31 is a pair electrode, it becomes possible to efficiently transmit high frequency signals using differential signal lines.
• the position of the protruding portion 3a in contact with the first electrode 31 is not limited.
• the first distance L1 which is the shortest distance between the grounding conductor 23 and the first electrode 31, is longer than the second distance L2, which is the shortest distance between the grounding conductor 23 and the protruding portion 3a.
• the protruding portion 3a may be in contact with the first electrode 31 so as to be short. If the protruding portion 3a is in contact with the first electrode 31 such that the first distance L1 is shorter than the second distance L2, the electrical characteristics can be measured more accurately.
• first electrode 31 and the protruding portion 3a are in contact with each other, and the first electrode 31 and the protruding portion 3a can be seen as one electrode (pad).
• the first electrode 31 is connected to the first via hole conductor 41, and the protruding portion 3a is connected to the second via hole conductor 42. Therefore, since two via hole conductors are connected to what appears to be one electrode (pad), it is possible to improve the adhesion of the first electrode 31 and the protruding portion 3a to the first insulating layer 1a.
• the shape of the protruding portion 3a is not limited. As shown in FIGS. 3 and 4, the protruding portion 3a may have a circular shape. The circular shape enables more accurate measurement when using the de-embedding technique described below.
• the electrode When the first electrode 31 and the protruding portion 3a are viewed as one electrode (pad), the electrode may have a teardrop shape. The teardrop shape makes it easier to form the electrode and reduces peeling of the protruding portion 3a. For the same reason, the shape of the protruding portion 3a may be square.
• the protruding portion 3a Precise measurements can be made by making the protruding portion 3a as small as possible in terms of manufacturing. For this reason, the protruding portion 3a only needs to have a necessary minimum size to which the second via hole conductor 42 (which is connected to the protruding portion 3a) can be connected, and for example, the maximum width may be about 100 ⁇ m. It's okay. In other words, the protrusion portion 3a has a width larger than the maximum width of the second via hole conductor 42 in plan view.
• the protrusion portions 3a are may be in contact with the first electrode 31. If the protruding portion 3a is in contact with the first electrode 31 such that the first distance L1 is shorter than the third distance L3, the electrical characteristics can be measured more accurately.
• the first signal wiring 21 is a circuit used to measure electrical characteristics. Therefore, the first signal wiring 21 is not connected to the electronic components and the motherboard 20. After the electronic components are mounted, signals are transmitted and received between the electronic components and the motherboard 20 via the second wiring pattern P2.
• the second wiring pattern P2 connects the fourth electrode 34 located on the lower surface of the first insulating layer 1a and the fifth electrode 35 located on the upper surface of the third insulating layer 1c. That is, the second wiring pattern P2 is a series of wiring paths from the via hole conductor connected to the fourth electrode 34 to the via hole conductor connected to the fifth electrode 35.
• the second wiring pattern P2 is the same wiring route pattern as the first wiring pattern P1 that connects the first electrode 31 and the third electrode 33. In other words, the first wiring pattern P1 and the second wiring pattern P2 have the same configuration in wiring length, wiring width, size, quantity, arrangement, etc. of via hole conductors.
• the first wiring pattern P1 which is a pattern for electrical measurement, has the same wiring route pattern as the second wiring pattern P2, which is an actual product pattern, and can measure electrical characteristics more accurately than conventional wiring boards. can do.
• the method of measuring the electrical characteristics is not limited, and for example, the measurement may be performed using a de-embedding technique, since the electrical characteristics can be measured more accurately.
• the electrical characteristics of the first signal wiring 21 are measured to obtain a measured value M1.
• the electrical characteristics of the portion from the protruding portion 3a to the second electrode 32 are measured to obtain a measured value M2.
• the measured value M2 is subtracted from the measured value M1, thereby obtaining the electrical characteristic value between the first electrode 31 and the third electrode 33.
• the wiring board 10 of the present disclosure has a first wiring pattern P1 connecting the first electrode 31 and the third electrode 33, a fourth electrode 34 connected to the motherboard 20, and a fifth electrode 35 connected to the electronic component. It has the same wiring route pattern as the second wiring pattern P2 connecting the two.
• the mounting structure according to one embodiment includes the wiring board 10 according to the above-described embodiment and electronic components located in the mounting area of the wiring board 10.
• Examples of electronic components include semiconductor devices such as ASICs (Application Specific Integrated Circuits), semiconductor integrated circuit devices, and optoelectronic devices.
• the electronic component is connected to the fifth electrode 35 by solder 6. That is, as described above, the electronic component is not electrically connected to the first wiring pattern P1 but is electrically connected to the second wiring pattern P2.
• the mounting structure according to one embodiment electronic components are mounted on a wiring board 10 whose electrical characteristics have been accurately measured. Therefore, the mounting structure according to one embodiment has excellent electrical reliability and can reduce defects such as malfunction of electronic components.
• the wiring board according to the present disclosure has a laminated structure in which a plurality of insulating layers and a plurality of conductor layers are alternately laminated.
• the plurality of insulating layers include at least a first insulating layer located at the bottom layer, a second insulating layer located one layer above the first insulating layer, and a third insulating layer located at the top layer and having a mounting area.
• the plurality of conductor layers include first signal wiring.
• the first signal wiring includes a first electrode and a second electrode located on the lower surface of the first insulating layer, a protruding portion located on the lower surface of the first insulating layer so as to be in contact with the first electrode, and a first insulating layer.
• a linear conductor located between the layer and the second insulating layer, having a first end and a second end, a third electrode located on the upper surface of the third insulating layer, and penetrating the upper and lower surfaces of the first insulating layer.
• a first via hole conductor, a second via hole conductor, and a third via hole conductor are positioned so as to be.
• the first electrode and the third electrode are connected by a first wiring pattern including a first via hole conductor.
• the protruding portion and the first end of the linear conductor are connected by a second via hole conductor.
• the second end of the linear conductor and the second electrode are connected by a third via hole conductor.
• the conductor layer further includes a fourth electrode located on the lower surface of the first insulating layer and a fifth electrode located on the upper surface of the third insulating layer.
• the fourth electrode and the fifth electrode are connected by a second wiring pattern having the same wiring route pattern as the first wiring pattern.
• the first electrode is a pair electrode having two electrodes located adjacent to each other, and the protruding portion is in contact with each of the two electrodes. ing.
• the conductor layer includes a grounding conductor on the lower surface of the first insulating layer and between the first insulating layer and the second insulating layer. , further has.
• the grounding conductor is located on both sides of the linear conductor and surrounding the first electrode in plan view.
• the first distance which is the shortest distance between the first electrode and the grounding conductor, is shorter than the second distance, which is the shortest distance between the protrusion and the grounding conductor. .
• the first electrode is a pair electrode having two electrodes located adjacent to each other, and the protruding portion is in contact with each of the two electrodes.
• the first distance, which is the shortest distance between the first electrode and the grounding conductor is shorter than the third distance, which is the shortest distance between the protruding portions of the pair electrodes.
• a mounting structure includes the wiring board according to any one of (1) to (6) above, and an electronic component located in a mounting area of the wiring board.
• the electronic component is not electrically connected to the first wiring pattern but is electrically connected to the second wiring pattern.
• Insulating layer 11 Insulating layer for core 1a First insulating layer 1b Second insulating layer 1c Third insulating layer 2 Conductor layer 21 First signal wiring 22 Second signal wiring 23 Grounding conductor 31 First electrode 32 Second electrode 33 3 electrodes 34 4th electrodes 35 5th electrodes 3a protruding portion 3b linear conductor 3b1 first end 3b2 second end 41 first via hole conductor 42 second via hole conductor 43 third via hole conductor 5 solder resist 6 solder 10 wiring board 20 motherboard P1 First wiring pattern P2 Second wiring pattern

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• 2023
  • 2023-04-21 JP JP2024517278A patent/JPWO2023210526A1/ja active Pending
  • 2023-04-21 CN CN202380035062.3A patent/CN119096701A/zh not_active Withdrawn
  • 2023-04-21 WO PCT/JP2023/015908 patent/WO2023210526A1/ja not_active Ceased
  • 2023-04-21 US US18/859,809 patent/US20250267792A1/en active Pending
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