WO2023210170A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023210170A1
WO2023210170A1 PCT/JP2023/008664 JP2023008664W WO2023210170A1 WO 2023210170 A1 WO2023210170 A1 WO 2023210170A1 JP 2023008664 W JP2023008664 W JP 2023008664W WO 2023210170 A1 WO2023210170 A1 WO 2023210170A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring
semiconductor device
wire
joint
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/008664
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
遼一 加藤
裕一朗 日向
悠馬 村田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to DE112023000186.3T priority Critical patent/DE112023000186T5/de
Priority to CN202380013536.4A priority patent/CN117981063A/zh
Priority to JP2024517881A priority patent/JP7670236B2/ja
Publication of WO2023210170A1 publication Critical patent/WO2023210170A1/ja
Priority to US18/605,500 priority patent/US20240222311A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/076—Connecting or disconnecting of strap connectors
    • H10W72/07651—Connecting or disconnecting of strap connectors characterised by changes in properties of the strap connectors during connecting
    • H10W72/07653—Connecting or disconnecting of strap connectors characterised by changes in properties of the strap connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H10W72/651—Materials of strap connectors
    • H10W72/652—Materials of strap connectors comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H10W72/651—Materials of strap connectors
    • H10W72/655—Materials of strap connectors of outermost layers of multilayered strap connectors, e.g. material of a coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/871—Bond wires and strap connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H10W76/42—Fillings
    • H10W76/47—Solid or gel fillings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/761—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors
    • H10W90/764—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a semiconductor device.
  • the semiconductor device includes a power device.
  • a semiconductor device has, for example, a power conversion function.
  • the power device is, for example, a semiconductor chip including an IGBT (Insulated Gate Bipolar Transistor) and a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • the semiconductor device further includes a circuit board on which the semiconductor chip is arranged, and connection wiring (for example, a lead frame) that electrically connects the semiconductor chip and the circuit board, and is sealed with a sealing member.
  • the connection wiring connects the main electrode on the front surface of the semiconductor chip and the wiring board included in the circuit board (see, for example, Patent Documents 1 to 4).
  • the semiconductor device may further include a shunt resistor.
  • the shunt resistor may also be connected directly to the wiring board of the circuit board by means of connection wiring (see, for example, Patent Documents 5 and 6).
  • the semiconductor device may include a lead frame on which a semiconductor chip is placed (Patent Documents 7 to 9).
  • the semiconductor device may include a wire for source sensing. Such wires may be joined to connection wiring (for example, Patent Documents 3 and 4).
  • the sealing member of a semiconductor device has low adhesion depending on the parts to be sealed.
  • the sealing member has low adhesion to the solder that joins the connection wiring to the circuit board. If there is a portion of the sealing member with low adhesion, peeling occurs there, and the peeling extends from the peeling as a starting point. If there is a source sensing wire bonded to the connection wiring at the end of such peeling, there is a risk that the wire may be cut due to the peeling.
  • the present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor device in which the occurrence of wire breakage is suppressed.
  • a first conductive part and a second conductive part are provided with a gap between them, and a first joint part joined to a first front surface of the first conductive part; a connection wiring including a second joint part joined to a second front surface of the second conductive part, and a wiring part connecting the first joint part and the second joint part across the gap;
  • the wiring part includes a vertical part whose lower end part is connected to the first joint part and whose upper end part stands vertically upward with respect to the first joint part, and a vertical part from the upper end part of the vertical part.
  • a semiconductor device is provided, including a parallel portion parallel to the first conductive portion and the second conductive portion, and an inclined portion inclined from the parallel portion toward the second bonding portion.
  • the occurrence of wire breakage is suppressed, and a decrease in reliability is prevented.
  • FIG. 1 is a plan view of a semiconductor device according to an embodiment.
  • FIG. 3 is a plan view of a storage area of a case included in the semiconductor device of the embodiment.
  • FIG. 2 is a plan view of a semiconductor unit included in the semiconductor device of the embodiment.
  • FIG. 2 is a plan view of an insulated circuit board of a semiconductor unit included in a semiconductor device according to an embodiment.
  • 1 is a cross-sectional view of a semiconductor unit included in a semiconductor device according to an embodiment.
  • FIG. 3 is a cross-sectional view of a lead frame included in the semiconductor device of the embodiment.
  • FIG. 3 is a plan view of a lead frame included in the semiconductor device of the embodiment.
  • FIG. 2 is a cross-sectional view (before wire bonding) of a lead frame included in a semiconductor device of a reference example.
  • FIG. 2 is a cross-sectional view (after wire bonding) of a lead frame included in a semiconductor device of a reference example.
  • FIG. 3 is a cross-sectional view of a lead frame included in the semiconductor device of the embodiment (Modification 1).
  • FIG. 7 is a plan view of a lead frame included in the semiconductor device of the embodiment (modification 1).
  • FIG. 7 is a cross-sectional view of a lead frame included in the semiconductor device of the embodiment (Modification 2).
  • FIG. 7 is a plan view of a lead frame included in the semiconductor device of the embodiment (Modification 2).
  • front surface and “top surface” refer to the XY plane facing upward (+Z direction) in the semiconductor device 10 shown in the figure.
  • above refers to the upper side (+Z direction) in the semiconductor device 10 of FIG. 1.
  • back surface and “bottom surface” refer to the XY plane facing downward (-Z direction) in the semiconductor device 10 shown in the figure.
  • lower refers to the lower side (-Z direction) in the semiconductor device 10 of FIG. Similar directions are indicated in other drawings as necessary.
  • High refers to the upper (+Z side) position in the semiconductor device 10 shown in the figure.
  • “lower” refers to a lower position (-Z side) in the semiconductor device 10 shown in the figure.
  • Front surface “top surface,” “top,” “back surface,” “bottom surface,” “bottom,” and “side surface” are merely convenient expressions for specifying relative positional relationships; It is not intended to limit the technical ideas of For example, “above” and “below” do not necessarily mean a direction perpendicular to the ground. That is, the “up” and “down” directions are not limited to the direction of gravity.
  • the term “main component” refers to a case where it contains 80 vol% or more.
  • FIG. 1 is a plan view of a semiconductor device according to an embodiment
  • FIG. 2 is a plan view of a storage area of a case included in the semiconductor device according to an embodiment.
  • FIG. 2 is a plan view of the terminal stack 25b (first power terminal 22b, insulating sheet 23b, second power terminal 24b) of the semiconductor device 10.
  • the storage area 21e2 of the main body 21 is indicated by a broken line.
  • FIG. 2 only shows the storage area 21e2 and the terminal stacking part 25b, and the storage areas 21e1 and 21e3 and the terminal stacking parts 25a and 25c can also be shown in the same manner.
  • the semiconductor device 10 includes a semiconductor unit (not shown), a heat dissipation base plate (not shown) on which the semiconductor unit is disposed, and a case 20 that is disposed on the heat dissipation base plate and stores the semiconductor unit. .
  • the case 20 includes a main body 21, terminal laminated parts 25a to 25c, a U terminal 27a, a V terminal 27b, a W terminal 27c, and a control terminal (not shown here; see FIG. 3). There is.
  • the main body portion 21 has a substantially rectangular shape in plan view, and is surrounded on all sides by first to fourth side portions 21a to 21d in that order.
  • the first side 21a and the third side 21c correspond to the long sides
  • the second side 21b and the fourth side 21d correspond to the short sides.
  • the main body 21 shown in FIG. 1 has fastening holes in the corners formed by the first side 21a and the second side 21b and the corners formed by the third side 21c and the fourth side 21d.
  • the figure shows the case where a is formed.
  • the main body portion 21 includes storage areas 21e1 to 21e3 and control frame portions 26a to 26c.
  • the storage areas 21e1 to 21e3 are partitioned by control frame portions 26a and 26b.
  • the storage areas 21e1 to 21e3 are partitioned into control frame parts 26a and 26b in the middle part of the main body part 21 in plan view, and are arranged along the longitudinal direction (first and third side parts 21a and 21c) of the main body part 21, respectively. It is a space that has been created.
  • the fourth side portion 21d of the storage area 21e3 may include a control frame portion 26c.
  • Semiconductor units are stored in the storage areas 21e1 to 21e3, respectively.
  • the storage areas 21e1 to 21e3 may have a shape and size that can accommodate semiconductor units in plan view.
  • the shape may be, for example, rectangular.
  • the sealing member includes a thermosetting resin and a filler contained in the thermosetting resin.
  • the thermosetting resin is, for example, an epoxy resin, a phenol resin, or a maleimide resin.
  • the filler is silicon oxide, aluminum oxide, boron nitride or aluminum nitride.
  • the main body portion 21 includes terminal stacked portions 25a to 25c along the first side portion 21a. Further, the terminal stacked portions 25a to 25c are exposed from the first side portion 21a.
  • the main body portion 21 includes a U terminal 27a, a V terminal 27b, and a W terminal 27c along the third side portion 21c. Further, the U terminal 27a, the V terminal 27b, and the W terminal 27c are exposed from the front surface of the third side portion 21c.
  • the control terminals are provided in the control frame portions 26a to 26c, respectively.
  • the main body portion 21 and control frame portions 26a to 26c are molded using thermoplastic resin.
  • the thermoplastic resin is, for example, polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, or acrylonitrile butadiene styrene (ABS) resin.
  • the main body portion 21 is formed of such a material by insert molding and includes the terminal laminated portions 25a to 25c, the U terminal 27a, the V terminal 27b, and the W terminal 27c.
  • the control frame portions 26a to 26c are formed by insert molding and include control terminals.
  • the control frame parts 26a to 26c may be separately attached to the main body part 21.
  • the terminal stacking portions 25a to 25c are stacked with first power terminals 22a to 22c, insulating sheets 23a to 23c, and second power terminals 24a to 24c.
  • One end of the front surface of the first power terminals 22a to 22c is exposed in the terminal areas 21a1 to 21a3 of the first side part 21a of the main body part 21, respectively, along the longitudinal direction (first side part 21a). There is. Here, one end portion of the first power terminals 22a to 22c protrudes outward (in the ⁇ Y direction) from the first side portion 21a. The other end portions of the first power terminals 22a to 22c are electrically connected to a portion corresponding to an N terminal of a semiconductor chip included in the semiconductor unit inside the main body portion 21 (storage areas 21e1 to 21e3).
  • the first power terminals 22a to 22c have a flat plate shape.
  • the first power terminals 22a to 22c are made of metal with excellent conductivity. Such metals are, for example, copper, copper alloys, aluminum, aluminum alloys.
  • One end of the front surface of the second power terminals 24a to 24c protrudes outward (in the ⁇ Y direction) from the first side portion 21a.
  • the second power terminals 24a to 24c are each exposed on the first side 21a of the main body 21 along the longitudinal direction (first side 21a). At this time, one end portion of the second power terminals 24a to 24c is exposed.
  • the tips (terrace portions 28a, 28b, 28c) of the insulating sheets 23a to 23c are located between the tips of the first power terminals 22a to 22c and the tips of the second power terminals 24a to 24c in plan view. It is located in This maintains insulation between the first power terminals 22a to 22c and the second power terminals 24a to 24c.
  • the other end portions of the second power terminals 24a to 24c are electrically connected to locations corresponding to P terminals of semiconductor chips included in the semiconductor unit inside the main body portion 21 (storage areas 21e1 to 21e3).
  • the second power terminals 24a to 24c have a flat plate shape.
  • the second power terminals 24a to 24c are made of metal with excellent conductivity. Such metals are, for example, copper, copper alloys, aluminum, aluminum alloys.
  • the insulating sheets 23a to 23c are made of an insulating material having insulation properties.
  • an insulating material for example, an insulating paper made of a wholly aromatic polyamide polymer, or a sheet-like material made of a fluorine-based or polyimide-based resin material is applied.
  • control terminals included in the control frame parts 26a to 26c are included by insert molding along the control frame parts 26a to 26c.
  • the control terminals 26b1 to 26b4 included in the control frame portion 26b form a J-shape when viewed from the side (as viewed from the arrow in the Y direction).
  • One end portion of the control terminals 26b1 to 26b4 extends vertically upward (+Z direction) from the front surface of the control frame portion 26b.
  • the other end portions of the control terminals 26b1 to 26b4 are exposed on the storage area 21e2 side of the control frame portion 26b.
  • the control terminals 26b1 to 26b4 are each directly connected to the control electrodes of the semiconductor chips included in the semiconductor unit within the storage area 21e2 by wiring members.
  • the control terminals included in the control frame portions 26a and 26c are connected to the control electrodes of the semiconductor chips included in the semiconductor units within the storage areas 21e1 and 21e3, respectively, by wiring members.
  • the wiring members are, for example, wires 70a, 70b, 71a, 71b, 71c, 71d, 72a, and 72b.
  • the wiring member may be a lead frame.
  • the wiring member is made of a material with excellent conductivity. Such materials are metals (eg, aluminum, copper) or alloys containing at least one of these.
  • Such control terminals are also made of metal with excellent conductivity.
  • Such metals are, for example, copper, copper alloys, aluminum, aluminum alloys.
  • the other ends of the U terminal 27a, V terminal 27b, and W terminal 27c are electrically connected to the source electrode (or emitter electrode) of the semiconductor chip of each semiconductor unit in the storage areas 21e1 to 21e3.
  • FIG. 2 illustrates the case of the V terminal 27b.
  • the other ends of the U terminal 27a and the W terminal 27c are also provided in the same manner with respect to the storage areas 21e1 and 21e3.
  • One end portions of the U terminal 27a, the V terminal 27b, and the W terminal 27c are exposed at the third side portion 21c of the main body portion 21 along the longitudinal direction (third side portion 21c) of the main body portion 21, respectively.
  • the other end portions of the second power terminals 24a to 24c are electrically connected to locations corresponding to P terminals of semiconductor chips included in the semiconductor unit inside the main body portion 21 (storage areas 21e1 to 21e3).
  • the U terminal 27a, the V terminal 27b, and the W terminal 27c are made of metal with excellent conductivity. Such metals are, for example, copper, copper alloys, aluminum, aluminum alloys.
  • FIG. 3 is a plan view of a semiconductor unit included in the semiconductor device of the embodiment.
  • FIG. 4 is a plan view of an insulated circuit board of a semiconductor unit included in the semiconductor device of the embodiment.
  • FIG. 5 is a cross-sectional view of a semiconductor unit included in the semiconductor device of the embodiment. Note that FIG. 4 shows only the insulated circuit board shown in FIG. 3.
  • FIG. 5 is a sectional view taken along the dashed line YY in FIG.
  • the semiconductor unit 30 is placed on the heat dissipation base plate 45 via a bonding member (not shown). Note that the case 20 is placed on the heat dissipation base plate 45 via an adhesive. At this time, the semiconductor units 30 are stored in the storage areas 21e1 to 21e3 of the case 20, respectively.
  • Such a semiconductor unit 30 includes an insulated circuit board 40, semiconductor chips 50a to 50d, and lead frames 60a to 60d.
  • solder or a sintered material is used as the joining member for joining the heat dissipation base plate 45 and the semiconductor unit 30 (insulated circuit board 40).
  • solder lead-free solder or lead-containing solder is used.
  • Lead-free solder has, for example, an alloy containing at least two of tin, silver, copper, zinc, antimony, indium, and bismuth as a main component.
  • the solder may contain additives. Additives are, for example, nickel, germanium, cobalt or silicon. When solder contains additives, wettability, gloss, and bonding strength are improved, and reliability can be improved.
  • Lead-containing solder further contains lead.
  • the sintered material for example, a metal material containing at least one of copper, copper alloy, nickel, nickel alloy, silver, and silver alloy is used.
  • the insulated circuit board 40 has a rectangular shape in plan view.
  • the insulated circuit board 40 includes an insulating board 41, a metal plate 42 formed on the back surface of the insulating board 41, and a plurality of wiring boards 43a to 43g formed on the front surface of the insulating board 41. .
  • the outer shapes of the plurality of wiring boards 43a to 43g and the metal plate 42 are smaller than the outer shape of the insulating plate 41 in plan view, and are formed inside the insulating plate 41. Note that the shape, number, and size of the plurality of wiring boards 43a to 43g in this embodiment are merely examples. Further, the plurality of wiring boards 43a to 43g are a specific example of a conductive part.
  • the insulating plate 41 has a rectangular shape in plan view. Furthermore, the corners of the insulating plate 41 may be chamfered. For example, it may be C-chamfered or R-chamfered.
  • the insulating plate 41 is surrounded on all sides by the outer periphery of a long side 41a, a short side 41b, a long side 41c, and a short side 41d. Further, the insulating plate 41 includes corner portions 41e to 41h.
  • the corner portion 41e is composed of a long side 41a and a short side 41b.
  • the corner portion 41f is composed of a short side 41b and a long side 41c.
  • the corner portion 41g is composed of a long side 41c and a short side 41d.
  • the corner portion 41h is composed of a short side 41d and a long side 41a.
  • Such an insulating plate 41 is made of ceramic with good thermal conductivity. Ceramics are made of, for example, a material whose main component is aluminum oxide, aluminum nitride, or silicon nitride. Further, the thickness of the insulating plate 41 is, for example, 0.2 mm or more and 2.0 mm or less.
  • the metal plate 42 has a rectangular shape in plan view. Further, the corner portions may be chamfered with a C or a radius, for example.
  • the metal plate 42 is smaller in size than the insulating plate 41 and is formed on the entire back surface of the insulating plate 41 except for the edges.
  • the metal plate 42 is mainly composed of a metal having excellent thermal conductivity.
  • the metal is, for example, copper, aluminum, or an alloy containing at least one of these. Further, the thickness of the metal plate 42 is, for example, 0.1 mm or more and 2.0 mm or less.
  • plating treatment may be performed. At this time, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.
  • the wiring boards 43a to 43h are formed over the entire surface of the insulating board 41 except for the edges.
  • the ends of the wiring boards 43a to 43g facing the outer periphery of the insulating plate 41 overlap the ends of the metal plate 42 on the outer periphery side of the insulating plate 41. Therefore, the stress balance between the insulating circuit board 40 and the metal plate 42 on the back surface of the insulating plate 41 is maintained. Damage such as excessive warping and cracking of the insulating plate 41 is suppressed.
  • the regions indicated by two broken lines above the wiring boards 43a and 43b represent chip regions 50a1 and 50c1 of the two semiconductor chips 50a and 50c, respectively.
  • the regions indicated by broken lines below the wiring boards 43c and 43d represent chip regions 50b1 and 50d1 of the two semiconductor chips 50b and 50d, respectively.
  • the thickness of the wiring boards 43a to 43h is, for example, 0.1 mm or more and 2.0 mm or less.
  • Wiring boards 43a to 43h are made of metal with excellent conductivity. Such metals are, for example, copper, aluminum, or alloys containing at least one of these. Further, the surfaces of the wiring boards 43a to 43h may be plated to improve corrosion resistance. At this time, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.
  • the wiring board 43a is formed on the long side 41a side of the insulating plate 41, along the long side 41a, from the short side 41b to the short side 41d.
  • a depression is formed on the lower side (-Y direction) of the long side 41c of the wiring board 43a.
  • the wiring board 43b is substantially symmetrical with respect to the center line in the ⁇ Y direction with respect to the wiring board 43a.
  • the wiring board 43b is formed on the long side 41c side of the insulating board 41, along the long side 41c, from the short side 41b to the short side 41d.
  • a recess is formed on the lower side (-Y direction) of the long side 41a of the wiring board 43b.
  • the wiring board 43c is adjacent to the wiring board 43a, parallel to the long side 41a, and extends in the -Y direction from the short side 41b.
  • the end of the wiring board 43c in the -Y direction is spaced apart from the short side 41d.
  • the upper part (+Y direction) of the wiring board 43c on the long side 41c side is recessed in the middle.
  • the wiring board 43d is substantially symmetrical with respect to the center line in the ⁇ Y direction with respect to the wiring board 43c.
  • the wiring board 43d is adjacent to the upper part (+Y direction) of the wiring board 43b, is parallel to the long side 41c, and extends from the short side 41b in the ⁇ Y direction.
  • the end of the wiring board 43d in the -Y direction is spaced apart from the short side 41d.
  • the upper part (+Y direction) of the wiring board 43d on the long side 41a side is recessed in the middle.
  • the wiring board 43e is arranged in an area surrounded by the lower part of the wiring board 43a (-Y direction), the lower part of the wiring board 43c (-Y direction), the short side 41d, and the wiring board 43c. That is, the wiring board 43e has a substantially L-shape.
  • the wiring board 43f is substantially symmetrical with respect to the center line in the ⁇ Y direction with respect to the wiring board 43e.
  • the wiring board 43f is arranged in an area surrounded by the lower part (-Y direction) of the wiring board 43b, the wiring board 43d, the short side 41d, and the wiring board 43d. That is, the wiring board 43e has a substantially L-shape.
  • the wiring board 43g has an I-shape in plan view, and is arranged in a region surrounded by the recesses of the wiring boards 43c and 43d, on the wiring board 43c side and parallel to the long side 41a.
  • Wiring board 43h has an L-shape in plan view, and is disposed on the wiring board 43d side in a region surrounded by the recesses of wiring boards 43c and 43d, parallel to long side 41c.
  • the wiring board 43h is arranged so as to surround the long side 41c and the short side 41d of the wiring board 43g.
  • Wiring board 43i has an I-shape in plan view, and is arranged between wiring boards 43c and 43d, parallel to long sides 41a and 41c.
  • the bonding portions of the second power terminals 24a to 24c are bonded to the lower ends ( ⁇ Y direction) of the wiring boards 43a and 43b of the insulated circuit board 40, respectively.
  • FIG. 3 illustrates a case where internal joint portions 24b1 and 24b2 of the second power terminal 24b are joined to wiring boards 43a and 43b, respectively.
  • the bonding portions of the first power terminals 22a to 22c are bonded to the lower ends (-Y direction) of the wiring boards 43c and 43d of the insulated circuit board 40, respectively.
  • FIG. 3 illustrates a case where internal joint portions 22b1 and 22b2 of the first power terminal 22b are joined to wiring boards 43c and 43d, respectively.
  • FIG. 3 illustrates a case where internal connection portions 27b1 and 27b2 of V terminal 27b are joined to wiring boards 43c and 43d, respectively.
  • the insulated circuit board 40 having such a configuration, for example, a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazed) board may be used.
  • the insulated circuit board 40 radiates heat generated by semiconductor chips 50a to 50d, which will be described later, by conducting it to the back side of the insulated circuit board 40 via wiring boards 43a to 43d, an insulating plate 41, and a metal plate 42.
  • Semiconductor chips 50a to 50d are power devices made of silicon carbide.
  • An example of this power device is a power MOSFET.
  • Such semiconductor chips 50a to 50d have drain electrodes as input electrodes (main electrodes) on the back surface, gate electrodes as control electrodes 51a to 51d, and source electrodes as output electrodes 52a to 52d (main electrodes) on the front surface.
  • Each is equipped with Note that the output electrodes 52a to 52d are one specific example of a conductive part.
  • the semiconductor chips 50a to 50d may be power devices made of silicon.
  • the power device in this case is, for example, an RC (Reverse Conducting)-IGBT.
  • the RC-IGBT has an IGBT as a switching element and an FWD (Free Wheeling Diode) as a diode element in one chip.
  • Such semiconductor chips 50a to 50d each have, for example, a collector electrode as an input electrode (main electrode) on the back surface, a gate electrode as a control electrode, and an emitter electrode as an output electrode (main electrode) on the front surface. There is.
  • FIG. 3 shows a case where two of each are arranged.
  • each of the semiconductor chips 50a to 50d is arranged such that the control electrodes 51a to 51d face each other.
  • Lead frames 60a to 60d electrically connect output electrodes on the front surfaces of semiconductor chips 50a to 50d and wiring boards 43a to 43f.
  • Lead frame 60a electrically and mechanically connects semiconductor chip 50a and wiring board 43c.
  • Lead frame 60b electrically and mechanically connects semiconductor chip 50b and wiring board 43e.
  • Lead frame 60c electrically and mechanically connects semiconductor chip 50c and wiring board 43d.
  • the lead frame 60d electrically and mechanically connects the semiconductor chip 50d and the wiring board 43f.
  • the lead frames 60a to 60d are made of a material with excellent conductivity. Such a material may be made of, for example, copper, aluminum, or an alloy containing at least one of these materials. Further, the surfaces of the lead frames 60a to 60d may be plated to improve corrosion resistance. The plating material in this case is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy. Lead frames 60a to 60d will be described as lead frame 60 unless otherwise distinguished. Details of the lead frame 60 will be described later.
  • control electrodes 51a to 51d of the semiconductor chips 50a to 50d are electrically connected to control terminals included in the control frames 26a to 26c by wires.
  • the control electrode 51a of the semiconductor chip 50a is electrically connected to the control terminal 26b1 via a wire 70a relayed to the wiring board 43g.
  • Control electrodes 51b and 51d of semiconductor chips 50b and 50d are electrically connected to control terminal 26b3 via wire 70b.
  • the control electrode 51c of the semiconductor chip 50c is electrically connected to the control terminal 26b1 via the wire 70a.
  • the lead frames 60a and 60c are electrically and mechanically connected to the wiring board 43h via wires 71a and 71b. Furthermore, wiring board 43h is electrically and mechanically connected to control terminal 26b2 via wire 72a. That is, the lead frames 60a and 60c are electrically connected to the control terminal 26b2. Lead frames 60b and 60d are electrically and mechanically connected to wiring board 43g via wires 71c and 71d. Further, the wiring board 43g is electrically and mechanically connected to the control terminal 26b4 via the wire 72b. That is, lead frames 60b and 60d are electrically connected to control terminal 26b4. Control terminals 26b2 and 26b4 are used for source sensing.
  • the wires 70a, 70b, 71a, 71b, 71c, 71d, 72a, and 72b described above are mainly composed of a material with excellent conductivity. Such a material is made of, for example, gold, copper, aluminum, or an alloy containing at least one of these.
  • the wires 70a, 70b, 71a, 71b, 71c, 71d, 72a, 72b may be an aluminum alloy containing a trace amount of silicon.
  • the diameter of the wires 70a, 70b, 71a, 71b, 71c, 71d, 72a, and 72b is, for example, 100 ⁇ m or more and 400 ⁇ m or less.
  • FIG. 6 is a cross-sectional view of a lead frame included in the semiconductor device of the embodiment
  • FIG. 7 is a plan view of the lead frame included in the semiconductor device of the embodiment. Note that FIGS. 6 and 7 correspond to the lead frame 60c in FIG. 3. However, since the other lead frames have similar configurations, the lead frame 60 is used here.
  • the lead frame 60 is a specific example of connection wiring.
  • the lead frame 60 includes a chip bonding portion 61, a wiring bonding portion 62, and a wiring portion 63.
  • the chip bonding portion 61 is bonded to the output electrode 52c on the front surface of the semiconductor chip 50c via the bonding member 46.
  • This joining member 46 may be solder in this case as described above.
  • the wiring joint portion 62 is joined to the front surface of the wiring board 43d.
  • the wiring joint portion 62 is joined to the wiring board 43d by the previously described joining member 46. Alternatively, they are bonded by ultrasonic bonding.
  • the wiring section 63 bridges the gap G between the wiring boards 43d and 43b and connects the chip joint section 61 and the wiring joint section 62.
  • Such a lead frame 60 has a flat plate shape as a whole, and is integrally connected to a chip bonding portion 61, a wiring bonding portion 62, and a wiring portion 63. Further, the thickness of the lead frame 60 is generally uniform throughout, and may be, for example, 0.2 mm or more and 0.6 mm or less, and more preferably 0.3 mm or more and 0.5 mm or less. preferable.
  • the chip joint portion 61 has a rectangular shape in plan view, similar to the plan view shape of the output electrode 52c of the semiconductor chip 50c. Further, the area of the chip bonding portion 61 in a plan view may be 60% or more and 95% or less of the area of the output electrode 52c of the semiconductor chip 50c in a plan view.
  • the wiring section 63 further includes a vertical section 64, a parallel section 65, and an inclined section 66.
  • a lower end portion of the vertical portion 64 is connected to the chip joint portion 61, and an upper end portion of the vertical portion 64 rises vertically above the chip joint portion 61. Therefore, the angle R formed by the vertical portion 64 and the chip joint portion 61 is approximately 90 degrees.
  • the angle R may be substantially 90 degrees.
  • the angle R is preferably 90 degrees, but may be greater than or equal to 80 degrees and less than 90 degrees. In this embodiment, unless otherwise specified, the explanation will be made assuming that the angle R is 90 degrees.
  • connection point (heel portion 61b) between the lower end of the vertical portion 64 and the chip joint portion 61 may form an R surface. Alternatively, it may be chamfered. Therefore, the joining member 46 that joins the chip joining part 61 and the semiconductor chip 50c has a fillet shape at the toe part 61a (+X direction) of the chip joining part 61. Further, the joining member 46 also forms a fillet shape, covering the outside of the connection point with the vertical portion 64 in the heel portion 61b ( ⁇ X direction) of the chip joining portion 61. Note that the side portions of the tip joint portion 61 that are perpendicular to the toe portion 61a and the heel portion 61b also have a fillet shape.
  • the parallel portion 65 is connected to the upper end of the vertical portion 64, and is parallel to the wiring boards 43b, 43d and the semiconductor chip 50c from the upper end. Since the wiring portion 63 straddles the gap G, the parallel portion 65 extends from the upper end of the vertical portion 64 toward the wiring joint portion 62 side. In this case as well, the outside of the connection point P2 between the parallel portion 65 and the vertical portion 64 may form an R surface. Alternatively, it may be chamfered.
  • the angle formed by the parallel portion 65 and the vertical portion 64 is approximately 90 degrees. This angle may also be substantially 90 degrees.
  • one end portion of the wire 71b (wire joint portion 71b1) is joined to the front surface of the parallel portion 65.
  • the other end of the wire 71b is joined to a wiring board 43h (adjacent to the wiring board 43d in the ⁇ X direction).
  • the wire 71b is bonded to the parallel portion 65 by a bonding device, as described above. In the bonding device, ultrasonic waves are applied while pressing one end of the wire 71b against the parallel portion 65. At this time, the wire joint portion 71b1, in which one end portion of the wire 71b is plastically deformed, is joined to the parallel portion 65.
  • the wire joint portion 71b1 extends in any direction depending on the vibration direction of the ultrasonic wave.
  • the wire joint portion 71b1 extends in the wiring direction ( ⁇ X direction) of the wiring portion 63, and has an elliptical shape in plan view. Further, in this embodiment, the wire 71b is wired in a straight line with respect to the long axis of the wire joint portion 71b1.
  • the inclined portion 66 is inclined from the parallel portion 65 toward the wiring joint portion 62.
  • the angle of inclination of the inclined portion 66 with respect to the wiring joint portion 62 is assumed to be an angle ⁇ .
  • the outer side (upper side) of the connection point P3 between the inclined portion 66 and the parallel portion 65 may form an R surface. Alternatively, it may be chamfered.
  • the outer side (wiring board 43d side) of the connection point P1 (heel portion 62b) between the inclined portion 66 and the wiring joint portion 62 may form an R surface. Alternatively, it may be chamfered.
  • the joining member 46 that joins the wiring joining part 62 and the wiring board 43d has a fillet shape at the toe part 62a (-X direction) of the wiring joining part 62. Further, the joining member 46 has a fillet shape so as to cover the outside (on the wiring board 43d side) of the connection point P1 with the inclined portion 66 even in the heel portion 62b (+X direction) of the wiring joining portion 62.
  • the length between the connection points P1 and P2 in the wiring portion 63 of the lead frame 60 is defined as a length L. That is, the length L is the distance between the heel portion 61b of the chip joint portion 61 and the heel portion 62b of the wiring joint portion 62 in the ⁇ X direction.
  • the length between the connection points P2 and P3 is defined as length L1. That is, the length L1 is the length of the parallel portion 65 in the ⁇ X direction along the wiring direction of the lead frame 60.
  • the length between the connection points P3 and P1 in plan view is defined as length L2. That is, the length L2 is the length of the inclined portion 66 in the ⁇ X direction in a plan view along the wiring direction of the lead frame 60.
  • the actual length of the inclined portion 66 along the wiring direction of the lead frame 60 is expressed as length L2/COS ⁇ .
  • the width of the wiring portion 63 in plan view may be substantially uniform throughout.
  • the width of the wiring portion 63 may be smaller than the widths of the chip bonding portion 61 and the wiring bonding portion 62. Further, part of the width of the wiring portion 63 may be narrow. In order to stabilize the wiring portion 63, it is preferable that the width of the wiring portion 63 is substantially uniform throughout. For further stability, it is more preferable that the width of the lead frame 60 is substantially uniform throughout.
  • the wiring portions 63 may have different angles ⁇ .
  • the angle ⁇ is increased, the length L2 becomes shorter and the length L1 becomes longer.
  • the angle ⁇ is decreased, the length L2 becomes longer and the length L1 becomes shorter.
  • the wire 71b is joined to the front surface of the parallel portion 65.
  • the angle ⁇ of the parallel portion 65 is such that a bondable area (length L1) is ensured.
  • FIG. 8 is a cross-sectional view (before wire bonding) of a lead frame included in the semiconductor device of the reference example
  • FIG. 9 is a cross-sectional view (after wire bonding) of the lead frame included in the semiconductor device of the reference example.
  • a lead frame 160 is provided in place of the lead frame 60 in FIGS. 6 and 7.
  • the other configurations are the same as those in FIGS. 6 and 7.
  • the lead frame 160 also includes a chip bonding portion 61, a wiring bonding portion 62, and a wiring portion 63.
  • the wiring section 63 of the reference example further includes a vertical section 64a, a parallel section 65, and a vertical section 64b.
  • the lower end portion of the vertical portion 64a is connected to the chip joint portion 61 similarly to the vertical portion 64, and the upper end portion of the vertical portion 64a rises vertically above the chip joint portion 61.
  • An angle R1 formed by the vertical portion 64a and the chip joint portion 61 is approximately 90 degrees.
  • the angle R1 may be substantially 90 degrees.
  • the parallel part 65 is connected to the upper end of the vertical part 64a, and is parallel to the wiring boards 43b, 43d and the semiconductor chip 50c from the upper end.
  • the vertical portion 64b extends vertically from the parallel portion 65 toward the wiring joint portion 62.
  • the vertical portion 64b is at an angle R2 with respect to the wiring joint portion 62.
  • the angle R2 formed by the vertical portion 64b and the wiring joint portion 62 is approximately 90 degrees.
  • the angle R2 may be substantially 90 degrees.
  • the semiconductor unit 30 is sealed with a sealing member 29.
  • the components included in the semiconductor unit 30 include those that have low adhesion to the sealing member 29.
  • the sealing member 29 has low adhesion to, for example, the solder that is the joining member 46. For this reason, there is a possibility that the sealing member 29 that seals the semiconductor unit 30 may peel off at a portion where it is in close contact with the bonding member 46 . The peeling that occurs in the sealing member 29 extends. If the wire joint portion 71b1 of the wire 71b is present at the extension destination of the peeling, the wire 71b may be cut due to the peeling.
  • the lead frame 160 has a rectangular shape when viewed from the side. For this reason, for example, even if the sealing member 29 peels off along the broken line arrows A1 and A2 in FIG. 8, one end of the wire 71b is away from the peeling location, so it will not be affected by the peeling. The possibility increases. Further, peeling of the sealing member 29 extending along the broken line arrows A1 and A2 is suppressed at the connection points between the parallel portion 65 and the vertical portions 64a and 64b. Therefore, the peeling of the sealing member 29 does not extend to the wire 71b. It is expected that cutting of the wire 71b will be prevented in this way.
  • both angles R1 and R2 may be similarly inclined at acute angles to make the lead frame 160 trapezoidal in side view. Conceivable. In this case, although the occurrence of distortion in the parallel portion 65 is prevented more than when the angles R1 and R2 are 90 degrees, the occurrence of distortion cannot be reliably suppressed.
  • the lead frame 60 of this embodiment includes a chip bonding portion 61, a wiring bonding portion 62, and a wiring portion 63.
  • the chip bonding portion 61 is bonded to the output electrode 52c on the front surface of the semiconductor chip 50c via a bonding member.
  • the wiring joint portion 62 is joined to the front surface of the wiring board 43d.
  • the wiring part 63 connects the chip joint part 61 and the wiring joint part 62 across the gap G between the wiring boards 43d and 43b.
  • the wiring section 63 further includes a vertical section 64, a parallel section 65, and an inclined section 66. A lower end portion of the vertical portion 64 is connected to the chip joint portion 61, and an upper end portion of the vertical portion 64 rises vertically above the chip joint portion 61.
  • the angle R of the vertical portion 64 with respect to the chip joint portion 61 is a right angle (90 degrees).
  • the parallel portion 65 is connected to the upper end of the vertical portion 64 and extends from the upper end in parallel to the wiring boards 43b, 43d and the semiconductor chip 50c.
  • the inclined portion 66 is inclined from the parallel portion 65 toward the wiring joint portion 62 . Even if the wire 71b is bonded to the front surface of the parallel portion 65 of the wiring portion 63 included in the lead frame 60, the occurrence of distortion of the parallel portion 65 toward the insulated circuit board 40 side is suppressed. In particular, when the angle ⁇ is between 30 degrees and 60 degrees, the distortion of the parallel portion 65 toward the insulated circuit board 40 occurs as shown in FIG.
  • the angle R of the vertical portion 64 is not limited to 90 degrees, but as described above, even when it is 80 degrees or more and less than 90 degrees, the insulation circuit of the parallel portion 65 is It has been confirmed that the occurrence of strain on the substrate 40 side is suppressed.
  • the angle ⁇ is preferably 30 degrees or more and 60 degrees, and more preferably 30 degrees or more and 45 degrees or less.
  • the wire 71b be joined to the vertical portion 64 side with respect to the parallel portion 65.
  • the pressure applied during bonding is supported by the vertical portion 64, thereby further preventing distortion of the parallel portion 65. Therefore, the wire 71b can be reliably joined to the parallel portion 65 of the lead frame 60.
  • the sealing member 29 peels off near the wiring joint portion 62, and the wiring joint portion 62 Even if the peeling extends from the tip to the inclined portion 66, the wire 71b is far away from the location where the peeling occurs, so the peeling does not extend. Therefore, cutting due to peeling of the wire 71b is also prevented. As a result, deterioration in reliability of the semiconductor device 10 including the lead frame 60 is also suppressed.
  • the vertical portion 64 extends vertically upward from the chip joint portion 61, the height H from the front surface of the semiconductor chip 50c to the parallel portion 65 can be ensured.
  • the height H By increasing the height H, the influence of local heat generation by the semiconductor chip 50c on the parallel portion 65 connected to the vertical portion 64 can be reduced. Therefore, even if peeling occurs in the sealing member 29 near the chip joint portion 61 of the lead frame 60, the peeling does not easily extend from the chip joint portion 61 to the vertical portion 64.
  • the height H from the front surface of the semiconductor chip 50c to the parallel portion 65 can be ensured.
  • a coating material mainly composed of a thermoplastic resin is sprayed into the storage areas 21e1 to 21e3 of the case 20. That is, the surface of the semiconductor unit 30 is covered with a film. Such a film can protect the semiconductor unit 30. In particular, the adhesion of the semiconductor unit 30 to the sealing member 29 is improved through this film.
  • Such a coating material is sprayed onto the object by air spray from a nozzle of a coating device.
  • the application by the nozzle spreads to a diameter of about 8 mm with respect to the object.
  • the film needs to be applied to the entire surface of the semiconductor unit 30.
  • the sealing member 29 has poor adhesion to the solder that is the joining member 46.
  • the nozzle can also reliably apply the film around the heel portion 61b (in the ⁇ X direction) of the chip joint portion 61 of the lead frame 60. Therefore, in the semiconductor unit 30, a film is applied to the front surface of the insulated circuit board 40, the semiconductor chips 50a to 50d, the wires 70a, 70b, 71a, 71b, 71c, 71d, 72a, 72b, and the surface of the lead frame 60. Ru.
  • the lead frame 60 connects the wiring board 43d and the output electrode 52c of the semiconductor chip 50c. Therefore, in the lead frame 60, the chip joint portion 61 is located higher than the wiring joint portion 62.
  • the lead frame 60 may connect wiring boards in some cases. Further, instead of the semiconductor chip 50c, it may be connected to another element. That is, the lead frame 60 may connect different conductive parts across a gap.
  • FIG. 10 is a cross-sectional view of a lead frame included in the semiconductor device of the embodiment (Modification 1)
  • FIG. 11 is a plan view of the lead frame included in the semiconductor device of the embodiment (Modification 1). be. Note that FIGS. 10 and 11 correspond to FIGS. 6 and 7.
  • FIG. 10 is a sectional view taken along the dashed line YY in FIG.
  • one or more groove portions 66a are formed on the front surface (the surface facing the +X direction) of the vertical portion 64.
  • the groove portion 66a is formed to be perpendicular to the long axis of the wire joint portion 71b1 of the wire 71b.
  • the groove portion 66a is continuously formed in a straight line so as to cross the width ( ⁇ Y direction) of the vertical portion 64.
  • the depth and width (the length in the wiring direction of the lead frame 60) of the groove portion 66a are set within a range that does not affect the conduction of electricity in the vertical portion 64.
  • Such depth may be, for example, 20% or more and 45% or less of the thickness of the vertical portion 64.
  • the groove portion 66a does not need to be continuous. That is, the groove portion 66a may be formed in a straight broken line shape (discontinuous). Further, the groove portion 66a does not have to be linear, and may be, for example, V-shaped, wavy, or jagged.
  • the semiconductor unit 30 including such a lead frame 60 is sealed by the sealing member 29.
  • the sealing member 29 may peel off in the range where it comes into contact with the solder of the joining member 46 that joins the chip joining portion 61 and the output electrode 50c of the semiconductor chip 50c.
  • the groove portion 66a formed in the vertical portion 64 suppresses the extension of the peeling. Therefore, the peeling is suppressed from reaching the wire 71b, and cutting due to the peeling of the wire 71b is also prevented. As a result, deterioration in reliability of the semiconductor device 10 including the lead frame 60 is also suppressed.
  • one or more such groove portions 66a may be further formed on the front surface (the surface facing the ⁇ X direction) of the inclined portion 66.
  • the groove portion 66a formed in the inclined portion 66 is also similar to the groove portion 66a formed in the vertical portion 64. That is, the groove 66a is formed to be perpendicular to the long axis of the wire joint portion 71b1 of the wire 71b.
  • the groove portion 66a may be continuously formed in a straight line so as to cross the width ( ⁇ Y direction) of the inclined portion 66.
  • the depth and width (the length of the lead frame 60 in the wiring direction) of the groove portion 66a may also be the same as above, and the groove portion 66a may not be continuous.
  • the sealing member 29 may peel off in the range where it comes into contact with the solder of the joining member 46 that joins the wiring joining portion 62 and the wiring board 43d.
  • peeling extends from the wiring bonding portion 62 along the inclined portion 66, the groove portion 66a formed in the inclined portion 66 suppresses the extension of the peeling.
  • FIG. 12 is a cross-sectional view of a lead frame included in the semiconductor device of the embodiment (Modification 2)
  • FIG. 13 is a plan view of the lead frame included in the semiconductor device of the embodiment (Modification 2). be.
  • FIGS. 12 and 13 correspond to FIGS. 6 and 7.
  • FIG. 12 is a sectional view taken along the dashed line YY in FIG. 13.
  • FIG. 3 can also be referred to.
  • a plurality of protrusions 66b are formed on the front surface (the surface facing the +X direction) of the vertical section 64 of the wiring section 63.
  • the protrusion 66b is semicircular and two rows of four protrusions 66b are formed.
  • the protrusion 66b is formed to be perpendicular to the wire joint portion 71b1 of the wire 71b.
  • the four protrusions 66b are just an example, and if the width ( ⁇ Y direction) of the vertical portion 64 can be roughly covered, one, two, three, five or more may be used depending on the area of the protrusions 66b. There may be.
  • the protrusion 66b is not limited to a semispherical shape, but may be a convex shape, for example, a triangular pyramid shape, a quadrangular pyramid shape, or a cubic shape. Further, the protruding portion 66b may be continuously linear so as to cross the width ( ⁇ Y direction) of the inclined portion 66, and may be formed to have a convex cross section. In this case, the protrusion 66b extends in a direction perpendicular to the long axis of the wire joint 71b1. Further, the height and width (the length of the lead frame 60 in the wiring direction) of the protrusion 66b in this case may be within a range that does not interfere with the wire 71b.
  • the semiconductor unit 30 including the lead frame 60 is sealed with the sealing member 29.
  • the sealing member 29 will peel off in the range where it comes into contact with the solder of the joining member 46 that joins the chip joining portion 61 and the output electrode 52c of the semiconductor chip 50c.
  • this peeling extends from the chip joint portion 61 along the vertical portion 64, the extension of the peeling is suppressed by the protrusion 66b formed on the vertical portion 64 of the lead frame 60. Therefore, cutting due to peeling of the wire 71b is also prevented. As a result, deterioration in reliability of the semiconductor device 10 including the lead frame 60 is also suppressed.
  • Such a plurality of protrusions 66b may be further formed on the front surface (the surface facing the ⁇ X direction) of the inclined portion 66.
  • the plurality of protrusions 66b formed on the inclined portion 66 are also similar to those formed on the vertical portion 64. That is, the plurality of protrusions 66b are formed to be perpendicular to the long axis of the wire joint portion 71b1 of the wire 71b.
  • the plurality of projections 66b formed on the slope 66 may also be one or more, depending on the area of the projection 66b, as long as the width ( ⁇ Y direction) of the slope 66 can be approximately covered. Moreover, one or more rows may be sufficient.
  • the sealing member 29 may peel off in the range where it comes into contact with the solder of the joining member 46 that joins the wiring joining portion 62 and the wiring board 43d.
  • peeling extends from the wiring joint portion 62 along the inclined portion 66, the plurality of protrusions 66b formed on the inclined portion 66 suppresses the extension of the peeling.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
PCT/JP2023/008664 2022-04-25 2023-03-07 半導体装置 Ceased WO2023210170A1 (ja)

Priority Applications (4)

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DE112023000186.3T DE112023000186T5 (de) 2022-04-25 2023-03-07 Halbleitervorrichtung
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007288075A (ja) * 2006-04-19 2007-11-01 Nippon Inter Electronics Corp 半導体装置
JP2019075524A (ja) * 2017-10-19 2019-05-16 株式会社デンソー リードフレーム
JP7028391B1 (ja) * 2020-06-30 2022-03-02 富士電機株式会社 半導体モジュールおよび半導体モジュールの製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61137352A (ja) 1984-12-10 1986-06-25 Hitachi Ltd 半導体装置
JP5757979B2 (ja) 2013-07-25 2015-08-05 セイコーインスツル株式会社 半導体装置パッケージ
US9633967B2 (en) 2013-10-21 2017-04-25 Nsk Ltd. Semiconductor module
CN106471617B (zh) 2014-04-04 2019-05-10 三菱电机株式会社 半导体装置
JP6338937B2 (ja) 2014-06-13 2018-06-06 ローム株式会社 パワーモジュールおよびその製造方法
JP7025181B2 (ja) 2016-11-21 2022-02-24 ローム株式会社 パワーモジュールおよびその製造方法、グラファイトプレート、および電源装置
JP2019075521A (ja) 2017-10-19 2019-05-16 株式会社デンソー シャント抵抗器及びその製造方法
JP2019075959A (ja) 2017-10-19 2019-05-16 株式会社デンソー 制御装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007288075A (ja) * 2006-04-19 2007-11-01 Nippon Inter Electronics Corp 半導体装置
JP2019075524A (ja) * 2017-10-19 2019-05-16 株式会社デンソー リードフレーム
JP7028391B1 (ja) * 2020-06-30 2022-03-02 富士電機株式会社 半導体モジュールおよび半導体モジュールの製造方法

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