WO2023197344A1 - 版图及布线方法、比较方法、制备方法、设备和存储介质 - Google Patents

版图及布线方法、比较方法、制备方法、设备和存储介质 Download PDF

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Publication number
WO2023197344A1
WO2023197344A1 PCT/CN2022/087763 CN2022087763W WO2023197344A1 WO 2023197344 A1 WO2023197344 A1 WO 2023197344A1 CN 2022087763 W CN2022087763 W CN 2022087763W WO 2023197344 A1 WO2023197344 A1 WO 2023197344A1
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WIPO (PCT)
Prior art keywords
layout
ports
connection layer
virtual connection
node
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PCT/CN2022/087763
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English (en)
French (fr)
Inventor
李忠华
宋志浩
Original Assignee
长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP22783272.2A priority Critical patent/EP4287062A4/en
Priority to US17/945,233 priority patent/US20230015810A1/en
Publication of WO2023197344A1 publication Critical patent/WO2023197344A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/303—Contactless testing of integrated circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/305—Contactless testing using electron beams
    • G01R31/307—Contactless testing using electron beams of integrated circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
    • G01R31/311—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation of integrated circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a layout and wiring method, a comparison method, a preparation method, a device and a storage medium.
  • Embodiments of the present disclosure provide a layout and wiring method, a comparison method, a preparation method, a device and a storage medium.
  • the layout wiring method is at least conducive to improving the accuracy of layout wiring and the efficiency of layout wiring.
  • the embodiments of the present disclosure provide a layout wiring method, including: obtaining the names of all ports in the layout, and the ports have first nodes and second nodes; detecting the Whether the first node and the second node are both connected to other ports through the actual connection layer; if not, the first node and/or the second node that are not connected to the actual connection layer are The port is used as a port to be connected; a virtual connection layer is used to connect at least two ports to be connected with the same name.
  • the layout wiring method before using the virtual connection layer to connect at least two ports to be connected with the same name, the layout wiring method further includes: obtaining the number of the ports to be connected, if the ports to be connected The number is at least three, and using a virtual connection layer to connect at least two ports to be connected with the same name includes: detecting the connection relationship between all the ports with the same name, and making any of the ports The other two ports with the same name are connected through the virtual connection layer and/or the actual connection layer, and all the ports with the same name form a connection loop through the virtual connection layer and the actual connection layer. .
  • the layout wiring method before using a virtual connection layer to connect at least two ports to be connected with the same name, the layout wiring method further includes: passing neither the first node nor the second node through The port to be connected that the actual connection layer is connected to other ports is used as a target port; the use of a virtual connection layer to connect at least two ports to be connected with the same name includes: obtaining the target port distance information between the first node and the second node and other ports to be connected with the same name; based on the distance information, use the virtual connection layer to connect the first node of the target port and the distance The port to be connected that is closest to the first node of the target port uses the virtual connection layer to connect the second node of the target port with all the closest nodes to the second node of the target port. Describe the port to be connected.
  • the embodiments of the present disclosure also provide a method for comparing the consistency between a layout and a schematic diagram, which includes: providing a layout and a schematic diagram corresponding to the layout, and the layout includes: at least two names The same port, and at least one virtual connection layer connecting the two ports; any one of the virtual connection layers is selected as the target virtual connection layer, and the layout and layout are performed without identifying the target virtual connection layer.
  • the layout and schematic consistency comparison method further includes: if the first result is a virtual connection error and the second result is an abnormality, detecting all connections connected to the target virtual connection layer. Check whether the port is correct; use the target virtual connection layer to connect the other two ports that need to be tested to re-obtain the first result and the second result until the layout meets the requirements.
  • the layout and schematic consistency comparison method further includes: traversing all the virtual connection layers, so that each virtual connection layer serves as the target virtual connection layer once.
  • another aspect of the embodiments of the present disclosure also provides a method for comparing the consistency of a layout and a schematic diagram, including: providing a layout and a schematic diagram corresponding to the layout, and the layout includes at least two identically named port, and the layout does not include a virtual connection layer; without identifying the virtual connection layer, compare the consistency of the layout and the schematic diagram to obtain the first result; if the first result is None Abnormal, it means that the layout meets the requirements.
  • the layout and schematic consistency comparison method further includes: using a virtual connection layer to connect at least two of the ports that need to be tested; after identifying the Under the premise of the virtual connection layer, the consistency comparison between the layout and the schematic diagram is performed, and the second result is obtained; if the second result is no abnormality, it means that the layout meets the requirements.
  • the layout and schematic consistency comparison method further includes: using the virtual connection layer to connect at least two other ports that need to be tested to re- The first result and/or the second result are obtained until the layout meets the requirements.
  • the embodiments of the present disclosure also provide a layout, including: at least two ports with the same name, and the ports have a first node and a second node; an actual connection layer, the connection part is named The same port, and the first node and/or the second node of the partially named port are not connected to the actual connection layer, the first node and/or the second node
  • the port of a node that is not connected to the actual connection layer is used as the port to be connected; the virtual connection layer connects at least two ports to be connected with the same name.
  • the number of the ports to be connected is at least three, and any of the ports is connected to the other two ports through the virtual connection layer and/or the actual connection layer, and all The ports with the same name form a connection loop through the virtual connection layer and the actual connection layer.
  • neither the first node nor the second node of some of the ports to be connected is connected to the actual connection layer, and neither the first node nor the second node is connected to the actual connection layer.
  • the port to be connected connected by the actual connection layer serves as a target port, wherein the virtual connection layer connects the first node of the target port and the to-be-connected port closest to the first node of the target port.
  • a connection port is connected, and the virtual connection layer connects the second node of the target port and the port to be connected that is closest to the second node of the target port.
  • another aspect of the embodiments of the present disclosure further provides a circuit preparation method, including: a layout preparation circuit formed according to any of the above layout wiring methods, or, according to any of the above The layout of the circuit is prepared, wherein in the process of preparing the circuit, the virtual connection layer does not participate in the production of the prepared circuit, and the virtual electrical connection layer will not be reflected in the circuit.
  • another aspect of the embodiments of the present disclosure further provides an electronic device, including: at least one processor; a memory communicatively connected to the at least one processor; wherein the memory stores information that can be used by all
  • the instructions executed by the at least one processor are executed by the at least one processor so that the at least one processor can execute the layout wiring method as described in any one of the above, or the instructions are executed by the at least one processor.
  • the at least one processor executes, so that the at least one processor can execute the layout and schematic diagram consistency comparison method as described in any one of the above.
  • another aspect of the embodiments of the disclosure further provides a computer-readable storage medium storing a computer program.
  • the layout wiring as described in any one of the above is implemented.
  • Method, or when the computer program is executed by the processor, the method for comparing the consistency of the layout and the schematic diagram as described in any one of the above claims is implemented.
  • a virtual connection layer to connect at least two ports with the same name to be connected together, so that the ports with the same name in the layout are connected through the actual connection layer and/or the virtual connection layer.
  • the layout and schematic diagram are consistent.
  • it is helpful to avoid virtual connection errors in the layout that is, to prevent some ports with the same names in the layout from being disconnected from each other, thereby improving the accuracy of the consistency comparison between the layout and the schematic diagram.
  • a virtual connection layer is added to the layout.
  • the virtual connection layer always exists in the layout. There is no need to remove the virtual connection layer in the layout later, which is conducive to reducing the number of modifications of layout wiring, thereby helping to improve the accuracy of layout wiring. performance and layout efficiency.
  • Figure 1 is a flow chart of a layout wiring method provided by an embodiment of the present disclosure
  • Figure 2 is a partial structural schematic diagram of a layout provided by an embodiment of the present disclosure
  • Figure 3 is another flow chart of a layout wiring method provided by an embodiment of the present disclosure.
  • Figure 4 is another flow chart of a layout wiring method provided by an embodiment of the present disclosure.
  • Figure 5 is a partial structural schematic diagram of a layout provided by an embodiment of the present disclosure.
  • Figure 6 is a flow chart of a method for comparing the consistency of a layout and a schematic diagram provided by another embodiment of the present disclosure
  • Figure 7 is a flow chart of a method for comparing the consistency of layout and schematic diagram provided by yet another embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram of an electronic device according to yet another embodiment of the present disclosure.
  • multi-voltage design is generally adopted, that is, multi-power domain design is adopted. Therefore, there are multiple ports with different names. Differently named ports are powered by different power domains, and the named The same multiple ports may be connected through internal circuits in the schematic diagram, that is, there is no direct connection relationship between at least two ports with the same name connected through internal circuits. However, since there is no internal circuit in the layout, the connection relationship between at least two ports with the same name connected through the internal circuit cannot be reflected in the layout, which will cause inconsistencies between the layout and the schematic diagram, further affecting the layout wiring. accuracy and efficiency.
  • connection between multiple ports with the same name through the internal circuit in the schematic diagram can be understood as: some of the ports with the same name are all electrically connected to the same substrate, that is, all the ports are Power can be supplied to the substrate.
  • the internal circuit is the substrate, and this part of the port is connected through the substrate. That is, there is no direct connection relationship between at least two ports with the same name connected through the internal circuit.
  • the distance between the local substrates that the ports are connected to is relatively large, so that the resistance between the ports is relatively large.
  • the high resistance makes the ports basically disconnected from each other, so the layout The connection relationship between at least two ports with the same name that are connected through internal circuits cannot be reflected.
  • the disclosed implementation provides a layout and wiring method, comparison method, preparation method, equipment and storage medium.
  • a virtual connection layer is used to connect at least two ports with the same name to be connected together, so that the names in the layout are the same.
  • the ports are connected through the actual connection layer and/or the virtual connection layer.
  • the internal circuit connections are represented as disconnected from each other in the layout, which helps to improve the accuracy of the consistency comparison between the layout and the schematic diagram.
  • a virtual connection layer is added to the layout. The virtual connection layer always exists in the layout.
  • FIG. 1 is a flow chart of a layout wiring method provided by an embodiment of the present disclosure
  • Figure 2 is a partial structural schematic diagram of a layout provided by an embodiment of the present disclosure
  • Figure 3 is a layout wiring method provided by an embodiment of the present disclosure.
  • Figure 4 is another flowchart of a layout wiring method provided by an embodiment of the present disclosure
  • Figure 5 is a partial structural schematic diagram of a layout provided by an embodiment of the present disclosure.
  • the layout wiring method includes the following steps:
  • S101 Obtain the names of all ports 100 in the layout, and the port 100 has a first node 110 and a second node 120.
  • the first node 110 and the second node 120 serve as connection nodes connecting the port 100 to the actual connection layer 101 or the virtual connection layer 102 .
  • each port 100 only has one first node 110 and one second node 120 as an example. In this way, it is beneficial to pass a smaller number of actual connection layers 101 and virtual connection layers 102. Realize the connection between ports 100 and simplify the connection relationship between multiple ports 100. In practical applications, there is no limit on the number of first nodes 110 or second nodes 120 included in each port 100.
  • Figure 2 and Figure 5 only illustrate the port 100 named VDD. In the actual layout, there are other names, such as the port 100 of VSS.
  • S102 Check whether the first node 110 and the second node 120 of the port 100 are connected to other ports 100 through the actual connection layer 101. If not, the first node 110 and/or the second node 120 are not connected to the actual connection layer 101. Port 100 is used as port 130 to be connected.
  • the port 100 of the first node 110 and/or the second node 120 in the layout that is not connected to the actual connection layer 101 is connected through an internal circuit in the schematic diagram, or the first node 110 and/or the first node 110 in the layout is connected to the actual connection layer 101 .
  • the ports 100 of the second node 120 that are not connected to the actual connection layer 101 are powered through different power domains in the schematic diagram. Therefore, in the schematic diagram, the ports 100 with the same name are at the same potential, either through The actual connection layer realizes the same potential, either through the connection of internal circuits, or through at least two power domains that provide the same voltage, respectively providing voltage to the port 100 .
  • the way in which the ports 100 with the same name are at the same potential through internal circuits or different power domains providing the same voltage cannot be accurately reflected in the layout. Therefore, during the layout routing process, it is necessary to configure the first node 110 and/or Or the to-be-connected port 130 of the second node 120 that is not connected to the actual connection layer 101 is processed to eliminate the adverse effects on layout wiring caused by the differences between the schematic diagram and the layout due to the above reasons.
  • ports 100 with the same name are connected through internal circuits, which can be understood as: these ports 100 are all electrically connected to the same substrate. This connection relationship cannot be reflected in the layout, that is, this part of the ports 100 cannot be reflected in the layout. At the same potential, they are represented as disconnected from each other in the layout.
  • S103 Use the virtual connection layer 102 to connect at least two to-be-connected ports 130 with the same name.
  • the ports 100 with the same name in the layout it is beneficial for the ports 100 with the same name in the layout to be connected through the actual connection layer 101 and/or the virtual connection layer 102.
  • it is beneficial to avoid virtual connection errors in the layout that is, it is avoided that some of the ports 100 with the same names in the layout are represented as disconnected from each other in the layout, which is beneficial to improving the accuracy of the consistency comparison between the layout and the schematic diagram.
  • the virtual connection layer 102 is added to the layout.
  • the virtual connection layer 102 always exists in the layout. There is no need to remove the virtual connection layer 102 in the layout later, and there is no need to change the actual connection layer 101, which is helpful to avoid changes. Unnecessary mistakes caused by actually connecting the layer 101 are beneficial to reducing the number of layout wiring modifications, thereby helping to improve the accuracy and efficiency of layout wiring.
  • some of the ports 100 with the same name are powered by different power domains that provide the same voltage. In this way, it is beneficial to isolate at least two ports 100 with the same name to reduce the noise impact between the ports 100 .
  • the layout routing method may also include: before using the virtual connection layer 102 to connect at least two to-be-connected ports 130 with the same name: S104: Obtain the number of ports 130 to be connected.
  • step S103: using the virtual connection layer 102 to connect at least two ports 130 with the same name to be connected may include: detecting the connection relationship between all ports 100 with the same name, and making any One port 100 is connected to two other ports 100 with the same name through the virtual connection layer 102 and/or the actual connection layer 101, and all the ports 100 with the same name form a connection loop through the virtual connection layer 102 and the actual connection layer 101, that is, Step S113.
  • all ports 100 with the same name may have one and only one connection loop formed by the virtual connection layer 102 and the actual connection layer 101. If there is one and only one connection loop, then for any Each port 100 has only one first node 110 and one second node 120.
  • the first node 110 and the second node 120 are respectively connected to the third node of the other port 100 through the virtual connection layer 102 and/or the actual connection layer 101.
  • One node 110 or a second node 120 is connected.
  • connection loops formed by all the ports 100 with the same name through the virtual connection layer 102 and the actual connection layer 101 which is beneficial to reducing the complexity of the connection loop, thereby helping the operator to intuitively understand from the layout Whether the ports 100 with the same name are all connected to the same potential will also help reduce the time spent in subsequent comparisons of consistency between the schematic diagram and the layout.
  • the layout routing method is performed before using the virtual connection layer 102 to connect at least two to-be-connected ports 130 with the same name. It may also include: S105: Use the to-be-connected port 130, in which neither the first node 110 nor the second node 120 is connected to other ports 100 through the actual connection layer 101, as the target port 140; Step S103: Use the virtual connection layer 102 to connect the port 130 with the same name.
  • the at least two to-be-connected ports 130 may include: obtaining distance information between the first node 110 and the second node 120 of the target port 140 and other to-be-connected ports 130 with the same name; based on the distance information, using the virtual connection layer 102 to connect the target
  • the first node 110 of the port 140 and the to-be-connected port 130 closest to the first node 110 of the target port 140 use the virtual connection layer 102 to connect the second node 120 of the target port 140 and the second node 120 closest to the target port 140
  • the port 130 to be connected is step S123.
  • the target port 140 it is beneficial for the target port 140 to be connected to two to-be-connected ports 100 that are closer to the target port 140, thus simplifying the connection loop formed by all the ports 100 with the same name through the virtual connection layer 102 and the actual connection layer 101. It is also helpful for operators to subsequently analyze the designed layout and continue to correct errors in the designed layout, which is conducive to improving the accuracy of layout wiring and layout wiring efficiency.
  • the layout wiring method provided by an embodiment of the present disclosure is conducive to enabling ports 100 with the same name to be connected through the actual connection layer 101 and/or the virtual connection layer 102.
  • the virtual connection layer 102 in the layout always exists, and there is no need to remove the virtual connection layer 102 in the layout later, and there is no need to modify the actual connection layer 101, which is helpful to avoid unnecessary changes caused by modifying the actual connection layer 101. mistakes, and it is helpful to reduce the number of modifications of layout wiring, which is conducive to improving the accuracy and efficiency of layout wiring.
  • FIG. 6 is a flow chart of a method for comparing the consistency of a layout and a schematic diagram provided by another embodiment of the present disclosure.
  • the consistency comparison method between the layout and the schematic diagram includes the following steps:
  • S201 Provide a layout and a schematic diagram corresponding to the layout.
  • the layout includes: at least two ports 100 with the same name, and at least one virtual connection layer 102 connecting the two ports 100.
  • S202 Select any virtual connection layer 102 as the target virtual connection layer, perform a consistency comparison between the layout and the schematic diagram without identifying the target virtual connection layer, and obtain the first result.
  • the first result obtained without identifying the target virtual connection layer will at least display a virtual connection error, that is, among some ports 100 with the same name in the layout. There is no connection relationship between them.
  • the first result is that the virtual connection error is caused by the two ports 100 connected by the target virtual connection layer, which can prove that the layout is consistent with the schematic diagram.
  • the virtual connection can be understood as: some ports 100 are connected through internal circuits in the schematic diagram, or are provided with the same voltage. Different power domain control potentials.
  • some ports 100 are connected through internal circuits, which can be understood as: some ports 100 are electrically connected to the same substrate, that is, all ports 100 supply power to the substrate.
  • the internal circuit That is, the substrate, the partial ports 100 are connected through the substrate.
  • the distance between the partial substrates where the partial ports 100 are in contact with each other is relatively large, so that the resistance between the partial ports 100 is relatively large and the resistance is high.
  • the value makes the part of the ports 100 basically disconnected from each other, so it is determined that the part of the ports 100 is a virtual connection.
  • the layout and schematic consistency comparison method may also include: if the first result is a virtual connection error and the second result is an abnormality, detect whether the port 100 connected to the target virtual connection layer is correct; use the target virtual connection The connection layer connects the other two ports 100 that need to be tested to re-obtain the first result and the second result until the layout meets the requirements.
  • the first result is a virtual connection error, it means that there are virtual connections between some ports 100 with the same name in the layout, and it cannot be determined whether the partial ports 100 are ports 100 connected to the target virtual connection layer; furthermore, the second result is abnormal. , it can be determined that the virtual connection error is not caused by the two ports 100 connected by the target virtual connection layer. Therefore, the operator needs to check the two ports 100 connected by the target virtual connection layer to see whether the two ports 100 connected by the target virtual connection layer are connected. Whether the ports 100 are disconnected.
  • the target virtual connection layer uses the target virtual connection layer to connect the other two ports 100 that need to be tested to re-obtain the first result and the second result. If the first result is a virtual connection error and the second result is no abnormality, it can be determined that the One result is that the virtual connection error is caused by the two ports 100 connected to the target virtual connection layer at this time, which can prove that the layout is consistent with the schematic diagram, and is helpful for the operator to learn based on the consistency comparison method between the layout and the schematic diagram. Specifically, which ports 100 are connected virtually in the layout.
  • all virtual connection layers 102 are traversed so that each virtual connection layer 102 serves as a target virtual connection layer. In this way, it is helpful to verify whether the two ports 100 connected by each virtual connection layer 102 are in a disconnected state, so that the operator can correct the layout to improve the accuracy of layout wiring.
  • Yet another embodiment of the present disclosure also provides a method for comparing the consistency between a layout and a schematic diagram.
  • the method for comparing the consistency between a layout and a schematic diagram provided by yet another embodiment of the present disclosure is the same as the method for comparing the consistency between a layout and a schematic diagram provided by the aforementioned embodiment.
  • the main differences include not being sure whether there are virtual connection issues in the layout until comparing the layout to the schematic for consistency.
  • a method for comparing the consistency between a layout and a schematic diagram provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • FIG. 7 is a flow chart of a method for comparing the consistency of layout and schematic diagram provided by yet another embodiment of the present disclosure.
  • the consistency comparison method between the layout and the schematic diagram includes the following steps:
  • S301 Provide a layout and a schematic diagram corresponding to the layout.
  • the layout includes at least two ports 100 with the same name, and the layout does not include the virtual connection layer 102.
  • the virtual connection layer 102 is not included in the layout at this time does not mean that there is no virtual connection problem in the layout. That is, all ports 100 with the same name in the layout may have formed a connection loop, or may not have formed a connection loop yet, but it does not mean that there is no virtual connection problem in the layout. Know which ports 100 are disconnected in the layout.
  • the consistency comparison method between the layout and the schematic diagram may also include: using the virtual connection layer 102 to connect at least two ports 100 that need to be tested; Under the premise, compare the consistency between the layout and the schematic diagram, and obtain the second result; if the second result is no abnormality, it means that the layout meets the requirements.
  • the first result is a virtual connection error
  • the operator can determine which ports 100 are disconnected based on experience and use the virtual connection layer 102 Connect at least two ports 100 that need to be tested.
  • the second result is no abnormality, it means that the at least two ports 100 that need to be tested are connected using the virtual connection layer 102 and are the ports 100 with the same name that are in a disconnected state in the layout. In this way, it is helpful for the operator to know which ports 100 in the layout are virtual connections based on the consistency comparison method between the layout and the schematic diagram, and it is also convenient for the operator to correct the layout based on the consistency comparison method between the layout and the schematic diagram.
  • the layout and schematic consistency comparison method may also include: using the virtual connection layer 102 to connect at least two other ports 100 that need to be tested to re-obtain the first result and /or the second result until the layout meets the requirements. In this way, the ports 100 with the same name in the layout can be checked one after another, so that the operator can correct the layout to improve the accuracy of layout wiring.
  • Yet another embodiment of the present disclosure further provides a layout formed by the layout wiring method provided by an embodiment of the present disclosure.
  • the layout provided by yet another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • the layout includes: at least two ports 100 with the same name, and the port 100 has a first node 110 and a second node 120; an actual connection layer 101, which connects some of the ports 100 with the same name and some of the ports 100 with the same name.
  • the first node 110 and/or the second node 120 are not connected to the actual connection layer 101, and the port 100 of the first node 110 and/or the second node 120 that is not connected to the actual connection layer 101 is used as the port to be connected 130; virtual connection Layer 102 connects at least two to-be-connected ports 130 with the same name.
  • the number of ports 130 to be connected is at least three, and any port 100 is connected to two other ports 100 through the virtual connection layer 102 and/or the actual connection layer 101 , and all Ports 100 with the same name form a connection loop through the virtual connection layer 102 and the actual connection layer 101 .
  • all ports 100 with the same name can have one and only one connection loop formed by the virtual connection layer 102 and the actual connection layer 101, which is beneficial to reducing the complexity of the connection loop, thereby helping the operator to intuitively view the layout from the layout. Knowing whether the ports 100 with the same name are all connected to the same potential will also help reduce the time spent in subsequent comparisons of consistency between the schematic diagram and the layout. In practical applications, there is no limit to the number of connection loops formed by all the ports 100 with the same name through the virtual connection layer 102 and the actual connection layer 101, as long as all the ports 100 with the same name are at the same potential.
  • neither the first node 110 nor the second node 120 of some to-be-connected ports 130 is connected to the actual connection layer 101
  • neither the first node 110 nor the second node 120 is connected to the actual connection layer.
  • 101 connects the to-be-connected port 130 as the target port 140
  • the virtual connection layer 102 connects the first node 110 of the target port 140 and the to-be-connected port 130 closest to the first node 110 of the target port 140
  • the virtual connection layer 102 connects The second node 120 of the target port 140 and the to-be-connected port 130 closest to the second node 120 of the target port 140 .
  • the target port 140 it is beneficial for the target port 140 to be connected to two to-be-connected ports 100 that are closer to the target port 140, thus simplifying the connection loop formed by all the ports 100 with the same name through the virtual connection layer 102 and the actual connection layer 101. It is also helpful for operators to subsequently analyze the designed layout and continue to correct errors in the designed layout, thereby helping to improve the accuracy of the designed layout.
  • Yet another embodiment of the present disclosure also provides a circuit preparation method for preparing a circuit corresponding to a layout formed according to a layout wiring method provided by an embodiment of the present disclosure, or for preparing a circuit corresponding to a layout provided by yet another embodiment of the present disclosure. corresponding circuit.
  • the circuit preparation method includes: a layout preparation circuit formed according to the layout wiring method provided by one embodiment of the present disclosure, or a layout preparation circuit provided according to yet another embodiment of the present disclosure, wherein during the process of preparing the circuit, the virtual connection layer is not Involved in the production of prepared circuits, the virtual electrical connection layer will not be reflected in the circuit.
  • the virtual connection layer is not Involved in the production of prepared circuits, the virtual electrical connection layer will not be reflected in the circuit.
  • FIG. 8 is a schematic structural diagram of an electronic device according to yet another embodiment of the present disclosure.
  • the electronic device includes: at least one processor 113; a memory 123 communicatively connected to the at least one processor 113; wherein the memory 123 stores instructions that can be executed by the at least one processor.
  • the instructions may be executed by at least one processor 113, so that the at least one processor 113 can execute the layout routing method as described in an embodiment of the present disclosure, so as to reduce the number of modifications of layout routing and improve layout routing. accuracy and layout routing efficiency.
  • the instructions may be executed by the at least one processor 113 to enable the at least one processor 113 to execute the layout and principles described in another embodiment of the present disclosure or another embodiment of the present disclosure.
  • the diagram consistency comparison method is helpful for the operator to know which ports in the layout are virtual connections based on the consistency comparison method between the layout and the schematic diagram.
  • Yet another embodiment of the present disclosure also provides a computer-readable storage medium for implementing the layout layout and wiring method provided by the foregoing embodiment, or for implementing the consistency comparison method between the layout and the schematic diagram provided by the foregoing embodiment.
  • the computer-readable storage medium stores computer programs.
  • the layout wiring method as described in an embodiment of the present disclosure is implemented, so as to reduce the number of modifications of layout wiring and improve the accuracy and efficiency of layout wiring.
  • the method for comparing the consistency of the layout and the schematic diagram as described in another embodiment of the present disclosure or another embodiment of the present disclosure is beneficial to the operator based on the layout and the schematic diagram.
  • the graph consistency comparison method knows which ports in the layout are virtual connections.

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Abstract

一种版图及布线方法、比较方法、制备方法、设备和存储介质，版图布线方法包括：获取版图中所有端口(100)的命名，且端口(100)具有第一节点(110)和第二节点(120)(S101)；检测端口(100)的第一节点(110)和第二节点(120)是否均通过实际连接层(101)与其他端口(100)连接，若否，将第一节点(110)和/或第二节点(120)未与实际连接层(101)连接的端口(100)作为待连接端口(130)(S102)；采用虚拟连接层(102)连接命名相同的至少两个待连接端口(130)(S103)。有利于降低版图布线的修改次数，以及有利于提高版图布线的准确性和版图布线效率。

Description

版图及布线方法、比较方法、制备方法、设备和存储介质
交叉引用
本申请要求于2022年04月11日递交的名称为“版图及布线方法、比较方法、制备方法、设备和存储介质”、申请号为202210377288.9的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本公开实施例涉及半导体技术领域，特别涉及一种版图及布线方法、比较方法、制备方法、设备和存储介质。
背景技术
在集成电路设计过程中，所设计的电路功能是否与所需求的一致，是每个设计阶段都必须进行验证的问题。在设计流程的后端阶段，即依据原理图设计出版图之后，版图与原理图一致性检查(LVS，Layout Versus Schematic)用于确认电路版图是否与其原理图一致。
然而，由于版图中没有内部电路，但原理图中部分结构之间是通过内部电路实现连接，因此，该部分结构之间的连接关系无法在版图中体现，从而引起版图与原理图之间不一致的问题，进一步影响版图布线的准确性以及效率。
发明内容
本公开实施例提供一种版图及布线方法、比较方法、制备方法、设备和存储介质，版图布线方法至少有利于提高版图布线的准确性和版图布线效率。
根据本公开一些实施例，本公开实施例一方面提供一种版图布线方法，包括：获取所述版图中所有端口的命名，且所述端口具有第一节点和第二节点；检测所述端口的所述第一节点和所述第二节点是否均通过实际连接层与其他所述端口连接，若否，将所述第一节点和/或所述第二节点未与所述实际连接层连接的所述端口作为待连接端口；采用虚拟连接层连接命名相同的至少两个所述待连接端口。
在一些实施例中，在所述采用虚拟连接层连接命名相同的至少两个所述待连接端口之前，所述版图布线方法还包括：获取所述待连接端口的数量，若 所述待连接端口的数量为至少三个，所述采用虚拟连接层连接命名相同的至少两个所述待连接端口，包括：检测所有命名相同的所述端口之间的连接关系，并使得任一所述端口均通过所述虚拟连接层和/或所述实际连接层与另外两个命名相同的所述端口连接，且所有命名相同的所述端口通过所述虚拟连接层和所述实际连接层形成一个连接回路。
在一些实施例中，在所述采用虚拟连接层连接命名相同的至少两个所述待连接端口之前，所述版图布线方法还包括：将所述第一节点和所述第二节点均未通过所述实际连接层与其他所述端口连接的所述待连接端口作为目标端口；所述采用虚拟连接层连接命名相同的至少两个所述待连接端口，包括：获取所述目标端口的所述第一节点和所述第二节点与其他命名相同的所述待连接端口之间的距离信息；基于所述距离信息，采用所述虚拟连接层连接所述目标端口的所述第一节点与距离所述目标端口的所述第一节点最近的所述待连接端口，采用所述虚拟连接层连接所述目标端口的所述第二节点与距离所述目标端口的所述第二节点最近的所述待连接端口。
根据本公开一些实施例，本公开实施例另一方面还提供一种版图与原理图一致性比较方法，包括：提供版图以及与所述版图对应的原理图，所述版图包括：至少两个命名相同的端口，以及至少一个连接两个所述端口的虚拟连接层；任选一所述虚拟连接层作为目标虚拟连接层，在不识别所述目标虚拟连接层的前提下，进行所述版图与原理图一致性比较，获取第一结果；在识别所述目标虚拟连接层的前提下，进行所述版图与原理图一致性比较，并获取第二结果；若所述第一结果为虚拟连接错误，且所述第二结果为无异常，则表征所述版图符合要求。
在一些实施例中，所述版图与原理图一致性比较方法还包括：若所述第一结果为虚拟连接错误，且所述第二结果为异常，则检测所述目标虚拟连接层连接的所述端口是否正确；采用所述目标虚拟连接层连接需要进行测试的另外两个所述端口，以重新获取所述第一结果和所述第二结果，直至所述版图符合要求。
在一些实施例中，所述版图与原理图一致性比较方法还包括：遍历所有所述虚拟连接层，以使每一所述虚拟连接层均作为一次所述目标虚拟连接层。
根据本公开一些实施例，本公开实施例又一方面还提供一种版图与原理图一致性比较方法，包括：提供版图以及与所述版图对应的原理图，所述版图包括至少两个命名相同的端口，且所述版图中不包括虚拟连接层；在不识别所述虚拟连接层的前提下，进行所述版图与原理图一致性比较，获取第一结果；若所述第一结果为无异常，则表征所述版图符合要求。
在一些实施例中，若所述第一结果为虚拟连接错误，所述版图与原理图一致性比较方法还包括：采用虚拟连接层连接需要进行测试的至少两个所述端口；在识别所述虚拟连接层的前提下，进行所述版图与原理图一致性比较，并获取第二结果；若所述第二结果为无异常，则表征所述版图符合要求。
在一些实施例中，若所述第二结果为异常，所述版图与原理图一致性比较方法还包括：采用所述虚拟连接层连接需要进行测试的另外的至少两个所述端口，以重新获取所述第一结果和/或所述第二结果，直至所述版图符合要求。
根据本公开一些实施例，本公开实施例再一方面还提供一种版图，包括：命名相同的至少两个端口，且所述端口具有第一节点和第二节点；实际连接层，连接部分命名相同的所述端口，且部分命名相同的所述端口的所述第一节点和/或所述第二节点未与所述实际连接层连接，将所述第一节点和/或所述第二节点未与所述实际连接层连接的所述端口作为待连接端口；虚拟连接层，连接命名相同的至少两个所述待连接端口。
在一些实施例中，所述待连接端口的数量为至少三个，且任一所述端口均通过所述虚拟连接层和/或所述实际连接层与另外两个所述端口连接，且所有命名相同的所述端口通过所述虚拟连接层和所述实际连接层形成一个连接回路。
在一些实施例中，部分所述待连接端口的所述第一节点和所述第二节点均未与所述实际连接层连接，将所述第一节点和所述第二节点均未与所述实际连接层连接的所述待连接端口作为目标端口，其中，所述虚拟连接层连接所述目标端口的所述第一节点与距离所述目标端口的所述第一节点最近的所述待连接端口，且所述虚拟连接层连接所述目标端口的所述第二节点与距离所述目标端口的所述第二节点最近的所述待连接端口。
根据本公开一些实施例，本公开实施例再一方面还提供一种电路制备方 法，包括：依据上述任一项所述的版图布线方法形成的版图制备电路，或者，依据上述任一项所述的版图制备电路，其中，在所述制备电路的过程中，所述虚拟连接层不参与所述制备电路的生产，所述虚拟电连接层不会体现在所述电路中。
根据本公开一些实施例，本公开实施例再一方面还提供一种电子设备，包括：至少一个处理器；与所述至少一个处理器通信连接的存储器；其中，所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行如上述任一项所述的版图布线方法，或者，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行如上述任一项所述的版图与原理图一致性比较方法。
根据本公开一些实施例，本公开实施例再一方面还提供一种计算机可读存储介质，存储有计算机程序，所述计算机程序被处理器执行时实现如上述中任一项所述的版图布线方法，或者，所述计算机程序被处理器执行时实现如权利要求上述中任一项所述的版图与原理图一致性比较方法。
本公开实施例提供的技术方案至少具有以下优点：
采用虚拟连接层将命名相同的至少两个待连接端口连接在一起，以实现版图中命名相同的端口均通过实际连接层和/或虚拟连接层实现连接，如此，在进行版图与原理图一致性比较时，有利于避免版图中出现虚拟连接错误，即避免版图中部分命名相同的端口表征的状态是彼此断开，从而有利于提高版图与原理图一致性比较的准确性。此外，在版图中加入了虚拟连接层，在版图中虚拟连接层一直存在，后续无需对版图中的虚拟连接层进行去除操作，有利于降低版图布线的修改次数，从而有利于提高版图布线的准确性和版图布线效率。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图 仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的版图布线方法的一种流程图；
图2为本公开一实施例提供的版图的一种局部结构示意图；
图3为本公开一实施例提供的版图布线方法的另一种流程图；
图4为本公开一实施例提供的版图布线方法的又一种流程图；
图5为本公开一实施例提供的版图的一种局部结构示意图；
图6为本公开另一实施例提供的版图与原理图一致性比较方法的一种流程图；
图7为本公开又一实施例提供的版图与原理图一致性比较方法的一种流程图；
图8为本公开再一实施例提供的电子设备的结构示意图。
具体实施方式
由背景技术可知，版图布线的准确性以及效率有待提高。
在现有芯片设计中，为降低芯片功耗，一般采用多电压设计，也即采用多电源域设计，因而，存在多种命名不同的端口，命名不同的端口由不同的电源域供电，且命名相同的多个端口之间可能通过原理图中的内部电路实现连接，即通过内部电路连接的至少两个命名相同的端口之间不存在直接连接关系。然而，由于版图中没有内部电路，则版图中无法体现出通过内部电路连接的至少两个命名相同的端口之间的连接关系，从而会引起版图与原理图之间不一致的问题，进一步影响版图布线的准确性以及效率。
需要说明的是，在一个例子中，命名相同的多个端口之间通过原理图中的内部电路实现连接可以理解为：部分命名相同的端口都与同一衬底接触电连接，即该部分端口均可以向衬底供电，此时内部电路即为衬底，则该部分端口通过衬底连接，即通过内部电路连接的至少两个命名相同的端口之间不存在直接连接关系。然而，该部分端口各自接触连接的局部衬底之间的距离较大，使得该部分端口彼此之间的电阻较大，高阻值使得该部分端口彼此之间基本处于 断开状态，则版图中无法体现出通过内部电路连接的至少两个命名相同的端口之间的连接关系。
本公开实施提供一种版图及布线方法、比较方法、制备方法、设备和存储介质，版图布线方法中，采用虚拟连接层将命名相同的至少两个待连接端口连接在一起，使得版图中命名相同的端口均通过实际连接层和/或虚拟连接层实现连接，如此，在进行版图与原理图一致性比较时，有利于避免版图中出现虚拟连接错误，即避免版图中部分命名相同的端口因通过内部电路连接而在版图中表征为彼此断开的状态，从而有利于提高版图与原理图一致性比较的准确性。此外，在版图中加入了虚拟连接层，在版图中虚拟连接层一直存在，后续无需对版图中的虚拟连接层进行去除操作，有利于降低版图布线的修改次数，从而有利于提高版图布线的准确性和版图布线效率。需要说明的是，部分命名相同的端口通过内部电路连接可以理解为：该部分端口都与同一衬底接触电连接，该连接关系在版图中无法体现，而且，该部分端口各自接触连接的局部衬底之间的距离较大，使得该部分端口彼此之间的电阻较大，高阻值使得该部分端口彼此之间基本处于断开状态，因而，该部分端口在版图中表征为彼此断开的状态。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
本公开一实施例提供一种版图布线方法，以下将结合附图对本公开一实施例提供的版图布线方法进行详细说明。图1为本公开一实施例提供的版图布线方法的一种流程图；图2为本公开一实施例提供的版图的一种局部结构示意图；图3为本公开一实施例提供的版图布线方法的另一种流程图；图4为本公开一实施例提供的版图布线方法的又一种流程图；图5为本公开一实施例提供的版图的一种局部结构示意图。
参考图1至图5，版图布线方法包括如下步骤：
S101：获取版图中所有端口100的命名，且端口100具有第一节点110和第二节点120。
其中，第一节点110和第二节点120作为端口100与实际连接层101或者虚拟连接层102连接的连接节点。需要说明的是，图2和图5中以每一端口100仅具有一第一节点110和一第二节点120为示例，如此，有利于通过数量较少的实际连接层101和虚拟连接层102实现端口100之间的连接，简化多个端口100之间的连接关系，实际应用中，对每一端口100包含的第一节点110或第二节点120的数量不做限制。
此外，图2和图5仅示意出了命名为VDD的端口100，实际的版图中，还具有其他命名，例如VSS的端口100。
S102：检测端口100的第一节点110和第二节点120是否均通过实际连接层101与其他端口100连接，若否，将第一节点110和/或第二节点120未与实际连接层101连接的端口100作为待连接端口130。
需要说明的是，版图中第一节点110和/或第二节点120未与实际连接层101连接的端口100在原理图中通过内部电路实现了连接，或者，版图中第一节点110和/或第二节点120未与实际连接层101连接的端口100在原理图中通过不同的电源域进行了供电，因此，在原理图中，命名相同的端口100之间均处于相同的电位，要么是通过实际连接层实现电位的相同，要么是通过内部电路的连接实现，要么是通过至少两个提供的电压相同的电源域分别对端口100提供电压实现。
然而，通过内部电路或者提供的电压相同的不同电源域实现命名相同的端口100处于相同的电位的方式无法在版图中准确体现，因而，在版图布线的过程中，需要对第一节点110和/或第二节点120未与实际连接层101连接的待连接端口130进行处理，以消除原理图与版图中由于上述原因导致的差异给版图布线带来的不利影响。
需要说明的是，部分命名相同的端口100通过内部电路连接可以理解为：该部分端口100都与同一衬底接触电连接，该连接关系在版图中无法体现，即版图中无法体现该部分端口100处于相同的电位，在版图中表征为彼此断开的状态。
S103：采用虚拟连接层102连接命名相同的至少两个待连接端口130。
如此，有利于使得版图中命名相同的端口100均通过实际连接层101和/ 或虚拟连接层102实现连接，如此，在进行版图与原理图一致性比较时，有利于避免版图中出现虚拟连接错误，即避免版图中部分命名相同的端口100在版图中表征为彼此断开的状态，从而有利于提高版图与原理图一致性比较的准确性。此外，在版图中加入了虚拟连接层102，在版图中虚拟连接层102一直存在，后续无需对版图中的虚拟连接层102进行去除操作，也无需对实际连接层101进行改动，有利于避免改动实际连接层101而引发的不必要的失误，以及有利于降低版图布线的修改次数，从而有利于提高版图布线的准确性和版图布线效率。
此外，原理图中，通过提供的电压相同的不同电源域分别对部分命名相同的端口100进行供电，如此，有利于隔离至少两个命名相同的端口100，以降低该端口100之间的噪声影响。
关于采用虚拟连接层102连接命名相同的至少两个待连接端口130的具体步骤，以下通过两种实施例对其进行详细说明。
在一些实施例中，参考图3，版图布线方法处理除包括上述步骤S101-S103之外，在采用虚拟连接层102连接命名相同的至少两个待连接端口130之前，版图布线方法还可以包括：S104：获取待连接端口130的数量。若待连接端口130的数量为至少三个，步骤S103：采用虚拟连接层102连接命名相同的至少两个待连接端口130可以包括：检测所有命名相同的端口100之间的连接关系，并使得任一端口100均通过虚拟连接层102和/或实际连接层101与另外两个命名相同的端口100连接，且所有命名相同的端口100通过虚拟连接层102和实际连接层101形成一个连接回路，即步骤S113。
需要说明的是，参考图2，所有命名相同的端口100通过虚拟连接层102和实际连接层101形成的连接回路可以有且仅有一个，若该连接回路有且仅有一个，则对于任一端口100而沿均只具有一个第一节点110和一个第二节点120，该第一节点110和该第二节点120分别通过虚拟连接层102和/或实际连接层101与另一端口100的第一节点110或第二节点120连接。其中，使得所有命名相同的端口100通过虚拟连接层102和实际连接层101形成的连接回路有且仅有一个，有利于降低连接回路的复杂度，从而有利于操作人员直观地从版图中了解到命名相同的端口100是否均连接于同一电位，也有利于降低后续进行原理图与版图一致性比较时耗费的时间。在实际应用中，对所有命名相同的端口100 通过虚拟连接层102和实际连接层101形成的连接回路的数量可以不做限制，只需满足所有命名相同的端口100所处的电位相同即可。
在另一些实施例中，参考图4和图5，版图布线方法处理除包括上述步骤S101-S103之外，在采用虚拟连接层102连接命名相同的至少两个待连接端口130之前，版图布线方法还可以包括：S105：将第一节点110和第二节点120均未通过实际连接层101与其他端口100连接的待连接端口130作为目标端口140；步骤S103：采用虚拟连接层102连接命名相同的至少两个待连接端口130可以包括：获取目标端口140的第一节点110和第二节点120与其他命名相同的待连接端口130之间的距离信息；基于距离信息，采用虚拟连接层102连接目标端口140的第一节点110与距离目标端口140的第一节点110最近的待连接端口130，采用虚拟连接层102连接目标端口140的第二节点120与距离目标端口140的第二节点120最近的待连接端口130，即步骤S123。
如此，有利于使得目标端口140可以与和该目标端口140距离较近的两个待连接端口100连接，从而简化所有命名相同的端口100通过虚拟连接层102和实际连接层101形成的连接回路，以及有利于操作人员后续分析设计的版图以及对设计的版图继续纠错，从而有利于提高版图布线的准确性以及版图布线效率。
综上所述，本公开一实施例提供的版图布线方法有利于使得命名相同的端口100均通过实际连接层101和/或虚拟连接层102实现连接，如此，在进行版图与原理图一致性比较时，有利于避免版图中部分命名相同的端口100之间处于断开的状态，从而有利于提高版图与原理图一致性比较的准确性。此外，版图中的虚拟连接层102一直存在，后续无需对版图中的虚拟连接层102进行去除操作，也无需对实际连接层101进行改动，有利于避免改动实际连接层101而引发的不必要的失误，以及有利于降低版图布线的修改次数，从而有利于提高版图布线的准确性和版图布线效率。
本公开另一实施例还提供一种版图与原理图一致性比较方法。以下将结合附图对本公开另一实施例提供的版图与原理图一致性比较方法进行详细说明。图6为本公开另一实施例提供的版图与原理图一致性比较方法的一种流程图。
结合参考图5和图6，版图与原理图一致性比较方法包括如下步骤：
S201：提供版图以及与版图对应的原理图，版图包括：至少两个命名相同的端口100，以及至少一个连接两个端口100的虚拟连接层102。
S202：任选一虚拟连接层102作为目标虚拟连接层，在不识别目标虚拟连接层的前提下，进行版图与原理图一致性比较，获取第一结果。
需要说明的是，由于版图中已经存在虚拟连接层102，因而在不识别目标虚拟连接层的前提下获取的第一结果中，至少会显示虚拟连接错误，即版图中命名相同的部分端口100之间不存在连接关系。
S203：在识别目标虚拟连接层的前提下，进行版图与原理图一致性比较，并获取第二结果；若第一结果为虚拟连接错误，且第二结果为无异常，则表征版图符合要求。
由于第二结果为无异常，因此可以判定第一结果为虚拟连接错误是由目标虚拟连接层连接的两个端口100造成的，从而可以佐证该版图为与原理图一致，此外，也有利于操作人员基于该版图与原理图一致性比较方法获知版图中哪些端口100之间为虚拟连接，其中，虚拟连接可以理解为：部分端口100在原理图中通过内部电路连接，或者由提供的电压相同的不同电源域控制电位，其中，部分端口100在原理图中通过内部电路连接可以理解为：部分端口100都与同一衬底接触电连接，即该部分端口100均向衬底供电，此时内部电路即为衬底，则该部分端口100通过衬底连接，然而，该部分端口100各自接触连接的局部衬底之间的距离较大，使得该部分端口100彼此之间的电阻较大，高阻值使得该部分端口100彼此之间基本处于断开状态，因而判定该部分端口100之间为虚拟连接。
在一些实施例中，版图与原理图一致性比较方法还可以包括：若第一结果为虚拟连接错误，且第二结果为异常，则检测目标虚拟连接层连接的端口100是否正确；采用目标虚拟连接层连接需要进行测试的另外两个端口100，以重新获取第一结果和第二结果，直至版图符合要求。
由于第一结果为虚拟连接错误，则表征版图中命名相同的部分端口100之间存在虚拟连接，且无法确定该部分端口100是否为目标虚拟连接层连接的端口100；而且，第二结果为异常，则可以判定虚拟连接错误并不是目标虚拟连 接层连接的两个端口100引起的，因此，需要操作人员对目标虚拟连接层连接的两个端口100进行检查，看是否目标虚拟连接层连接的两个端口100之间是否处于断开状态。
然后，采用目标虚拟连接层连接需要进行测试的另外两个端口100，以重新获取第一结果和第二结果，若第一结果为虚拟连接错误，且第二结果为无异常，则可以判定第一结果为虚拟连接错误是由此时目标虚拟连接层连接的两个端口100造成的，从而可以佐证该版图为与原理图一致，以及有利于操作人员基于该版图与原理图一致性比较方法获知版图中具体是哪些端口100之间为虚拟连接。
在一些实施例中，遍历所有虚拟连接层102，以使每一虚拟连接层102均作为一次目标虚拟连接层。如此，有利于验证每一虚拟连接层102连接的两个端口100之间是否处于断开状态，以便于操作人员对版图进行修正，以提高版图布线的准确性。
本公开又一实施例还提供一种版图与原理图一致性比较方法，本公开又一实施例提供的版图与原理图一致性比较方法与前述实施例提供的版图与原理图一致性比较方法，主要区别包括在进行版图与原理图一致性比较之前，不确定版图中是否存在虚拟连接问题。以下将结合附图对本公开另一实施例提供的版图与原理图一致性比较方法进行详细说明。图7为本公开又一实施例提供的版图与原理图一致性比较方法的一种流程图。
结合参考图5和图7，版图与原理图一致性比较方法包括如下步骤：
S301：提供版图以及与版图对应的原理图，版图包括至少两个命名相同的端口100，且版图中不包括虚拟连接层102。
需要说明的是，此时版图中不包括虚拟连接层102不代表版图中不存在虚拟连接问题，即版图中所有命名相同的端口100可能已经形成连接回路，也可能还未形成连接回路，只是不知道哪些端口100在版图中处于断开状态。
S302：在不识别虚拟连接层的前提下，进行版图与原理图一致性比较，获取第一结果，若第一结果为无异常，则表征版图符合要求，即版图中无需虚拟连接层102，所有命名相同的端口100之间已经形成连接回路。
在一些实施例中，若第一结果为虚拟连接错误，版图与原理图一致性比较方法还可以包括：采用虚拟连接层102连接需要进行测试的至少两个端口100；在识别虚拟连接层102的前提下，进行版图与原理图一致性比较，并获取第二结果；若第二结果为无异常，则表征版图符合要求。
由于第一结果为虚拟连接错误，因此可以判定版图中命名相同的部分端口100之间处于断开状态，操作人员可以基于经验判定是哪些端口100之间处于断开状态，并采用虚拟连接层102连接需要进行测试的至少两个端口100，后续在识别虚拟连接层102的前提下，进行版图与原理图一致性比较，以验证采用虚拟连接层102连接需要进行测试的至少两个端口100是否准确，即采用虚拟连接层102连接需要进行测试的至少两个端口100是否为版图中处于断开状态的命名相同的端口100。若第二结果为无异常，则表征采用虚拟连接层102连接需要进行测试的至少两个端口100即为版图中处于断开状态的命名相同的端口100。如此，有利于操作人员基于该版图与原理图一致性比较方法获知版图中具体是哪些端口100之间为虚拟连接，以及便于操作人员基于该版图与原理图一致性比较方法对版图进行修正。
在一些实施例中，若第二结果为异常，版图与原理图一致性比较方法还可以包括：采用虚拟连接层102连接需要进行测试的另外的至少两个端口100，以重新获取第一结果和/或第二结果，直至版图符合要求。如此，可以逐次对版图中命名相同的端口100进行排查，以便于操作人员对版图进行修正，以提高版图布线的准确性。
本公开再一实施例还提供一种版图，通过本公开一实施例提供的版图布线方法形成。以下将结合附图对本公开再一实施例提供的版图进行详细说明。
参考图2，版图包括：命名相同的至少两个端口100，且端口100具有第一节点110和第二节点120；实际连接层101，连接部分命名相同的端口100，且部分命名相同的端口100的第一节点110和/或第二节点120未与实际连接层101连接，将第一节点110和/或第二节点120未与实际连接层101连接的端口100作为待连接端口130；虚拟连接层102，连接命名相同的至少两个待连接端口130。
如此，有利于通过虚拟连接层102使得版图中命名相同的端口100之间 均实现连接，如此，在后续进行版图与原理图一致性比较时，有利于避免版图中出现虚拟连接错误，即避免版图中部分命名相同的端口100在版图中表征为彼此断开的状态，从而有利于提高版图与原理图一致性比较的准确性。此外，版图中的虚拟连接层102一直存在，后续无需对版图中的虚拟连接层102进行去除操作，也无需对实际连接层101进行改动，有利于提高设计的版图的准确性。
在一些实施例中，继续参考图2，待连接端口130的数量为至少三个，且任一端口100均通过虚拟连接层102和/或实际连接层101与另外两个端口100连接，且所有命名相同的端口100通过虚拟连接层102和实际连接层101形成一个连接回路。
需要说明的是，所有命名相同的端口100通过虚拟连接层102和实际连接层101形成的连接回路可以有且仅有一个，有利于降低连接回路的复杂度，从而有利于操作人员直观地从版图中了解到命名相同的端口100是否均连接于同一电位，也有利于降低后续进行原理图与版图一致性比较时耗费的时间。在实际应用中，对所有命名相同的端口100通过虚拟连接层102和实际连接层101形成的连接回路的数量可以不做限制，只需满足所有命名相同的端口100所处的电位相同即可。
在一些实施例中，参考图5，部分待连接端口130的第一节点110和第二节点120均未与实际连接层101连接，将第一节点110和第二节点120均未与实际连接层101连接的待连接端口130作为目标端口140，其中，虚拟连接层102连接目标端口140的第一节点110与距离目标端口140的第一节点110最近的待连接端口130，且虚拟连接层102连接目标端口140的第二节点120与距离目标端口140的第二节点120最近的待连接端口130。
如此，有利于使得目标端口140可以与和该目标端口140距离较近的两个待连接端口100连接，从而简化所有命名相同的端口100通过虚拟连接层102和实际连接层101形成的连接回路，以及有利于操作人员后续分析设计的版图以及对设计的版图继续纠错，从而有利于提高设计的版图的准确性。
本公开再一实施例还提供一种电路制备方法，用于制备与依据本公开一实施例提供的版图布线方法形成的版图对应的电路，或者用于制备与本公开再 一实施例提供的版图对应的电路。
电路制备方法包括：依据本公开一实施例提供的版图布线方法形成的版图制备电路，或者，依据本公开再一实施例提供的版图制备电路，其中，在制备电路的过程中，虚拟连接层不参与制备电路的生产，虚拟电连接层不会体现在电路中。可以理解的是，依据前述实施例提供的版图制备的电路中，不存在与版图中虚拟连接层对应的电路结构，即虚拟连接层不会对电路中命名相同的端口之间的连接关系造成影响。此外，电路中，可以通过提供的电压相同的不同电源域分别对部分命名相同的端口进行供电，如此，有利于隔离至少两个命名相同的端口，以降低该端口之间的噪声影响。
本公开再一实施例还提供一种电子设备，用于执行本公开一实施例提供的版图布线方法，或者执行本公开另一实施例或本公开又一实施例提供的版图与原理图一致性比较方法。以下将结合附图对本公开再一实施例提供的电子设备进行详细说明。图8为本公开再一实施例提供的电子设备的结构示意图。
参考图8，电子设备包括：至少一个处理器113；与至少一个处理器113通信连接的存储器123；其中，存储器123存储有可被至少一个处理器执行的指令。
在一些实施例中，指令可以被至少一个处理器113执行，以使至少一个处理器113能够执行如本公开一实施例所述的版图布线方法，以降低版图布线的修改次数，以及提高版图布线的准确性和版图布线效率。
在另一些实施例中，指令可以被所述至少一个处理器113执行，以使所述至少一个处理器113能够执行如本公开另一实施例或本公开又一实施例所述的版图与原理图一致性比较方法，有利于操作人员基于该版图与原理图一致性比较方法获知版图中具体是哪些端口之间为虚拟连接。
本公开再一实施例还提供一种计算机可读存储介质，用于实现前述实施例提供的版图布局布线方法，或者实现前述实施例提供的版图与原理图一致性比较方法。其中，计算机可读存储介质存储有计算机程序。
在一些实施例中，计算机程序被处理器执行时实现如本公开一实施例所述的版图布线方法，以降低版图布线的修改次数，以及提高版图布线的准确性和版图布线效率。
在另一些实施例中，计算机程序被处理器执行时实现如本公开另一实施例或本公开又一实施例所述的版图与原理图一致性比较方法，有利于操作人员基于该版图与原理图一致性比较方法获知版图中具体是哪些端口之间为虚拟连接。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各自更动与修改，因此本公开的保护范围应当以权利要求限定的范围为准。

Claims (15)

  1. 一种版图布线方法，包括：
    获取所述版图中所有端口的命名，且所述端口具有第一节点和第二节点；
    检测所述端口的所述第一节点和所述第二节点是否均通过实际连接层与其他所述端口连接，若否，将所述第一节点和/或所述第二节点未与所述实际连接层连接的所述端口作为待连接端口；
    采用虚拟连接层连接命名相同的至少两个所述待连接端口。
  2. 如权利要求1所述的版图布线方法，其中，在所述采用虚拟连接层连接命名相同的至少两个所述待连接端口之前，所述版图布线方法还包括：获取所述待连接端口的数量，若所述待连接端口的数量为至少三个，所述采用虚拟连接层连接命名相同的至少两个所述待连接端口，包括：
    检测所有命名相同的所述端口之间的连接关系，并使得任一所述端口均通过所述虚拟连接层和/或所述实际连接层与另外两个命名相同的所述端口连接，且所有命名相同的所述端口通过所述虚拟连接层和所述实际连接层形成一个连接回路。
  3. 如权利要求1所述的版图布线方法，其中，在所述采用虚拟连接层连接命名相同的至少两个所述待连接端口之前，所述版图布线方法还包括：将所述第一节点和所述第二节点均未通过所述实际连接层与其他所述端口连接的所述待连接端口作为目标端口；
    所述采用虚拟连接层连接命名相同的至少两个所述待连接端口，包括：
    获取所述目标端口的所述第一节点和所述第二节点与其他命名相同的所述待连接端口之间的距离信息；
    基于所述距离信息，采用所述虚拟连接层连接所述目标端口的所述第一节点与距离所述目标端口的所述第一节点最近的所述待连接端口，采用所述虚拟连接层连接所述目标端口的所述第二节点与距离所述目标端口的所述第二节点最近的所述待连接端口。
  4. 一种版图与原理图一致性比较方法，包括：
    提供版图以及与所述版图对应的原理图，所述版图包括：至少两个命名相同的端口，以及至少一个连接两个所述端口的虚拟连接层；
    任选一所述虚拟连接层作为目标虚拟连接层，在不识别所述目标虚拟连接层 的前提下，进行所述版图与原理图一致性比较，获取第一结果；
    在识别所述目标虚拟连接层的前提下，进行所述版图与原理图一致性比较，并获取第二结果；
    若所述第一结果为虚拟连接错误，且所述第二结果为无异常，则表征所述版图符合要求。
  5. 如权利要求4所述的版图与原理图一致性比较方法，其中，所述版图与原理图一致性比较方法还包括：若所述第一结果为虚拟连接错误，且所述第二结果为异常，则检测所述目标虚拟连接层连接的所述端口是否正确；采用所述目标虚拟连接层连接需要进行测试的另外两个所述端口，以重新获取所述第一结果和所述第二结果，直至所述版图符合要求。
  6. 如权利要求4或5所述的版图与原理图一致性比较方法，其中，所述版图与原理图一致性比较方法还包括：遍历所有所述虚拟连接层，以使每一所述虚拟连接层均作为一次所述目标虚拟连接层。
  7. 一种版图与原理图一致性比较方法，包括：提供版图以及与所述版图对应的原理图，所述版图包括至少两个命名相同的端口，且所述版图中不包括虚拟连接层；
    在不识别所述虚拟连接层的前提下，进行所述版图与原理图一致性比较，获取第一结果；
    若所述第一结果为无异常，则表征所述版图符合要求。
  8. 如权利要求7所述的版图与原理图一致性比较方法，其中，若所述第一结果为虚拟连接错误，所述版图与原理图一致性比较方法还包括：
    采用虚拟连接层连接需要进行测试的至少两个所述端口；
    在识别所述虚拟连接层的前提下，进行所述版图与原理图一致性比较，并获取第二结果；
    若所述第二结果为无异常，则表征所述版图符合要求。
  9. 如权利要求8所述的版图与原理图一致性比较方法，其中，若所述第二结果为异常，所述版图与原理图一致性比较方法还包括：
    采用所述虚拟连接层连接需要进行测试的另外的至少两个所述端口，以重新获取所述第一结果和/或所述第二结果，直至所述版图符合要求。
  10. 一种版图，包括：
    命名相同的至少两个端口，且所述端口具有第一节点和第二节点；
    实际连接层，连接部分命名相同的所述端口，且部分命名相同的所述端口的所述第一节点和/或所述第二节点未与所述实际连接层连接，将所述第一节点和/或所述第二节点未与所述实际连接层连接的所述端口作为待连接端口；
    虚拟连接层，连接命名相同的至少两个所述待连接端口。
  11. 如权利要求10所述的版图，其中，所述待连接端口的数量为至少三个，且任一所述端口均通过所述虚拟连接层和/或所述实际连接层与另外两个所述端口连接，且所有命名相同的所述端口通过所述虚拟连接层和所述实际连接层形成一个连接回路。
  12. 如权利要求11所述的版图，其中，部分所述待连接端口的所述第一节点和所述第二节点均未与所述实际连接层连接，将所述第一节点和所述第二节点均未与所述实际连接层连接的所述待连接端口作为目标端口，其中，所述虚拟连接层连接所述目标端口的所述第一节点与距离所述目标端口的所述第一节点最近的所述待连接端口，且所述虚拟连接层连接所述目标端口的所述第二节点与距离所述目标端口的所述第二节点最近的所述待连接端口。
  13. 一种电路的制备方法，包括：依据如权利要求1至3任一项所述的版图布线方法形成的版图制备电路，或者，依据如权利要求7至9任一项所述的版图制备电路，其中，在所述制备电路的过程中，所述虚拟连接层不参与所述制备电路的生产，所述虚拟电连接层不会体现在所述电路中。
  14. 一种电子设备，包括：
    至少一个处理器；
    与所述至少一个处理器通信连接的存储器；
    其中，所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行如权利要求1至3中任一项所述的版图布线方法，或者，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行如权利要求4至9中任一项所述的版图与原理图一致性比较方法。
  15. 一种计算机可读存储介质，存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至3中任一项所述的版图布线方法，或者，所述计算机程序被处理器执行时实现如权利要求4至9中任一项所述的版图与原理图一致性比较方法。
PCT/CN2022/087763 2022-04-11 2022-04-19 版图及布线方法、比较方法、制备方法、设备和存储介质 WO2023197344A1 (zh)

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