WO2021249129A1 - 集成电路版图设计规则文件检查工具及检查方法 - Google Patents

集成电路版图设计规则文件检查工具及检查方法 Download PDF

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Publication number
WO2021249129A1
WO2021249129A1 PCT/CN2021/094219 CN2021094219W WO2021249129A1 WO 2021249129 A1 WO2021249129 A1 WO 2021249129A1 CN 2021094219 W CN2021094219 W CN 2021094219W WO 2021249129 A1 WO2021249129 A1 WO 2021249129A1
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Prior art keywords
integrated circuit
circuit layout
design rule
test case
layout design
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PCT/CN2021/094219
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English (en)
French (fr)
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陈川江
白黎
赵康
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长鑫存储技术有限公司
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Priority to EP21766371.5A priority Critical patent/EP3951636A4/en
Priority to US17/399,107 priority patent/US11983480B2/en
Publication of WO2021249129A1 publication Critical patent/WO2021249129A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

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  • the embodiments of the present application relate to the technical field of semiconductor integrated circuits, and in particular, to an inspection tool and inspection method for integrated circuit layout design rule files.
  • Layout design rule checking is produced along with the design of semiconductor transistor circuits. Whether it is designing a single transistor or a complex system on chip (System on Chip, SOC for short), design rule checking is required to ensure that the layout design is correct. The process is reliable and can be produced smoothly.
  • Figure 1 is a schematic diagram of the flow chart of integrated circuit layout design rule inspection provided by the prior art. See Figure 1. At present, the layout is manually checked by the layout engineer to find out all the violations of the design rules caused by the layout. Potential short circuit, open circuit, or other undesirable errors.
  • the embodiment of the application provides an integrated circuit layout design rule file inspection tool and inspection method, so as to ensure that the design rule inspection file is consistent with the design rules defined in the design rule manual and improve the chip manufacturing yield.
  • an integrated circuit layout design rule file inspection tool which includes:
  • Intelligent library building engine used to generate test case database
  • Intelligent placement engine used to generate standard integrated circuit layout based on test case database
  • the intelligent detection and analysis engine is used to detect and analyze the target integrated circuit layout design rule file according to the standard integrated circuit layout.
  • target integrated circuit layout design rule file contains multiple standard specifications of the integrated circuit layout design rule, and each standard specification establishes a standard specification test case library.
  • the standard specifications include positive specifications and negative specifications.
  • the standard specification test case library is used to generate multiple standard integrated circuit layouts, and the standard specification test case library is set in the intelligent library building engine.
  • the intelligent detection and analysis engine is also used to generate a detection report, which contains information for judging whether the target integrated circuit layout design rule file is correct or not.
  • test report contains the first type of error information of the standard specification, the intelligent library building engine is not updated;
  • test report contains the second type of error information of the standard specification, update the intelligent library engine.
  • the updated intelligent library building engine is used to check the target integrated circuit layout design rule file and generate a target detection report, which does not contain the second type of error information.
  • an embodiment of the present application also provides an integrated circuit layout design rule file inspection method, which is applied to the integrated circuit layout design rule file inspection tool of the embodiment of the first aspect of the present application, and the inspection method includes:
  • the intelligent detection analysis engine Provide the target integrated circuit layout design rule file to the intelligent detection analysis engine, and control the intelligent detection analysis engine to detect and analyze the target integrated circuit layout design rule file according to the standard integrated circuit layout.
  • the inspection method also includes:
  • the target integrated circuit layout design rule file is generated.
  • the integrated circuit layout design rule file checking tool includes: an intelligent library building engine, used to generate a test case database; an intelligent placement engine, used to generate a standard integrated circuit layout based on the test case database; intelligent detection
  • the analysis engine is used to detect and analyze the target integrated circuit layout design rule file according to the standard integrated circuit layout. It solves the problem that the layout in the prior art is only manually checked by the layout engineer for the design rules, and the physical verification errors that may be caused are not found, which affects the subsequent production and manufacturing of the chip or even the chip cannot be used, and ultimately causes huge economic losses. Ensure that the design rule check file is consistent with the design rule defined in the design rule manual, and improve the chip manufacturing yield.
  • FIG. 1 is a schematic diagram of a flow chart for checking the layout design rules of an integrated circuit provided by the prior art
  • FIG. 2 is a schematic diagram of the structure of an integrated circuit layout design rule file inspection tool provided by an embodiment of the present application
  • FIG. 3 is a schematic diagram of a process of generating a test case database by an intelligent database construction engine provided by an embodiment of the present application;
  • FIG. 4 is a schematic diagram of a standard integrated circuit layout generated by the smart placement engine provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a detection report generated by an intelligent detection analysis engine provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a flow chart of an integrated circuit layout design rule check provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the consistency percentage between the integrated circuit layout design rule inspection document and the integrated circuit layout design inspection manual provided by an embodiment of the present application;
  • FIG. 8 is a schematic flowchart of a method for checking an integrated circuit layout design rule file provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an integrated circuit layout design rule file inspection tool provided by an embodiment of this application. This embodiment can be applied to the case of performing reliability analysis on the layout design rule inspection file.
  • the integrated circuit layout design rule file inspection The structure of the tool 100 specifically includes the following:
  • the intelligent library building engine 110 is used to generate a test case database
  • the intelligent placement engine 120 is used to generate a standard integrated circuit layout 150 according to the test case database;
  • the intelligent detection and analysis engine 130 is used to detect and analyze the target integrated circuit layout design rule file 140 according to the standard integrated circuit layout 150.
  • test case database includes multiple test cases, and each test case may, but is not limited to, include multiple design rules.
  • the intelligent database construction engine 110 generates multiple test case databases through the test case intelligent database construction algorithm, and each test case database corresponds to a design rule.
  • the smart placement engine 120 generates a standard integrated circuit layout 150 through the test case smart placement algorithm. It can be understood that multiple test case databases correspond to multiple standard integrated circuit layouts 150, and multiple standard integrated circuit layouts 150 correspond to each Design rules corresponding to the test case database.
  • the intelligent detection and analysis engine 130 detects and analyzes the target integrated circuit layout design rule file 140 according to the standard integrated circuit layout 150 to ensure the realization of the design rules in the target integrated circuit layout design rule file 140 and the definition of the design rules in the layout design rule manual They are completely consistent, so as to ensure the follow-up chip function and manufacturing yield.
  • the target integrated circuit layout design rule file 140 contains multiple standard specifications of the integrated circuit layout design rules, and each standard specification establishes a standard specification test case library.
  • the standard specifications are the design rules in the layout design.
  • the target integrated circuit layout design rule file 140 includes multiple design rules of the integrated circuit layout design rule, and each design rule establishes a standard specification test case library corresponding to the design rule.
  • the standard specifications include positive specifications and negative specifications.
  • the positive specifications are design rules that comply with the layout design rules of integrated circuits
  • the negative specifications are design rules that do not comply with the layout design rules of integrated circuits.
  • each standard specification corresponds to the establishment of a standard specification test case library
  • each standard specification test case library contains test cases of positive specifications and test cases of negative specifications, test cases of positive rules and
  • the number of test cases of the negative specification can be the same or different.
  • the number of test cases in the specific standard specification test case library can be selected and set according to the actual needs of those skilled in the art, and this embodiment does not impose any limitation on this .
  • test case database established for each standard specification contains multiple test cases.
  • the test case database of design rule A is the test case database corresponding to standard specification A
  • the test case database of standard specification A contains The multiple test cases are A_testpattren1, A_testpattren2, A_testpattren3...A_testpattrenX, A_testpattren1, A_testpattren2, A_testpattren3...A_testpattrenX respectively correspond to different test cases.
  • A_testpattren1 can be a test case of a positive specification or a test case of a negative specification.
  • A_testpattrenX can be a test case of a positive specification or a test case of a negative specification. This embodiment The example does not impose any restrictions on the specification type corresponding to each test case.
  • test case database of design rule B is the test case database corresponding to standard specification B
  • B_testpattren1 can be a test case of a positive specification or a test case of a negative specification.
  • B_testpattrenX can be a test case of a positive specification or a test case of a negative specification.
  • the test case database of design rule M is the test case database corresponding to standard specification M.
  • the test case database of standard specification A contains multiple test cases respectively M_testpattren1, M_testpattren2, M_testpattren3...M_testpattrenX, M_testpattren1, M_testpattren2, M_testpattren3...M_testpattrenX Corresponding to different test cases.
  • M_testpattren1 can be a test case of a positive specification or a test case of a negative specification.
  • M_testpattrenX can be a test case of a positive specification or a test case of a negative specification.
  • test case library corresponding to each standard specification can contain the same number of test cases or different numbers of test cases, that is, the corresponding X in each test case library can be the same value or can be Different values.
  • the standard specification test case library is used to generate a plurality of standard integrated circuit layouts 150, and the standard specification test case library is set in the intelligent library building engine 110.
  • the multiple standard integrated circuit layouts 150 include a standard integrated circuit layout with a positive specification and a standard integrated circuit layout with a negative specification.
  • Each design rule establishes a standard specification test case library corresponding to the design rule.
  • the standard specification test case library corresponding to each design rule contains a standard integrated circuit layout with positive specifications and a standard integrated circuit layout with negative specifications.
  • the smart placement engine 120 intelligently places all test cases corresponding to the standard specifications through the smart placement algorithm of test cases, and generates multiple standard integrated circuit layouts 150.
  • the standard integrated circuit layout 150 can display the differences between the included devices. Design rules.
  • FIG. 4 is a schematic diagram of a standard integrated circuit layout 150 generated by the smart placement engine 120 provided by an embodiment of the present application.
  • the multiple test cases contained in each test case database corresponding to each standard specification are all
  • a standard integrated circuit layout 150 is generated. It can be understood that the standard integrated circuit layout 150 corresponding to all test cases in the test case database corresponding to a standard specification includes: the standard integrated circuit layout corresponding to the test case of the forward specification, And the standard integrated circuit layout corresponding to the test case of the negative specification.
  • the test case database of design rule A in Figure 3 contains multiple test cases A_testpattren1, A_testpattren2, A_testpattren3, A_testpattren4, A_testpattren5...A_testpattrenX respectively generates the standard integrated circuit layout 150 in Figure 4,
  • the standard integrated circuit layouts 150 corresponding to the test cases in the test case database of design rule A are respectively A_testpattren1, A_testpattren2, A_testpattren3, A_testpattren4, A_testpattren5...A_testpattrenX to indicate the standard integrated circuit layout 150 corresponding to the test case. .
  • test case database of design rule B in Figure 3 contains multiple test cases B_testpattren1, B_testpattren2, B_testpattren3, B_testpattren4, B_testpattren5...BtestpattrenX, respectively corresponding to the standard integrated circuit layout 150 in Figure 4 to be generated as B_testpattren1, B_testpattren2 , B_testpattren3, B_testpattren4, B_testpattren5...B_testpattrenX, to indicate the standard integrated circuit layout 150 corresponding to the test case.
  • the test case database of the design rule M in Figure 3 contains multiple test cases M_testpattren1, M_testpattren2, M_testpattren3, M_testpattren4, M_testpattren5...M_testpattrenX, which correspond to the standard integrated circuit layout 150 in Figure 4 to be generated respectively as M_testpattren1, M_testpattren2, M_testpattren3, M_testpattren3, M_testpattren4, M_testpattren5...M_testpattrenX, to indicate the standard integrated circuit layout 150 corresponding to the test case.
  • test case layout of each standard specification can be enlarged or reduced, rotated or mirrored, that is, M_testpattren1, M_testpattren2, M_testpattren3, M_testpattren4 can be performed.
  • M_testpattren5 Each standard integrated circuit layout 150 in M_testpattrenX generates a new standard integrated circuit layout 150 through operations such as zooming in or out, rotating or mirroring.
  • the standard integrated circuit layout 150 may display specific design rules corresponding to the standard specifications, for example, rules such as width or spacing involved in the design rules.
  • the corresponding result can be stored on the integrated circuit design rule layout corresponding to the current test case through the integrated circuit layout design rule file check tool.
  • the golden result 160 corresponding to each standard integrated circuit layout 150 is different.
  • the golden result 160 corresponding to the standard integrated circuit layout 150 is the correct placement of the corresponding device in the standard integrated circuit layout 150, and the golden result 160 corresponding to the standard integrated circuit layout 150 is generated at the same time as the standard integrated circuit layout 150 is generated. .
  • the golden result 160 corresponding to each standard integrated circuit layout 150 can be different, or the result within a specified error range can be used as the golden result 160, and the golden result 160 corresponding to each standard integrated circuit layout 150 can also be the same.
  • the intelligent detection analysis engine 130 is also used to generate a detection report 170, and the detection report 170 contains information for determining whether the target integrated circuit layout design rule file 140 is correct.
  • the test report 170 is the result of the test and analysis of the target integrated circuit layout design rule file 140 based on the standard integrated circuit layout 150.
  • the test report 170 can reflect whether each design rule in the target integrated circuit layout design rule file 140 is consistent with the layout design rule.
  • the design rules defined in the manual are consistent.
  • the test report 170 includes test results obtained based on the standard specification test case library corresponding to each standard specification, that is to say, the standard specification test case library contains both positive specification test cases and negative specification test cases.
  • the test report 170 includes test results obtained from test cases based on positive specifications and test results obtained from test cases based on negative specifications.
  • the development engineer of the layout design rule check file needs to carefully analyze the test cases reporting errors in the test report 170, that is, to see whether the test cases reporting errors are positive or negative specifications.
  • the intelligent library building engine 110 is not updated;
  • the intelligent library building engine 110 is updated.
  • the first type of error information of the standard specification can be that the detection result obtained by the test case based on the positive specification shows correct, and the detection result obtained by the test case based on the negative specification shows an error, then the target integrated circuit layout design rule file The design rules corresponding to 140 are modified without the need to update the intelligent library engine 110.
  • the second type of error information of the standard specification can be that the detection result obtained by the test case based on the positive specification shows an error, and the detection result obtained by the test case based on the negative specification shows an error, and the current test case library may not include the current
  • the layout engineer needs to be notified to use the layout corresponding to the current target integrated circuit layout design rule file 140 as a new test case and update it to the intelligent library engine 110 in time to adapt to the unappeared layout design rule check file.
  • the detection result obtained by the test case based on the positive specification is displayed correctly, and the detection result obtained by the test case based on the negative specification is displayed correctly, it can indicate that the current target integrated circuit layout design rule file 140 is correct. No need to make any changes; when the test result obtained by the test case based on the positive specification shows correct, and the test result obtained by the test case based on the negative specification shows an error, it can also indicate that the current target integrated circuit layout design rule file 140 is correct , You don’t need to make any changes.
  • FIG. 5 is a schematic diagram of a detection report 170 generated by the intelligent detection analysis engine 130 provided by an embodiment of the present application.
  • Rule represents the design rules contained in the target integrated circuit layout design rule file 140
  • Bad pattern represents Analyze and detect test cases based on negative specifications, and display the test results corresponding to test cases based on negative specifications.
  • Good pattern means that test cases based on positive specifications are analyzed and tested, and test results are obtained corresponding to test cases based on positive specifications. To display.
  • Rule A corresponds to the test result obtained by the test case based on the positive specification, and the test result obtained by the test case based on the negative specification is correct, that is, the result displayed by the Good pattern corresponds to pass, and the result displayed by Bad pattern corresponds to pass , It can be explained that the current target integrated circuit layout design rule file 140 is correct and does not need to be modified; Rule B corresponds to the test result obtained from the test case based on the negative specification, and the test result is obtained based on the test case of the positive specification.
  • the detection result shows an error, that is, the result displayed by the Good pattern corresponds to fail, and the result displayed by Bad pattern corresponds to pass, and the design rules corresponding to the target integrated circuit layout design rule file 140 are directly modified, without the need to update the intelligent library engine 110;
  • Rule C corresponds to the test result obtained by the test case based on the positive specification shows an error, and the test result obtained by the test case based on the negative specification shows an error, that is, the result displayed by the Good pattern corresponds to fail, and the result displayed by the Bad pattern corresponds to If it is fail, it is updated to the intelligent library engine 110 in time to adapt to the layout design rule check file that has not appeared;
  • Rule M corresponds to the test result obtained by the test case based on the positive specification, and the test case based on the negative specification is obtained
  • the detection result of is incorrect, that is, the result displayed by the Good pattern corresponds to pass, and the result displayed by Bad pattern corresponds to fail. It can also indicate that the current target integrated circuit layout design rule file 140 is correct, and
  • the updated intelligent library building engine 110 is used to check the target integrated circuit layout design rule file 140 and generate a target detection report 170, which does not contain the second type of error information.
  • the target integrated circuit layout design rule file 140 is detected and analyzed by the intelligent detection and analysis engine 130 to obtain the target detection report 170. At this time, the target detection report 170 no longer contains The second type of error message.
  • FIG. 6 is a schematic diagram of a flow chart for checking the layout design rules of an integrated circuit provided by an embodiment of the present application. See FIG.
  • the test case database generates a standard integrated circuit layout 150; the intelligent detection and analysis engine 130 detects and analyzes the target integrated circuit layout design rule file 140 according to the standard integrated circuit layout 150.
  • the integrated circuit layout design rule check tool provided by the embodiment of this application uses a large number of test cases to automatically perform rapid and accurate check on the integrated circuit layout design rule check file, and can record and trace all physical verification problems in the process through the test case database In order to confirm that the integrated circuit layout design rule check file used by the layout engineer is correct, in order to obtain accurate design rule check results, and ultimately improve the chip manufacturing yield and save costs.
  • FIG. 7 is a schematic diagram of the consistency percentage between the integrated circuit layout design rule inspection document and the integrated circuit layout design inspection manual provided by the embodiment of the application. See FIG. 7, the abscissa indicates that the integrated circuit layout design rule inspection document passes the integrated circuit layout design rule. The number of inspection tool runs. With the continuous accumulation of the test case library, when the number of runs of the integrated circuit layout design rule check tool is increased, the layout design rules in the integrated circuit layout design rule check file can be in the integrated circuit layout design rule manual. The defined design rules tend to be consistent, and ultimately improve the chip manufacturing yield.
  • FIG. 8 is a schematic flowchart of a method for checking an integrated circuit layout design rule file according to an embodiment of the application. This embodiment is applicable to the case of performing reliability analysis on the layout design rule check file. The method of this embodiment specifically includes:
  • S110 Generate a test case database according to the intelligent database construction engine 110.
  • the intelligent database construction engine 110 generates multiple test case databases through the test case intelligent database construction algorithm, and each test case database corresponds to a design rule.
  • the control intelligent placement engine 120 uses the test case intelligent placement algorithm to generate a standard integrated circuit layout 150 based on the test case database.
  • Multiple test case databases correspond to multiple standard integrated circuit layouts 150, and multiple standard integrated circuit layouts 150 correspond to each Design rules corresponding to a test case database.
  • S130 Provide the target integrated circuit layout design rule file 140 to the intelligent detection and analysis engine 130, and control the intelligent detection analysis engine 130 to detect and analyze the target integrated circuit layout design rule file 140 according to the standard integrated circuit layout 150.
  • the intelligent detection and analysis engine 130 performs detection and analysis on the target integrated circuit layout design rule file 140 according to the standard integrated circuit layout 150 to ensure that the design rules in the target integrated circuit layout design rule file 140 are implemented and designed in the layout design rule manual.
  • the definition of the rules is completely consistent, so as to ensure the follow-up chip function and manufacturing yield.
  • the inspection method further includes: generating the target integrated circuit layout design rule file 140 according to the integrated circuit layout design rule manual formulated by the semiconductor manufacturing plant.
  • the technical solution of the embodiment of the present application generates a test case database according to the intelligent library building engine 110, controls the intelligent placement engine 120 to generate a standard integrated circuit layout according to the test case database, and provides the target integrated circuit layout design rule file 140 to the intelligent detection and analysis engine 130 , And control the intelligent detection and analysis engine 130 to detect and analyze the target integrated circuit layout design rule file 140 according to the standard integrated circuit layout 150.

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Abstract

本申请实施例公开了一种集成电路版图设计规则文件检查工具及检查方法。该集成电路版图设计规则文件检查工具（100）包括：智能建库引擎（110），用于生成测试用例数据库；智能摆放引擎（120），用于根据所述测试用例数据库生成标准集成电路版图（150）；智能检测分析引擎（130），用于根据所述标准集成电路版图（150）对目标集成电路版图设计规则文件（140）进行检测分析。

Description

集成电路版图设计规则文件检查工具及检查方法
交叉引用
本申请引用于2020年6月9日递交的名称为“集成电路版图设计规则文件检查工具及检查方法”的第202010517448.6号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及半导体集成电路技术领域，尤其涉及一种集成电路版图设计规则文件检查工具及检查方法。
背景技术
在集成电路制造中，晶圆工厂需要根据不同的工艺参数制定出满足芯片制造良率的同一工艺层及不同工艺层之间的几何尺寸约束，这些几何尺寸约束的集合就是版图设计规则手册(Design Rule Manual，简称DRM)。开发工程师负责把DRM中的每一条约束实现在版图设计规则检查文件(DRC rule deck)中，版图工程师拿到DRC rule deck后，需要使用对所设计的版图做版图设计规则检查(Design Rule Check，简称DRC)。
版图设计规则检查(DRC)是随着半导体晶体管电路设计一同产生的，无论是设计单个晶体管，还是复杂的片上系统(System on Chip，简称SOC)，都需要进行设计规则检查，以确保版图设计是工艺可靠的，能够顺利出产。图1是现有技术提供的集成电路版图设计规则检查的流程示意图，参见图1，目前，版图是通过版图工程师人工手动进行设计规则检查，以实现找出版图中因违反设计规则而引起的所有潜在短路、断路或其它不良效应的错误。如果版图工程 师没有发现这些物理验证错误，则导致芯片在生产后期才发现版图是不符合工艺制造要求的，将会极大影响芯片的后续生产制造，严重的甚至会使工厂生产的芯片无法使用，最终造成巨大的经济损失。
发明内容
本申请实施例提供一种集成电路版图设计规则文件检查工具及检查方法，以实现保证设计规则检查文件与设计规则手册中定义的设计规则的一致，提高芯片制造良率。
第一方面，本申请实施例提供了一种集成电路版图设计规则文件检查工具，该检查工具包括：
智能建库引擎，用于生成测试用例数据库；
智能摆放引擎，用于根据测试用例数据库生成标准集成电路版图；
智能检测分析引擎，用于根据标准集成电路版图对目标集成电路版图设计规则文件进行检测分析。
进一步的，目标集成电路版图设计规则文件包含集成电路版图设计规则的多条标准规格，每一条标准规格对应建立一个标准规格测试用例库。
进一步的，标准规格包括正向规格和负向规格。
进一步的，标准规格测试用例库用于生成多个标准集成电路版图，标准规格测试用例库设置于智能建库引擎中。
进一步的，每个标准集成电路版图对应的黄金结果不同。
进一步的，智能检测分析引擎还用于生成检测报告，检测报告包含判断目标集成电路版图设计规则文件正确与否的信息。
进一步的，如果检测报告包含标准规格的第一类错误信息，则不更新智 能建库引擎；
如果检测报告包含标准规格的第二类错误信息，则更新智能建库引擎。
进一步的，更新后的智能建库引擎用于对目标集成电路版图设计规则文件进行检查，生成目标检测报告，目标检测报告不包含第二类错误信息。
第二方面，本申请实施例还提供了一种集成电路版图设计规则文件检查方法，应用于本申请第一方面实施例的集成电路版图设计规则文件检查工具，该检查方法包括：
根据智能建库引擎生成测试用例数据库；
控制智能摆放引擎根据测试用例数据库生成标准集成电路版图；
向智能检测分析引擎提供目标集成电路版图设计规则文件，并控制智能检测分析引擎根据标准集成电路版图对目标集成电路版图设计规则文件进行检测分析。
进一步的，检查方法还包括：
根据半导体制造工厂制定的集成电路版图设计规则手册生成目标集成电路版图设计规则文件。
本申请实施例的技术方案，该集成电路版图设计规则文件检查工具包括：智能建库引擎，用于生成测试用例数据库；智能摆放引擎，用于根据测试用例数据库生成标准集成电路版图；智能检测分析引擎，用于根据标准集成电路版图对目标集成电路版图设计规则文件进行检测分析。解决了现有技术中版图仅是通过版图工程师人工手动进行设计规则检查，可能导致的物理验证错误未被发现，从而影响芯片后续生产制造甚至芯片无法使用，最终造成巨大经济损失的问题，以实现保证设计规则检查文件与设计规则手册中定义的设计规则的一 致，提高芯片制造良率。
附图说明
图1是现有技术提供的集成电路版图设计规则检查的流程示意图；
图2是本申请实施例提供的一种集成电路版图设计规则文件检查工具的结构示意图；
图3是本申请实施例提供的一种智能建库引擎生成测试用例数据库的流程示意图；
图4是本申请实施例提供的智能摆放引擎生成标准集成电路版图的示意图；
图5是本申请实施例提供的一种智能检测分析引擎生成的检测报告的示意图；
图6是本申请实施例提供的一种集成电路版图设计规则检查的流程示意图；
图7是本申请实施例提供的集成电路版图设计规则检查文件与集成电路版图设计检查手册一致百分比的示意图；
图8是本申请实施例提供的一种集成电路版图设计规则文件检查方法的流程示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面结合附图对本申请具体实施例作进一步的详细描述。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。
另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的 部分而非全部内容。在更加详细地讨论示例性实施例之前应当提到的是，一些示例性实施例被描述成作为流程图描绘的处理或方法。虽然流程图将各项操作(或步骤)描述成顺序的处理，但是其中的许多操作可以被并行地、并发地或者同时实施。此外，各项操作的顺序可以被重新安排。当其操作完成时处理可以被终止，但是还可以具有未包括在附图中的附加步骤。处理可以对应于方法、函数、规程、子例程、子程序等等。
图2为本申请实施例提供的一种集成电路版图设计规则文件检查工具的结构示意图，本实施例可适用于对版图设计规则检查文件做可靠性分析的情况，该集成电路版图设计规则文件检查工具100的结构具体包括如下：
智能建库引擎110，用于生成测试用例数据库；
智能摆放引擎120，用于根据测试用例数据库生成标准集成电路版图150；
智能检测分析引擎130，用于根据标准集成电路版图150对目标集成电路版图设计规则文件140进行检测分析。
其中，测试用例数据库包括多个测试用例，每个测试用例可以但不限于包括多条设计规则。
智能建库引擎110通过测试用例智能建库算法生成多个测试用例数据库，每个测试用例数据库对应一条设计规则。
示例性的，图3是本申请实施例提供的一种智能建库引擎110生成测试用例数据库的流程示意图，参见图3，依据设计规则的不同类型分为设计规则A、设计规则B、设计规则C……设计规则M，智能建库引擎110通过测试用例智能建库算法为每条设计规则建立一个测试用例数据库，分别对应有设计规则A的测试用例数据库、设计规则B的测试用例数据库、设计规则C的测试用 例数据库……设计规则M的测试用例数据库。
智能摆放引擎120通过测试用例智能摆放算法生成标准集成电路版图150，可以理解的是，多个测试用例数据库对应生成多个标准集成电路版图150，多个标准集成电路版图150分别对应每个测试用例数据库对应的设计规则。
智能检测分析引擎130根据标准集成电路版图150对目标集成电路版图设计规则文件140进行检测分析，以确保目标集成电路版图设计规则文件140中的设计规则的实现与版图设计规则手册中设计规则的定义完全一致，从而保证后续芯片功能和制造良率。
在上述实施例的基础上，目标集成电路版图设计规则文件140包含集成电路版图设计规则的多条标准规格，每一条标准规格对应建立一个标准规格测试用例库。
其中，标准规格即为版图设计中的设计规则。
可以理解的是，目标集成电路版图设计规则文件140中包括集成电路版图设计规则的多条设计规则，每一条设计规则对应建立一个与设计规则对应的标准规格测试用例库。
在上述实施例的基础上，标准规格包括正向规格和负向规格。
其中，正向规格即为符合集成电路版图设计规则的设计规则，负向规格即为不符合集成电路版图设计规则的设计规则。
可以理解的是，每一条标准规格对应建立一个标准规格测试用例库，则每一个标准规格测试用例库中均包含正向规格的测试用例和负向规格的测试用例，正向规则的测试用例和负向规格的测试用例的数量可以相同的，也可以是不同的，具体标准规格测试用例库中的测试用例数量可以根据本领域技术人员 根据实际需求进行选择设置，本实施例对此不作任何限制。
示例性的，继续参见图3，每个标准规格建立的测试用例数据库包含多个测试用例，设计规则A的测试用例数据库即为标准规格A对应的测试用例数据库，标准规格A的测试用例数据库包含的多个测试用例分别为A_testpattren1、A_testpattren2、A_testpattren3……A_testpattrenX，A_testpattren1、A_testpattren2、A_testpattren3……A_testpattrenX分别对应不同的测试用例。可以理解的是，A_testpattren1可以为正向规格的测试用例，也可以为负向规格的测试用例，同理，A_testpattrenX可以为正向规格的测试用例，也可以为负向规格的测试用例，本实施例对每个测试用例对应的规格类型不作任何限制。
同理，设计规则B的测试用例数据库即为标准规格B对应的测试用例数据库，标准规格A的测试用例数据库包含的多个测试用例分别为B_testpattren1、B_testpattren2、B_testpattren3……B_testpattrenX，B_testpattren1、B_testpattren2、B_testpattren3……B_testpattrenX分别对应不同的测试用例。可以理解的是，B_testpattren1可以为正向规格的测试用例，也可以为负向规格的测试用例，同理，B_testpattrenX可以为正向规格的测试用例，也可以为负向规格的测试用例。
设计规则M的测试用例数据库即为标准规格M对应的测试用例数据库，标准规格A的测试用例数据库包含的多个测试用例分别为M_testpattren1、M_testpattren2、M_testpattren3……M_testpattrenX，M_testpattren1、M_testpattren2、M_testpattren3……M_testpattrenX分别对应不同的测试用例。可以理解的是，M_testpattren1可以为正向规格的测试用例，也可以为负向规格的测试用例，同理，M_testpattrenX可以为正向规格的测试用例，也可以为负向规格的测试用例。
可以理解的是，每个标准规格对应的测试用例库可以包含相同数量的测 试用例，也可以包含不同数量的测试用例，即每个测试用例库中对应的X可以为相同的值，也可以为不同的值。
在上述实施例的基础上，标准规格测试用例库用于生成多个标准集成电路版图150，标准规格测试用例库设置于智能建库引擎110中。
其中，多个标准集成电路版图150包括正向规格的标准集成电路版图和负向规格的标准集成电路版图。
每一条设计规则对应建立一个与设计规则对应的标准规格测试用例库，每一条设计规则对应的标准规格测试用例库中均包含正向规格的标准集成电路版图和负向规格的标准集成电路版图。
具体的，智能摆放引擎120通过测试用例智能摆放算法将标准规格对应的所有测试用例做智能摆放，生成多个标准集成电路版图150，标准集成电路版图150可以展示所包含器件之间的设计规则。
示例性的，图4是本申请实施例提供的智能摆放引擎120生成标准集成电路版图150的示意图，参见图4，每一条标准规格对应的每一个测试用例数据库中包含的多个测试用例均对应生成一个标准集成电路版图150，可以理解的是，在一条标准规格对应的测试用例数据库中的所有测试用例对应的标准集成电路版图150包括：正向规格的测试用例对应的标准集成电路版图，以及负向规格的测试用例对应的标准集成电路版图。
继续参见图3和图4，图3中的设计规则A的测试用例数据库包含的多个测试用例A_testpattren1、A_testpattren2、A_testpattren3、A_testpattren4、A_testpattren5……A_testpattrenX分别对应生成图4中的标准集成电路版图150，则在图4中，设计规则A的测试用例数据库中测试用例对应的标准集成电路版 图150分别为A_testpattren1、A_testpattren2、A_testpattren3、A_testpattren4、A_testpattren5……A_testpattrenX，以表示与测试用例对应的标准集成电路版图150。
同理，图3中的设计规则B的测试用例数据库包含的多个测试用例B_testpattren1、B_testpattren2、B_testpattren3、B_testpattren4、B_testpattren5……BtestpattrenX，分别对应生成图4中的标准集成电路版图150分别为B_testpattren1、B_testpattren2、B_testpattren3、B_testpattren4、B_testpattren5……B_testpattrenX，以表示与测试用例对应的标准集成电路版图150。
图3中的设计规则M的测试用例数据库包含的多个测试用例M_testpattren1、M_testpattren2、M_testpattren3、M_testpattren4、M_testpattren5……M_testpattrenX，分别对应生成图4中的标准集成电路版图150分别为M_testpattren1、M_testpattren2、M_testpattren3、M_testpattren4、M_testpattren5……M_testpattrenX，以表示与测试用例对应的标准集成电路版图150。
需要说明的是，在生成图4所示的标准集成电路版图150后，可以对每个标准规格的测试用例版图进行放大或缩小或旋转或镜像等操作，即可以对M_testpattren1、M_testpattren2、M_testpattren3、M_testpattren4、M_testpattren5……M_testpattrenX中每个标准集成电路版图150通过放大或缩小或旋转或镜像等操作再生成新的标准集成电路版图150。
可选的，依据工艺设定，标准集成电路版图150可以展示对应标准规格的具体设计规则，例如，设计规则中涉及到的宽度或间距等规则。
需要说明的是，当测试用例中存在对应的设计规则的物理验证错误，可 以通过集成电路版图设计规则文件检查工具将对应的结果存放至当前测试用例对应的集成电路设计规则版图上。
在上述实施例的基础上，每个标准集成电路版图150对应的黄金结果160不同。
其中，标准集成电路版图150对应的黄金结果160即为标准集成电路版图150中对应器件的正确摆放位置，标准集成电路版图150对应的黄金结果160是在生成标准集成电路版图150的同时生成的。
每个标准集成电路版图150对应的黄金结果160可以是不同的，也可以为在指定误差范围内的结果作为黄金结果160，则每个标准集成电路版图150对应的黄金结果160也是可以相同的。
继续参见图2，在上述实施例的基础上，智能检测分析引擎130还用于生成检测报告170，检测报告170包含判断目标集成电路版图设计规则文件140正确与否的信息。
其中，检测报告170为基于标准集成电路版图150对目标集成电路版图设计规则文件140进行检测分析的结果，检测报告170可以反映出目标集成电路版图设计规则文件140中各个设计规则是否与版图设计规则手册中定义的设计规则一致。
检测报告170中包括基于每一条标准规格对应的标准规格测试用例库得到的检测结果，也就是说，标准规格测试用例库中均包含正向规格的测试用例和负向规格的测试用例，检测报告170中包括基于正向规格的测试用例得到的检测结果，以及基于负向规格的测试用例得到的检测结果。
需要说明的是，在本实施例中，版图设计规则检查文件的开发工程师需 要认真分析检测报告170中报告错误的测试用例，即看报告错误的测试用例是正向规格的还是负向规格的。
在上述实施例的基础上，如果检测报告170包含标准规格的第一类错误信息，则不更新智能建库引擎110；
如果检测报告170包含标准规格的第二类错误信息，则更新智能建库引擎110。
其中，标准规格的第一类错误信息可以为基于正向规格的测试用例得到的检测结果显示正确，基于负向规格的测试用例得到的检测结果显示错误，则直接对目标集成电路版图设计规则文件140对应的设计规则进行修改，而不需要更新智能建库引擎110。
标准规格的第二类错误信息可以为基于正向规格的测试用例得到的检测结果显示错误，基于负向规格的测试用例得到的检测结果显示错误，则当前测试用例库中可能并不包括当前的测试用例版图，需要通知版图工程师将当前目标集成电路版图设计规则文件140对应的版图作为新的测试用例，及时更新至智能建库引擎110，以适应未出现的版图设计规则检查文件。
需要说明的是，当基于正向规格的测试用例得到的检测结果显示正确，基于负向规格的测试用例得到的检测结果显示正确，则可以说明当前目标集成电路版图设计规则文件140是正确的，不需要进行任何改动；当基于正向规格的测试用例得到的检测结果显示正确，基于负向规格的测试用例得到的检测结果显示错误，亦可以说明当前目标集成电路版图设计规则文件140是正确的，则不需要进行任何改动。
示例性的，图5是本申请实施例提供的一种智能检测分析引擎130生成 的检测报告170的示意图，参见图5，Rule表示目标集成电路版图设计规则文件140包含的设计规则，Bad pattern表示基于负向规格的测试用例进行分析检测，对应基于负向规格的测试用例得到检测结果进行显示，Good pattern表示基于正向规格的测试用例进行分析检测，对应基于正向规格的测试用例得到检测结果进行显示。
Rule A对应于基于正向规格的测试用例得到的检测结果显示正确，基于负向规格的测试用例得到的检测结果显示正确，即Good pattern显示的结果对应为pass，Bad pattern显示的结果对应为pass，则可以说明当前目标集成电路版图设计规则文件140是正确的，不需要进行任何改动；Rule B对应于基于负向规格的测试用例得到的检测结果显示正确，基于正向规格的测试用例得到的检测结果显示错误，即Good pattern显示的结果对应为fail，Bad pattern显示的结果对应为pass，则直接对目标集成电路版图设计规则文件140对应的设计规则进行修改，而不需要更新智能建库引擎110；Rule C对应于基于正向规格的测试用例得到的检测结果显示错误，基于负向规格的测试用例得到的检测结果显示错误，即Good pattern显示的结果对应为fail，Bad pattern显示的结果对应为fail，则及时更新至智能建库引擎110，以适应未出现的版图设计规则检查文件；Rule M对应于基于正向规格的测试用例得到的检测结果显示正确，基于负向规格的测试用例得到的检测结果显示错误，即Good pattern显示的结果对应为pass，Bad pattern显示的结果对应为fail，亦可以说明当前目标集成电路版图设计规则文件140是正确的，则不需要进行任何改动。
在上述实施例的基础上，更新后的智能建库引擎110用于对目标集成电路版图设计规则文件140进行检查，生成目标检测报告170，目标检测报告170 不包含第二类错误信息。
可以理解的是，在更新智能建库引擎110后，则目标集成电路版图设计规则文件140通过智能检测分析引擎130进行检测分析后得到的目标检测报告170，此时目标检测报告170中不再包含第二类错误信息。
图6是本申请实施例提供的一种集成电路版图设计规则检查的流程示意图，参见图6，本申请实施例的技术方案，通过智能建库引擎110生成测试用例数据库；智能摆放引擎120根据测试用例数据库生成标准集成电路版图150；智能检测分析引擎130根据标准集成电路版图150对目标集成电路版图设计规则文件140进行检测分析。本申请实施例提供的集成电路版图设计规则检查工具，利用海量测试用例自动对集成电路版图设计规则检查文件进行快速、精准的检查，并可以通过测试用例数据库记录和追溯工艺上所有的物理验证问题，以确定版图工程师所使用的集成电路版图设计规则检查文件正确无误，以得到准确的设计规则检查结果，最终提高芯片制造良率，节约成本。
此外，图7是本申请实施例提供的集成电路版图设计规则检查文件与集成电路版图设计检查手册一致百分比的示意图，参见图7，横坐标表示集成电路版图设计规则检查文件通过集成电路版图设计规则检查工具运行次数，随着测试用例库的持续积累，当加大集成电路版图设计规则检查工具的运行次数，可使集成电路版图设计规则检查文件中的版图设计规则与集成电路版图设计规则手册中定义的设计规则趋于一致，最终提高芯片制造良率。
图8为本申请实施例提供的一种集成电路版图设计规则文件检查方法的流程示意图。本实施例可适用于对版图设计规则检查文件做可靠性分析的情况，本实施例的方法具体包括：
S110、根据智能建库引擎110生成测试用例数据库。
具体的，智能建库引擎110通过测试用例智能建库算法生成多个测试用例数据库，每个测试用例数据库对应一条设计规则。
S120、控制智能摆放引擎120根据测试用例数据库生成标准集成电路版图150。
控制智能摆放引擎120通过测试用例智能摆放算法，根据测试用例数据库生成标准集成电路版图150，多个测试用例数据库对应生成多个标准集成电路版图150，多个标准集成电路版图150分别对应每个测试用例数据库对应的设计规则。
S130、向智能检测分析引擎130提供目标集成电路版图设计规则文件140，并控制智能检测分析引擎130根据标准集成电路版图150对目标集成电路版图设计规则文件140进行检测分析。
具体的，智能检测分析引擎130根据标准集成电路版图150对目标集成电路版图设计规则文件140进行检测分析，以确保目标集成电路版图设计规则文件140中的设计规则的实现与版图设计规则手册中设计规则的定义完全一致，从而保证后续芯片功能和制造良率。
进一步的，在上述实施例的基础上，检查方法还包括：根据半导体制造工厂制定的集成电路版图设计规则手册生成目标集成电路版图设计规则文件140。
本申请实施例的技术方案，根据智能建库引擎110生成测试用例数据库，控制智能摆放引擎120根据测试用例数据库生成标准集成电路版图，向智能检测分析引擎130提供目标集成电路版图设计规则文件140，并控制智能检测分 析引擎130根据标准集成电路版图150对目标集成电路版图设计规则文件140进行检测分析。解决了现有技术中人工检查可能导致的不可避免的错误，通过集成电路版图设计规则文件检查工具确保在集成电路版图设计规则文件中实现的设计规则与集成电路版图设计规则手册中定义的设计规则的一致性，同时保证集成电路版图设计规则文件的开发质量，以在保证集成电路版图设计规则文件的稳定、质量可靠性及提高项目的制造良率上起到了显著的作用。
注意，上述仅为本申请的实施例及所运用技术原理。本领域技术人员会理解，本申请不限于这里的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本申请的保护范围。因此，虽然通过以上实施例对本申请进行了较为详细的说明，但是本申请不仅仅限于以上实施例，在不脱离本申请构思的情况下，还可以包括更多其他等效实施例，而本申请的范围由所附的权利要求范围决定。

Claims (10)

  1. 一种集成电路版图设计规则文件检查工具，其特征在于，包括：
    智能建库引擎，用于生成测试用例数据库；
    智能摆放引擎，用于根据所述测试用例数据库生成标准集成电路版图；
    智能检测分析引擎，用于根据所述标准集成电路版图对目标集成电路版图设计规则文件进行检测分析。
  2. 根据权利要求1所述的检查工具，其特征在于，所述目标集成电路版图设计规则文件包含集成电路版图设计规则的多条标准规格，每一条所述标准规格对应建立一个标准规格测试用例库。
  3. 根据权利要求2所述的检查工具，其特征在于，所述标准规格包括正向规格和负向规格。
  4. 根据权利要求2所述的检查工具，其特征在于，所述标准规格测试用例库用于生成多个所述标准集成电路版图，所述标准规格测试用例库设置于所述智能建库引擎中。
  5. 根据权利要求4所述的检查工具，其特征在于，每个所述标准集成电路版图对应的黄金结果不同。
  6. 根据权利要求1所述的检查工具，其特征在于，所述智能检测分析引擎还用于生成检测报告，所述检测报告包含判断所述目标集成电路版图设计规则文件正确与否的信息。
  7. 根据权利要求2所述的检查工具，其特征在于，如果所述检测报告包含所述标准规格的第一类错误信息，则不更新所述智能建库引擎；
    如果所述检测报告包含所述标准规格的第二类错误信息，则更新所述智能建 库引擎。
  8. 根据权利要求7所述的检查工具，其特征在于，更新后的智能建库引擎用于对所述目标集成电路版图设计规则文件进行检查，生成目标检测报告，所述目标检测报告不包含所述第二类错误信息。
  9. 一种集成电路版图设计规则文件检查方法，应用于权利要求1-8任一项所述的集成电路版图设计规则文件检查工具，其特征在于，包括：
    根据智能建库引擎生成测试用例数据库；
    控制智能摆放引擎根据所述测试用例数据库生成标准集成电路版图；
    向智能检测分析引擎提供目标集成电路版图设计规则文件，并控制所述智能检测分析引擎根据所述标准集成电路版图对所述目标集成电路版图设计规则文件进行检测分析。
  10. 根据权利要求9所述的检查方法，其特征在于，所述检查方法还包括：
    根据半导体制造工厂制定的集成电路版图设计规则手册生成所述目标集成电路版图设计规则文件。
PCT/CN2021/094219 2020-06-09 2021-05-17 集成电路版图设计规则文件检查工具及检查方法 WO2021249129A1 (zh)

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