1245914 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種印刷電路板測試技術 可藉由程式模擬測試條件以減少 尤心一種 試系統及方法。守間之印刷電路板測 【先前技術】 印刷電路板(PCB)係於絕緣基板上具有導體配缘之物 =’並依據具體之需求於其上裝載各類電子零件，、夢由導 妾以完成不同之功能。隨著電子㈣曰新 刷電路板構造亦越來越複雜，單層電路板 業已逐y被夕層或增層電路板所替代。在多層印刷 板以及增層印刷電路板上，裝载了極大數目之電子元件， 其目的即用以發揮更多整體功能。 印刷電路板之結構愈複雜則造成印刷電路板品質出現 瑕疵之機率也愈大，且一旦印刷電路板發生故障的話所造 成之影響將會相當廣泛，職是，印刷電路板於製程中之^ 管技術即更顯重要，因此，為確保印刷電路板之出貨品質印 故於出貨前遂必須對印刷電路板進行一完成品測試（fa function test)作業，若於測試過程中檢測得知完成品中存 有不合格之印刷電路板，則該塊印刷電路板將完全作廢。 然，减而易見者，该測試作業針對僅於某一處出現較小問 題之印刷電路板亦判定為不良品而予以排除，遂因此造成 浪費。 是故，爲避免前述先前技術易造成印刷電路板浪費之 5 17965 1245914 2 u it有人提—種解決印刷電^試問題之 該方案係於生產過程中進行工程内檢查，亦即針對 士P刷電路板進行半成品功能測試（s A fu⑽_ _)，藉此及 過程環節中’檢測出印刷電路板所出現的問題， 進而將半成品重新製造，而不致造成浪費。 線，:：方：1=於印刷電路板上並未組設外設的模擬佈 …、觸於生產過程中要進行半成品 檢測均需透過專業技術人員進行繁瑣的測試。此：t: 之賴工作得明利進行，復需增力 ; :=?rr’若將人力以及物力㈣ 之後’若要對不良品進行維修，對於維L=j 吕亦需經過繁_檢測步驟方可準確的針對不良口2而 ’料，若存麵多之不良品，則 (WIP)中之不良品數目過多之狀況出現。再者，羽:寺4 線測試技術亦僅可測試出功能模组内核之白σ之流水 現其它不良品之成因。 良’而無法發 因此，如何解決上述先前技 、 簡單地測試出印刷電路板於生産過程中可能=為準確、 成因，遂爲目前亟待解決之技術問題。 之不良品 【發明内容】 鑒於上述先前技術之缺失，本發明之 供一種印刷電路板測試系統及方法，其η β上目的在於提 試效率並節省生産測試時間。彳/、可提高電路板之測 17965 6 1245914 本毛明之S目的在於提供—種印刷電路板測試系統 及方法，其可準石崔定位不良品之故障位置並可全面性的對， 電路板進行測試，藉以發現更多非功能模組之故障導致印 刷板電路不良的因素。 為達上揭及其他目的，本發明即提供一種印刷板電路 之測試系統及方法。本發明印刷板電路之測試方法，首先， 2將功能模組㈣於—待騎刷電路板上，鋪由該印刷 組°又之連接埠連接該些功能模組，若該電路板需於. ㈣連接時’則藉由該電路板上之介科進行連接；接著，· 设將用於測試該些功能模組之程式儲存於一擴展控制模 处/擴展&制;^組係可依據不同之需要將該些已連接功 的n遞於—模擬外設模組，並同時將相應之連 布線^，而_與賴無關之連接佈線，藉以確保測 乂之可罪性；隨後’令該模擬外設模組依據所接收之不同 =對應模擬不同外設之測試條件。此外，前述之測試用-=復包含模擬測試功能模組時必須輸入之條件編輯，以 、、個部件it行龍，如對單條數據線或訊號線贼，藉 以準確疋位不良品之故障部位。 +本么月印刷電路板測之試系統係至少包含：-待測印 板’其係藉由一介面埠與外部進行連接；一擴展控 自u ’其可依據不同之需要傳遞已連接功能模組的訊 :’並同時將相應之連接佈線打開’而關閉無關之連接佈 、隹保測试之可靠性；一模擬外設模組，係用以模擬 / 包路板之外設條件，以及復數個連接佈線，用以傳 17965 7 1245914 遞各模組間之數位訊號及模擬訊號。 本發明印刷板電路之測試系統及方法，係可解失明 測試技術的諸多缺失，進而高效、準確地測試出印刷=知 板於生産中可能出現不良品之原因。 兒路 【實施方式】 、 以下係藉由特定的具體實施例說明本發明之實於方 式，熟悉此技藝之人士可由本說明書所揭示之内容_易地 瞭解本發明之其他優點與功效。本發明亦可藉由其:不^ 的具體實施例加以施行或應用，本說明書中的各項細節= 可基於不同觀點與應用，在不悖離本發明之精神下 = 種修劍i與變更。 仃口 貫施例： 第1圖為一方塊圖，其顯示應用本發明方法之印刷電 路板10的結構圖。如圖所示，該印刷電路板1〇係為一^ ，過測試系統1進行測試之待測電路板，其具有若干之預 疋區域，該些區域係用以連接各個不同模組之用，且於該 印刷電路板ίο層内已形成圖案化導電層將該些區域電性 連接。該印刷電路板10上復包括一介面埠區u，一功能 模組區12,-擴展控制模組區13以及—模擬外設模組區 14°需特別説明者，該些區域之排佈並不局限於圖示之方 案。该些區域上具備復數個連接佈線（圖式未標註）以提 供將各個外設模組連接於該印刷電路板10上。 第2圖係用以顯示第1圖所示之印刷電路板外接各個 功能模組之後的印刷電路板2G之結構示意圖，如圖所示， 17965 8 1245914 預定之介面埠區π (第1圖）上搭接了一第一介面210以 及一第二介面211 ’預定之功能模組區12 (第1圖）上組 接了 弟功此模組2 2 0以及一弟二功能模組2 21，預定 之擴展控制模組區⑴第1圖）上搭接了-擴展控制模組 23，預定之模擬外設模組區14 (第j圖）上搭接了 一模擬 外设杈組24，此外，於該印刷電路板20上復包括一控制 杈組25 ’該控制模組25係與該印刷電路板2〇上相應之模 組電性連接。需特別説明者，本圖係用以詳細説明本發明 之測試方法及系統之具體設計，而非以此限制各功能組件 之排列及連接狀態，易言之，此些功能組件於實際實施時 均可按實際需求而加以變更。 、 第3圖係將各個模組之間的連線標出，並將各個模組 做-具體界定之主機板結構示意圖，藉以詳細説明本發明 印刷私路板之測試系統及方法，於此，該印刷電路板係為 一主機板30,其上係包含一第一介面31〇，一第二介面 31卜一第一功能模組320, 一第二功能模組321 ;二第2 圖所示之擴展功能模組13於此係具體化為—類BI〇S33， 該模擬外設模組24則具體化為一積體f路晶片34，此外， ::!圖所示之控制模組13具體化為—主機板刪％。 上述各個模組係藉由複數個連接佈線％予以連接，該此連 接佈線36除可位於該主機板30之圖案化導電層亦可為外 設連接線。 包膺丌j馬外 其係用以顯示本發明印刷 於本實施例中，係以第一 第4圖係為一運作流程圖 電路板之測試方法的實行步驟 17965 9 1245914 驟S1， 遂並進 力=模、、且320為預定測試之電路板。首先，執行步 將第功能模組320組裝於該主機板3〇上。接著， 至步驟S2。 =驟S2中，將待測試電路板加人流水線測試隊列 ，3始執行該待測試電路板之流水線測試進程。， 逐並進至步驟S3。 思傻’ BIOS ^驟中，由主機板BI〇S 35發出一組訊號給類 Μ将失」错以通知該類BI0S 33目前正要進行測試之外 »又係為弟—功能模組32q。接著，遂並進至步驟 ，步驟S4中，該類BI〇S33收到由該主機板_5 ^ °K#U ’並發出—組訊號給模擬外設龍電路晶片34。 I1 返後，遂並進至步驟S5。 …於步驟S5中，該模擬外設積體電路晶片34收到發自 ^ BIOS33發出之訊號，並識別出目前測試之外設係為 =功能模組320後，該模擬外設㈣電路晶片Μ即模擬 六弟—功能模組32G進行測試之測試條件，此過程可由儲 =子於該模擬外設積體電路晶片34内部之程式完成，接著， 執行步驟S6。 於步驟S6中，由該類BI〇s 33開啟與第一功能模組 2〇相關之線路’並同時關閉其它無關之連線。最後，執 仃步驟S 7以開始對第一功能模組3 2 〇進行測試。 第5圖k為另—主機板結構示意圖，其係、顯示於前述 义V §4 S6之後，„亥主機板3〇上之連接佈線狀況。由於先 則已將與第一功能模組32G無關之連接佈線關目，故於本 17965 10 1245914 圖^僅標示出相關之連接佈線3 6。如圖所示 1 向類_33發出一謂觀訊號，藉以告知該類 S 33要K之待測電路板係為該第—倾模組32〇 ; 電亥收一 路曰^ 34 ^ RESET_2訊號’該模擬外設積體電 320曰曰之測RESET·2訊號後隨即模擬第—功能模組 〇之収條件’同時，該類則s33則開啟與第一 :=Γ線路，並同時關閉其它無關之連線，俾： 取弟5圖所不之連接狀況。 中儲時需要m訊號，則可由類㈣⑶ 組進行單二路，同時，該程式可編寫成對某個模 定位:早1 卞線路測減，以便能夠對不良部進行更加準確之 |』m局例小]土，兀％不贫明之 :非用於限制本發明。任何熟習此項技藝：人 違背本發明之精神及範缚下 : ：可在 化。ra uu a. 4只知例進行修飾盥 範圍所列。 I如後述之申請專 【圖式簡單説明】 電路板之測試系 統中所使用 弟1圖係顯示本發明印刷 之印刷電路板結構圖； 路板外接各個功 並將各個模組做 处第2圖係顯示於第1圖所示之印刷電 月匕杈組之後的印刷電路板結構示意圖； 第3圖係將各個模組間之連線標出， 17965 11 1245914 一具體界定之主機板結構示意圖； 弟4圖係為^一運作流程圖5其係顯不本發明印刷電路 之板測試方法的運作程序；以及 第5圖係為另一主機板結構之示意圖，其係顯示主機 板上連接佈線之變化態樣。 【主要元件符號說明】 1，Γ 印刷電路板之測試系統 10,20 印刷電路板 30 主機板 11 介面埠區 12 功能模組區 13 擴展控制模組區 14 模擬外設模組區 210.310 第一介面 211.311 第二介面 220,320第一功能模組 221，321第二功能模組 23 擴展控制模組 24 模擬外設模組 25 控制模組1245914 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a printed circuit board test technology. A test system and method can be reduced by simulating test conditions through a program. Mori's printed circuit board test [prior art] The printed circuit board (PCB) is a thing with a conductive edge on an insulating substrate = ', and various electronic parts are loaded on it according to specific needs. Complete different functions. With the new electronic circuit board structure becoming more and more complex, single-layer circuit boards have been gradually replaced by tier or layered circuit boards. Multilayer printed boards and build-up printed circuit boards are loaded with a large number of electronic components, the purpose of which is to perform more overall functions. The more complicated the structure of the printed circuit board, the greater the probability of causing defects in the quality of the printed circuit board. Once the printed circuit board fails, the impact will be quite extensive. It is the responsibility of the printed circuit board in the manufacturing process. Technology is more important. Therefore, in order to ensure the quality of the printed circuit board shipment, it is necessary to perform a fa function test on the printed circuit board before shipment. If the test is completed during the test, it will be completed. If there is a defective printed circuit board in the product, the printed circuit board will be completely obsolete. However, to the extent that it is easy to see, the test operation was ruled out that the printed circuit board with minor problems only in one place was also judged to be defective and was wasted. Therefore, in order to avoid the waste of the printed circuit board caused by the foregoing prior technology, 5 17965 1245914 2 u it was suggested that a solution to the problem of printed electrical testing is to conduct an in-engineering inspection during the production process, that is, to target the P brush. The circuit board is subjected to a semi-finished product functional test (s A fu⑽_ _), so as to detect problems in the printed circuit board during the process and then re-manufacture the semi-finished product without causing waste. Line, ::: Square: 1 = Analog cloth with no peripherals on the printed circuit board…, semi-finished products that need to be inspected in the production process require tedious testing by professional technicians. This: t: It depends on the work to be carried out clearly, and it needs to increase the strength;: =? Rr 'If the manpower and material resources are saved,' If you want to repair the defective products, you must also go through the _ detection steps for the dimension L = j Lu. Accurately target the defective product 2 and if there are many defective products on the surface, there will be too many defective products in (WIP). In addition, the Yu: Temple 4-wire test technology can only test the causes of the white σ of the core of the function module and other defective products. Therefore, how to solve the above-mentioned prior art and simply test that the printed circuit board may be accurate and cause in the production process is a technical problem that needs to be solved at present. Defective Product [Content of the Invention] In view of the lack of the foregoing prior art, the present invention provides a printed circuit board test system and method, the purpose of which is to improve efficiency and save production test time.彳 /, can improve the testing of circuit boards 17965 6 1245914 The purpose of this Maoming S is to provide a printed circuit board testing system and method, which can locate the fault location of defective products and comprehensively check the circuit board. Testing to discover more factors that cause malfunctions of printed circuit boards due to the failure of non-functional modules. In order to achieve the disclosure and other objectives, the present invention provides a test system and method for a printed circuit board. The test method of the printed circuit of the present invention, first, 2 the functional module is placed on the circuit board to be brushed, paved by the printing group ° and the port to connect the functional modules, if the circuit board is needed.时 When connecting, 'it is connected through the media department on the circuit board; then, · The program for testing the functional modules is stored in an expansion control module / extension &system; Different needs to pass the n of the connected work to the analog peripheral module, and at the same time wire the corresponding connection ^, and _ has nothing to do with the connection wiring to ensure the conviction of the test; then ' Make the analog peripheral module according to the difference received = corresponding to the test conditions of different peripherals. In addition, the aforementioned test-= contains the conditions that must be entered when the simulation test function module is edited. It is based on the components, such as a single data line or signal line thief, so as to accurately locate the defective part of the defective product . + The test system for the printed circuit board test this month includes at least:-the test board to be tested 'which is connected to the outside through an interface port; an extended control u' which can transfer the connected functional modules according to different needs The group's message: 'and open the corresponding connection wiring at the same time' and close the irrelevant connection cloth, to ensure the reliability of the test; an analog peripheral module, which is used to simulate / set conditions outside the circuit board, and A plurality of connection wirings are used to transmit digital signals and analog signals between 17965 7 1245914. The test system and method for printed circuit board of the present invention can solve many shortcomings of the blind test technology, and then efficiently and accurately test the reason why the printed board may produce defective products in production. [Embodiment] The following is a description of the practical method of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied by its specific embodiments. The details in this specification = can be based on different perspectives and applications, without departing from the spirit of the present invention = a kind of sword repair and changes . Nakaguchi Example: Figure 1 is a block diagram showing the structure of a printed circuit board 10 to which the method of the present invention is applied. As shown in the figure, the printed circuit board 10 is a circuit board, and the circuit board under test that is tested by the test system 1 has a plurality of pre-defined areas, which are used to connect different modules. A patterned conductive layer has been formed in the printed circuit board layer to electrically connect these areas. The printed circuit board 10 includes an interface port area u, a function module area 12, an expansion control module area 13 and an analog peripheral module area 14 °. If special description is needed, the arrangement and arrangement of these areas Not limited to the scheme shown. These areas are provided with a plurality of connection wirings (not shown in the figure) to provide connection of various peripheral modules to the printed circuit board 10. Fig. 2 is a schematic diagram showing the structure of the printed circuit board 2G after the printed circuit board shown in Fig. 1 is connected with various functional modules. As shown in the figure, 17965 8 1245914 predetermined interface port area π (Fig. 1) A first interface 210 and a second interface 211 are connected to the predetermined function module area 12 (Fig. 1). This module 2 2 0 and a second function module 2 21 are assembled. The planned expansion control module area (Figure 1) is connected to the expansion control module 23, and the planned analog peripheral module area 14 (Figure j) is connected to an analog peripheral group 24. In addition, The printed circuit board 20 further includes a control block group 25 ′. The control module 25 is electrically connected to a corresponding module on the printed circuit board 20. It should be noted that this figure is used to explain the specific design of the test method and system of the present invention in detail, rather than to limit the arrangement and connection status of the functional components. In other words, these functional components are all implemented in actual implementation. It can be changed according to actual needs. Figure 3 shows the connection between each module, and each module is a schematic diagram of the structure of the motherboard specifically defined to explain the test system and method of printed circuit boards of the present invention in detail. Here, The printed circuit board is a motherboard 30, which includes a first interface 31, a second interface 31, a first function module 320, and a second function module 321; as shown in FIG. 2 The extended function module 13 is embodied here as a class BIOS33, and the analog peripheral module 24 is embodied as an integrated f chip 34. In addition, the control module 13 shown in ::! Reified as: — Motherboard delete%. Each of the above modules is connected by a plurality of connection wirings. The connection wirings 36 may be external connection wires in addition to the patterned conductive layer on the motherboard 30. The package is used to show that the present invention is printed in this embodiment. The first and fourth diagrams are used to implement the test method of the operation flowchart circuit board. Steps 17965 9 1245914 Step S1 = Mode, and 320 is a circuit board scheduled to be tested. First, execute the step of assembling the third functional module 320 on the motherboard 30. Then, it proceeds to step S2. In step S2, the circuit board to be tested is added to the pipeline test queue, and the pipeline test process of the circuit board to be tested is started at step 3. , Go to step S3 one by one. In the "BIOS" step, the motherboard BIOS 35 sends a set of signals to the class M and will fail "to notify the class that the BIOS 33 is currently undergoing testing» It is also a brother—function module 32q. Then, it proceeds to step. In step S4, this type of BIOS33 receives the motherboard _5 ^ ° K # U 'and sends out a group signal to the analog peripheral circuit chip 34. After I1 returns, it proceeds to step S5. … In step S5, the analog peripheral integrated circuit chip 34 receives a signal sent from ^ BIOS33, and recognizes that the current test device is set to = function module 320, and the analog peripheral circuit chip M That is, the test conditions for the simulation of the sixth brother-function module 32G are tested. This process can be completed by a program stored in the analog peripheral integrated circuit chip 34. Then, step S6 is performed. In step S6, this type of BI0s 33 opens the lines related to the first function module 20 and closes other unrelated lines at the same time. Finally, step S7 is executed to start the test of the first functional module 3 2 0. Figure 5k is another—a schematic diagram of the main board structure, which is shown in the above-mentioned meaning V §4 S6, “the connection and wiring conditions on the main board 30. Since the first function will have nothing to do with the first function module 32G The connection wiring is closed, so in this 17965 10 1245914 Figure ^ only shows the relevant connection wiring 3 6. As shown in the figure 1 sends a so-called observation signal to class _33 to inform the class S 33 that K is to be tested The circuit board is the first inclination module 32; the electric signal is received all the way ^ 34 ^ RESET_2 signal 'The analog peripheral integrated circuit 320 is called the test RESET · 2 signal, and then the first-functional module 0 is simulated. At the same time, this class will open the s33 and the first: = Γ line, and close other irrelevant connections at the same time. ㈣⑶ The group performs single and two-way. At the same time, the program can be written to locate a certain module: 1 早 As early as possible, the line can be measured and subtracted, so that the defective part can be more accurate. : Not intended to limit the invention. Anyone skilled in the art: people violate the spirit and scope of the invention Bottom: ： Can be used. Ra uu a. 4 known examples are listed in the scope of modification. I as shown in the application below [Simplified illustration of the diagram] The diagram used in the test system of the circuit board shows the printing of the present invention The structure of the printed circuit board; the circuit board is connected with each function and each module is used. Figure 2 is a schematic diagram of the structure of the printed circuit board after the printed electric dagger set shown in Figure 1; Figure 3 is The connection between each module is marked as 17965 11 1245914 a specific definition of the structure of the motherboard; Figure 4 is a flow chart of operation 5 which shows the operation procedure of the printed circuit board test method of the present invention; and Figure 5 is a schematic diagram of the structure of another motherboard, which shows the changes of the connection and wiring on the motherboard. [Description of the main component symbols] 1. Γ Test system for printed circuit boards 10, 20 Printed circuit boards 30 Main boards 11 Interface port area 12 Function module area 13 Extended control module area 14 Analog peripheral module area 210.310 First interface 211.111 Second interface 220, 320 First function module 221, 321 Second function module 23 Extended control module 24 analog peripherals module control module 25
33 類 BIOS 34 模擬外設積體電路晶片Type 33 BIOS 34 Analog Peripheral Integrated Circuit Chip
35 主機板BIOS 36 連接佈線 12 1796535 Motherboard BIOS 36 Connection wiring 12 17965