WO2023226084A1 - 信号线检查方法及设备 - Google Patents

信号线检查方法及设备 Download PDF

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Publication number
WO2023226084A1
WO2023226084A1 PCT/CN2022/097526 CN2022097526W WO2023226084A1 WO 2023226084 A1 WO2023226084 A1 WO 2023226084A1 CN 2022097526 W CN2022097526 W CN 2022097526W WO 2023226084 A1 WO2023226084 A1 WO 2023226084A1
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Prior art keywords
signal line
target signal
layout
circuit
label
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PCT/CN2022/097526
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English (en)
French (fr)
Inventor
闵敏
姜伟
白黎
陈川江
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长鑫存储技术有限公司
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Priority to US17/898,727 priority Critical patent/US20230385516A1/en
Publication of WO2023226084A1 publication Critical patent/WO2023226084A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/06—Structured ASICs

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a signal line inspection method and equipment.
  • circuit layout design is a key link between circuit design and process manufacturing.
  • layout engineers are also required to check the key signal lines in the circuit layout to prevent signal crosstalk.
  • Embodiments of the present disclosure provide a signal line inspection method and equipment, which can reduce the inspection complexity of key signal lines in a circuit layout and improve the design efficiency of the circuit layout.
  • an embodiment of the present disclosure provides a signal line inspection method, which method includes:
  • a first label is added to the position of the target signal line in the circuit layout, and the first label is used to indicate the The target signal line does not meet the layout design rules.
  • an embodiment of the present disclosure provides a signal line inspection device, which includes:
  • An acquisition module is used to obtain custom design information of the target signal line in the circuit schematic diagram, and generate layout design rules corresponding to the target signal line based on the custom design information;
  • a checking module used to check whether the target signal line in the circuit layout corresponding to the circuit schematic diagram meets the layout design rules
  • a first marking module configured to add a first label to the position of the target signal line in the circuit layout when the target signal line in the circuit layout does not meet the layout design rules.
  • a label is used to indicate that the target signal line does not satisfy the layout design rule.
  • embodiments of the present disclosure provide an electronic device, including: at least one processor and a memory;
  • the memory stores computer execution instructions
  • the at least one processor executes the computer execution instructions stored in the memory, so that the at least one processor executes the signal line inspection method provided in the first aspect.
  • embodiments of the present disclosure provide a computer-readable storage medium that stores computer-executable instructions.
  • a processor executes the computer-executed instructions, the signal provided in the first aspect is implemented. line inspection method.
  • an embodiment of the present disclosure provides a computer program product, which includes a computer program.
  • the computer program is executed by a processor, the signal line inspection method as provided in the first aspect is implemented.
  • the signal line inspection method and device provided by the embodiments of the present disclosure generate layout design rules based on the custom design information obtained from the circuit schematic diagram, and inspect each target signal line in the circuit layout according to the layout design rules. Tags are added to the target signal lines that meet the layout design rules, which helps layout engineers quickly and accurately locate the target signal lines with design defects. Since the present disclosure does not require layout engineers to manually inspect each key signal line, it can not only effectively reduce the inspection complexity of key signal lines in the circuit layout, greatly shorten the time spent by layout engineers on later inspections, but also ensure the accuracy of the circuit layout design. Accuracy, improving circuit layout design efficiency.
  • Figure 1 is a schematic step flow diagram of a signal line inspection method provided in an embodiment of the present disclosure
  • Figure 2 is a schematic flowchart 2 of the steps of a signal line inspection method provided in an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of a circuit layout inspection result provided in an embodiment of the present disclosure.
  • Figure 4 is a schematic flowchart three of steps of a signal line inspection method provided in an embodiment of the present disclosure
  • Figure 5 is a schematic diagram of a circuit layout with custom design information added in an embodiment of the present disclosure
  • Figure 6 is a schematic diagram of a program module of a signal line inspection device provided in an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present disclosure.
  • module refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic or combination of hardware or/and software code capable of performing the functions associated with that element .
  • the embodiments of the present disclosure can be applied in the semiconductor field, for example, in the semiconductor layout design inspection process.
  • the above-mentioned circuit schematic diagram can also be called an electronic circuit diagram or circuit diagram. It is a diagram drawn with agreed symbols to represent the circuit structure. It can reflect the electrical connection and working principle of each component in the electronic product. It is usually applied In designing and analyzing circuits. When analyzing a circuit, you can understand the working principle of the circuit by identifying the various circuit component symbols drawn on the circuit schematic diagram and the connections between them.
  • the circuit schematic diagram may be composed of component symbols, signal lines, nodes, etc.
  • the component symbol represents the component in the actual circuit. Its shape is not necessarily similar to the actual component, or even completely different, but it generally indicates the characteristics of the component, and the number of pins remains the same as the actual component. consistent.
  • the signal line represents the wire in the actual circuit. Although it is a wire in the circuit schematic diagram, it is often not a wire in commonly used chips or printed circuit boards, but metal wires of various shapes and with a certain width. Nodes represent the mutual connection relationships between several component pins or several signal lines. All component pins and signal lines connected to the node, regardless of the number, are conductive.
  • the reasons for errors in circuit logic due to crosstalk are mainly reflected in the following aspects: the length of the signal line is too long, resulting in a significant increase in near-end and far-end voltage drops; the spacing between signal lines is too close, resulting in too strong coupling ; The rising edge of the signal is blocked; the ratio of the coupling capacitance between two adjacent signal lines to the equivalent capacitance between the signal line and the substrate increases, etc.
  • methods to reduce noise in the circuit layout include: adding guard rings, reducing local resistance, and reducing substrate noise; reducing the resistance of signal lines; increasing the spacing of signal lines; using power lines and ground wires as shielding lines; Use signal lines with low impact as shielded lines, and keep signal lines with high noise away from key signal lines, etc.
  • circuit engineers will check these key signal lines through post-simulation, and feedback the simulation results to the layout engineer for modification. If the circuit is relatively large, the simulation will take a long time, and such repetitions will inevitably affect the development process. . Therefore, generally after the circuit layout is produced, the layout engineer usually checks whether the key signal lines meet the empirical values or the requirements put forward by the circuit engineer.
  • embodiments of the present disclosure provide a signal line inspection method, which generates layout design rules based on customized design information of key signal lines obtained in the circuit schematic diagram, and performs layout design rules according to the layout design rules. Check each key signal line in the circuit layout and add labels to the key signal lines that do not meet the layout design rules. This helps layout engineers quickly and accurately locate key signal lines with design defects and greatly reduces the layout engineer's post-inspection costs. time to improve circuit layout design efficiency.
  • the detailed process can refer to the following embodiments.
  • FIG. 1 is a schematic flowchart 1 of a signal line inspection method provided in an embodiment of the present disclosure.
  • the above signal line inspection method includes:
  • Sensitive signal lines are signal lines that are susceptible to interference from noise signals, such as the input of analog-to-digital converters and high-precision comparisons.
  • noise signal lines are signal lines generated by noise sources, such as high-frequency digital circuits, PLLL (Phase Locked Loop, phase-locked loop), etc.
  • the circuit engineer in the process of making the circuit schematic diagram, can use the above-mentioned key signal lines in the circuit schematic diagram as target signal lines, and based on the simulation results and own experience, in the circuit schematic diagram Add custom design information for each target signal line.
  • the custom design information includes the width, surrounding environment, spacing, etc. of the target signal line.
  • the custom design information of the target signal line added in advance in the circuit schematic diagram is obtained, and the layout design rules corresponding to the target signal line are generated based on the custom design information.
  • the above layout design rules include constraints such as the width, surrounding environment, spacing, etc. of each target signal line, such as the minimum value of the width corresponding to each target signal line.
  • a layout design rule check file may be generated based on the layout design rules.
  • only one signal line can be selected as the target signal line, or multiple signal lines can be selected as the target signal line, which is not limited in the embodiment of the present disclosure.
  • the circuit layout can also be called the integrated circuit layout.
  • Circuit layout design is to map the circuit schematic diagram to the physical description level, so that the designed circuit can be mapped to the wafer for production.
  • the circuit layout usually contains relevant physical information such as the device type, device size, relative position between devices, and the connection relationship between each device of the integrated circuit.
  • circuit schematic diagram after the above circuit schematic diagram is designed, its corresponding circuit layout can be generated based on the circuit schematic diagram.
  • the above layout design rule check file can be run on the generated circuit layout to check whether the target signal lines in the circuit layout corresponding to the circuit schematic diagram meet the above layout design rules.
  • the above-mentioned first label is used to indicate that the target signal line does not meet the above-mentioned layout design rules.
  • a first label can be added to the position of the target signal line in the circuit layout, and the first label is used to Indicates that the width of the target signal line does not meet the layout design rules.
  • the signal line inspection method provided by the embodiment of the present disclosure generates layout design rules based on the custom design information obtained from the circuit schematic diagram, and checks each target signal line in the circuit layout according to the layout design rules. Add labels to the target signal lines of the layout design rules, which helps layout engineers quickly and accurately locate the target signal lines with design defects. Since the present disclosure does not require layout engineers to manually inspect each key signal line, it can not only effectively reduce the inspection complexity of key signal lines in the circuit layout, greatly shorten the time spent by layout engineers on later inspections, but also ensure the accuracy of the circuit layout design. Accuracy, improving circuit layout design efficiency.
  • FIG. 2 is a schematic flow chart 2 of a signal line inspection method provided in an embodiment of the present disclosure.
  • the above signal line inspection method includes:
  • circuit engineers can list custom design information such as the width, spacing, and surrounding environment of each target signal line in the circuit schematic diagram based on the simulation results of the circuit schematic diagram or their own experience.
  • Table 1 is a schematic table of customized design information for each target signal line.
  • Table 1 Customized design information for each target signal line
  • VREF represents the reference signal
  • refa represents the pin name of the target signal line a
  • refb represents the pin name of the target signal line b
  • Metal1 and Metal2 represent different metal layers in the circuit layout
  • GND represents the ground.
  • the circuit engineer adds the custom design information of the predetermined target signal lines to the circuit schematic.
  • circuit engineers can set labels (or mark) on the pin points of the target signal lines in the circuit schematic diagram, and write their corresponding labels in the labels set on each pin point. custom design information.
  • test platform when the test platform receives the custom design information corresponding to the target signal line input by the circuit engineer, it adds a second label to the target signal line in the circuit schematic diagram according to the operation of the circuit engineer.
  • second label Includes custom design information for target signal lines.
  • the LVS tool can also be used to perform a consistency check on the above-mentioned circuit schematic diagram and circuit layout.
  • the LVS (Layout Versus Schematics) tool is a tool used to verify whether the circuit layout and circuit schematic are consistent.
  • the error types that LVS can verify can be roughly divided into two categories: inconsistent points and mismatched devices.
  • the inconsistencies can be divided into node inconsistencies and device inconsistencies.
  • Node inconsistency means that there is a node in the circuit layout and the circuit schematic diagram.
  • the devices connected to the two nodes are similar, but not exactly the same.
  • Device inconsistency means that there is a device in the circuit layout and the circuit schematic.
  • the two devices are the same and the nodes connected are very similar, but not exactly the same.
  • mismatched devices refer to all devices that are present in the circuit schematic diagram but not in the circuit layout, or are present in the circuit layout but not in the circuit schematic diagram.
  • LVS can also verify the substrate type of the device (such as NMOS and PMOS in CMOS circuits) and some device parameters, which are not limited in the embodiments of the present disclosure.
  • the above-mentioned circuit layout when the above-mentioned circuit layout fails the consistency check of the LVS tool, the above-mentioned circuit layout can be modified according to the circuit schematic diagram, and the LVS tool can be reused to perform a consistency check on the modified circuit layout until The above circuit layout has passed the consistency check of the LVS tool.
  • the DRC code file needs to be used to perform DRC check on the above-mentioned circuit layout to verify whether the current layout design violates the design rules.
  • the DRC code file includes multiple DRC code segments, and each DRC code segment corresponds to a design rule.
  • the design rule includes at least one design rule of width, distance, area, inclusion relationship, and extension relationship of the semiconductor structure in the layout.
  • width-based design rules are used to limit the width of semiconductor structures; distance-based design rules are used to limit the distance between semiconductor structures; area-based design rules are used to limit the area of the chip area occupied by semiconductor structures; design based on inclusion relationships Rules are used to define a positional relationship between semiconductors, such as defining that a certain semiconductor structure also contains another semiconductor structure; design rules based on extension relationships are used to define another positional relationship between semiconductors, such as defining the extension of polysilicon The length to the outside of the semiconductor layer is greater than the preset length to avoid short circuits.
  • the above-mentioned circuit layout fails the DRC inspection
  • the above-mentioned circuit layout can be modified according to the circuit schematic diagram until the above-mentioned circuit layout passes the DRC inspection.
  • design rules in the above-mentioned DRC code files are determined by process parameters specified by industry standards, and the layout design rules corresponding to the target signal lines generated in the embodiments of the present disclosure are based on designs customized by circuit engineers. Parameters are generated.
  • the custom design of the target signal line in the obtained circuit schematic diagram can be Information, generate the following information files:
  • the above layout design rules include constraints such as the width, surrounding environment, spacing, etc. of each target signal line, such as the minimum value of the width corresponding to each target signal line.
  • the LVS tool can be used to determine the location of the target signal line in the circuit layout based on the location of the target signal line in the circuit schematic diagram.
  • a first label is added to the position of the target signal line in the circuit layout, and the first label is used to indicate that the target signal line does not meet the above layout design rules.
  • FIG. 3 is a schematic diagram of a circuit layout inspection result provided in the embodiment of the present disclosure.
  • the design parameters of the target signal line when it is checked that the target signal line does not meet the layout design rules, can also be modified based on the check result and the custom design information corresponding to the target node, so that the target signal line The design parameters of the lines can meet the layout design rules, thereby improving the accuracy of the layout design.
  • the circuit engineer adds the customized design information of each target signal line to the circuit schematic diagram in advance based on the simulation results or his own experience; after completing the design of the circuit layout based on the circuit schematic diagram, Obtain the custom design information added to the circuit schematic diagram, and generate layout design rules based on the obtained custom design information; check each target signal line in the circuit layout according to the layout design rules, and check any target signal lines that do not meet the layout design rules. Add labels to the target signal lines, which helps the layout engineer quickly and accurately locate the target signal lines with design defects. It does not require the layout engineer to manually inspect each key signal line, which can greatly shorten the time spent by the layout engineer on post-inspection and improve Design efficiency of circuit layout.
  • FIG. 4 is a schematic flowchart 3 of a signal line inspection method provided in an embodiment of the present disclosure.
  • the above signal line inspection method includes:
  • a third label can be added to the location of the target signal line in the circuit layout, and the third label includes customized design information corresponding to the target signal line.
  • FIG. 5 is a schematic diagram of a circuit layout with custom design information added in the embodiment of the present disclosure.
  • the custom design information added in advance in the circuit schematic diagram is the custom design information listed in Table 1 above
  • the following information file can be generated based on the obtained custom design information of the target signal line in the circuit schematic diagram:
  • label 3 can be added at the location of target signal line a.
  • the content in label 3 is "VREF refa Metal1 width 0.4Metal1 spacing 0.4Metal2 width 0.4Metal2 spacing 0.4GND"; in the target signal line b Add label 4 at the location.
  • the content in label 4 is "VREF refb Metal1 width 0.4Metal1 spacing 0.4Metal2 width 0.4Metal2 spacing 0.4GND".
  • the target signal line a and the target signal line b may be in the same metal layer or may be in different metal layers. Therefore, in Before adding the third label, you can first determine the coordinates of each target signal line in the metal layer where it is located, and add a third label to each target signal line based on the coordinates of each target signal line in the metal layer where it is located.
  • a first label is added to the position of the target signal line in the circuit layout, and the first label is used to indicate that the target signal line does not meet the layout design rules.
  • the layout engineer when it is checked that the above target signal line does not meet the layout design rules, can add a third label to the position of the target signal line in the circuit layout to perform editing on the target signal line in the circuit layout. Modify until the target signal lines in the circuit layout meet the above layout design rules.
  • the signal line inspection method provided by the embodiment of the present disclosure can reduce the frequent early communication between the circuit engineer and the layout engineer by marking the customized design information of the target signal line into the circuit schematic diagram, and also avoid errors caused by communication; using customization
  • the layout design rules generated by the design information can quickly and accurately locate the target signal lines with design defects in the circuit layout, greatly shortening the time spent by layout engineers on post-inspection, improving the layout quality, and effectively shortening the research and development process.
  • FIG. 6 is a schematic diagram of a program module of a design rule checking device provided in an embodiment of the present disclosure.
  • the design rule checking device includes:
  • the acquisition module 601 is used to obtain customized design information of the target signal line in the circuit schematic diagram, and generate layout design rules corresponding to the target signal line based on the customized design information.
  • the checking module 602 is used to check whether the target signal line in the circuit layout corresponding to the circuit schematic diagram meets the above layout design rules.
  • the first marking module 603 is used to add a first label to the position of the target signal line in the circuit layout when the target signal line in the circuit layout does not meet the above layout design rules.
  • the first label is used to indicate that the target signal line does not meet the above layout design rules. Meet the above layout design rules.
  • the above device further includes a second marking module, used for:
  • the above device further includes a third marking module, used for:
  • the above device further includes a modification module:
  • the target signal line in the circuit layout is modified until the target signal line in the circuit layout meets the above layout design rules.
  • the inspection module 602 is also used to:
  • the signal line inspection device provided by the embodiment of the present disclosure generates layout design rules based on the custom design information obtained from the circuit schematic diagram, and inspects each target signal line in the circuit layout according to the layout design rules. Add labels to the target signal lines of the layout design rules, which helps layout engineers quickly and accurately locate the target signal lines with design defects. Since the present disclosure does not require layout engineers to manually inspect each key signal line, it can not only effectively reduce the inspection complexity of key signal lines in the circuit layout, greatly shorten the time spent by layout engineers on later inspections, but also ensure the accuracy of the circuit layout design. Accuracy, improving circuit layout design efficiency.
  • embodiments of the present disclosure also provide an electronic device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor The computer execution instructions stored in the memory are executed to implement each step in the signal line inspection method as described in the above embodiment, which will not be described again in this embodiment.
  • FIG. 7 is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present disclosure.
  • the electronic device 70 of this embodiment includes: a processor 701 and a memory 702; wherein:
  • Memory 702 used to store computer execution instructions
  • the processor 701 is configured to execute computer execution instructions stored in the memory to implement various steps in the signal line inspection method described in the above embodiments. For details, please refer to the relevant descriptions in the foregoing method embodiments.
  • the memory 702 can be independent or integrated with the processor 701 .
  • the device When the memory 702 is provided independently, the device also includes a bus 703 for connecting the memory 702 and the processor 701 .
  • embodiments of the present disclosure also provide a computer-readable storage medium, which stores computer-executable instructions.
  • the processor executes the computer-executed instructions, , to implement each step in the signal line inspection method described in the above embodiment, which will not be described again in this embodiment.
  • embodiments of the present disclosure also provide a computer program product, including a computer program.
  • the computer program When the computer program is executed by a processor, the signal line as described in the above embodiments is implemented. Each step in the inspection method will not be described again in this embodiment.
  • the disclosed devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the above modules is only a logical function division. In actual implementation, there may be other division methods.
  • multiple modules may be combined or integrated into Another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, indirect coupling or communication connection of devices or modules, and may be in electrical, mechanical or other forms.
  • the modules described above as separate components may or may not be physically separated.
  • the components shown as modules may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional module in various embodiments of the present disclosure can be integrated into a processing unit, or each module can exist physically alone, or two or more modules can be integrated into one unit.
  • the above-mentioned module integrated units can be implemented in the form of hardware or in the form of hardware plus software functional units.

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Abstract

一种信号线检查方法及设备，涉及半导体技术领域，方法包括：获取电路原理图中目标信号线的自定义设计信息，并根据该自定义设计信息生成目标信号线对应的版图设计规则（S101）；检查电路原理图对应的电路版图中，目标信号线是否满足上述版图设计规则（S102）；当电路版图中的目标信号线不满足上述版图设计规则时，在电路版图中目标信号线所在的位置添加第一标签（S103），用于指示目标信号线未满足上述版图设计规则。该信号线检查方法及设备，可以有效降低电路版图中关键信号线的检查复杂度，提升电路版图的设计效率。

Description

信号线检查方法及设备
本公开要求于2022年05月25日提交中国专利局、申请号为202210577511.4、申请名称为“信号线检查方法及设备”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开实施例涉及半导体技术领域，尤其涉及一种信号线检查方法及设备。
背景技术
集成电路版图(以下简称为电路版图)设计是连接电路设计与工艺制造的关键环节。为了保证半导体器件工作的可靠性，在电路版图完成基本物理验证及功能验证后，还需要版图工程师对电路版图中的关键信号线进行检查，以防止发生信号串扰。
然而，随着半导体器件的集成度越来越高，电路版图中信号线的数量也越来越多，对版图中的关键信号线进行检查的过程也变得越来越复杂、繁琐，极大的影响了版图的设计效率。
发明内容
本公开实施例提供了一种信号线检查方法及设备，可以降低电路版图中关键信号线的检查复杂度，提升电路版图的设计效率。
第一方面，本公开实施例提供了一种信号线检查方法，该方法包括：
获取电路原理图中目标信号线的自定义设计信息，并根据所述自定义设计信息生成所述目标信号线对应的版图设计规则；
检查所述电路原理图对应的电路版图中，所述目标信号线是否满足所述版图设计规则；
当所述电路版图中的所述目标信号线不满足所述版图设计规则时，在所述电路版图中所述目标信号线所在的位置添加第一标签，所述第一标签用于指示所述目标信号线未满足所述版图设计规则。
第二方面，本公开实施例提供了一种信号线检查装置，该装置包括：
获取模块，用于获取电路原理图中目标信号线的自定义设计信息，并根据所述自定义设计信息生成所述目标信号线对应的版图设计规则；
检查模块，用于检查所述电路原理图对应的电路版图中，所述目标信号线是否满足所述版图设计规则；
第一标记模块，用于当所述电路版图中的所述目标信号线不满足所述版图设计规则时，在所述电路版图中所述目标信号线所在的位置添加第一标签，所述第一标签用于指示所述目标信号线未满足所述版图设计规则。
第三方面，本公开实施例提供了一种电子设备，包括：至少一个处理器和存储器；
所述存储器存储计算机执行指令；
所述至少一个处理器执行所述存储器存储的计算机执行指令，使得所述至少一个处理器执行如第一方面提供的信号线检查方法。
第四方面，本公开实施例提供了一种计算机可读存储介质，该计算机可读存储介质中存储有计算机执行指令，当处理器执行所述计算机执行指令时，实现如第一方面提供的信号线检查方法。
第五方面，本公开实施例提供了一种计算机程序产品，包括计算机程序，该计算机程序被处理器执行时，实现如第一方面提供的信号线检查方法。
本公开实施例提供的信号线检查方法及设备，基于电路原理图中获取的自定义设计信息来生成版图设计规则，并根据该版图设计规则对电路版图中的各个目标信号线进行检查，对不满足该版图设计规则的目标信号线添加标签，从而有助于版图工程师快速精确定位到存在设计缺陷的目标信号线。由于本公开不需要版图工程师人工对各个关键信号线进行检查，因此不仅可以有效降低电路版图中关键信号线的检查复杂度，大幅缩短版图工程师后期检查花费的时间，而且还能够保证电路版图设计的准确性，提升电路版图的设计效率。
附图说明
图1为本公开实施例中提供的一种信号线检查方法的步骤流程示意图 一；
图2为本公开实施例中提供的一种信号线检查方法的步骤流程示意图二；
图3为本公开实施例中提供的一种电路版图检查结果示意图；
图4为本公开实施例中提供的一种信号线检查方法的步骤流程示意图三；
图5为本公开实施例中提供的一种添加有自定义设计信息的电路版图示意图；
图6为本公开实施例中提供的一种信号线检查装置的程序模块示意图；
图7为本公开实施例提供的一种电子设备的硬件结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。此外，虽然本公开中公开内容按照示范性一个或几个实例来介绍，但应理解，可以就这些公开内容的各个方面也可以单独构成一个完整实施方式。
需要说明的是，本公开中对于术语的简要说明，仅是为了方便理解接下来描述的实施方式，而不是意图限定本公开的实施方式。除非另有说明，这些术语应当按照其普通和通常的含义理解。
本公开中说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似或同类的对象或实体，而不必然意味着限定特定的顺序或先后次序，除非另外注明。应该理解这样使用的用语在适当情况下可以互换，例如能够根据本公开实施例图示或描述中给出那些以外的顺序实施。
此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖但不排他的包含，例如，包含了一系列组件的产品或设备不必限于清楚地列出的那些组件，而是可包括没有清楚地列出的或对于这些产品或设备固有的其它组件。
本公开实施例中使用的术语“模块”，是指任何已知或后来开发的硬件、软件、固件、人工智能、模糊逻辑或硬件或/和软件代码的组合，能够执行与该元件相关的功能。
本公开实施例可以应用于半导体领域，例如可以应用于半导体版图设计检查环节中。
在半导体领域中，一般的芯片设计都会采用签核(sign off)流程，即芯片设计完成后，会通过设计规则检查(design rule check，简称DRC)，来检查当前的设计是否违反设计规则。普通的版图设计通过LVS(Layout Versus Schematics，版图与电路图)和一般的DRC，即可保证设计的电路原理图和电路版图一致，以及保证半导体器件的功能可以正常实现。
其中，上述电路原理图也可以称之为电子电路图或电路图，它是用约定的符号绘制的一种表示电路结构的图形，可以反映电子产品中各元器件的电气连接情况和工作原理，通常应用于设计、分析电路中。在分析电路时，通过识别电路原理图上所绘制的各种电路元件符号，以及它们之间的连接方式，就可以了解电路的工作原理。
在一些实施例中，电路原理图可以由元件符号、信号线、节点等组成。其中，元件符号表示实际电路中的元器件，它的形状与实际的元件不一定相似，甚至完全不一样，但是它一般都表示出了元器件的特点，而且引脚的数目都和实际元件保持一致。信号线表示的是实际电路中的导线，在电路原理图中虽然是一根线，但在常用的芯片或印刷电路板中往往不是线，而是各种形状的、具有一定宽度的金属导线。节点表示几个元器件引脚或几条信号线之间相互的连接关系。所有和节点相连的元器件引脚、信号线，不论数目多少，都是导通的。
随着电路版图工艺尺寸的逐渐缩小，电路版图中相邻信号线之间的间距越来越小，耦合程度也越来越强。其中，相邻信号线之间的这种耦合作用会破坏电路的工作状态，耦合如果足够强时，会增加被耦合信号线远端的电压，一旦超过远端信号线的逻辑门的阈值电压，就会产生逻辑错误。
根据经验，由于串扰导致电路逻辑发生错误的原因主要体现在以下几方面：信号线长度过长，导致近端和远端压降明显增大；信号线之间间距过近，导致耦合性过强；信号的上升沿过堵；相邻两条信号线间的耦合电 容与信号线和衬底间的等效电容的比值增大等。
在一些实施方式中，电路版图中减少噪声的方法包括：增加保护环，减少局部电阻，降低衬底噪声；减少信号线的电阻；增加信号线的间距；用电源线和地线做屏蔽线；用影响小的信号线做屏蔽线，噪声大的信号线远离关键信号线等。
在一些实施方式中，电路工程师会通过后仿来检查这些关键信号线，并将仿真结果反馈给版图工程师进行修改，如果电路比较大，仿真会需要很长的时间，这样反复难免会影响研发进程。所以一般在电路版图制作完后，版图工程师通常会自行检查一下关键信号线是否符合经验值或电路工程师提出的要求。
然而，随着芯片集成度高越来越高，电路版图中信号线的数量也越来越多，对电路版图中的关键信号线进行检查的过程也变得越来越复杂、繁琐，极大的增加了版图工程师后期人工检查的工作量和难度，导致电路版图的设计效率较低。
面对上述技术问题，本公开实施例中提供了一种信号线检查方法，该方法基于电路原理图中获取的关键信号线的自定义设计信息来生成版图设计规则，并根据该版图设计规则对电路版图中的各个关键信号线进行检查，对不满足该版图设计规则的关键信号线添加标签，从而有助于版图工程师快速精确定位到存在设计缺陷的关键信号线，大幅缩短版图工程师后期检查花费的时间，提升电路版图的设计效率。详细过程可以参照以下实施例。
参照图1，图1为本公开实施例中提供的一种信号线检查方法的步骤流程示意图一。在本公开一些实施例中，上述信号线检查方法包括：
S101、获取电路原理图中目标信号线的自定义设计信息，并根据该自定义设计信息生成目标信号线对应的版图设计规则。
示例性的，在集成电路中，存在许多关键信号线，一般分为敏感信号线和噪声信号线，敏感信号线为易受到噪声信号干扰的信号线，如模数转换器的输入、高精度比较器的输入、幅度很低的信号线等，以及容易出现串扰耦合的信号线；噪声信号线为噪声源产生的信号线，如高频数字电路、PLLL(Phase Locked Loop，锁相环)等。
在本公开一些实施例中，电路工程师在制作电路原理图的过程中，可 以将电路原理图中的上述多个关键信号线作为目标信号线，并基于仿真结果和自身经验，在电路原理图中添加各个目标信号线的自定义设计信息，该自定义设计信息包括目标信号线的宽度、周围环境、间距等。
在基于上述电路原理图生成电路版图之后，获取电路原理图中预先添加的目标信号线的自定义设计信息，并根据该自定义设计信息生成目标信号线对应的版图设计规则。
其中，上述版图设计规则中包括各目标信号线对应的宽度、周围环境、间距等的约束条件，如包括各目标信号线对应的宽度的最小值。
在本公开一些实施例中，在生成版图设计规则后，可以基于该版图设计规则生成版图设计规则检查文件。
可选的，上述电路原理图中可以只选择一条信号线作为目标信号线，也可以选择多条信号线作为目标信号线，本公开实施例中不做限制。
S102、检查电路原理图对应的电路版图中，目标信号线是否满足上述版图设计规则。
其中，电路版图也可以称之为集成电路版图，电路版图设计是将电路原理图映射到物理描述层面，从而可以将设计好的电路映射到晶圆上生产。电路版图中通常包含集成电路的器件类型、器件尺寸、器件之间的相对位置以及各个器件之间的连接关系等相关物理信息。
在本公开一些实施例中，在上述电路原理图设计完成之后，可以基于该电路原理图生成其对应的电路版图。
在本公开一些实施例中，可以在生成的电路版图上运行上述版图设计规则检查文件，以检查电路原理图对应的电路版图中，目标信号线是否满足上述版图设计规则。
S103、当电路版图中的目标信号线不满足上述版图设计规则时，在电路版图中目标信号线所在的位置添加第一标签。
其中，上述第一标签用于指示目标信号线未满足上述版图设计规则。
示例性的，当电路版图中某条目标信号线的宽度小于版图设计规则中规定的最小宽度时，可以在电路版图中该条目标信号线所在的位置添加第一标签，该第一标签用于指示该目标信号线的宽度未满足版图设计规则。
本公开实施例提供的信号线检查方法，基于电路原理图中获取的自定 义设计信息来生成版图设计规则，并根据该版图设计规则对电路版图中的各个目标信号线进行检查，对不满足该版图设计规则的目标信号线添加标签，从而有助于版图工程师快速精确定位到存在设计缺陷的目标信号线。由于本公开不需要版图工程师人工对各个关键信号线进行检查，因此不仅可以有效降低电路版图中关键信号线的检查复杂度，大幅缩短版图工程师后期检查花费的时间，而且还能够保证电路版图设计的准确性，提升电路版图的设计效率。
基于上述实施例中所描述的内容，参照图2，图2为本公开实施例中提供的一种信号线检查方法的步骤流程示意图二。在本公开一些实施例中，上述信号线检查方法包括：
S201、在电路原理图中添加目标信号线的自定义设计信息。
在本公开一些实施例中，电路工程师可以根据电路原理图的仿真结果或者其自身经验，列出电路原理图中每个目标信号线的宽度、间距以及周边环境等自定义设计信息。
示例性的，参照表1，表1为各目标信号线的自定义设计信息示意表。
表1：各目标信号线的自定义设计信息示意表
Figure PCTCN2022097526-appb-000001
其中，VREF表示参考信号，refa表示目标信号线a的引脚名称，refb表示目标信号线b的引脚名称，Metal1与Metal2表示电路版图中不同的金属层，GND表示接地。
在电路原理图制作过程中，或者在电路原理图制作完成后，电路工程师将预先确定的目标信号线的自定义设计信息添加在电路原理图中。
在本公开一些实施例中，电路工程师可以对电路原理图中的目标信号线的引脚点pin上设置标签(或打标记)，并在各引脚点pin上设置的标签中写入其对应的自定义设计信息。
示例性的，测试平台在接收的电路工程师输入的目标信号线对应的自 定义设计信息时，根据电路工程师的操作，在电路原理图中的目标信号线上添加第二标签，该第二标签中包括目标信号线的自定义设计信息。
S202、基于电路原理图生成电路版图。
S203、对电路版图完成LVS与DRC验证。
在本公开一些实施例中，在基于上述电路原理图生成对应的电路版图之后，还可以利用LVS工具，对上述电路原理图和电路版图进行一致性检查。
其中，LVS(Layout Versus Schematics)工具是一种用来验证电路版图和电路原理图是否一致的一种工具。
其中，LVS可以验证的错误类型大体可以分为两类：不一致的点和失配器件。其中，不一致的点可分为节点不一致和器件不一致。节点不一致是指电路版图和电路原理图中各有一节点，这两个节点所连器件的情况相似，但是又不完全相同。器件不一致是指电路版图和电路原理图中各有一器件，这两个器件相同，所连接的节点情况很相似，但又不完全相同。其中，失配器件是指所有的器件在电路原理图中有而在电路版图中没有，或在电路版图中有而在电路原理图中没有。
另外，LVS也还可以验证器件的衬底类型(例如CMOS电路中的NMOS和PMOS)和一些器件参数，本公开实施例中不做限制。
在本公开一些实施例中，当上述电路版图未通过LVS工具的一致性检查时，可以根据电路原理图修改上述电路版图，并重新利用LVS工具，对修改后的电路版图进行一致性检查，直至上述电路版图通过LVS工具的一致性检查。
另外，在基于上述电路原理图生成对应的电路版图之后，还需要利用DRC代码文件对上述电路版图进行DRC检查，以验证当前的版图设计是否违反设计规则。其中，DRC代码文件包括多段DRC代码，每段DRC代码对应一种设计规则，该设计规则包括版图中半导体结构的宽度(width)、距离、面积、包含关系、延伸关系的至少一项设计规则。如基于宽度的设计规则用于限定半导体结构的宽度；基于距离的设计规则用于限定半导体结构之间的距离；基于面积的设计规则用于限定半导体结构占用芯片区域的面积；基于包含关系的设计规则用于限定半导体之间的一种位置关系， 例如限定某个半导体结构内还包含另一半导体结构；基于延伸关系的设计规则用于限定半导体之间的另一种位置关系，例如限定多晶硅延伸到半导体层之外的长度大于预设长度，以避免短路。
当上述电路版图未通过DRC检查时，可以根据电路原理图修改上述电路版图，直至上述电路版图通过DRC检查。
需要说明的是，上述DRC代码文件中的设计规则是由行业标准规定的工艺参数来确定的，而本公开实施例中生成的目标信号线对应的版图设计规则，是根据电路工程师自定义的设计参数来生成的。
S204、获取电路原理图中目标信号线的自定义设计信息。
在本公开一些实施例中，假设在电路原理图中预先添加的自定义设计信息为上述表1中列举的自定义设计信息，则可以根据获取到的电路原理图中目标信号线的自定义设计信息，生成如下信息文件：
VREF refa Metal1宽度0.4Metal1间距0.4Metal2宽度0.4Metal2间距0.4GND
VREF refb Metal1宽度0.4Metal1间距0.4Metal2宽度0.4Metal2间距0.4GND
S205、根据上述自定义设计信息生成版图设计规则。
其中，上述版图设计规则中包括各目标信号线对应的宽度、周围环境、间距等的约束条件，如包括各目标信号线对应的宽度的最小值。
S206、检查电路版图中目标信号线是否满足上述版图设计规则。
在本公开一些实施例中，可以利用LVS工具，根据目标信号线在电路原理图中的位置，确定出电路版图中目标信号线所在的位置。
在确定出电路版图中目标信号线所在的位置之后，检查电路版图中的目标信号线是否满足上述版图设计规则。
当电路版图中的目标信号线不满足上述版图设计规则时，在电路版图中目标信号线所在的位置添加第一标签，该第一标签用于指示目标信号线未满足上述版图设计规则。
为了更好的理解本公开实施例，参照图3，图3为本公开实施例中提供的一种电路版图检查结果示意图。
如图3所示，当电路版图中目标信号线a的宽度小于版图设计规则中 规定的最小宽度0.5um时，在目标信号线a所在的位置添加标签1，标签1中的内容为“宽度<0.5um”，用于提示版图工程师目标信号线a的宽度未满足版图设计规则。
当电路版图中目标信号线b的周围环境未屏蔽时，在目标信号线b所在的位置添加标签2，标签2中的内容为“未屏蔽”，用于提示版图工程师目标信号线b的周围环境未满足版图设计规则。
S207、根据检查结果完善电路版图。
在本公开一些实施例中，当检查出上述目标信号线不满足版图设计规则时，还可以基于检查结果与目标节点对应的自定义设计信息，修改上述目标信号线的设计参数，使得上述目标信号线的设计参数能够满足版图设计规则，由此来提高版图设计的准确性。
本公开实施例提供的信号线检查方法，电路工程师预先根据仿真结果或者自身经验，将各目标信号线的自定义设计信息添加在电路原理图中；在基于电路原理图完成电路版图的设计之后，获取电路原理图中添加的自定义设计信息，并基于获取的自定义设计信息来生成版图设计规则；根据该版图设计规则对电路版图中的各个目标信号线进行检查，对不满足该版图设计规则的目标信号线添加标签，从而有助于版图工程师快速精确定位到存在设计缺陷的目标信号线，不需要版图工程师人工对各个关键信号线进行检查，可以大幅缩短版图工程师后期检查花费的时间，提升电路版图的设计效率。
基于上述实施例中所描述的内容，参照图4，图4为本公开实施例中提供的一种信号线检查方法的步骤流程示意图三。在本公开一些实施例中，上述信号线检查方法包括：
S401、在电路原理图中添加目标信号线的自定义设计信息。
S402、基于电路原理图生成电路版图。
S403、对电路版图完成LVS与DRC验证。
S404、获取电路原理图中目标信号线的自定义设计信息。
S405、将目标信号线的自定义设计信息添加在电路版图中。
在本公开一些实施例中，可以在电路版图中目标信号线所在的位置添加第三标签，该第三标签中包括目标信号线对应的自定义设计信息。
为了更好的理解本公开实施例，参照图5，图5为本公开实施例中提供的一种添加有自定义设计信息的电路版图示意图。
假设在电路原理图中预先添加的自定义设计信息为上述表1中列举的自定义设计信息，则可以根据获取到的电路原理图中目标信号线的自定义设计信息，生成如下信息文件：
VREF refa Metal1宽度0.4Metal1间距0.4Metal2宽度0.4Metal2间距0.4GND
VREF refb Metal1宽度0.4Metal1间距0.4Metal2宽度0.4Metal2间距0.4GND
在本公开一些实施例中，可以在目标信号线a所在的位置添加标签3，标签3中的内容为“VREF refa Metal1宽度0.4Metal1间距0.4Metal2宽度0.4Metal2间距0.4GND”；在目标信号线b所在的位置添加标签4，标签4中的内容为“VREF refb Metal1宽度0.4Metal1间距0.4Metal2宽度0.4Metal2间距0.4GND”。
可以理解的是，由于上述电路版图是由多层金属层叠加在一起形成的，因此目标信号线a与目标信号线b可能会处在同一金属层，也有可能处于不同的金属层，因此，在添加第三标签前，可以先确定各个目标信号线在其所在的金属层中的坐标，根据各个目标信号线在其所在的金属层中的坐标，为各个目标信号线添加第三标签。
S406、根据自定义设计信息生成版图设计规则。
S407、检查电路版图中目标信号线是否满足版图设计规则。
当电路版图中的目标信号线不满足上述版图设计规则时，在电路版图中目标信号线所在的位置添加第一标签，该第一标签用于指示目标信号线未满足版图设计规则。
S207、根据检查结果完善电路版图。
在本公开一些实施例中，当检查出上述目标信号线不满足版图设计规则时，版图工程师可以基于电路版图中目标信号线所在的位置添加的第三标签，对电路版图中的目标信号线进行修改，直至电路版图中的目标信号线满足上述版图设计规则。
本公开实施例提供的信号线检查方法，通过将目标信号线的自定义设 计信息标记入电路原理图，可以减少工程师电路与版图工程师前期频繁的沟通，也避免了沟通产生的误差；利用自定义设计信息生成的版图设计规则，可以快速精确定位出电路版图中存在设计缺陷的目标信号线，大大缩短了版图工程师后期检查花费的时间，提高了版图质量，并有效的缩短了研发进程。
基于上述实施例中所描述的内容，本公开实施例中还提供一种设计规则检查装置。参照图6，图6为本公开实施例中提供的一种设计规则检查装置的程序模块示意图，该设计规则检查装置包括：
获取模块601，用于获取电路原理图中目标信号线的自定义设计信息，并根据该自定义设计信息生成目标信号线对应的版图设计规则。
检查模块602，用于检查电路原理图对应的电路版图中，目标信号线是否满足上述版图设计规则。
第一标记模块603，用于当电路版图中的目标信号线不满足上述版图设计规则时，在电路版图中目标信号线所在的位置添加第一标签，该第一标签用于指示目标信号线未满足上述版图设计规则。
在一些实施例中，上述装置还包括第二标记模块，用于：
接收用户输入的目标信号线对应的自定义设计信息；在电路原理图中的目标信号线上添加第二标签，该第二标签中包括上述自定义设计信息。
在一些实施例中，上述装置还包括第三标记模块，用于：
在电路版图中目标信号线所在的位置添加第三标签，该第三标签中包括目标信号线对应的自定义设计信息。
在一些实施例中，上述装置还包括修改模块：
基于电路版图中目标信号线所在的位置添加的第三标签，对电路版图中的目标信号线进行修改，直至电路版图中的目标信号线满足上述版图设计规则。
在一些实施例中，检查模块602还用于：
利用LVS工具，根据目标信号线在电路原理图中的位置，确定电路版图中目标信号线所在的位置。
本公开实施例提供的信号线检查装置，基于电路原理图中获取的自定义设计信息来生成版图设计规则，并根据该版图设计规则对电路版图中的 各个目标信号线进行检查，对不满足该版图设计规则的目标信号线添加标签，从而有助于版图工程师快速精确定位到存在设计缺陷的目标信号线。由于本公开不需要版图工程师人工对各个关键信号线进行检查，因此不仅可以有效降低电路版图中关键信号线的检查复杂度，大幅缩短版图工程师后期检查花费的时间，而且还能够保证电路版图设计的准确性，提升电路版图的设计效率。
需要说明的是，本公开实施例中获取模块601、检查模块602及第一标记模块603具体执行的内容可以参阅图1至图5所示实施例中相关内容，此处不做赘述。
进一步的，基于上述实施例中所描述的内容，本公开实施例中还提供了一种电子设备，该电子设备包括至少一个处理器和存储器；其中，存储器存储计算机执行指令；上述至少一个处理器执行存储器存储的计算机执行指令，以实现如上述实施例中描述的信号线检查方法中的各个步骤，本实施例此处不再赘述。
为了更好的理解本公开实施例，参照图7，图7为本公开实施例提供的一种电子设备的硬件结构示意图。
如图7所示，本实施例的电子设备70包括：处理器701以及存储器702；其中：
存储器702，用于存储计算机执行指令；
处理器701，用于执行存储器存储的计算机执行指令，以实现上述实施例中描述的信号线检查方法中的各个步骤，具体可以参见前述方法实施例中的相关描述。
可选地，存储器702既可以是独立的，也可以跟处理器701集成在一起。
当存储器702独立设置时，该设备还包括总线703，用于连接存储器702和处理器701。
进一步的，基于上述实施例中所描述的内容，本公开实施例中还提供了一种计算机可读存储介质，该计算机可读存储介质中存储有计算机执行指令，当处理器执行计算机执行指令时，以实现如上述实施例中描述的信号线检查方法中的各个步骤，本实施例此处不再赘述。
进一步的，基于上述实施例中所描述的内容，本公开实施例中还提供了一种计算机程序产品，包括计算机程序，该计算机程序被处理器执行时，实现如上述实施例中描述的信号线检查方法中的各个步骤，本实施例此处不再赘述。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，上述模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
上述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能模块可以集成在一个处理单元中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个单元中。上述模块集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (15)

  1. 一种信号线检查方法，所述方法包括：
    获取电路原理图中目标信号线的自定义设计信息，并根据所述自定义设计信息生成所述目标信号线对应的版图设计规则；
    检查所述电路原理图对应的电路版图中，所述目标信号线是否满足所述版图设计规则；
    当所述电路版图中的所述目标信号线不满足所述版图设计规则时，在所述电路版图中所述目标信号线所在的位置添加第一标签，所述第一标签用于指示所述目标信号线未满足所述版图设计规则。
  2. 根据权利要求1所述的方法，其中，所述获取电路原理图中目标信号线的自定义设计信息之前，还包括：
    接收用户输入的所述目标信号线对应的自定义设计信息；
    在所述电路原理图中的所述目标信号线上添加第二标签，所述第二标签中包括所述自定义设计信息。
  3. 根据权利要求1所述的方法，其中，所述获取电路原理图中目标信号线的自定义设计信息之后，还包括：
    在所述电路版图中所述目标信号线所在的位置添加第三标签，所述第三标签中包括所述目标信号线对应的自定义设计信息。
  4. 根据权利要求3所述的方法，其中，所述在所述电路版图中所述目标信号线所在的位置添加第一标签之后，还包括：
    基于所述电路版图中所述目标信号线所在的位置添加的所述第三标签，对所述电路版图中的所述目标信号线进行修改，直至所述电路版图中的所述目标信号线满足所述版图设计规则。
  5. 根据权利要求1所述的方法，其中，还包括：
    利用LVS工具，根据所述目标信号线在所述电路原理图中的位置，确定所述电路版图中所述目标信号线所在的位置。
  6. 根据权利要求1至5任一项所述的方法，其中，所述自定义设计信息包括以下信息中的一个或者多个：所述目标信号线的宽度、周围环境、所述目标信号线间的间距。
  7. 一种信号线检查装置，所述装置包括：
    获取模块，用于获取电路原理图中目标信号线的自定义设计信息，并根据所述自定义设计信息生成所述目标信号线对应的版图设计规则；
    检查模块，用于检查所述电路原理图对应的电路版图中，所述目标信号线是否满足所述版图设计规则；
    第一标记模块，用于当所述电路版图中的所述目标信号线不满足所述版图设计规则时，在所述电路版图中所述目标信号线所在的位置添加第一标签，所述第一标签用于指示所述目标信号线未满足所述版图设计规则。
  8. 根据权利要求7所述的装置，其中，还包括第二标记模块，用于：
    接收用户输入的所述目标信号线对应的自定义设计信息；
    在所述电路原理图中的所述目标信号线上添加第二标签，所述第二标签中包括所述自定义设计信息。
  9. 根据权利要求7所述的装置，其中，还包括第三标记模块，用于：
    在所述电路版图中所述目标信号线所在的位置添加第三标签，所述第三标签中包括所述目标信号线对应的自定义设计信息。
  10. 根据权利要求9所述的装置，其中，还包括修改模块：
    基于所述电路版图中所述目标信号线所在的位置添加的所述第三标签，对所述电路版图中的所述目标信号线进行修改，直至所述电路版图中的所述目标信号线满足所述版图设计规则。
  11. 根据权利要求7所述的装置，其中，所述检查模块还用于：
    利用LVS工具，根据所述目标信号线在所述电路原理图中的位置，确定所述电路版图中所述目标信号线所在的位置。
  12. 根据权利要求7至11任一项所述的装置，其中，所述自定义设计信息包括以下信息中的一个或者多个：所述目标信号线的宽度、周围环境、所述目标信号线间的间距。
  13. 一种电子设备，包括：至少一个处理器和存储器；
    所述存储器存储计算机执行指令；
    所述至少一个处理器执行所述存储器存储的计算机执行指令，使得所述至少一个处理器执行如权利要求1至6任一项所述的信号线检查方法。
  14. 一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，当处理器执行所述计算机执行指令时，实现如权利要求1至 6任一项所述的信号线检查方法。
  15. 一种计算机程序产品，包括计算机程序，所述计算机程序被处理器执行时，实现权利要求1至6任一项所述的信号线检查方法。
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