WO2023035471A1 - 一种布线质量检测方法、装置及存储介质 - Google Patents

一种布线质量检测方法、装置及存储介质 Download PDF

Info

Publication number
WO2023035471A1
WO2023035471A1 PCT/CN2021/138400 CN2021138400W WO2023035471A1 WO 2023035471 A1 WO2023035471 A1 WO 2023035471A1 CN 2021138400 W CN2021138400 W CN 2021138400W WO 2023035471 A1 WO2023035471 A1 WO 2023035471A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring
level
expected
connection
detected
Prior art date
Application number
PCT/CN2021/138400
Other languages
English (en)
French (fr)
Inventor
杜涛
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/936,838 priority Critical patent/US20230039473A1/en
Publication of WO2023035471A1 publication Critical patent/WO2023035471A1/zh

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/394Routing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Definitions

  • the present disclosure relates to the field of integrated circuit design, and in particular to a wiring quality detection method, device and storage medium.
  • the wiring quality needs to be tested. If the wiring quality is detected through manual inspection and post-simulation verification, the detection time spent is too long.
  • the embodiments of the present disclosure expect to provide a wiring quality testing method, device and storage medium, which can quickly complete the wiring quality testing, realize automatic wiring quality testing, and save testing time.
  • An embodiment of the present disclosure provides a wiring quality detection method, the method comprising:
  • the wired layout Based on the wired layout, determine a wiring result topology and an expected topology corresponding to each signal to be detected in the set of signals to be detected; the expected topology is obtained based on the position of the connection point in the wired layout;
  • topology comparison result is greater than a preset threshold, it is determined that the corresponding signal to be detected has a detection result of unreasonable wiring
  • a quality detection report is generated based on the detection result of each signal to be detected.
  • An embodiment of the present disclosure also provides a wiring quality detection device, including:
  • the determining unit is configured to determine, based on the wired layout, a wiring result topology and an expected topology corresponding to each signal to be detected in the set of signals to be detected; the expected topology is based on the position of the connection point in the wired layout owned;
  • the comparison unit is configured to compare the topology structure of the wiring result with the expected topology structure for each signal to be detected, and obtain a topology comparison result corresponding to each signal to be detected;
  • the determining unit is further configured to determine that the corresponding signal to be detected has an unreasonable wiring detection result if the topology comparison result is greater than a preset threshold;
  • a generating unit configured to generate a quality inspection report based on the detection result of each signal to be detected.
  • An embodiment of the present disclosure also provides a wiring quality detection device, including:
  • the processor is configured to implement the wiring quality detection method in the above solution when executing the executable instructions stored in the memory.
  • An embodiment of the present disclosure further provides a storage medium, storing executable instructions, for causing a processor to implement the wiring quality detection method in the above solution when executed.
  • the embodiments of the present disclosure provide a wiring quality detection method, device, and storage medium, which can determine the wiring result topology and expected topology corresponding to each signal to be detected in the signal set to be detected based on the layout of the wiring; Then, for each signal to be detected, the topology structure of the wiring result is compared with the expected topology structure to obtain the topology comparison result corresponding to each signal to be detected; then the topology comparison result is judged. If the threshold is set, it is determined that the corresponding signal to be detected has a detection result of unreasonable wiring; then, based on the detection result of each signal to be detected, a quality detection report is generated. In this way, the automatic wiring results can be detected by running the program, without the need for designers to search and verify one by one, quickly complete the wiring quality detection, realize the automation of wiring quality detection, and save detection time.
  • FIG. 1 is a flow chart 1 of a wiring quality detection method provided by an embodiment of the present disclosure
  • FIG. 2 is an example diagram of an expected topology in an embodiment of the present disclosure
  • FIG. 3A is a first schematic diagram of obtaining an actual wiring pattern in an embodiment of the present disclosure
  • FIG. 3B is a second schematic diagram of obtaining an actual wiring pattern in an embodiment of the present disclosure.
  • FIG. 3C is a third schematic diagram of obtaining an actual wiring pattern in an embodiment of the present disclosure.
  • FIG. 4A is a schematic diagram of a type of actual wiring pattern in an embodiment of the present disclosure.
  • FIG. 4B is a second schematic diagram of the type of the actual wiring pattern in the embodiment of the present disclosure.
  • FIG. 4C is a third schematic diagram of the type of the actual wiring pattern in the embodiment of the present disclosure.
  • FIG. 5 is a second flow chart of a wiring quality detection method provided by an embodiment of the present disclosure.
  • FIG. 6 is an effect diagram showing detection results in an embodiment of the present disclosure.
  • FIG. 7 is a third flowchart of a wiring quality detection method provided by an embodiment of the present disclosure.
  • FIG. 8 is a flowchart 4 of a wiring quality detection method provided by an embodiment of the present disclosure.
  • FIG. 9 is a flowchart five of a wiring quality detection method provided by an embodiment of the present disclosure.
  • FIG. 10 is a flowchart six of a wiring quality detection method provided by an embodiment of the present disclosure.
  • FIG. 11 is a flowchart VII of a wiring quality detection method provided by an embodiment of the present disclosure.
  • FIG. 12 is a flow chart eighth of a wiring quality detection method provided by an embodiment of the present disclosure.
  • FIG. 13 is a flowchart nine of a wiring quality detection method provided by an embodiment of the present disclosure.
  • FIG. 14 is a flowchart ten of a wiring quality detection method provided by an embodiment of the present disclosure.
  • FIG. 15 is a flow chart eleventh of a wiring quality detection method provided by an embodiment of the present disclosure.
  • FIG. 16 is a flowchart twelve of a wiring quality detection method provided by an embodiment of the present disclosure.
  • FIG. 17 is a first structural schematic diagram of a wiring quality detection device provided by an embodiment of the present disclosure.
  • FIG. 18 is a second structural schematic diagram of a wiring quality detection device provided by an embodiment of the present disclosure.
  • first/second in the invention document, add the following explanation.
  • first ⁇ second ⁇ third are only used to distinguish similar objects and do not mean Regarding the specific ordering of objects, it can be understood that “first ⁇ second ⁇ third” can be exchanged for a specific order or sequence if allowed, so that the embodiments of the present disclosure described here can operate in a performed in an order other than that shown or described.
  • the Peripheral (peripheral) layer of the DRAM (Dynamic Random Access Memory) chip layout contains more than 15,000 signal lines. Therefore, it is necessary to complete the connection of a large number of signal lines with the help of automatic wiring tools, that is, to perform a large number of automatic wiring, in order to meet the requirements of the project deadline.
  • FIG. 1 is a schematic flowchart of an optional wiring quality inspection method provided by an embodiment of the present disclosure, which will be described in conjunction with the steps shown in FIG. 1 .
  • the wiring quality detection device may respectively determine the topology structure of the wiring result and the expected topology structure corresponding to each signal to be detected in the set of signals to be detected based on the layout of the wiring.
  • the expected topology is obtained based on the positions of the connection points in the routed layout.
  • the wiring quality detection device before the wiring quality detection device determines the topology structure of the wiring result and the expected topology structure, it needs to first determine the connection point (pin) through which the signal to be detected passes. Since it may be difficult to clearly display all the connection objects and connection points that the signal to be detected passes through in the wired layout, the wiring quality detection device can first obtain the wired circuit diagram corresponding to the wired layout, and then, based on the wired layout and the wired A circuit diagram, determining at least one connection point corresponding to each signal to be detected, the process may include the following steps:
  • Step 1 Obtain the connection object identifier in the wired circuit diagram.
  • the wiring quality detection device may first acquire at least one connection object identifier corresponding to each signal to be detected in the wired circuit diagram.
  • connection object identifier is a symbol of an electrical connection object in the wired circuit diagram, and represents a module (instance) with a specific function in the circuit.
  • Any connection object identifier in the routed circuit diagram has a corresponding connection object in the routed layout diagram.
  • the connection object is a graph in the wired layout, which represents that the corresponding physical area in the chip can form the module and realize the function of the module.
  • Step 2 matching connection objects in the routed layout.
  • the wiring quality detection device may match at least one connection object corresponding to the at least one connection object identifier in the wired layout.
  • Step 3 determine the connection point in the wired layout.
  • the wiring quality detection device may determine at least one connection point corresponding to each signal to be detected in the wired layout based on the at least one connection object. It should be noted that the connection objects are electrically connected through the connection point, and the determination of the connection point means the determination of the end point through which the signal to be detected passes through the connection line.
  • the wiring quality detection device may respectively determine the expected value corresponding to each signal to be detected in the wired layout based on the at least one connection point.
  • Topology and routing result topology reflects the desired result of the layout and routing
  • the layout result topology reflects the actual result of the layout and routing.
  • the expected topology can be used as a standard and reference for the topology of the routing result to guide the actual layout and routing work.
  • topology structure in the embodiments of the present disclosure is an abstract description of the signal lines in the layout using two graphic elements, points and lines; wherein, points are used to describe at least one corresponding to each signal to be detected. Connection points, specify the positions of these connection points in the wired layout; use lines to describe the wiring graph between at least one connection point, and specify the path and length of the signal line.
  • the wiring quality detection device can determine N levels of expected connections hierarchically (N is greater than or equal to 1), thereby forming an expected topology structure, which includes at least one connection point and N levels of expected connections.
  • the process can include the following steps:
  • Step 1 Determine the N-level intermediate baseline.
  • the wiring quality detection device may take at least one connection point as a first-level connection point in the wired layout; then, determine the two first-level edge connection points that are farthest along the first axial direction among the first-level connection points , and then passing through the midpoint of the line connecting the two first-level edge connection points, the first-level intermediate reference line along the second axis is determined.
  • the wiring quality detection device can determine the first-level connection point whose axial distance is less than the second-level preset threshold as the second-level connection point; wherein, the axial distance is the distance along the first axis or the second axis, and the first axis is perpendicular to the second axis.
  • the wiring quality detection device can use a method similar to determining the first-level intermediate reference line to determine the second-level intermediate reference line in the second-level connection point, that is, the wiring quality detection device can determine the second-level connection Among the points, the two second-level edge connection points farthest along the first axis, and then the midpoint of the line passing through the two second-level edge connection points, determine the second-level intermediate reference line along the second axis .
  • the wiring quality detection device may determine the third-level intermediate reference line in a similar manner, and so on until the N-th intermediate reference line is determined. That is to say, the wiring quality detection device can determine the connection point whose axial distance is less than the i-th level preset threshold among the i-1th level connection points as the i-th level connection point; wherein, i is greater than or equal to 2, and i is less than or equal to N-1.
  • Step 2 Determine the N-level expected connections.
  • the wiring quality detection device can determine the expected connection of each level based on the connection points of the N levels and the intermediate reference lines of the N levels, and determine the expected connection of each level, so as to determine the expected connection of the N levels.
  • the wiring quality detection device can connect the first connection point of each level to the vertical foot of the corresponding middle reference line of each level, and obtain The first sub-expected connection line corresponding to the first connection point; wherein, the preset distance condition corresponding to each level of connection point is that the axial distance is less than the preset threshold of the next level.
  • the wiring quality detection device can connect the intermediate reference line of the level corresponding to the second connection point of each level to the intermediate reference line of the next level
  • the public perpendicular line segment of the line is obtained to obtain the second sub-expected connection line corresponding to the second connection point.
  • the first sub-expected connection and the second sub-expected connection are used as each level of expected connection until the connection of N-level connection points is completed, and N-level expected connections can be determined.
  • the wiring quality detection device may first determine the N-level expected connection line based on the N-level connection point and the N-level intermediate reference line , and then determine the expected connection of the upper level step by step, and finally determine the expected connection of the first level. That is to say, the wiring quality detection device can determine the expected connection line of level j based on the connection point of level j, the intermediate reference line of level j and the expected connection line of level j+1, wherein j is greater than or equal to 2, and j is less than It is equal to N-1. Then, continue to determine the j-1th level of expected connections until the first level of expected connections is determined, so that N levels of expected connections are determined.
  • the wiring quality detection device may first determine the Nth level expected connection based on the Nth level connection point and the Nth level intermediate reference line.
  • the wiring quality detection device can respectively establish a vertical line segment from each group of Nth-level connection points to the corresponding N-th-level intermediate reference line in the N-th-level connection point, and obtain the N-th-level connection point connection line; wherein, each group of N-th level The level connection points are the connection points whose mutual axial distances are smaller than the preset threshold of the Nth level.
  • the wiring quality detection device can respectively establish the vertical line segment from each group of N-1th level connection points to the corresponding N-1th level intermediate reference line, and the Nth-level reference line connection To the corresponding public perpendicular line segment of the N-1th level intermediate datum line, the connection point of the N-1st level is obtained; wherein, the axial distance between each group of N-1st level connection points is less than the Nth level - Connection points for level 1 preset thresholds.
  • the wiring quality detection device can respectively establish the vertical line segment from each group of jth-level connection points to the corresponding j-th-level intermediate reference line, and the line connecting the j+1-th-level reference line to the corresponding j-th-level intermediate reference line
  • the public vertical line segment of the j-level connection point is obtained; wherein, each group of j-level connection points is the connection point whose axial distance between each other is smaller than the j-level preset threshold.
  • FIG. 2 is an optional example diagram of an expected topology provided by an embodiment of the present disclosure.
  • at least one connection point includes connection points p1, p2, p3, p4, p5, p6, and p7, which are respectively Corresponds to connection objects I1, I2, I3, I4, I5, I6 and I7.
  • the wiring quality inspection device may first confirm the connection points p1, p2, p3, p4, p5, p6 and p7 as the first-level connection points, and then determine the two first-level edges farthest along the Y axis Connect points p3 and p7.
  • the first-level edge lines L1 and L2 extend along the X axis, pass through p3 and p7 respectively, and represent the positions of p3 and p7 on the Y axis.
  • the wiring quality inspection device can determine the first-level intermediate reference line L3 according to the positions of p3 and p7 in the Y axis, wherein, L3 is the intermediate parallel line between L1 and L2, and the distance from L3 to L1 and L2 is equal.
  • the wiring quality inspection device can confirm that the axial distance is less than the second level in the first-level connection points p1, p2, p3, p4, p5, p6 and p7 Level 2 connection points for level preset thresholds.
  • the second-level preset threshold is 150
  • the axial distances between p3 and p4 in the X-axis and Y-axis are both less than 150
  • p3 and p4 are determined as a group of second-level connection points
  • p5, p6 and The axial distance between any two points in p7 in the X-axis and Y-axis is less than 150
  • p5, p6 and p7 are determined as another group of second-level connection points; that is, each group of second-level connection points All within the 150x150 range.
  • the wiring quality detection device may separately determine the second-level intermediate reference line corresponding to each group of second-level connection points. For example, for the group of second-level connection points p3 and p4, the wiring quality inspection device first determines the two second-level edge connection points that are farthest along the Y axis, since there are only two members of the second-level connection point in this group , so they are directly used as the second-level edge connection points respectively; then the corresponding second-level edge lines L1 and L4 extend along the X-axis (L1 is also the first-level edge line), passing through p3 and p4 respectively, representing p3 and the positions of p4 in the Y axis; the wiring quality inspection device can determine the second-level intermediate reference line L6 corresponding to the group of second-level connection points according to the positions of p3 and p4 in the Y axis, where L6 is L1 Parallel to the middle of L4, L
  • the wiring quality inspection device first determines the two second-level edge connection points p5 and p7 that are farthest along the Y axis; then the corresponding second-level The edge lines L5 and L2 extend along the X axis (L2 is also the first-level edge line), passing through p5 and p7 respectively, which characterizes the positions of p5 and p7 in the Y axis; the wiring quality detection device can be based on p5 and p7 in Y The axial position determines the second-level intermediate reference line L7 corresponding to the group of second-level connection points, where L7 is the middle parallel line between L5 and L2, and the distance from L7 to L5 and L2 is equal.
  • the wiring quality inspection device can make a vertical line segment from each level of connection point to the corresponding intermediate reference line of each level;
  • the vertical line segments y1 and y2 from p1 and p2 to L3 are respectively made into the vertical line segments ys1 and ys2 from p3 and p4 to L6, and the vertical line segments ys3, ys4 and ys5 from p5, p6 and p7 to L7 are respectively made.
  • the wiring quality inspection device can respectively make common vertical line segments yb1 and yb2 from the second-level intermediate reference line L6 and L7 to the first-level intermediate reference line L3. Then, the wiring quality detection device can respectively connect all the perpendicular segments and the vertical feet of the public vertical segments on the middle reference line of each level; that is, connect the vertical feet of ys1 and ys2 on L6 to obtain x1; and connect y1, y2, and yb1 and the foot of yb2 on L3 to get x2; and connect the feet of ys3, ys4 and ys5 to L7 to get x3.
  • connection points p1, p2, p3, p4, p5, p6 and p7, and line segments x1, x2, x3, y1, y2, ys1, ys2, ys3, ys4 and ys5 is obtained.
  • the wiring quality detection device may determine at least one actual wiring pattern connected to at least one connection point in the wired layout; then determine the category of each actual wiring pattern according to a preset classification rule, and perform each The corresponding actual wiring graphs are simplified to obtain at least one corresponding actual connection line, thereby obtaining a wiring result topology structure including at least one connection point and at least one actual connection line.
  • FIG. 3A, FIG. 3B and FIG. 3C illustrate the process of obtaining the actual wiring pattern, which will be described with reference to the diagrams.
  • the wiring quality detection device can determine the connection points p11 , p12 , p13 , p14 , p15 , p16 , p17 and p18 in the wired circuit diagram.
  • the wiring quality detection device can determine the corresponding positions of the connection points p11, p12, p13, p14, p15, p16, p17 and p18 in the wired layout, and determine the corresponding positions of these connection points in the wired layout.
  • FIG. 3C the obtained actual wiring pattern is extracted.
  • the categories of actual wiring graphics include: rectangle (Rectangle), path (Path) and polygon (Polygon), and FIG. 4A, FIG. 4B and FIG. At least one actual connection line corresponding to the wiring pattern will be described with reference to the diagram.
  • the actual wiring pattern G1 is a rectangle, and the wiring quality detection device may use the perpendicular line a of the short side of the rectangle in G1 as the actual connection line corresponding to G1 .
  • the actual wiring pattern G2 belongs to the path, and the wiring quality detection device can connect the center points along the axis of the path in G2 to obtain the actual connection lines b, c and d corresponding to G2.
  • the actual wiring patterns G3 and G4 belong to polygons
  • G3 and the through-layer hole V1 are connected to the through-layer hole connection line j
  • G4 and the through-layer hole V2 are connected to the through-layer hole connection line k, wherein the through-layer hole
  • the wiring quality detection device can use the vertical line g of the layer through hole connection line j as the actual connection line corresponding to G3, and determine the actual connection lines e and f according to the method corresponding to the actual wiring pattern of the path category, so as to obtain The actual connections e, f and g corresponding to G3 are shown.
  • the wiring quality inspection device can use the vertical line i of the through-hole connection line k as the actual connection line corresponding to G4, and determine the actual connection line h according to the method corresponding to the actual wiring pattern of the rectangular category, thereby obtaining G4 The corresponding actual connection h and i.
  • the wiring quality detection device may compare the topology structure of the wiring result with the expected topology, so as to obtain a topology comparison result corresponding to each signal to be detected.
  • the wiring quality detection device can calculate the expected wiring length of the expected topology and the actual wiring length of the wiring result topology, and compare the actual wiring length with the expected wiring length to obtain the topology compare results.
  • the expected routing length includes: the total expected routing length, that is, the total length of all expected connections in the expected topology; the actual routing length includes: the total actual routing length, that is, the total length of all actual connections in the routing result topology.
  • the wiring quality detection device can use the ratio of the actual total length of the wiring to the expected total length of the wiring as the result of the topology comparison. As shown in Table 1:
  • netA 963.417 679.419 141.8% netB 5691.201 5169.737 110.1% netC 2134.079 944.885 225.9%
  • the expected wiring length also includes: at least one expected wiring layer length, that is, the expected wiring length corresponding to at least one metal layer; the actual wiring length also includes: at least one actual wiring layer length, that is, at least one metal layer corresponding to actual line length.
  • the wiring quality detection device can compare each actual wiring layer length with the expected wiring layer length corresponding to the same metal layer, and obtain at least one metal layer ratio as a topology comparison result. It should be noted that at least one metal layer is included in the wired layout, and the metal wirings in different metal layers are in different positions in the actual chip structure, that is, the upper metal wirings are located above the lower metal wirings.
  • At least one expected wiring layer length may be a preset length corresponding to at least one metal layer, that is, the expected wiring length may be a preset value. As shown in Table 2:
  • netA has no actual wiring layer length in Mx, which means that netA has no metal wiring in the metal layer of Mx;
  • the actual wiring layer length of netB in Mx is 615.245;
  • the actual wiring layer length of netC in Mx is 246.874.
  • the expected wiring layer lengths of netA, netB, and netC at Mx are all preset to 150.
  • the wiring quality detection device can compare the topology structure comparison result of each signal to be detected with a preset threshold; if the topology structure comparison result is greater than the preset threshold, it can be determined that the corresponding signal to be detected has different The detection results of reasonable wiring.
  • the wiring quality detection device may compare the ratio of the actual total length of the wiring corresponding to the signal to be detected to the expected total length of the wiring with a corresponding preset threshold of the total length ratio. For example, if the preset threshold is 120%, the ratios of netA and netC in Table 1 are both greater than the preset threshold, and it can be determined that netA and netC have unreasonable wiring detection results.
  • the wiring quality detection device may also compare the ratio of the actual wiring layer length to the expected wiring layer length with the corresponding layer length ratio preset threshold for any metal layer. For example, if the preset threshold is 100%, the ratios of netB and netC in Table 2 are both greater than the preset threshold, and it can be determined that netB and netC have unreasonable wiring detection results. It can be understood that setting the layer length ratio preset threshold to 100% means that the actual wiring layer length should not be greater than the corresponding expected wiring layer length.
  • the wiring quality detection device may generate a quality detection report based on the detection result of each signal to be detected.
  • the quality detection report may include the topology structure comparison result and wiring position information of each signal to be detected.
  • the wiring position information is used to display the actual wiring pattern corresponding to the signal to be detected in the wired layout, which may be the coordinate information of the connection point.
  • the wiring quality detection device can determine unreasonable wiring by obtaining the topology structure of the wiring result and the expected topology structure, and comparing and judging.
  • the automatic wiring results can be detected by running the program, without the need for designers to search and verify one by one, quickly complete the wiring quality detection, realize the automation of wiring quality detection, and save detection time. Therefore, it is convenient for designers to modify and improve the automatic wiring at a later stage, and the chip development cycle is shortened.
  • S105 shown in FIG. 5 is further included after S104 shown in FIG. 1 , which will be described in combination with each step.
  • the wiring quality testing device may display the testing results in the wired layout based on the quality testing report, so as to assist the designer in checking and locating the unreasonable wiring.
  • the designer opens the wired layout, he can read the quality inspection report and select the signal to be displayed that he wants to view in the set of signals to be inspected.
  • the wiring quality detection device can receive the selection operation of the signal set to be detected, determine the signal to be displayed, and determine the detection result corresponding to the signal to be displayed based on the quality detection report; if the detection result indicates that the signal to be displayed has unreasonable wiring, the wiring quality
  • the detection device can highlight unreasonable wiring in the wired layout.
  • the wiring quality detection device will highlight the unreasonable wiring passing through the connection points p21, p22, p23 and p24 in the wiring layout; wherein, p21, p22, The direct connection between p23 and p24 is not an actual wiring, but is used to help the designer find the location of the connection point. This completes the display of inspection results in the routed layout.
  • the designer can modify the unreasonable wiring.
  • the wiring quality detection device highlights the unreasonable wiring in the wired layout, which can help designers modify and improve the unreasonable wiring, so as to optimize the actual wiring to an optimal solution.
  • S101 shown in FIG. 1 may be implemented through S201 to S204 shown in FIG. 7 , which will be described in conjunction with each step.
  • the wiring quality detection device may first obtain the wired circuit diagram corresponding to the wired layout.
  • the wiring quality detection device may determine at least one connection point corresponding to each signal to be detected based on the wired layout and the wired circuit diagram.
  • the wiring quality detection device can first obtain the identification of the connection object in the wired circuit diagram, and then match the connection object in the wired layout and determine the connection point.
  • the wiring quality detection device may determine the expected topology corresponding to each signal to be detected from the layout layout based on the at least one connection point.
  • the wiring quality detection device can determine N levels of expected connections (N is greater than or equal to 1) hierarchically, so as to form an expected topology.
  • the wiring quality detection device may also determine the topology of the wiring result corresponding to each signal to be detected from the layout layout based on the at least one connection point structure.
  • the wiring quality detection device may first determine at least one actual wiring pattern connected to at least one connection point in the wired layout; then, simplify each actual wiring pattern according to the category to obtain at least one corresponding actual connection line, thereby Form the routing result topology.
  • the wiring quality detection device first determines the position of at least one connection point that the connection passes through in the layout layout, and then obtains the topology structure of the wiring result and the expected topology structure respectively based on the at least one connection point. In this way, the obtained The expected topological structure of can be more in line with the actual situation, and it can be used as the comparison object of the topological structure of the wiring result more accurately, so that the unreasonable wiring can be judged more accurately.
  • connection point includes N-level connection points, where N is greater than or equal to 1;
  • S203 shown in FIG. 7 can be implemented through S301-S305 shown in FIG. 8 , and will be described in conjunction with various steps.
  • connection point corresponding to each signal to be detected is used as a first-level connection point; based on the first-level connection point, determine a first-level intermediate reference line.
  • the wiring quality detection device may firstly use at least one connection point as a first-level connection point in the wired layout, and determine the first-level intermediate reference line based on the first-level connection points.
  • connection point whose axial distance is smaller than the preset threshold of the i-th level among the i-1-th level connection points as the i-th level connection point; based on the i-th level connection point, determine the i-th level intermediate reference line; where, i greater than or equal to 2, and i is less than or equal to N-1; the axial distance is the distance along the first axis or the second axis; the first axis is perpendicular to the second axis.
  • the wiring quality detection device may start from determining the second-level intermediate reference line, and determine the connection point whose axial distance is less than the preset threshold value of the i-th level among the i-1-th level connection points as the i-level connection point , and determine the i-th level intermediate reference line based on the i-th level connection point.
  • i is greater than or equal to 2, and i is less than or equal to N-1;
  • the axial distance is the distance along the first axis or the second axis, and the first axis is perpendicular to the second axis.
  • the wiring quality detection device may continue to determine the i+1th level connection point and the i+1th level intermediate reference line until the Nth level connection point and the Nth level intermediate reference line are determined, In this way, N-level connection points and N-level intermediate reference lines are obtained.
  • each level of connection points and each level of intermediate reference lines determine the expected connections of each level, so as to determine the expected connections of N levels.
  • the wiring quality detection device can determine the expected connection line of each level based on each level of connection points and each level of intermediate reference lines in the N-level connection points and N-level intermediate reference lines, so as to determine the N-level expected connection Wire.
  • connection point and N-level expected connections form an expected topology corresponding to each signal to be detected in the set of signals to be detected.
  • the wiring quality detection device may form at least one connection point and N-level expected connections into an expected topology structure corresponding to each signal to be detected in the set of signals to be detected.
  • the wiring quality detection device classifies all the connection points according to the axial distance between the connection points, and determines N-level expected connection lines step by step, which can reduce the total length of the expected connection lines. At the same time, the determined expected connection lines The lines are also more in line with the design habits in actual wiring, so that unreasonable wiring can be judged more accurately.
  • S304 shown in FIG. 8 may be implemented through S3041 to S3043, which will be described in conjunction with each step.
  • the wiring quality detection device may first determine the N-level expected connection line based on the N-level connection point and the N-level intermediate reference line.
  • the wiring quality inspection device may start from the N-1th level expected connection, and determine the jth level expected Connection; wherein, j is greater than or equal to 2, and j is less than or equal to N-1.
  • the wiring quality inspection device may continue to determine the j-1th level of expected connection until the first level of expected connection is determined, so as to determine the N-level expected connection.
  • the wiring quality detection device may first determine the expected connection of the Nth level, and then determine the expected connection of the upper level step by step until the expected connection of the first level is determined, thereby completing the determination of the expected connection of the Nth level. Wire. Since the expected connection includes the connection between the reference lines from the intermediate reference line of each level to the intermediate reference line of the previous level, the reverse order determination can effectively ensure that the connection between the reference lines will not be missed.
  • S301 shown in FIG. 8 may be implemented through S3011-S3012, which will be described in conjunction with each step.
  • the wiring quality detection device may determine two first-level edge connection points that are farthest along the first axial direction among the first-level connection points. As shown in FIG. 2 , p3 and p7 are the two farthest first-level edge connection points along the Y axis (ie, the first axis).
  • the wiring quality detection device after the wiring quality detection device determines the two first-level edge connection points, it can pass through the midpoint of the line connecting the two first-level edge connection points, and determine the first-level intermediate reference along the second axis Wire.
  • L3 is the midpoint of the line passing through p3 and p7, and is the first-level intermediate reference line along the X axis (ie, the second axis).
  • S302 shown in FIG. 8 may be implemented through S3021-S3022, which will be described in conjunction with each step.
  • the wiring quality detection device may determine the connection point whose axial distance is smaller than the preset threshold value of the i-th level among the i-1-th level connection points as the i-th level connection point , and then determine the two ith-level edge connection points that are farthest along the first axis among the i-level connection points.
  • the wiring quality detection device determines the two i-th level edge connection points, it can pass through the midpoint of the connection line between the two i-th level edge connection points, and determine the i-th level intermediate reference along the second axis Wire. In this way, the Nth level intermediate reference line can be determined sequentially.
  • S304 shown in FIG. 8 may be implemented through S3044-S3046, which will be described in conjunction with each step.
  • the wiring quality detection device can connect the first connection point of each level to its corresponding intermediate reference of each level The vertical foot of the line is obtained to obtain the first sub-expected connection line corresponding to the first connection point; wherein, the preset distance condition corresponding to each level of connection point is that the axial distance is less than the preset threshold of the next level.
  • connection point For the second connection point that satisfies the preset distance condition among the connection points of each level of N-level connection points, connect the common vertical line between the intermediate reference line of the level corresponding to the second connection point of each level and the intermediate reference line of the next level A line segment to obtain a second sub-expected connection corresponding to the second connection point; wherein, the first sub-expected connection and the second sub-expected connection are used as each level of the expected connection.
  • the wiring quality detection device can connect the middle reference line of the level corresponding to the second connection point of each level to The public vertical line segment of the intermediate reference line of the next level obtains the second sub-expected connection line corresponding to the second connection point.
  • the first sub-expected connection and the second sub-expected connection serve as each level of expected connection.
  • the wiring quality detection device completes the above-mentioned process sequentially until the connection of the N-level connection points is completed, and N-level expected connection lines can be determined.
  • the N-level expected connections can be determined step by step by the wiring quality detection device, which can reduce the total length of the expected connections. Accurately determine unreasonable wiring.
  • S204 shown in FIG. 7 may be implemented through S401 to S403 shown in FIG. 9 , which will be described in conjunction with each step.
  • the wiring quality detection device may first determine at least one actual wiring pattern connected to the at least one connection point in the layout of the wiring.
  • the actual wiring pattern represents the metal wires electrically connecting each connection point in the layout.
  • S402. Determine the category of each actual wiring pattern in the at least one actual wiring pattern, and simplify the correspondence of each actual wiring pattern to obtain at least one actual connection line corresponding to the at least one actual wiring pattern.
  • the wiring quality detection device may first determine the category of each actual wiring pattern, and then simplify the correspondence of each actual wiring pattern according to the corresponding category, so as to obtain at least one actual wiring pattern At least one actual connection line corresponding to the graph.
  • connection point and at least one actual connection form a wiring result topology corresponding to each signal to be detected in the set of signals to be detected.
  • the wiring quality detection device may form at least one connection point and at least one actual connection to form a wiring result topology corresponding to each signal to be detected.
  • S402 shown in FIG. 9 may be implemented through S4021 to S4024, which will be described in conjunction with each step.
  • the categories of actual wiring graphics may include: rectangles, paths and polygons.
  • the wiring quality detection device can determine that each actual wiring pattern belongs to one of rectangles, paths and polygons.
  • any actual wiring pattern belongs to a rectangle, use the perpendicular line of the short side of the rectangle in the actual wiring pattern as at least one corresponding actual connection line.
  • the wiring quality detection device may use the perpendicular line of the short side of the rectangle in the actual wiring pattern as the corresponding at least one actual connection line.
  • the actual wiring pattern G1 is a rectangle, and the wiring quality detection device may use the perpendicular line a of the short side of the rectangle in G1 as the actual connection line corresponding to G1 .
  • any actual wiring pattern belongs to the path, connect the center points of the actual wiring pattern along the axis of the path as at least one corresponding actual connection line.
  • the wiring quality detection device determines that any actual wiring pattern belongs to a path, it can connect the center points of the actual wiring pattern along the axis of the path as at least one corresponding actual connection line. As shown in FIG. 4B , the actual wiring pattern G2 belongs to the path, and the wiring quality detection device can connect the center points along the axis of the path in G2 to obtain the actual connection lines b, c and d corresponding to G2.
  • any actual wiring pattern belongs to a polygon, which indicates that the actual wiring pattern is connected to the through-layer hole connection line, use the perpendicular line of the layer through-hole connection line in the actual wiring pattern as the corresponding at least one actual connection, so as to obtain at least one actual connection corresponding to at least one actual wiring pattern.
  • the wiring quality detection device determines that any actual wiring pattern belongs to a polygon, it can use the perpendicular line of the layer through-hole connection line in the actual wiring pattern as the corresponding at least one actual connection line, so as to obtain at least At least one actual connection corresponding to an actual wiring pattern.
  • belonging to a polygon represents that the actual wiring pattern is connected to a through-layer hole connection line.
  • the actual wiring patterns G3 and G4 belong to polygons; for G3, the wiring quality detection device can use the vertical line g of the layer through hole connection line j as the actual connection line corresponding to G3; for G4, the wiring quality detection device The device may use the vertical line i of the layer through hole connection line k as the actual connection line corresponding to G4.
  • the wiring quality detection device simplifies the actual wiring pattern according to its type, and the obtained actual wiring is more in line with the design concept and habits of the layout layout design, and can more accurately reflect the electrical meaning of the layout layout design, thereby Can get more accurate routing result topology.
  • S202 shown in FIG. 7 may be implemented through S2021 to S2023 shown in FIG. 10 , which will be described in conjunction with each step.
  • connection object identifier corresponding to each signal to be detected in the wired circuit diagram.
  • the wiring quality detection device may first obtain at least one connection object identifier corresponding to each signal to be detected in the wired circuit diagram.
  • connection object identifier is a symbol of an electrical connection object in the wired circuit diagram, and represents a module (instance) with a specific function in the circuit.
  • Any connection object identifier in the routed circuit diagram has a corresponding connection object in the routed layout diagram.
  • the connection object is a graph in the wired layout, which represents that the corresponding physical area in the chip can form the module and realize the function of the module.
  • the wiring quality detection device may match at least one connection object corresponding to the at least one connection object identifier in the wired layout.
  • the wiring quality detection device may determine at least one connection point corresponding to each signal to be detected in the wired layout based on the at least one connection object.
  • connection objects are electrically connected through the connection point, and the determination of the connection point means the determination of the end point through which the signal to be detected passes through the connection line.
  • the wiring quality detection device determines at least one connection point based on the wired circuit diagram, which can more comprehensively determine the required connection point and avoid omission.
  • S102 shown in FIG. 1 may be implemented through S1021-S1022, which will be described in conjunction with each step.
  • the wiring quality detection device may first calculate the expected wiring length of the expected topology and the actual wiring length of the wiring result topology.
  • the wiring quality detection device may compare the actual wiring length with the expected wiring length to obtain a topology structure comparison result.
  • the wiring quality detection device compares the actual wiring length with the expected wiring length, which helps to adjust the actual wiring length and appropriately reduce the actual wiring length, thereby reducing the occupation of the processing area, reducing the chip size, and saving Processing costs.
  • the actual routing length includes: the actual routing total length; the actual routing total length is the total length of all actual wires in the routing result topology; the expected routing length includes: the expected routing total length; the expected routing total length The length is the total length of all expected connections in the expected topology; the above S1022 can be implemented through S1023, which will be described in conjunction with each step.
  • the wiring quality detection device may use the ratio of the actual total length of the wiring to the expected total length of the wiring as the result of the topology structure comparison.
  • the actual wiring length further includes: at least one actual wiring layer length; at least one actual wiring layer length is the actual wiring length corresponding to at least one metal layer in the routing result topology; the expected wiring The length also includes: at least one expected wiring layer length; at least one expected wiring layer length is the expected wiring length corresponding to at least one metal layer; the above S1022 can be implemented through S1024, which will be described in conjunction with each step.
  • the wiring quality detection device may compare each actual wiring layer length in at least one actual wiring layer length with the corresponding expected wiring layer length in at least one expected wiring layer length, and obtain at least one The metal layer ratio is used as a result of topology comparison.
  • the wiring quality detection device adopts various comparison methods such as total length comparison and layered length comparison, which can more comprehensively evaluate the actual wiring, thereby helping designers to optimize the actual wiring to an optimal solution.
  • S105 shown in FIG. 5 may be implemented through S1051 to S1053, which will be described in conjunction with each step.
  • S1051. Receive a selection operation of a signal set to be detected, and determine a signal to be displayed.
  • the wiring quality detection device after the wiring quality detection device generates the quality detection report, it can receive the selection operation of the signal set to be detected by the designer, and determine the signal to be displayed.
  • the wiring quality detection device after the wiring quality detection device determines the signal to be displayed, it can determine the detection result corresponding to the signal to be displayed based on the quality detection report, wherein the detection result can represent whether the signal to be displayed has unreasonable wiring.
  • the wiring quality detection device can highlight the unreasonable wiring in the layout layout, for example, highlight the unreasonable wiring, as shown in Figure 6 shown. This completes the display of inspection results in the routed layout.
  • the wiring quality detection device receives the designer's viewing and selection operation, and highlights the unreasonable wiring in the wired layout, which can help the designer to modify and improve the unreasonable wiring, so as to optimize the actual wiring to the optimal solution .
  • FIG. 11 is a schematic flowchart of an optional wiring quality detection method provided by an embodiment of the present disclosure, which will be described in conjunction with the steps shown in FIG. 11 .
  • the wiring quality detection device first obtains a list of signals to be detected.
  • the list of signals to be detected includes all signals to be detected that need to be inspected for wiring quality.
  • the wiring quality detection device may extract the topology structure of the wiring result corresponding to each signal to be detected in the wiring layout.
  • the wiring quality detection device will generate an expected topology structure corresponding to each signal to be detected.
  • the wiring quality detection device analyzes and compares the two topological structures to determine whether the automatic wiring meets expectations.
  • the wiring quality detection device determines that the automatic wiring of any signal to be detected does not meet design expectations, it generates a wiring error report for the signal to be detected, and reports that the signal to be detected does not meet the expected type and wiring position.
  • the types that do not meet expectations may include: the total length of the wiring exceeds the limit, and the length of the layered wiring exceeds the limit.
  • the wiring quality detection device can visualize the detection result, so that it is easy for the designer to modify and improve.
  • S502 shown in FIG. 11 may be implemented through S5021 to S5027 shown in FIG. 12 , which will be described in conjunction with each step.
  • the wiring quality detection device can capture all instances and connections of the signal to be detected in the wiring circuit diagram corresponding to the layout.
  • the routed circuit diagram exactly matches the name of the corresponding instance in the routed layout.
  • the wiring quality detection device can match the corresponding instance in the layout, and find the pins that need to be connected.
  • the wiring quality detection device can obtain the actual wiring pattern of the pin connection and the actual wiring pattern of the connection through CT (Contect, connection hole) or Via (through hole) in the already wired layout. .
  • the wiring quality detection device may extract the obtained actual wiring pattern for subsequent simplification and calculation.
  • the wiring quality detection device can read all the actual wiring patterns obtained in S5024.
  • the wiring quality detection device can classify the actual wiring patterns:
  • the actual wiring graphics can be divided into rectangles (Rectangle), paths (Path) and polygons (Polygon), and corresponding simplifications.
  • the simplification method can refer to Figure 4A, Figure 4B and Figure 4C .
  • the wiring quality detection device may form a topology structure of a wiring result by combining the actual connection obtained in S5026 with the connection points obtained in S5022.
  • the wiring quality detection device can calculate the length of each actual wiring pattern, and summarize the total wiring length and the wiring layer length corresponding to the signal to be detected, so that the calculation result of the physical connection of the automatic wiring is obtained; wherein, the total wiring length That is, the length of all actual connections corresponding to the signal to be detected, and the wiring layer length is the length of the actual connections corresponding to each metal layer obtained by adding the actual connections corresponding to different metal layers.
  • S503 shown in FIG. 11 may be implemented through S5031 to S5035 shown in FIG. 13 , which will be described in conjunction with each step.
  • the wiring quality detection device may obtain the position coordinates of all pins connected by signals to be detected in the layout layout.
  • I1, I2, I3, I4, I5, I6 and I7 represent the instance to be connected to the signal to be detected;
  • p1, p2, p3, p4, p5, p6 and p7 represent the pin to be connected to the signal to be detected,
  • the position coordinates of all pins can be obtained.
  • the wiring quality detection device can calculate the maximum and minimum Y coordinates of all pin coordinates. As shown in FIG. 2 , the Y coordinates of p3 and p7 are the maximum and minimum Y coordinates, represented as L1 and L2. The wiring quality inspection device can obtain the middle parallel line L3 between L1 and L2, and L3 is the middle reference line.
  • the wiring quality inspection device may establish a connection from a pin to an intermediate reference line, such as y1 and y2 shown in FIG. 2 .
  • the wiring quality inspection device can separately calculate the intermediate sub-base line and connection line of each group, which is more in line with the layout design expected.
  • p3 and p4 can form a group
  • p5, p6 and p7 can form another group
  • the wiring quality inspection device can calculate the maximum and minimum Y coordinates of the pin coordinates in the group to obtain the intermediate sub-baselines L6 and L7 ; Then establish a separate group of connection lines ys1 and ys2 from the pin to the sub-baseline, and ys3, ys4, and ys5; finally, establish a connection yb1 and yb2 from the middle sub-baseline L6 and L7 to the middle baseline L3.
  • the wiring quality detection device can finally generate the connection line in the X direction at the positions of the intermediate reference line and the intermediate sub-reference line, so as to form an expected topology.
  • This expected topology can be used to calculate the total expected wiring length as a baseline for comparison.
  • S504 shown in FIG. 11 may be implemented through S5041 to S5043 shown in FIG. 14 , which will be described in conjunction with each step.
  • the wiring quality detection device may extract the wiring layer lengths corresponding to different metal layers from the length of the actual wiring pattern obtained in S5027.
  • the wiring quality detection device may obtain the limiting conditions for each metal layer in the quality testing, and compare the wiring layer lengths corresponding to different metal layers with the limiting conditions to determine whether the wiring layering length exceeds the limit. If the wiring layer length is greater than the limit value, it is determined that the wiring layer length exceeds the limit.
  • the wiring quality detection device determines that the wiring layer length exceeds the limit, it will generate a layer length wiring error report, and report information such as signal name and corresponding metal layer position.
  • S504 shown in FIG. 11 may be implemented through S5044 to S5046 shown in FIG. 15 , which will be described in conjunction with each step.
  • the wiring quality detection device may extract the total wiring length of all actual wiring lines from the length of the actual wiring pattern obtained in S5027.
  • the wiring quality detection device may compare the total length of the wiring with the limited condition. If the ratio of the total wiring length to the expected value exceeds the limit condition, it is determined that the total wiring length exceeds the expected ratio.
  • the wiring quality detection device determines that the total length of the wiring exceeds the expected ratio, it will generate a total length wiring error report, and report information such as signal name and automatic wiring path.
  • S506 shown in FIG. 11 may be implemented through S5061 to S5065 shown in FIG. 16 , which will be described in conjunction with each step.
  • the wiring quality detection device reads all detection results.
  • the wiring quality detection device after receiving the instruction to open the layout issued by the designer, the wiring quality detection device can read all the detection results corresponding to the layout.
  • the window of the wiring quality detection device displays all signals and corresponding detection results.
  • the wiring quality detection device can display all signals and corresponding detection results in a window for the designer to click and operate.
  • the designer can click on the signal name, so that the wiring quality inspection device can be visualized, and in this way, the designer can be assisted in modifying and improving the layout.
  • the wiring quality detection device can highlight the physical path of unreasonable wiring in the layout, such as the thickened path in FIG. 6 .
  • the direct connections between p21, p22, p23, and p24 are not actual wiring, but are used to help the designer find the location of the connection point.
  • the designer Layout modifies the layout layout.
  • the designer can re-layout the unreasonable wiring to improve it.
  • the designer after the designer completes the modification, he can click the signal name here to perform the wiring quality detection method of S501-S505 again. If the signal passes the detection, that is, there is no longer unreasonable wiring, the wiring quality detection device will pop up a "pass" prompt and cancel all highlighting of the signal. If the signal does not pass the test, that is, there is still unreasonable wiring, the wiring quality testing device pops up the unreasonable item information of the test result, and highlights the unreasonable wiring of the signal again to prompt the designer to continue to modify.
  • the wiring quality detection method proposed by the embodiment of the present disclosure establishes an expected layout topology, and compares it with the layout automatic wiring results. If the use of the specified metal layer exceeds the limit or the wiring path is unreasonable, report The signal name that needs to be corrected, and the corresponding connection relationship and location information. Furthermore, according to the generated inspection report, the assistant designer can revise the signal wiring. In this way, problems can be found in time before the simulation stage, effectively saving the time of manual inspection, thereby shortening the project development cycle. That is to say, the embodiments of the present disclosure achieve the following effects: realize the automatic and efficient detection of layout automatic wiring quality, and can detect problems such as unreasonable automatic wiring and overuse of specified metal layers early, helping designers to extract, modify and improve, and shorten chip time. Development cycle; automatic wiring quality inspection results are visualized, assisting layout designers to quickly modify and improve.
  • FIG. 17 is a schematic structural diagram of an option of a wiring quality detection device provided by an embodiment of the present disclosure. As shown in FIG. 17 , the embodiment of the present disclosure also provides a wiring quality detection device 800, including: a determining unit 804, a comparing unit 805, and a generating unit 806, wherein:
  • the determining unit 804 is configured to determine, based on the wired layout, a wiring result topology and an expected topology corresponding to each signal to be detected in the set of signals to be detected; the expected topology is based on the position of the connection point in the wired layout obtained;
  • the comparison unit 805 is configured to compare the wiring result topology with the expected topology for each signal to be detected, and obtain a topology comparison result corresponding to each signal to be detected;
  • the determination unit 804 is further configured to determine that the corresponding signal to be detected has a detection result of unreasonable wiring if the topology comparison result is greater than a preset threshold;
  • the generating unit 806 is configured to generate a quality detection report based on the detection result of each signal to be detected.
  • the wiring quality inspection device 800 further includes: a display unit 807, wherein:
  • the display unit 807 is configured to display a detection result in the wired layout based on the quality detection report.
  • the wiring quality detection device 800 further includes: an acquisition unit 808, wherein:
  • the obtaining unit 808 is configured to obtain a wired circuit diagram corresponding to the wired layout.
  • the determining unit 804 is further configured to determine at least one connection point corresponding to each signal to be detected based on the wired layout and the wired circuit diagram; based on the at least one connection point corresponding to each signal to be detected point, from the wired layout, determine the expected topology corresponding to each signal to be detected in the set of signals to be detected; and, based on at least one connection point corresponding to each signal to be detected, from the already In the wiring layout, a wiring result topology corresponding to each signal to be detected in the set of signals to be detected is determined.
  • the determining unit 804 is further configured to use the at least one connection point corresponding to each signal to be detected as a first-level connection point in the wired layout; based on The first-level connection point is determined as the first-level intermediate reference line; the connection point whose axial distance is less than the i-level preset threshold among the i-1-th level connection points is determined as the i-level connection point; based on the i-th level The i-level connection point determines the i-level intermediate reference line; wherein, i is greater than or equal to 2, and i is less than or equal to N-1; the axial distance is the distance along the first axis or the second axis; the first One axis is perpendicular to the second axis; continue to determine the i+1th level connection point and the i+1th level intermediate reference line until the Nth level connection point and the Nth level intermediate reference line are determined ; Based on the N-level connection points and the N-level intermediate reference lines, each
  • the determination unit 804 is further configured to determine the Nth-level expected connection based on the Nth-level connection point and the N-level intermediate reference line; based on the j-th level connection point , the j-th level intermediate reference line and the j+1-th level expected connection, determine the j-th level expected connection; wherein, j is greater than or equal to 2, and j is less than or equal to N-1; proceed to the j-1 level expected connection until the first-level expected connection is determined, so that the N-level expected connection is determined.
  • the determination unit 804 is further configured to determine two first-level edge connection points that are farthest along the first axial direction among the first-level connection points; A midpoint of a line connecting two first-level edge connection points along the second axis determines the first-level middle reference line.
  • the determination unit 804 is further configured to determine the two i-th-level edge connection points that are farthest along the first axial direction among the i-th-level connection points; A midpoint of a line connecting two i-th-level edge connection points along the second axis determines the i-th-level intermediate reference line.
  • the determining unit 804 is further configured to connect the first connection of each level for the first connection point in each level of connection points of N levels of connection points that does not meet the preset distance condition Point to the vertical foot of its corresponding intermediate reference line of each level to obtain the first sub-expected connection line corresponding to the first connection point; for the second connection that satisfies the preset distance condition in each level of connection points of N-level connection points point, connecting the middle reference line of the level corresponding to the second connection point of each level to the common vertical line segment of the middle reference line of the next level to obtain the second sub-expected connection line corresponding to the second connection point; wherein, The first sub-expected connection and the second sub-expected connection are used as each level of expected connection; until the connection of N-level connection points is completed, the N-level expected connection is determined.
  • the determining unit 804 is further configured to, in the routed layout, determine at least one actual wiring pattern connected to the at least one connection point; determine the at least one actual wiring pattern class of each actual wiring pattern, and simplify the correspondence of each actual wiring pattern to obtain at least one actual connection line corresponding to the at least one actual wiring pattern; the at least one connection point and the at least one actual wiring pattern
  • the wiring forms the topology structure of the wiring result corresponding to each signal to be detected in the set of signals to be detected.
  • the determination unit 804 is further configured to determine that each actual wiring pattern belongs to one of rectangle, path and polygon; if any actual wiring pattern belongs to a rectangle, then the actual The perpendicular line of the short side of the rectangle in the wiring pattern is used as at least one corresponding actual connection line; or, if any actual wiring pattern belongs to the path, connect the center point of the actual wiring pattern along the axis of the path as the corresponding at least one An actual connection line; or, if any actual wiring pattern belongs to a polygon, indicating that the actual wiring pattern is connected to the layer through-hole connection line, then the sag of the layer through-hole connection line in the actual wiring pattern line as the corresponding at least one actual connection, so that at least one actual connection corresponding to the at least one actual wiring pattern is obtained.
  • the obtaining unit 808 is further configured to obtain at least one connection object identifier corresponding to each signal to be detected in the wired circuit diagram; in the wired layout diagram, Match at least one connection object corresponding to the at least one connection object identifier.
  • the determining unit 804 is further configured to determine the at least one connection point corresponding to each signal to be detected based on the at least one connection object in the wired layout.
  • the wiring quality detection device 800 further includes: a calculation unit 809, wherein:
  • the calculation unit 809 is configured to separately calculate the actual wiring length corresponding to the wiring result topology and the expected wiring length corresponding to the expected topology.
  • the comparison unit 805 is further configured to compare the actual wiring length with the expected wiring length to obtain the topology structure comparison result.
  • the actual routing length includes: the total actual routing length; the actual routing total length is the total length of all actual connections in the routing result topology; the expected routing length includes: The expected total length of wiring; the expected total length of wiring is the total length of all expected wiring in the expected topology; the comparison unit 805 is further configured to compare the actual total length of wiring with the expected total length of wiring The ratio is used as the result of the topology comparison.
  • the actual wiring length further includes: at least one actual wiring layer length; the at least one actual wiring layer length is the actual wiring length corresponding to at least one metal layer in the wiring result topology
  • the wiring length; the expected wiring length further includes: at least one expected wiring layer length; the at least one expected wiring layer length is the expected wiring length corresponding to the at least one metal layer; the comparison unit 805, It is also configured to compare each actual wiring layer length in the at least one actual wiring layer length with the corresponding expected wiring layer length in the at least one expected wiring layer length, and obtain at least one metal layer ratio as The topology comparison results.
  • the determining unit 804 is further configured to receive a selection operation on the set of signals to be detected, determine the signal to be displayed; and determine the signal corresponding to the signal to be displayed based on the quality inspection report. Test results.
  • the display unit 807 is further configured to highlight the unreasonable wiring in the already-wired layout if the detection result indicates that the signal to be displayed has unreasonable wiring, thereby completing the The detection results are displayed in the wiring layout.
  • FIG. 18 is a schematic structural diagram of an optional wiring quality detection device provided by an embodiment of the present disclosure.
  • the hardware entities of the wiring quality detection device 800 include: a processor 801, a communication interface 802 and memory 803, wherein:
  • the processor 801 generally controls the overall operation of the wiring quality inspection device 800 .
  • the communication interface 802 can enable the wiring quality detection device 800 to communicate with other devices or devices through the network.
  • the memory 803 is configured to store instructions and applications executable by the processor 801, and can also cache data to be processed or processed by each module in the processor 801 and the wiring quality detection device 800 (for example, image data, audio data, voice communication Data and video communication data), can be realized by flash memory (FLASH) or random access memory (Random Access Memory, RAM).
  • timing task execution method is implemented in the form of software function modules and sold or used as an independent product, it can also be stored in a computer-readable storage medium.
  • the computer software products are stored in a storage medium, and include several instructions to make
  • the wiring quality detection apparatus 800 (which may be a personal computer, a server, or a network device, etc.) executes all or part of the methods described in various embodiments of the present disclosure.
  • the aforementioned storage medium includes: various media that can store program codes such as U disk, mobile hard disk, read-only memory (Read Only Memory, ROM), magnetic disk or optical disk.
  • embodiments of the present disclosure are not limited to any specific combination of hardware and software.
  • an embodiment of the present disclosure provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps in the method corresponding to the above-mentioned wiring quality detection device are implemented.
  • the disclosed devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical or other forms of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may be used as a single unit, or two or more units may be integrated into one unit; the above-mentioned integration
  • the unit can be realized in the form of hardware or in the form of hardware plus software functional unit.
  • the embodiments of the present disclosure provide a wiring quality detection method, device, and storage medium, which can determine the wiring result topology and expected topology corresponding to each signal to be detected in the signal set to be detected based on the layout of the wiring; Then, for each signal to be detected, the topology structure of the wiring result is compared with the expected topology structure to obtain the topology comparison result corresponding to each signal to be detected; then the topology comparison result is judged. If the threshold is set, it is determined that the corresponding signal to be detected has a detection result of unreasonable wiring; then, based on the detection result of each signal to be detected, a quality detection report is generated. In this way, the automatic wiring results can be detected by running the program, without the need for designers to search and verify one by one, quickly complete the wiring quality detection, realize the automation of wiring quality detection, and save detection time.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

一种布线质量检测方法、装置及存储介质;方法包括:基于已布线版图,确定待检测信号集合中每个待检测信号对应的布线结果拓扑结构和预期拓扑结构;针对每个待检测信号,将布线结果拓扑结构和预期拓扑结构进行对比,得到每个待检测信号对应的拓扑结构对比结果;若拓扑结构对比结果大于预设阈值,则确定对应的该待检测信号具有不合理布线的检测结果;基于每个待检测信号的检测结果,生成质量检测报告。

Description

一种布线质量检测方法、装置及存储介质
相关申请的交叉引用
本公开基于申请号为202111049249.8、申请日为2021年09月08日、发明名称为“一种布线质量检测方法、装置及存储介质”的中国专利申请提出,并要求该中国专利申请的优先权,该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及集成电路设计领域,尤其涉及一种布线质量检测方法、装置及存储介质。
背景技术
随着半导体技术的不断发展,集成电路中的电子元件数量不断增多,内部结构越来越复杂,这给集成电路的设计带来了更大的挑战。
在集成电路版图设计开发中,完成布线设计后,需要对布线质量进行检测。若通过人工检查和后仿验证来对布线质量进行检测,则花费的检测时间过长。
发明内容
本公开实施例期望提出一种布线质量检测方法、装置及存储介质,能够快速完成布线质量检测,实现布线质量检测自动化,节省检测时间。
本公开的技术方案是这样实现的:
本公开实施例提供一种布线质量检测方法,所述方法包括:
基于已布线版图,确定待检测信号集合中每个待检测信号对应的布线结果拓扑结构和预期拓扑结构;所述预期拓扑结构是基于所述已布线版图中的连接点位置而得到的;
针对所述每个待检测信号,将所述布线结果拓扑结构和所述预期拓扑结构进行对比,得到所述每个待检测信号对应的拓扑结构对比结果;
若所述拓扑结构对比结果大于预设阈值,则确定对应的该待检测信号具有不合理布线的检测结果;
基于所述每个待检测信号的所述检测结果,生成质量检测报告。
本公开实施例还提供一种布线质量检测装置,包括:
确定单元,配置为基于已布线版图,确定待检测信号集合中每个待检测信号对应的布线结果拓扑结构和预期拓扑结构;所述预期拓扑结构是基于所述已布线版图中的连接点位置而得到的;
对比单元,配置为针对所述每个待检测信号,将所述布线结果拓扑结构和所述预期拓扑结构进行对比,得到所述每个待检测信号对应的拓扑结构对比结果;
所述确定单元,还配置为若所述拓扑结构对比结果大于预设阈值,则确定对应的该待检测信号具有不合理布线的检测结果;
生成单元,配置为基于所述每个待检测信号的所述检测结果,生成质量检测报告。
本公开实施例还提供一种布线质量检测装置,包括:
存储器,用于存储可执行指令;
处理器,用于执行所述存储器中存储的可执行指令时,实现上述方案中的布线质量检测方法。
本公开实施例还提供一种存储介质,存储有可执行指令,用于引起处理器执行时,实现上述方案中的布线质量检测方法。
由此可见,本公开实施例提供了一种布线质量检测方法、装置及存储介质,能够基于已布线版图,确定待检测信号集合中每个待检测信号对应的布线结果拓扑结构和预期拓扑结构;而后,针对每个待检测信号,将布线结果拓扑结构和预期拓扑结构进行对比,得到每个待检测信号对应的拓扑结构对比结果;再对拓扑结构对比结果进行判定,若拓扑结构对比结果大于预设阈值,则确定出对应的该待检测信号具有不合理布线的检测结果;而后,基于每个待检测信号的检测结果,生成质量检测报告。这样,通过运行程序即可对自动布线结果进行检测,而不需要设计人员逐一查找验证,快速地完成了布线质量检测,实现了布线质量检测自动化,节省了检测时间。
附图说明
图1为本公开实施例提供的一种布线质量检测方法的流程图一;
图2为本公开实施例中预期拓扑结构的示例图;
图3A为本公开实施例中获取实际布线图形的示意图一;
图3B为本公开实施例中获取实际布线图形的示意图二;
图3C为本公开实施例中获取实际布线图形的示意图三;
图4A为本公开实施例中实际布线图形的类型示意图一;
图4B为本公开实施例中实际布线图形的类型示意图二;
图4C为本公开实施例中实际布线图形的类型示意图三;
图5为本公开实施例提供的一种布线质量检测方法的流程图二;
图6为本公开实施例中显示检测结果的效果图;
图7为本公开实施例提供的一种布线质量检测方法的流程图三;
图8为本公开实施例提供的一种布线质量检测方法的流程图四;
图9为本公开实施例提供的一种布线质量检测方法的流程图五;
图10为本公开实施例提供的一种布线质量检测方法的流程图六;
图11为本公开实施例提供的一种布线质量检测方法的流程图七;
图12为本公开实施例提供的一种布线质量检测方法的流程图八;
图13为本公开实施例提供的一种布线质量检测方法的流程图九;
图14为本公开实施例提供的一种布线质量检测方法的流程图十;
图15为本公开实施例提供的一种布线质量检测方法的流程图十一;
图16为本公开实施例提供的一种布线质量检测方法的流程图十二;
图17为本公开实施例提供的一种布线质量检测装置的结构示意图一;
图18为本公开实施例提供的一种布线质量检测装置的结构示意图二。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚,下面结合附图和实施例对本公开的技术方案进一步详细阐述,所描述的实施例不应视为对本公开的限制,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例,都属于本公开保护的范围。
在以下的描述中,涉及到“一些实施例”,其描述了所有可能实施例的子集,但是可以理解,“一些实施例”可以是所有可能实施例的相同子集或不同子集,并且可以在 不冲突的情况下相互结合。
如果发明文件中出现“第一/第二”的类似描述则增加以下的说明,在以下的描述中,所涉及的术语“第一\第二\第三”仅仅是区别类似的对象,不代表针对对象的特定排序,可以理解地,“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序,以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
除非另有定义,本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的,不是旨在限制本公开。
在集成电路版图设计开发中,版图中包含了大量的信号线,例如,DRAM(Dynamic Random Access Memory,动态随机存取存储器)芯片版图的Peripheral(外围)层中包含了大于15000条的信号线。因此,需要借助自动布线工具完成大量信号线的连线,即进行大量的自动布线,才能满足项目期限的要求。
然而,自动布线无法完全符合设计要求,例如,布线线路过长、关键信号所使用的大阻值金属线过长等,从而会导致对应信号失效。因此,在完成了自动布线后,必须对版图进行布线质量检测。
相关技术中,只有通过人工逐个检查和后仿验证等方法,存在周期过长和后期修改困难等问题。
图1是本公开实施例提供的布线质量检测方法的一个可选的流程示意图,将结合图1示出的步骤进行说明。
S101、基于已布线版图,确定待检测信号集合中每个待检测信号对应的布线结果拓扑结构和预期拓扑结构;预期拓扑结构是基于已布线版图中的连接点位置而得到的。
本公开实施例中,布线质量检测装置可以基于已布线版图,分别确定待检测信号集合中每个待检测信号对应的布线结果拓扑结构和预期拓扑结构。其中,预期拓扑结构是基于已布线版图中的连接点位置而得到的。
需要说明的是,集成电路中需要用到多个信号,各信号会各自途径集成电路中的部分连线。因此,在已布线版图中,可以确定待检测信号途径连线对应的实际布线图形。
在本公开实施例中,布线质量检测装置在确定布线结果拓扑结构和预期拓扑结构前,需要先确定待检测信号途经的连接点(pin)。由于已布线版图中可能难以明确显示出待检测信号途经的所有连接对象和连接点,因此,布线质量检测装置可以先获取与已布线版图对应的已布线电路图,进而,基于已布线版图和已布线电路图,确定每个待检测信号对应的至少一个连接点,该过程可以包括以下步骤:
步骤一、在已布线电路图中获取连接对象标识。布线质量检测装置可以先在已布线电路图中获取每个待检测信号对应的至少一个连接对象标识。
需要说明的是,连接对象标识是已布线电路图中电连接对象的符号,表征电路中具有特定功能的模块(instance)。已布线电路图中的任一连接对象标识,在已布线版图中均有对应的连接对象。连接对象为已布线版图中的图形,表征芯片中的对应物理区域能够形成该模块,实现该模块的功能。
步骤二、在已布线版图中匹配连接对象。布线质量检测装置获取了至少一个连接对象标识后,可以在已布线版图中匹配至少一个连接对象标识对应的至少一个连接对象。
步骤三、在已布线版图中确定连接点。布线质量检测装置匹配了至少一个连接对象后,可以基于至少一个连接对象,在已布线版图中确定每个待检测信号对应的至少一个连接点。需要说明的是,连接对象通过连接点进行电连接,确定了连接点即确定了待检测信号途经连线所要经过的端点。
在本公开实施例中,布线质量检测装置在确定了每个待检测信号对应的至少一个连接点后,可以基于该至少一个连接点,在已布线版图中分别确定每个待检测信号对应的预期拓扑结构和布线结果拓扑结构。其中,预期拓扑结构反映了版图布线所希望达到的 结果,而布线结果拓扑结构则反映了版图布线的实际结果。预期拓扑结构可以作为布线结果拓扑结构的标准与参考,用以指导实际版图布线工作。
需要说明的是,本公开实施例中的拓扑结构,是运用点与线这两种图形元素,对版图中的信号线的抽象化描述;其中,用点描述每个待检测信号对应的至少一个连接点,明确这些连接点在已布线版图中的位置;用线描述至少一个连接点之间的布线图形,明确信号线的路径与长度。
在本公开实施例中,布线质量检测装置可以分级确定出N级预期连线(N大于等于1),从而形成预期拓扑结构,预期拓扑结构中包括了至少一个连接点和N级预期连线。该过程可以包括以下步骤:
步骤一、确定N级中间基准线。布线质量检测装置可以在已布线版图中,将至少一个连接点均作为第1级连接点;而后,确定第1级连接点中沿第一轴向距离最远的两个第1级边缘连接点,再经过两个第1级边缘连接点的连线的中点,确定了沿第二轴向第1级中间基准线。
完成了第1级中间基准线的确定后,布线质量检测装置可以将第1级连接点中轴向距离小于第2级预设阈值的连接点确定为第2级连接点;其中,轴向距离为沿第一轴向或第二轴向的距离,第一轴向垂直于第二轴向。进而,布线质量检测装置可以采用类似于确定第1级中间基准线的方法,在第2级连接点中确定出第2级中间基准线,也就是说,布线质量检测装置可以确定第2级连接点中沿第一轴向距离最远的两个第2级边缘连接点,再经过两个第2级边缘连接点的连线的中点,确定了沿第二轴向第2级中间基准线。
完成了第2级中间基准线的确定后,布线质量检测装置可以按照类似的方法确定第3级中间基准线,依次类推,直到确定出第N中间基准线。也就是说,布线质量检测装置可以将第i-1级连接点中轴向距离小于第i级预设阈值的连接点确定为第i级连接点;其中,i大于等于2,且i小于等于N-1。而后,确定第i级连接点中沿第一轴向距离最远的两个第i级边缘连接点,再经过两个第i级边缘连接点的连线的中点,沿第二轴向确定出第i级中间基准线。进而,继续进行第i+1级连接点和第i+1级中间基准线的确定,直到确定出第N级连接点和第N级中间基准线时为止,从而确定出了N级中间基准线。
步骤二、确定N级预期连线。布线质量检测装置可以基于N级连接点和N级中间基准线中,每级连接点和每级中间基准线,确定每级预期连线,从而确定出N级预期连线。
针对N级连接点的每级连接点中不满足预设距离条件的第一连接点,布线质量检测装置可以连接每级的第一连接点到其对应的每级中间基准线的垂足,得到第一连接点对应的第一子预期连线;其中,每级连接点对应的预设距离条件为轴向距离小于下一级预设阈值。针对N级连接点的每级连接点中满足预设距离条件的第二连接点,布线质量检测装置则可以连接每级的第二连接点对应的该级中间基准线到其下一级中间基准线的公垂线段,得到第二连接点对应的第二子预期连线。将第一子预期连线和第二子预期连线作为每级预期连线,直至N级连接点连接完成时,即可确定出N级预期连线。
另一方面,在本公开的一些实施例中,布线质量检测装置在确定了N级中间基准线之后,可以先基于第N级连接点和第N级中间基准线,确定第N级预期连线,再逐级确定上一级预期连线,最终确定第1级预期连线。也就是说,布线质量检测装置可以基于第j级连接点、第j级中间基准线和第j+1级预期连线,确定第j级预期连线,其中,j大于等于2,且j小于等于N-1。而后,继续进行第j-1级预期连线的确定,直到确定出第1级预期连线时为止,从而确定出N级预期连线。
布线质量检测装置可以先基于第N级连接点和第N级中间基准线,确定第N级预期连线。布线质量检测装置可以在第N级连接点中,分别建立每组第N级连接点到对 应的第N级中间基准线的垂线段,得到第N级连接点连线;其中,每组第N级连接点即相互之间的轴向距离均小于第N级预设阈值的连接点。而后,分别连接第N级连接点连线在对应的第N级中间基准线上的垂足,得到第N级基准线连线,从而得到包括第N级连接点连线和第N级基准线连线的第N级预期连线。
在确定出第N级预期连线后,布线质量检测装置可以分别建立每组第N-1级连接点到对应的第N-1级中间基准线的垂线段,以及第N级基准线连线到对应的第N-1级中间基准线的公垂线段,得到第N-1级连接点连线;其中,每组第N-1级连接点即相互之间的轴向距离均小于第N-1级预设阈值的连接点。而后,分别连接第N-1级连接点连线在对应的第N-1级中间基准线上的垂足,得到第N-1级基准线连线,从而得到包括第N-1级连接点连线和第N-1级基准线连线的第N-1级预期连线。按照该过程依次递推,直到确定出第1级预期连线。也就是说,布线质量检测装置可以分别建立每组第j级连接点到对应的第j级中间基准线的垂线段,以及第j+1级基准线连线到对应的第j级中间基准线的公垂线段,得到第j级连接点连线;其中,每组第j级连接点即相互之间的轴向距离均小于第j级预设阈值的连接点。而后,分别连接第j级连接点连线在对应的第j级中间基准线上的垂足,得到第j级基准线连线,从而得到包括第j级连接点连线和第j级基准线连线的第j级预期连线。
在本公开的一些实施例中,N=2。图2是本公开实施例提供的预期拓扑结构的一个可选的示例图,如图2所示,至少一个连接点包括了连接点p1、p2、p3、p4、p5、p6和p7,其分别对应于连接对象I1、I2、I3、I4、I5、I6和I7。布线质量检测装置可以首先将连接点p1、p2、p3、p4、p5、p6和p7均确认为第1级连接点,而后,在其中确定出沿Y轴向最远的两个第1级边缘连接点p3和p7。第1级边缘线L1和L2沿X轴向延伸,分别经过p3和p7,表征了p3和p7在Y轴向的位置。布线质量检测装置可以根据p3和p7在Y轴向的位置,确定出第1级中间基准线L3,其中,L3是L1和L2的中间平行线,L3到L1和L2的距离相等。
继续参考图2,在确定出第1级中间基准线L3后,布线质量检测装置可以在第1级连接点p1、p2、p3、p4、p5、p6和p7中,确认轴向距离小于第2级预设阈值的第2级连接点。例如,若第2级预设阈值为150,p3和p4在X轴向和Y轴向的轴向距离均小于150,则将p3和p4确定为一组第2级连接点;p5、p6和p7中任意两点在X轴向和Y轴向的轴向距离均小于150,则将p5、p6和p7确定为另一组第2级连接点;也就是说,每组第2级连接点都处在150×150的范围内。
继续参考图2,确定了每组第2级连接点后,布线质量检测装置可以分别确定每组第2级连接点对应的第2级中间基准线。例如,针对p3和p4这一组第2级连接点,布线质量检测装置首先确定出沿Y轴向最远的两个第2级边缘连接点,由于该组第2级连接点只有两个成员,因此直接将其分别作为第2级边缘连接点;则对应的第2级边缘线L1和L4沿X轴向延伸(L1亦为第1级边缘线),分别经过p3和p4,表征了p3和p4在Y轴向的位置;布线质量检测装置可以根据p3和p4在Y轴向的位置,确定出与该组第2级连接点对应的第2级中间基准线L6,其中,L6是L1和L4的中间平行线,L6到L1和L4的距离相等。又如,针对p5、p6和p7这一组第2级连接点,布线质量检测装置首先确定出沿Y轴向最远的两个第2级边缘连接点p5和p7;则对应的第2级边缘线L5和L2沿X轴向延伸(L2亦为第1级边缘线),分别经过p5和p7,表征了p5和p7在Y轴向的位置;布线质量检测装置可以根据p5和p7在Y轴向的位置,确定出与该组第2级连接点对应的第2级中间基准线L7,其中,L7是L5和L2的中间平行线,L7到L5和L2的距离相等。
继续参考图2,在完成了第1级中间基准线和第2级中间基准线的确定后,布线质量检测装置可以做每级连接点到对应的每级中间基准线的垂线段;即分别做p1和p2到L3的垂线段y1和y2,分别做p3和p4到L6的垂线段ys1和ys2,分别做p5、p6和p7 到L7的垂线段ys3、ys4和ys5。同时,布线质量检测装置可以分别做第2级中间基准线L6和L7到第1级中间基准线L3的公垂线段yb1和yb2。而后,布线质量检测装置可以分别连接所有垂线段和公垂线段在每级中间基准线上的垂足;即连接ys1和ys2在L6上的垂足,得到x1;以及,连接y1、y2、yb1和yb2在L3上的垂足,得到x2;以及,连接ys3、ys4和ys5在L7上的垂足,得到x3。这样,便得到了由连接点p1、p2、p3、p4、p5、p6和p7,以及线段x1、x2、x3、y1、y2、ys1、ys2、ys3、ys4和ys5组成的预期拓扑结构。
在本公开实施例中,布线质量检测装置可以在已布线版图中,确定与至少一个连接点连接的至少一个实际布线图形;而后根据预设分类规则确定每个实际布线图形的类别,并对每个实际布线图形对应进行简化,得到对应的至少一条实际连线,从而得到了包括至少一个连接点和至少一条实际连线的布线结果拓扑结构。
图3A、图3B和图3C示例出了得到实际布线图形的过程,将结合图示进行说明。如图3A所示,布线质量检测装置可以在已布线电路图确定连接点p11、p12、p13、p14、p15、p16、p17和p18。而后,如图3B所示,布线质量检测装置可以在已布线版图中确定连接点p11、p12、p13、p14、p15、p16、p17和p18的对应位置,并在已布线版图中确定出将这些连接点相连的实际布线图形。最后,如图3C所示,将所得到的实际布线图形提取出来。
在本公开的一些实施例中,实际布线图形的类别包括了:矩形(Rectangle)、路径(Path)和多边形(Polygon),图4A、图4B和图4C分别示例出了获取这三种类别实际布线图形对应的至少一条实际连线,将结合图示进行说明。
如图4A所示,实际布线图形G1属于矩形,布线质量检测装置则可以将G1中矩形短边的中垂线a,作为G1对应的实际连线。
如图4B所示,实际布线图形G2属于路径,布线质量检测装置则可以连接G2中沿路径轴向的中心点,得到G2对应的实际连线b、c和d。
如图4C所示,实际布线图形G3和G4属于多边形,G3与层通孔V1连接于层通孔连接线j,G4与层通孔V2连接于层通孔连接线k,其中,层通孔V1和V2上有“next”标识,表示通过层通孔V1和V2可以连接到下一层布线。针对G3,布线质量检测装置则可以将层通孔连接线j的中垂线g作为G3对应的实际连线,并按照路径类别实际布线图形对应的方法确定出实际连线e和f,从而得到了G3对应的实际连线e、f和g。针对G4,布线质量检测装置则可以将层通孔连接线k的中垂线i作为G4对应的实际连线,并按照矩形类别实际布线图形对应的方法确定出实际连线h,从而得到了G4对应的实际连线h和i。
S102、针对每个待检测信号,将布线结果拓扑结构和预期拓扑结构进行对比,得到每个待检测信号对应的拓扑结构对比结果。
本公开实施例中,布线质量检测装置在获得了布线结果拓扑结构和预期拓扑结构之后,可以将布线结果拓扑结构和预期拓扑结构进行对比,从而得到每个待检测信号对应的拓扑结构对比结果。
在本公开实施例中,布线质量检测装置可以分别计算出预期拓扑结构的预期布线长度,以及,布线结果拓扑结构的实际布线长度,并将实际布线长度与预期布线长度进行对比,以得到拓扑结构对比结果。
其中,预期布线长度包括:预期布线总长度,即预期拓扑结构中全部预期连线的总长度;实际布线长度包括:实际布线总长度,即布线结果拓扑结构中全部实际连线的总长度。布线质量检测装置可以将实际布线总长度与预期布线总长度的比值,作为拓扑结构对比结果。如表1所示例:
信号名 实际布线总长度 预期布线总长度 比值
netA 963.417 679.419 141.8%
netB 5691.201 5169.737 110.1%
netC 2134.079 944.885 225.9%
表1
上表1中,分别针对netA、netB和netC三个待检测信号,列举了实际布线总长度、预期布线总长度和其比值。netA的实际布线总长度与预期布线总长度的比值为141.8%,netB的实际布线总长度与预期布线总长度的比值为110.1%,netC的实际布线总长度与预期布线总长度的比值为225.9%。
另外,预期布线长度还包括:至少一个预期布线分层长度,即至少一种金属层对应的预期连线长度;实际布线长度还包括:至少一个实际布线分层长度,即至少一种金属层对应的实际连线长度。布线质量检测装置可以将每个实际布线分层长度和对应于相同金属层的预期布线分层长度分别相比,得到至少一个金属层比值作为拓扑结构对比结果。需要说明的是,已布线版图中包括了至少一种金属层,不同金属层中的金属连线在实际芯片构造中处于不同的位置,即上层金属连线位于下层金属连线的上方。
在本公开的一些实施例中,至少一个预期布线分层长度可以是与至少一种金属层对应的预设长度,即预期连线长度可以是预设值。如表2所示例:
信号名 实际布线分层长度(Mx) 预期布线分层长度(Mx)
netA - 150
netB 615.245 150
netC 246.874 150
表2
上表2中,分别列举了netA、netB和netC三个待检测信号在Mx这一金属层的实际布线分层长度和预期布线分层长度。netA在Mx没有实际布线分层长度,即表征netA在Mx这一金属层没有金属布线;netB在Mx的实际布线分层长度为615.245;netC在Mx的实际布线分层长度为246.874。netA、netB和netC在Mx的预期布线分层长度均为预设值150。
S103、若拓扑结构对比结果大于预设阈值,则确定对应的该待检测信号具有不合理布线的检测结果。
本公开实施例中,布线质量检测装置可以将每个待检测信号的拓扑结构对比结果与预设阈值进行比较;若拓扑结构对比结果大于预设阈值,则可以确定对应的该待检测信号具有不合理布线的检测结果。
在本公开实施例中,布线质量检测装置可以将待检测信号对应的实际布线总长度与预期布线总长度的比值与对应的总长度比值预设阈值进行比较。例如,若预设阈值为120%,则表1中netA和netC的比值均大于预设阈值,可以确定netA和netC具有不合理布线的检测结果。
在本公开实施例中,布线质量检测装置还可以针对任一金属层,将实际布线分层长度和预期布线分层长度的比值与对应的分层长度比值预设阈值进行比较。例如,若预设阈值为100%,则表2中netB和netC的比值均大于预设阈值,可以确定netB和netC具有不合理布线的检测结果。可以理解,设置分层长度比值预设阈值为100%,即表征实际布线分层长度不应大于对应的预期布线分层长度。
S104、基于每个待检测信号的检测结果,生成质量检测报告。
本公开实施例中,布线质量检测装置在确定了每个待检测信号的检测结果之后,可以基于每个待检测信号的检测结果,生成质量检测报告。其中,质量检测报告可以包括每个待检测信号的拓扑结构对比结果和布线位置信息。布线位置信息用于在已布线版图中显示与待检测信号对应的实际布线图形,其可以是连接点的坐标信息。
可以理解的是,布线质量检测装置通过获得布线结果拓扑结构和预期拓扑结构,并进行对比与判定,能够确定出不合理布线。这样,通过运行程序即可对自动布线结果进行检测,而不需要设计人员逐一查找验证,快速地完成了布线质量检测,实现了布线质量检测自动化,节省了检测时间。从而,便于设计人员对自动布线进行后期修改完善,缩短了芯片开发周期。
在本公开的一些实施例中,在图1示出的S104后还包括图5示出的S105,将结合各步骤进行说明。
S105、基于质量检测报告,在已布线版图中显示检测结果。
本公开实施例中,布线质量检测装置可以基于质量检测报告,在已布线版图中显示检测结果,以辅助设计人员对不合理布线的查看与定位。设计人员打开已布线版图后,可以读取质量检测报告,并在待检测信号集合中选择想要查看的待显示信号。布线质量检测装置可以接收对待检测信号集合的选择操作,确定出待显示信号,并基于质量检测报告确定待显示信号对应的检测结果;如果检测结果表征该待显示信号具有不合理布线,则布线质量检测装置可以在已布线版图中将不合理布线突出显示。例如,将不合理布线高亮显示,如图6所示,布线质量检测装置在已布线版图中将经过连接点p21、p22、p23和p24的不合理布线高亮显示;其中,p21、p22、p23和p24之间的直接连线并非是实际布线,而是用于帮助设计人员找到连接点的位置。这样便完成了在已布线版图中显示检测结果。
在本公开实施例中,已布线版图中显示出某一待检测信号的不合理布线后,设计人员可以对不合理布线进行修改。修改完成后,设计人员再次在待检测信号集合中点击该待检测信号,则布线质量检测装置对该待检测信号重复进行上述的布线质量检测方法,得到该待检测信号对应的检测结果。如果检测结果不具有不合理布线,则布线质量检测装置在查看界面中弹出“通过”提示,并取消该待检测信号的高亮显示;如果检测结果仍具有不合理布线,则布线质量检测装置在查看界面中弹出该检测结果的不合理项信息,并再次高亮显示该待检测信号的不合理布线,以提示设计人员继续进行修改。如此重复,直到所有待检测信号的检测结果都不具有不合理布线为止。
需要说明的是,对不合理布线的修改也可以通过自动布线来完成,在此不作限制。
可以理解的是,布线质量检测装置在已布线版图中将不合理布线突出显示,能够帮助设计人员对不合理布线进行修改完善,从而将实际布线优化为最优方案。
在本公开的一些实施例中,可以通过图7示出的S201~S204来实现图1示出的S101,将结合各步骤进行说明。
S201、获取已布线版图对应的已布线电路图。
本公开实施例中,由于已布线版图中可能难以明确显示出待检测信号途经的所有连接对象和连接点,因此,布线质量检测装置可以先获取与已布线版图对应的已布线电路图。
S202、基于已布线版图和已布线电路图,确定每个待检测信号对应的至少一个连接点。
本公开实施例中,布线质量检测装置在获取了已布线电路图后,可以基于已布线版图和已布线电路图,确定每个待检测信号对应的至少一个连接点。布线质量检测装置可以先在已布线电路图中获取连接对象标识,而后在已布线版图中匹配连接对象,并确定连接点。
S203、基于每个待检测信号对应的至少一个连接点,从已布线版图中,确定待检测信号集合中每个待检测信号对应的预期拓扑结构。
本公开实施例中,布线质量检测装置在确定出每个待检测信号对应的至少一个连接点后,可以基于至少一个连接点,从已布线版图中确定每个待检测信号对应的预期拓扑结构。布线质量检测装置可以分级确定出N级预期连线(N大于等于1),从而形成预期拓扑结构。
S204、基于每个待检测信号对应的至少一个连接点,从已布线版图中,确定待检测信号集合中每个待检测信号对应的布线结果拓扑结构。
本公开实施例中,布线质量检测装置在确定出每个待检测信号对应的至少一个连接点后,还可以基于至少一个连接点,从已布线版图中确定每个待检测信号对应的布线结果拓扑结构。布线质量检测装置可以先在已布线版图中,确定与至少一个连接点连接的至少一个实际布线图形;而后,对每个实际布线图形按类别对应进行简化,得到对应的至少一条实际连线,从而形成布线结果拓扑结构。
可以理解的是,布线质量检测装置先在已布线版图中确定出连线所经过的至少一个连接点的位置,再基于至少一个连接点分别获得布线结果拓扑结构和预期拓扑结构,这样,所获取的预期拓扑结构能够更加符合实际情况,其作为布线结果拓扑结构的对比对象更加精确,从而能够更精确地判定不合理布线。
在本公开的一些实施例中,至少一个连接点包括N级连接点,N大于等于1;可以通过图8示出的S301~S305来实现图7示出的S203,将结合各步骤进行说明。
S301、在已布线版图中,将每个待检测信号对应的至少一个连接点作为第1级连接点;基于第1级连接点,确定第1级中间基准线。
本公开实施例中,布线质量检测装置可以在已布线版图中,先将至少一个连接点均作为第1级连接点,并基于第1级连接点确定第1级中间基准线。
S302、将第i-1级连接点中轴向距离小于第i级预设阈值的连接点确定为第i级连接点;基于第i级连接点,确定第i级中间基准线;其中,i大于等于2,且i小于等于N-1;轴向距离为沿第一轴向或第二轴向的距离;第一轴向垂直于第二轴向。
本公开实施例中,布线质量检测装置可以从确定第2级中间基准线开始,将第i-1级连接点中轴向距离小于第i级预设阈值的连接点确定为第i级连接点,并基于第i级连接点确定第i级中间基准线。其中,i大于等于2,且i小于等于N-1;轴向距离为沿第一轴向或第二轴向的距离,且第一轴向垂直于第二轴向。
S303、继续进行第i+1级连接点和第i+1级中间基准线的确定,直到确定出第N级连接点和第N级中间基准线时为止。
本公开实施例中,布线质量检测装置可以继续进行第i+1级连接点和第i+1级中间基准线的确定,直到确定出第N级连接点和第N级中间基准线时为止,这样,便得到了N级连接点和N级中间基准线。
S304、基于N级连接点和N级中间基准线中,每级连接点和每级中间基准线,确定每级预期连线,从而确定出N级预期连线。
本公开实施例中,布线质量检测装置可以基于N级连接点和N级中间基准线中的每级连接点和每级中间基准线,确定出每级预期连线,从而确定出N级预期连线。
S305、至少一个连接点和N级预期连线形成待检测信号集合中每个待检测信号对应的预期拓扑结构。
本公开实施例中,布线质量检测装置可以将至少一个连接点和N级预期连线形成待检测信号集合中每个待检测信号对应的预期拓扑结构。
可以理解的是,布线质量检测装置根据连接点间的轴向距离对所有连接点进行分级,逐级确定出N级预期连线,能够减少预期连线的总长度,同时,所确定的预期连线也更加贴合实际布线中的设计习惯,从而能够更精确地判定不合理布线。
在本公开的一些实施例中,可以通过S3041~S3043来实现图8示出的S304,将结合各步骤进行说明。
S3041、基于第N级连接点和第N级中间基准线,确定第N级预期连线。
本公开实施例中,布线质量检测装置在确定了N级连接点和N级中间基准线后,可以先基于第N级连接点和第N级中间基准线,确定第N级预期连线。
S3042、基于第j级连接点、第j级中间基准线和第j+1级预期连线,确定第j级预期连线;其中,j大于等于2,且j小于等于N-1。
本公开实施例中,布线质量检测装置可以从第N-1级预期连线开始,基于第j级连接点、第j级中间基准线和第j+1级预期连线,确定第j级预期连线;其中,j大于等于2,且j小于等于N-1。
S3043、继续进行第j-1级预期连线的确定,直到确定出第1级预期连线时为止,从而确定出N级预期连线。
本公开实施例中,布线质量检测装置可以继续进行第j-1级预期连线的确定,直到确定出第1级预期连线时为止,从而确定出N级预期连线。
可以理解的是,布线质量检测装置可以先确定第N级预期连线,然后逐级倒序确定上一级预期连线,直到确定出第1级预期连线时为止,从而完成确定N级预期连线。由于预期连线中包括了每级中间基准线到上一级中间基准线的基准线间连线,倒序确定可以有效保证该基准线间连线不被遗漏。
在本公开的一些实施例中,可以通过S3011~S3012来实现图8示出的S301,将结合各步骤进行说明。
S3011、确定第1级连接点中沿第一轴向距离最远的两个第1级边缘连接点。
本公开实施例中,布线质量检测装置将至少一个连接点均作为第1级连接点后,可以确定第1级连接点中沿第一轴向距离最远的两个第1级边缘连接点。如图2所示例,p3和p7即为沿Y轴向(即第一轴向)最远的两个第1级边缘连接点。
S3012、经过两个第1级边缘连接点的连线的中点,沿第二轴向,确定第1级中间基准线。
本公开实施例中,布线质量检测装置确定出两个第1级边缘连接点后,可以经过两个第1级边缘连接点的连线的中点,沿第二轴向确定第1级中间基准线。如图2所示例,L3即为经过p3和p7的连线的中点,沿X轴向(即第二轴向)的第1级中间基准线。
在本公开的一些实施例中,可以通过S3021~S3022来实现图8示出的S302,将结合各步骤进行说明。
S3021、确定第i级连接点中沿第一轴向距离最远的两个第i级边缘连接点。
本公开实施例中,从确定第2级中间基准线开始,布线质量检测装置可以将第i-1级连接点中轴向距离小于第i级预设阈值的连接点确定为第i级连接点,而后确定第i级连接点中沿第一轴向距离最远的两个第i级边缘连接点。
S3022、经过两个第i级边缘连接点的连线的中点,沿第二轴向,确定第i级中间基准线。
本公开实施例中,布线质量检测装置确定出两个第i级边缘连接点后,可以经过两个第i级边缘连接点的连线的中点,沿第二轴向确定第i级中间基准线。如此,可以依次确定到第N级中间基准线。
在本公开的一些实施例中,可以通过S3044~S3046来实现图8示出的S304,将结合各步骤进行说明。
S3044、针对N级连接点的每级连接点中不满足预设距离条件的第一连接点,连接每级的第一连接点到其对应的每级中间基准线的垂足,得到第一连接点对应的第一子预期连线。
本公开实施例中,针对N级连接点的每级连接点中不满足预设距离条件的第一连接 点,布线质量检测装置可以连接每级的第一连接点到其对应的每级中间基准线的垂足,得到第一连接点对应的第一子预期连线;其中,每级连接点对应的预设距离条件为轴向距离小于下一级预设阈值。
S3045、针对N级连接点的每级连接点中满足预设距离条件的第二连接点,连接每级的第二连接点对应的该级中间基准线到其下一级中间基准线的公垂线段,得到第二连接点对应的第二子预期连线;其中,第一子预期连线和第二子预期连线作为每级预期连线。
本公开实施例中,针对N级连接点的每级连接点中满足预设距离条件的第二连接点,布线质量检测装置则可以连接每级的第二连接点对应的该级中间基准线到其下一级中间基准线的公垂线段,得到第二连接点对应的第二子预期连线。第一子预期连线和第二子预期连线作为每级预期连线。
S3046、直至N级连接点连接完成时,确定出N级预期连线。
本公开实施例中,布线质量检测装置依次完成上述过程,直至N级连接点连接完成时,可以确定出N级预期连线。
可以理解的是,布线质量检测装置逐级确定出N级预期连线,能够减少预期连线的总长度,同时,所确定的预期连线也更加贴合实际布线中的设计习惯,从而能够更精确地判定不合理布线。
在本公开的一些实施例中,可以通过图9示出的S401~S403来实现图7示出的S204,将结合各步骤进行说明。
S401、在已布线版图中,确定与至少一个连接点连接的至少一个实际布线图形。
本公开实施例中,布线质量检测装置在得到布线结果拓扑结构的过程中,可以先在已布线版图中,确定与至少一个连接点连接的至少一个实际布线图形。其中,实际布线图形即在版图中表征了将各连接点电连接的金属线。
S402、确定至少一个实际布线图形中每个实际布线图形的类别,并对每个实际布线图形对应进行简化,得到至少一个实际布线图形对应的至少一条实际连线。
本公开实施例中,布线质量检测装置在确定了至少一个实际布线图形后,可以先确定每个实际布线图形的类别,再根据对应类别对个实际布线图形对应进行简化,从而得到至少一个实际布线图形对应的至少一条实际连线。
S403、至少一个连接点和至少一条实际连线形成待检测信号集合中每个待检测信号对应的布线结果拓扑结构。
本公开实施例中,布线质量检测装置得到了至少一条实际连线后,可以将至少一个连接点和至少一条实际连线形成每个待检测信号对应的布线结果拓扑结构。
在本公开的一些实施例中,可以通过S4021~S4024来实现图9示出的S402,将结合各步骤进行说明。
S4021、确定每个实际布线图形属于矩形、路径和多边形中的一种。
本公开实施例中,实际布线图形的类别可以包括:矩形、路径和多边形。布线质量检测装置可以确定每个实际布线图形属于矩形、路径和多边形中的一种。
S4022、若任一实际布线图形属于矩形,则将该实际布线图形中矩形短边的中垂线,作为对应的至少一条实际连线。
本公开实施例中,布线质量检测装置若确定任一实际布线图形属于矩形,则可以将该实际布线图形中矩形短边的中垂线,作为对应的至少一条实际连线。如图4A所示,实际布线图形G1属于矩形,布线质量检测装置则可以将G1中矩形短边的中垂线a,作为G1对应的实际连线。
S4023、若任一实际布线图形属于路径,则连接该实际布线图形中沿路径轴向的中心点,作为对应的至少一条实际连线。
本公开实施例中,布线质量检测装置若确定任一实际布线图形属于路径,则可以连 接该实际布线图形中沿路径轴向的中心点,作为对应的至少一条实际连线。如图4B所示,实际布线图形G2属于路径,布线质量检测装置则可以连接G2中沿路径轴向的中心点,得到G2对应的实际连线b、c和d。
S4024、若任一实际布线图形属于多边形,表征该实际布线图形与层通孔连接于层通孔连接线,则将该实际布线图形中层通孔连接线的中垂线,作为对应的至少一条实际连线,从而得到了至少一个实际布线图形对应的至少一条实际连线。
本公开实施例中,布线质量检测装置若确定任一实际布线图形属于多边形,则可以将该实际布线图形中层通孔连接线的中垂线,作为对应的至少一条实际连线,从而得到了至少一个实际布线图形对应的至少一条实际连线。其中,属于多边形表征该实际布线图形与层通孔连接于层通孔连接线。如图4C所示,实际布线图形G3和G4属于多边形;针对G3,布线质量检测装置则可以将层通孔连接线j的中垂线g作为G3对应的实际连线;针对G4,布线质量检测装置则可以将层通孔连接线k的中垂线i作为G4对应的实际连线。
可以理解的是,布线质量检测装置将实际布线图形按照其所属类型进行简化,所得到的实际连线更加符合版图布线设计的设计理念与习惯,能更准确地反应版图布线设计的电学含义,从而能得到更准确的布线结果拓扑结构。
在本公开的一些实施例中,可以通过图10示出的S2021~S2023来实现图7示出的S202,将结合各步骤进行说明。
S2021、在已布线电路图中,获取每个待检测信号对应的至少一个连接对象标识。
本公开实施例中,布线质量检测装置在获取至少一个连接点的过程中,可以先在已布线电路图中,获取每个待检测信号对应的至少一个连接对象标识。
需要说明的是,连接对象标识是已布线电路图中电连接对象的符号,表征电路中具有特定功能的模块(instance)。已布线电路图中的任一连接对象标识,在已布线版图中均有对应的连接对象。连接对象为已布线版图中的图形,表征芯片中的对应物理区域能够形成该模块,实现该模块的功能。
S2022、在已布线版图中,匹配至少一个连接对象标识对应的至少一个连接对象。
本公开实施例中,布线质量检测装置确定了至少一个连接对象标识后,可以在已布线版图中,匹配至少一个连接对象标识对应的至少一个连接对象。
S2023、在已布线版图中,基于至少一个连接对象,确定每个待检测信号对应的至少一个连接点。
本公开实施例中,布线质量检测装置匹配了至少一个连接对象后,可以基于至少一个连接对象,在已布线版图中确定每个待检测信号对应的至少一个连接点。
需要说明的是,连接对象通过连接点进行电连接,确定了连接点即确定了待检测信号途经连线所要经过的端点。
可以理解的是,布线质量检测装置基于已布线电路图来确定至少一个连接点,能够更全面地确定出所需要的连接点,避免了遗漏。
在本公开的一些实施例中,可以通过S1021~S1022来实现图1示出的S102,将结合各步骤进行说明。
S1021、分别计算布线结果拓扑结构对应的实际布线长度和预期拓扑结构对应的预期布线长度。
本公开实施例中,布线质量检测装置在将布线结果拓扑结构和预期拓扑结构进行对比的过程中,可以先分别计算出预期拓扑结构的预期布线长度,以及,布线结果拓扑结构的实际布线长度。
S1022、将实际布线长度与预期布线长度进行对比,得到拓扑结构对比结果。
本公开实施例中,布线质量检测装置可以将实际布线长度与预期布线长度进行对比,得到拓扑结构对比结果。
可以理解的是,布线质量检测装置将实际布线长度与预期布线长度进行对比,有助于对实际布线长度进行调整,适当减少实际布线长度,从而减少对加工面积的占用,缩小芯片尺寸,以及节省加工成本。
在本公开的一些实施例中,实际布线长度包括:实际布线总长度;实际布线总长度为布线结果拓扑结构中全部实际连线的总长度;预期布线长度包括:预期布线总长度;预期布线总长度为预期拓扑结构中全部预期连线的总长度;可以通过S1023来实现上述的S1022,将结合各步骤进行说明。
S1023、将实际布线总长度与预期布线总长度的比值,作为拓扑结构对比结果。
本公开实施例中,布线质量检测装置可以将实际布线总长度与预期布线总长度的比值,作为拓扑结构对比结果。
在本公开的一些实施例中,实际布线长度还包括:至少一个实际布线分层长度;至少一个实际布线分层长度为布线结果拓扑结构中至少一种金属层对应的实际连线长度;预期布线长度还包括:至少一个预期布线分层长度;至少一个预期布线分层长度为至少一种金属层对应的预期连线长度;可以通过S1024来实现上述的S1022,将结合各步骤进行说明。
S1024、将至少一个实际布线分层长度中每个实际布线分层长度与至少一个预期布线分层长度中对应的预期布线分层长度分别相比,所得至少一个金属层比值作为拓扑结构对比结果。
本公开实施例中,布线质量检测装置可以将至少一个实际布线分层长度中每个实际布线分层长度与至少一个预期布线分层长度中对应的预期布线分层长度分别相比,所得至少一个金属层比值作为拓扑结构对比结果。
可以理解的是,布线质量检测装置采用总长度对比和分层长度对比等多样化的对比方式,能够更全面地对实际布线进行评估,从而帮助设计人员将实际布线优化为最优方案。
在本公开的一些实施例中,可以通过S1051~S1053实现图5示出的S105,将结合各步骤进行说明。
S1051、接收对待检测信号集合的选择操作,确定待显示信号。
本公开实施例中,布线质量检测装置在生成质量检测报告后,可以接收设计人员对待检测信号集合的选择操作,确定出待显示信号。
S1052、基于质量检测报告,确定待显示信号对应的检测结果。
本公开实施例中,布线质量检测装置确定出待显示信号后,可以基于质量检测报告,确定待显示信号对应的检测结果,其中,检测结果可以表征该待显示信号是否具有不合理布线。
S1053、若检测结果表征待显示信号具有不合理布线,则在已布线版图中,将不合理布线突出显示,从而完成了在已布线版图中显示检测结果。
本公开实施例中,若检测结果表征待显示信号具有不合理布线,布线质量检测装置则可以在已布线版图中,将不合理布线突出显示,例如,将不合理布线高亮显示,如图6所示。这样便完成了在已布线版图中显示检测结果。
可以理解的是,布线质量检测装置接收设计人员的查看选择操作,在已布线版图中将不合理布线突出显示,能够帮助设计人员对不合理布线进行修改完善,从而将实际布线优化为最优方案。
图11是本公开实施例提供的布线质量检测方法的一个可选的流程示意图,将结合图11示出的步骤进行说明。
S501、获取待检测信号列表。
本公开实施例中,布线质量检测装置首先会获取待检测信号列表。待检测信号列表中包括了需要进行布线质量检测的所有待检测信号。
S502、在已布线版图中提取布线结果拓扑结构。
本公开实施例中,布线质量检测装置可以在已布线版图中提取每个待检测信号对应的布线结果拓扑结构。
S503、生成预期拓扑结构。
本公开实施例中,布线质量检测装置会生成每个待检测信号对应的预期拓扑结构。
S504、对两种拓扑结构进行分析对比,确定自动布线是否符合设计预期。
本公开实施例中,布线质量检测装置会对两种拓扑结构进行分析对比,以确定自动布线是否符合预期。
S505、生成布线错误报告,报告待检测信号不符合预期的类型及布线位置。
本公开实施例中,布线质量检测装置若确定出任一待检测信号的自动布线不符合设计预期,则生成该待检测信号的布线错误报告,报告该待检测信号不符合预期的类型及布线位置。其中,不符合预期的类型可以包括:布线总长度超限,以及布线分层长度超限。
S506、将检测结果可视化。
本公开实施例中,布线质量检测装置在得到了包括布线错误报告的检测结果后,可以将检测结果可视化,从而易于设计人员修改完善。
在本公开的一些实施例中,可以通过图12示出的S5021~S5027来实现图11示出的S502,将结合各步骤进行说明。
S5021、在已布线电路图中获取待检测信号连接的所有instance(模块)标识和pin(连接点)标识。
本公开实施例中,由于已布线版图中可能缺少待检测信号对应的pin或者label(标识),所以布线质量检测装置可以在版图对应的已布线电路图中抓取指定待检测信号连接的所有instance和pin的标识。该已布线电路图与已布线版图中对应instance的名字完全匹配。
S5022、在已布线版图中匹配对应的instance和pin。
本公开实施例中,布线质量检测装置可以在版图中匹配对应的instance,找到需要连接的pin。
S5023、在已布线版图中获取实际布线图形。
本公开实施例中,如图3B所示,布线质量检测装置可以在已布线版图中获取pin连接的实际布线图形,以及通过CT(Contect,连接孔)或Via(通孔)连接的实际布线图形。
S5024、提取所得到的实际布线图形。
本公开实施例中,如图3C所示,布线质量检测装置可以对所得到的实际布线图形提取出来,以便进行后续的简化与计算。
S5025、读取实际布线图形。
本公开实施例中,布线质量检测装置可以读取出S5024中所获得的所有实际布线图形。
S5026、对实际布线图形进行分类。
本公开实施例中,布线质量检测装置可以对实际布线图形进行分类:
一、按照实际布线图形的金属层进行分类;
二、根据实际布线图形的类别进行分类,可以将实际布线图形分为矩形(Rectangle)、路径(Path)和多边形(Polygon),并对应进行简化,简化方法可以参考图4A、图4B和图4C。
S5027、统计实际布线图形的长度。
本公开实施例中,布线质量检测装置可以将S5026中简化得到的实际连线与S5022中得到的连接点形成布线结果拓扑结构。同时,布线质量检测装置可以计算每个实际布 线图形的长度,并汇总待检测信号对应的布线总长度和布线分层长度,这样,便得到了自动布线的物理连接计算结果;其中,布线总长度即是待检测信号对应的所有实际连线的长度,布线分层长度即是将对应于不同金属层的实际连线分别相加,从而得到的与各金属层对应的实际连线的长度。
在本公开的一些实施例中,可以通过图13示出的S5031~S5035来实现图11示出的S503,将结合各步骤进行说明。
S5031、获取所有pin的位置坐标。
本公开实施例中,布线质量检测装置可以在已布线版图中,获取待检测信号连接的所有pin的位置坐标。如图2所示,I1、I2、I3、I4、I5、I6和I7代表待检测信号要连接的instance;p1、p2、p3、p4、p5、p6和p7代表待检测信号要连接的pin,可以获取所有pin的位置坐标。
S5032、计算所有pin坐标的最大和最小Y坐标,得到中间基准线。
本公开实施例中,布线质量检测装置可以计算所有pin坐标的最大和最小Y坐标,如图2所示,p3和p7的Y坐标即为最大和最小Y坐标,表征为L1和L2。布线质量检测装置可以得到L1和L2的中间平行线L3,L3即为中间基准线。
S5033、建立每个pin到中间基准线的连线。
本公开实施例中,布线质量检测装置可以建立pin到中间基准线的连线,如图2所示的y1和y2。
S5034、单独确定每个小组的中间子基准线和连线。
本公开实施例中,当多个pin位置坐标在150×150范围内,则这些pin构成小组,布线质量检测装置可以单独计算每个小组的中间子基准线和连线,这样更加符合版图的设计预期。如图2所示,p3和p4可以形成一个小组,p5、p6和p7可以形成另一个小组,布线质量检测装置可以计算小组内pin坐标的最大和最小Y坐标,得到中间子基准线L6和L7;再建立单独成组的pin到子基准线的连线ys1和ys2,以及ys3、ys4和ys5;最后,再建立中间子基准线L6和L7到中间基准线L3的连线yb1和yb2。
S5035、生成X方向连接线。
本公开实施例中,布线质量检测装置最后可以在中间基准线和中间子基准线位置生成X方向连接线,从而形成预期拓扑结构。该预期拓扑结构可以用于计算预期布线总长度,作为对比的基准。
在本公开的一些实施例中,可以通过图14示出的S5041~S5043来实现图11示出的S504,将结合各步骤进行说明。
S5041、提取不同金属层对应的布线分层长度。
本公开实施例中,布线质量检测装置可以从S5027中得到的实际布线图形的长度中,提取不同金属层对应的布线分层长度。
S5042、判定布线分层长度是否超限。
本公开实施例中,布线质量检测装置可以获取质量检测中对于各金属层的限定条件,将不同金属层对应的布线分层长度与限定条件进行对比,以判定布线分层长度是否超限。若布线分层长度大于限定值,则判定布线分层长度超限。
S5043、生成分层长度布线错误报告。
本公开实施例中,布线质量检测装置若判定出布线分层长度超限,则生成分层长度布线错误报告,报告信号名和对应金属层位置等信息。
在本公开的一些实施例中,可以通过图15示出的S5044~S5046来实现图11示出的S504,将结合各步骤进行说明。
S5044、提取布线总长度。
本公开实施例中,布线质量检测装置可以从S5027中得到的实际布线图形的长度中,提取所有实际连线的布线总长度。
S5045、判定布线总长度是否超出预期比例。
本公开实施例中,布线质量检测装置可以将布线总长度与限定条件进行对比。若布线总长度与预期值的比值超出限定条件,则判定布线总长度超出预期比例。
S5046、生成总长度布线错误报告。
本公开实施例中,布线质量检测装置若判定出布线总长度超出预期比例,则生成总长度布线错误报告,报告信号名和自动布线路径等信息。
在本公开的一些实施例中,可以通过图16示出的S5061~S5065来实现图11示出的S506,将结合各步骤进行说明。
S5061、布线质量检测装置读取所有检测结果。
本公开实施例中,布线质量检测装置在收到设计人员发出的打开版图的指令后,可以读取该版图对应的所有检测结果。
S5062、布线质量检测装置窗体显示所有信号及对应的检测结果。
本公开实施例中,布线质量检测装置可以将所有信号及对应的检测结果窗体显示,以供设计人员点击操作。
S5063、设计人员点击信号名,布线质量检测装置对应进行可视化显示。
本公开实施例中,设计人员可以点击信号名,以使得布线质量检测装置进行可视化显示,这样,可以辅助设计人员对版图进行修改完善。其中,布线质量检测装置可以在版图中高亮显示不合理布线的物理路径,如图6中的加粗路径。在图6中,p21、p22、p23和p24之间的直接连线并非是实际布线,而是用于帮助设计人员找到连接点的位置。
S5064、设计人员Layout(布局)修改版图布线。
本公开实施例中,设计人员可以对不合理布线进行重新布局,以将其修改完善。
S5065、设计人员点击信号名再次检测及显示。
本公开实施例中,设计人员完成修改后,可以在此点击该信号名,重新进行S501~S505的布线质量检测方法。若该信号通过检测,即不再具有不合理布线,则布线质量检测装置弹出“通过”提示,并取消该信号的所有高亮显示。若该信号不通过检测,即仍具有不合理布线,则布线质量检测装置弹出该检测结果的不合理项信息,并再次高亮显示该信号的不合理布线,以提示设计人员继续进行修改。
可以理解的是,本公开实施例提出的布线质量检测方法建立了一种预期版图拓扑结构,将其与版图自动布线结果进行对比分析,若指定金属层使用超限或者布线路径不合理,则报告需要修正的信号名、以及对应的连接关系和位置信息。进而,根据生成的检测报告,辅助设计人员对信号布线进行修正。这样,在仿真阶段之前即可及时发现问题,有效节约了人工检查时间,从而缩短了项目开发周期。也就是说,本公开实施例达到了以下效果:实现了版图自动布线质量的自动高效检测,能够及早发现自动布线不合理、指定金属层使用超限等问题,帮助设计人员提取修改完善,缩短芯片开发周期;自动布线质量检测结果可视化,辅助版图设计人员进行快速修改完善。
图17为本公开实施例提供的布线质量检测装置的一个可选的结构示意图。如图17所示,本公开实施例还提供了一种布线质量检测装置800,包括:确定单元804、对比单元805、生成单元806,其中:
确定单元804,配置为基于已布线版图,确定待检测信号集合中每个待检测信号对应的布线结果拓扑结构和预期拓扑结构;所述预期拓扑结构是基于所述已布线版图中的连接点位置而得到的;
对比单元805,配置为针对所述每个待检测信号,将所述布线结果拓扑结构和所述预期拓扑结构进行对比,得到所述每个待检测信号对应的拓扑结构对比结果;
所述确定单元804,还配置为若所述拓扑结构对比结果大于预设阈值,则确定对应的该待检测信号具有不合理布线的检测结果;
生成单元806,配置为基于所述每个待检测信号的所述检测结果,生成质量检测报 告。
在本公开的一些实施例中,所述布线质量检测装置800还包括:显示单元807,其中:
显示单元807,配置为基于所述质量检测报告,在所述已布线版图中显示检测结果。
在本公开的一些实施例中,所述布线质量检测装置800还包括:获取单元808,其中:
获取单元808,配置为获取所述已布线版图对应的已布线电路图。
所述确定单元804,还配置为基于所述已布线版图和所述已布线电路图,确定所述每个待检测信号对应的至少一个连接点;基于所述每个待检测信号对应的至少一个连接点,从所述已布线版图中,确定所述待检测信号集合中每个待检测信号对应的预期拓扑结构;以及,基于所述每个待检测信号对应的至少一个连接点,从所述已布线版图中,确定所述待检测信号集合中每个待检测信号对应的布线结果拓扑结构。
在本公开的一些实施例中,所述确定单元804,还配置为在所述已布线版图中,将所述每个待检测信号对应的所述至少一个连接点作为第1级连接点;基于所述第1级连接点,确定第1级中间基准线;将第i-1级连接点中轴向距离小于第i级预设阈值的连接点确定为第i级连接点;基于所述第i级连接点,确定第i级中间基准线;其中,i大于等于2,且i小于等于N-1;所述轴向距离为沿第一轴向或第二轴向的距离;所述第一轴向垂直于所述第二轴向;继续进行第i+1级连接点和第i+1级中间基准线的确定,直到确定出第N级连接点和第N级中间基准线时为止;基于N级连接点和N级中间基准线中,每级连接点和每级中间基准线,确定每级预期连线,从而确定出N级预期连线;所述至少一个连接点和所述N级预期连线形成所述待检测信号集合中每个待检测信号对应的所述预期拓扑结构。
在本公开的一些实施例中,所述确定单元804,还配置为基于所述第N级连接点和所述第N级中间基准线,确定第N级预期连线;基于第j级连接点、第j级中间基准线和第j+1级预期连线,确定第j级预期连线;其中,j大于等于2,且j小于等于N-1;继续进行第j-1级预期连线的确定,直到确定出第1级预期连线时为止,从而确定出所述N级预期连线。
在本公开的一些实施例中,所述确定单元804,还配置为确定所述第1级连接点中沿所述第一轴向距离最远的两个第1级边缘连接点;经过所述两个第1级边缘连接点的连线的中点,沿所述第二轴向,确定所述第1级中间基准线。
在本公开的一些实施例中,所述确定单元804,还配置为确定所述第i级连接点中沿所述第一轴向距离最远的两个第i级边缘连接点;经过所述两个第i级边缘连接点的连线的中点,沿所述第二轴向,确定所述第i级中间基准线。
在本公开的一些实施例中,所述确定单元804,还配置为针对N级连接点的每级连接点中不满足预设距离条件的第一连接点,连接每级的所述第一连接点到其对应的每级中间基准线的垂足,得到所述第一连接点对应的第一子预期连线;针对N级连接点的每级连接点中满足预设距离条件的第二连接点,连接每级的所述第二连接点对应的该级中间基准线到其下一级中间基准线的公垂线段,得到所述第二连接点对应的第二子预期连线;其中,所述第一子预期连线和所述第二子预期连线作为每级预期连线;直至N级连接点连接完成时,确定出所述N级预期连线。
在本公开的一些实施例中,所述确定单元804,还配置为在所述已布线版图中,确定与所述至少一个连接点连接的至少一个实际布线图形;确定所述至少一个实际布线图形中每个实际布线图形的类别,并对所述每个实际布线图形对应进行简化,得到所述至少一个实际布线图形对应的至少一条实际连线;所述至少一个连接点和所述至少一条实际连线形成所述待检测信号集合中每个待检测信号对应的所述布线结果拓扑结构。
在本公开的一些实施例中,所述确定单元804,还配置为确定所述每个实际布线图 形属于矩形、路径和多边形中的一种;若任一实际布线图形属于矩形,则将该实际布线图形中矩形短边的中垂线,作为对应的至少一条实际连线;或者,若任一实际布线图形属于路径,则连接该实际布线图形中沿路径轴向的中心点,作为对应的至少一条实际连线;或者,若任一实际布线图形属于多边形,表征该实际布线图形与层通孔连接于层通孔连接线,则将该实际布线图形中所述层通孔连接线的中垂线,作为对应的至少一条实际连线,从而得到了所述至少一个实际布线图形对应的至少一条实际连线。
在本公开的一些实施例中,所述获取单元808,还配置为在所述已布线电路图中,获取所述每个待检测信号对应的至少一个连接对象标识;在所述已布线版图中,匹配所述至少一个连接对象标识对应的至少一个连接对象。
所述确定单元804,还配置为在所述已布线版图中,基于所述至少一个连接对象,确定所述每个待检测信号对应的所述至少一个连接点。
在本公开的一些实施例中,所述布线质量检测装置800还包括:计算单元809,其中:
计算单元809,配置为分别计算所述布线结果拓扑结构对应的实际布线长度和所述预期拓扑结构对应的预期布线长度。
所述对比单元805,还配置为将所述实际布线长度与所述预期布线长度进行对比,得到所述拓扑结构对比结果。
在本公开的一些实施例中,所述实际布线长度包括:实际布线总长度;所述实际布线总长度为所述布线结果拓扑结构中全部实际连线的总长度;所述预期布线长度包括:预期布线总长度;所述预期布线总长度为所述预期拓扑结构中全部预期连线的总长度;所述对比单元805,还配置为将所述实际布线总长度与所述预期布线总长度的比值,作为所述拓扑结构对比结果。
在本公开的一些实施例中,所述实际布线长度还包括:至少一个实际布线分层长度;所述至少一个实际布线分层长度为所述布线结果拓扑结构中至少一种金属层对应的实际连线长度;所述预期布线长度还包括:至少一个预期布线分层长度;所述至少一个预期布线分层长度为所述至少一种金属层对应的预期连线长度;所述对比单元805,还配置为将所述至少一个实际布线分层长度中每个实际布线分层长度与所述至少一个预期布线分层长度中对应的预期布线分层长度分别相比,所得至少一个金属层比值作为所述拓扑结构对比结果。
在本公开的一些实施例中,所述确定单元804,还配置为接收对所述待检测信号集合的选择操作,确定待显示信号;基于所述质量检测报告,确定所述待显示信号对应的检测结果。
所述显示单元807,还配置为若所述检测结果表征所述待显示信号具有不合理布线,则在所述已布线版图中,将所述不合理布线突出显示,从而完成了在所述已布线版图中显示检测结果。
需要说明的是,图18为本公开实施例提供的布线质量检测装置的一个可选的结构示意图,如图18所示,布线质量检测装置800的硬件实体包括:处理器801、通信接口802和存储器803,其中:
处理器801通常控制布线质量检测装置800的总体操作。
通信接口802可以使布线质量检测装置800通过网络与其他装置或设备通信。
存储器803配置为存储由处理器801可执行的指令和应用,还可以缓存待处理器801以及布线质量检测装置800中各模块待处理或已经处理的数据(例如,图像数据、音频数据、语音通信数据和视频通信数据),可以通过闪存(FLASH)或随机访问存储器(Random Access Memory,RAM)实现。
需要说明的是,本公开实施例中,如果以软件功能模块的形式实现上述的定时任务执行的方法,并作为独立的产品销售或使用时,也可以存储在一个计算机可读取存储介 质中。基于这样的理解,本公开实施例的技术方案本质上或者说对相关技术做出贡献的部分可以以软件产品的形式体现出来,该计算机软件产品存储在一个存储介质中,包括若干指令用以使得布线质量检测装置800(可以是个人计算机、服务器、或者网络设备等)执行本公开各个实施例所述方法的全部或部分。而前述的存储介质包括:U盘、移动硬盘、只读存储器(Read Only Memory,ROM)、磁碟或者光盘等各种可以存储程序代码的介质。这样,本公开实施例不限制于任何特定的硬件和软件结合。
对应地,本公开实施例提供一种计算机可读存储介质,其上存储有计算机程序,该计算机程序被处理器执行时实现上述布线质量检测装置对应的方法中的步骤。
这里需要指出的是:以上存储介质和设备实施例的描述,与上述方法实施例的描述是类似的,具有同方法实施例相似的有益效果。对于本公开存储介质和设备实施例中未披露的技术细节,请参照本公开方法实施例的描述而理解。
需要说明的是,在本文中,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
在本公开所提供的几个实施例中,应该理解到,所揭露的设备和方法,可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的,例如,所述单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,如:多个单元或组件可以结合,或可以集成到另一个系统,或一些特征可以忽略,或不执行。另外,所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口,设备或单元的间接耦合或通信连接,可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的,作为单元显示的部件可以是、或也可以不是物理单元;既可以位于一个地方,也可以分布到多个网络单元上;可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外,在本公开各实施例中的各功能单元可以全部集成在一个处理单元中,也可以是各单元分别单独作为一个单元,也可以两个或两个以上单元集成在一个单元中;上述集成的单元既可以采用硬件的形式实现,也可以采用硬件加软件功能单元的形式实现。
以上所述,仅为本公开的实施方式,但本公开的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本公开揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本公开的保护范围之内。因此,本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
由此可见,本公开实施例提供了一种布线质量检测方法、装置及存储介质,能够基于已布线版图,确定待检测信号集合中每个待检测信号对应的布线结果拓扑结构和预期拓扑结构;而后,针对每个待检测信号,将布线结果拓扑结构和预期拓扑结构进行对比,得到每个待检测信号对应的拓扑结构对比结果;再对拓扑结构对比结果进行判定,若拓扑结构对比结果大于预设阈值,则确定出对应的该待检测信号具有不合理布线的检测结果;而后,基于每个待检测信号的检测结果,生成质量检测报告。这样,通过运行程序即可对自动布线结果进行检测,而不需要设计人员逐一查找验证,快速地完成了布线质量检测,实现了布线质量检测自动化,节省了检测时间。

Claims (19)

  1. 一种布线质量检测方法,所述方法包括:
    基于已布线版图,确定待检测信号集合中每个待检测信号对应的布线结果拓扑结构和预期拓扑结构;所述预期拓扑结构是基于所述已布线版图中的连接点位置而得到的;
    针对所述每个待检测信号,将所述布线结果拓扑结构和所述预期拓扑结构进行对比,得到所述每个待检测信号对应的拓扑结构对比结果;
    若所述拓扑结构对比结果大于预设阈值,则确定对应的该待检测信号具有不合理布线的检测结果;
    基于所述每个待检测信号的所述检测结果,生成质量检测报告。
  2. 根据权利要求1所述的布线质量检测方法,其中,所述基于已布线版图,确定待检测信号集合中每个待检测信号对应的布线结果拓扑结构和预期拓扑结构,包括:
    获取所述已布线版图对应的已布线电路图;
    基于所述已布线版图和所述已布线电路图,确定所述每个待检测信号对应的至少一个连接点;
    基于所述每个待检测信号对应的至少一个连接点,从所述已布线版图中,确定所述待检测信号集合中每个待检测信号对应的预期拓扑结构;以及,
    基于所述每个待检测信号对应的至少一个连接点,从所述已布线版图中,确定所述待检测信号集合中每个待检测信号对应的布线结果拓扑结构。
  3. 根据权利要求2所述的布线质量检测方法,其中,所述至少一个连接点包括N级连接点;N大于等于1;所述基于所述每个待检测信号对应的至少一个连接点,从所述已布线版图中,确定所述待检测信号集合中每个待检测信号对应的预期拓扑结构,包括:
    在所述已布线版图中,将所述每个待检测信号对应的所述至少一个连接点作为第1级连接点;基于所述第1级连接点,确定第1级中间基准线;
    将第i-1级连接点中轴向距离小于第i级预设阈值的连接点确定为第i级连接点;基于所述第i级连接点,确定第i级中间基准线;其中,i大于等于2,且i小于等于N-1;所述轴向距离为沿第一轴向或第二轴向的距离;所述第一轴向垂直于所述第二轴向;
    继续进行第i+1级连接点和第i+1级中间基准线的确定,直到确定出第N级连接点和第N级中间基准线时为止;
    基于N级连接点和N级中间基准线中,每级连接点和每级中间基准线,确定每级预期连线,从而确定出N级预期连线;
    所述至少一个连接点和所述N级预期连线形成所述待检测信号集合中每个待检测信号对应的所述预期拓扑结构。
  4. 根据权利要求3所述的布线质量检测方法,其中,所述基于N级连接点和N级中间基准线中,每级连接点和每级中间基准线,确定每级预期连线,从而确定出N级预期连线,包括:
    基于所述第N级连接点和所述第N级中间基准线,确定第N级预期连线;
    基于第j级连接点、第j级中间基准线和第j+1级预期连线,确定第j级预期连线;其中,j大于等于2,且j小于等于N-1;
    继续进行第j-1级预期连线的确定,直到确定出第1级预期连线时为止,从而确定出所述N级预期连线。
  5. 根据权利要求3所述的布线质量检测方法,其中,所述基于所述第1级连接 点,确定第1级中间基准线,包括:
    确定所述第1级连接点中沿所述第一轴向距离最远的两个第1级边缘连接点;
    经过所述两个第1级边缘连接点的连线的中点,沿所述第二轴向,确定所述第1级中间基准线。
  6. 根据权利要求5所述的布线质量检测方法,其中,所述基于所述第i级连接点,确定第i级中间基准线,包括:
    确定所述第i级连接点中沿所述第一轴向距离最远的两个第i级边缘连接点;
    经过所述两个第i级边缘连接点的连线的中点,沿所述第二轴向,确定所述第i级中间基准线。
  7. 根据权利要求3所述的布线质量检测方法,其中,所述基于N级连接点和N级中间基准线中,每级连接点和每级中间基准线,确定每级预期连线,从而确定出N级预期连线,包括:
    针对N级连接点的每级连接点中不满足预设距离条件的第一连接点,连接每级的所述第一连接点到其对应的每级中间基准线的垂足,得到所述第一连接点对应的第一子预期连线;
    针对N级连接点的每级连接点中满足预设距离条件的第二连接点,连接每级的所述第二连接点对应的该级中间基准线到其下一级中间基准线的公垂线段,得到所述第二连接点对应的第二子预期连线;
    其中,所述第一子预期连线和所述第二子预期连线作为每级预期连线;
    直至N级连接点连接完成时,确定出所述N级预期连线。
  8. 根据权利要求2所述的布线质量检测方法,其中,所述基于所述每个待检测信号对应的至少一个连接点,从所述已布线版图中,确定所述待检测信号集合中每个待检测信号对应的布线结果拓扑结构,包括:
    在所述已布线版图中,确定与所述至少一个连接点连接的至少一个实际布线图形;
    确定所述至少一个实际布线图形中每个实际布线图形的类别,并对所述每个实际布线图形对应进行简化,得到所述至少一个实际布线图形对应的至少一条实际连线;
    所述至少一个连接点和所述至少一条实际连线形成所述待检测信号集合中每个待检测信号对应的所述布线结果拓扑结构。
  9. 根据权利要求8所述的布线质量检测方法,其中,所述确定所述至少一个实际布线图形中每个实际布线图形的类别,并对所述每个实际布线图形对应进行简化,得到所述至少一个实际布线图形对应的至少一条实际连线,包括:
    确定所述每个实际布线图形属于矩形、路径和多边形中的一种;
    若任一实际布线图形属于矩形,则将该实际布线图形中矩形短边的中垂线,作为对应的至少一条实际连线;或者,
    若任一实际布线图形属于路径,则连接该实际布线图形中沿路径轴向的中心点,作为对应的至少一条实际连线;或者,
    若任一实际布线图形属于多边形,表征该实际布线图形与层通孔连接于层通孔连接线,则将该实际布线图形中所述层通孔连接线的中垂线,作为对应的至少一条实际连线,从而得到了所述至少一个实际布线图形对应的至少一条实际连线。
  10. 根据权利要求2所述的布线质量检测方法,其中,所述基于所述已布线版图和所述已布线电路图,确定所述每个待检测信号对应的至少一个连接点,包括:
    在所述已布线电路图中,获取所述每个待检测信号对应的至少一个连接对象标识;
    在所述已布线版图中,匹配所述至少一个连接对象标识对应的至少一个连接对象;
    在所述已布线版图中,基于所述至少一个连接对象,确定所述每个待检测信号对应的所述至少一个连接点。
  11. 根据权利要求1所述的布线质量检测方法,其中,所述针对所述每个待检测 信号,将所述布线结果拓扑结构和所述预期拓扑结构进行对比,得到所述每个待检测信号对应的拓扑结构对比结果,包括:
    分别计算所述布线结果拓扑结构对应的实际布线长度和所述预期拓扑结构对应的预期布线长度;
    将所述实际布线长度与所述预期布线长度进行对比,得到所述拓扑结构对比结果。
  12. 根据权利要求11所述的布线质量检测方法,其中,所述实际布线长度包括:实际布线总长度;所述实际布线总长度为所述布线结果拓扑结构中全部实际连线的总长度;所述预期布线长度包括:预期布线总长度;所述预期布线总长度为所述预期拓扑结构中全部预期连线的总长度;
    将所述实际布线长度与所述预期布线长度进行对比,得到所述拓扑结构对比结果,包括:
    将所述实际布线总长度与所述预期布线总长度的比值,作为所述拓扑结构对比结果。
  13. 根据权利要求11所述的布线质量检测方法,其中,所述实际布线长度还包括:至少一个实际布线分层长度;所述至少一个实际布线分层长度为所述布线结果拓扑结构中至少一种金属层对应的实际连线长度;所述预期布线长度还包括:至少一个预期布线分层长度;所述至少一个预期布线分层长度为所述至少一种金属层对应的预期连线长度;
    将所述实际布线长度与所述预期布线长度进行对比,得到所述拓扑结构对比结果,还包括:
    将所述至少一个实际布线分层长度中每个实际布线分层长度与所述至少一个预期布线分层长度中对应的预期布线分层长度分别相比,所得至少一个金属层比值作为所述拓扑结构对比结果。
  14. 根据权利要求1所述的布线质量检测方法,其中,所述基于所述每个待检测信号的所述检测结果,生成质量检测报告之后,所述方法还包括:
    基于所述质量检测报告,在所述已布线版图中显示检测结果。
  15. 根据权利要求14所述的布线质量检测方法,其中,所述基于所述质量检测报告,在所述已布线版图中显示检测结果,包括:
    接收对所述待检测信号集合的选择操作,确定待显示信号;
    基于所述质量检测报告,确定所述待显示信号对应的检测结果;
    若所述检测结果表征所述待显示信号具有不合理布线,则在所述已布线版图中,将所述不合理布线突出显示,从而完成了在所述已布线版图中显示检测结果。
  16. 一种布线质量检测装置,包括:
    确定单元,配置为基于已布线版图,确定待检测信号集合中每个待检测信号对应的布线结果拓扑结构和预期拓扑结构;所述预期拓扑结构是基于所述已布线版图中的连接点位置而得到的;
    对比单元,配置为针对所述每个待检测信号,将所述布线结果拓扑结构和所述预期拓扑结构进行对比,得到所述每个待检测信号对应的拓扑结构对比结果;
    所述确定单元,还配置为若所述拓扑结构对比结果大于预设阈值,则确定对应的该待检测信号具有不合理布线的检测结果;
    生成单元,配置为基于所述每个待检测信号的所述检测结果,生成质量检测报告。
  17. 根据权利要求16所述的布线质量检测装置,其中,所述装置还包括:
    显示单元,配置为基于所述质量检测报告,在所述已布线版图中显示检测结果。
  18. 一种布线质量检测装置,包括:
    存储器,用于存储可执行指令;
    处理器,用于执行所述存储器中存储的可执行指令时,实现权利要求1至15任 一项所述的方法。
  19. 一种存储介质,存储有可执行指令,用于引起处理器执行时,实现权利要求1至15任一项所述的方法。
PCT/CN2021/138400 2021-09-08 2021-12-15 一种布线质量检测方法、装置及存储介质 WO2023035471A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/936,838 US20230039473A1 (en) 2021-09-08 2022-09-29 Wiring quality test method and apparatus and storage medium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111049249.8A CN115774982A (zh) 2021-09-08 2021-09-08 一种布线质量检测方法、装置及存储介质
CN202111049249.8 2021-09-08

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/936,838 Continuation US20230039473A1 (en) 2021-09-08 2022-09-29 Wiring quality test method and apparatus and storage medium

Publications (1)

Publication Number Publication Date
WO2023035471A1 true WO2023035471A1 (zh) 2023-03-16

Family

ID=85388011

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/138400 WO2023035471A1 (zh) 2021-09-08 2021-12-15 一种布线质量检测方法、装置及存储介质

Country Status (2)

Country Link
CN (1) CN115774982A (zh)
WO (1) WO2023035471A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118068235B (zh) * 2024-04-19 2024-08-20 全芯智造技术有限公司 用于晶圆测试结构的检测方法、电子设备及存储介质

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005107556A (ja) * 2003-08-12 2005-04-21 Matsushita Electric Ind Co Ltd 半導体集積回路の配線処理方法
CN104112031A (zh) * 2013-04-22 2014-10-22 鸿富锦精密工业(深圳)有限公司 检测电路板上芯片电源引脚布线的方法和装置
CN109241594A (zh) * 2018-08-23 2019-01-18 郑州云海信息技术有限公司 T型拓扑结构线长检查方法、装置、设备及可读存储介质

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005107556A (ja) * 2003-08-12 2005-04-21 Matsushita Electric Ind Co Ltd 半導体集積回路の配線処理方法
CN104112031A (zh) * 2013-04-22 2014-10-22 鸿富锦精密工业(深圳)有限公司 检测电路板上芯片电源引脚布线的方法和装置
CN109241594A (zh) * 2018-08-23 2019-01-18 郑州云海信息技术有限公司 T型拓扑结构线长检查方法、装置、设备及可读存储介质

Also Published As

Publication number Publication date
CN115774982A (zh) 2023-03-10

Similar Documents

Publication Publication Date Title
US8566059B2 (en) Insertion of faults in logic model used in simulation
US8543965B1 (en) Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing
WO2020103385A1 (zh) Pcb设计版图的开短路检查方法、检测系统及电子设备
US9589096B1 (en) Method and apparatus for integrating spice-based timing using sign-off path-based analysis
US6564365B1 (en) Method of simultaneously displaying schematic and timing data
US20140310670A1 (en) Failure analysis and inline defect characterization
US8661383B1 (en) VLSI black-box verification
WO2020063721A1 (en) Wafer processing method and apparatus, storage medium and electronic device
CN106773541A (zh) 一种基于版图几何特征匹配的光刻解决方案预测方法
US20030196180A1 (en) Method to simplify and speed up design rule/electrical rule checks
WO2023035471A1 (zh) 一种布线质量检测方法、装置及存储介质
US11379649B2 (en) Advanced cell-aware fault model for yield analysis and physical failure analysis
TW202113656A (zh) 執行自動化整合扇出晶圓級封裝佈線的方法及系統
US20150234978A1 (en) Cell Internal Defect Diagnosis
US9378327B2 (en) Canonical forms of layout patterns
US10055533B2 (en) Visualization of analysis process parameters for layout-based checks
US11193974B2 (en) Failure diagnostic apparatus and failure diagnostic method
US20230039473A1 (en) Wiring quality test method and apparatus and storage medium
WO2019075920A1 (zh) 元器件极性检测方法、系统、计算机可读存储介质及设备
CN115081389B (zh) 一种印刷电路板走线检查方法、装置、设备、存储介质
US20220382943A1 (en) Identifying association of safety related ports to their safety mechanisms through structural analysis
JP6070337B2 (ja) 物理故障解析プログラム、物理故障解析方法および物理故障解析装置
US11775729B2 (en) Technology file process rule validation
US11861286B2 (en) Segregating defects based on computer-aided design (CAD) identifiers associated with the defects
CN101206679B (zh) 布局图设计规则检查的方法与计算机可读取记录介质

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21956640

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21956640

Country of ref document: EP

Kind code of ref document: A1