WO2023184729A1 - 埋设线路的pcb制作方法及埋设线路的pcb - Google Patents

埋设线路的pcb制作方法及埋设线路的pcb Download PDF

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WO2023184729A1
WO2023184729A1 PCT/CN2022/099872 CN2022099872W WO2023184729A1 WO 2023184729 A1 WO2023184729 A1 WO 2023184729A1 CN 2022099872 W CN2022099872 W CN 2022099872W WO 2023184729 A1 WO2023184729 A1 WO 2023184729A1
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board
hole
core
circuit
layer
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PCT/CN2022/099872
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English (en)
French (fr)
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何醒荣
王小平
杨凡
董凤蕊
林桂氽
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生益电子股份有限公司
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Publication of WO2023184729A1 publication Critical patent/WO2023184729A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • the present application relates to the technical field of circuit board manufacturing, such as a PCB manufacturing method with embedded circuits and a PCB with embedded circuits.
  • PCB printed Circuit Boards, printed circuit boards
  • PCB circuits are mainly produced by etching circuits on the metal layer, thereby realizing PCB circuit production.
  • the PCB in order to improve the bonding force of the lamination process, the PCB needs to be browned on the surface.
  • the etched circuits are directly produced on the PCB and will be browned together with the PCB, which increases the roughness of the circuit surface.
  • This application provides a PCB manufacturing method for buried circuits and a PCB for buried circuits, which can solve the problem of tolerances in PCB during the circuit etching process in related technologies, and avoid the circuit surface damage caused by browning the circuits.
  • the problem of increased roughness ensures that the insertion loss performance of PCB meets the signal transmission requirements.
  • a PCB manufacturing method for buried circuits including the following steps:
  • leads are divided from both ends of the circuit assembly, and the leads are fixed on the first core board; the tape is torn off, and the remaining core board, prepreg, and first core board are sequentially After superposition, they are laminated to form a multi-layer board; the leads are electrically connected to the multi-layer circuits of the multi-layer board.
  • electrically connecting the leads to the multi-layer circuits includes:
  • a welding pad is provided on the first core board, and the lead is welded to the welding pad;
  • the first core board, the prepreg and the remaining core boards are sequentially stacked and laminated to form the multi-layer board; via holes are opened at the pads on the multi-layer board. Vias penetrate the multilayer board;
  • the soldering pad includes a first soldering pad and a second soldering pad, the first soldering pad is electrically connected to the second soldering pad, and the lead welding On the first bonding pad, after lamination to form the multi-layer board, the via hole penetrates the second bonding pad.
  • electrically connecting the leads to the multi-layer circuits of the multi-layer board includes:
  • a plurality of remaining core boards, prepregs and first core boards are sequentially stacked and laminated to form a multi-layer board; an expanded hole coaxial with the through hole is opened on the multi-layer board. The diameter of the enlarged hole is larger than the through hole;
  • the inner wall of the enlarged hole is metallized.
  • electrically connecting the leads to the multi-layer circuits of the multi-layer board includes:
  • a coaxial through hole is provided on each of the core boards and the prepreg, and a soldering pad is provided on the through hole of the first core board;
  • a plurality of the remaining core boards, the prepreg and the first core board are stacked in sequence, a plurality of the through holes form guide holes, and the free ends of the leads pass through the pads and the guides in sequence Tighten after hole;
  • the receiving groove can be opened according to the preset shape of the circuit assembly.
  • the circuit assembly includes a circuit body, and the circuit body is made of wires in the receiving groove.
  • the inside of the groove is bent and circled along the groove wall of the accommodating groove.
  • a PCB with embedded circuits is produced using the PCB manufacturing method with embedded circuits in any of the above solutions.
  • the PCB manufacturing method for embedded circuits treats the circuit component as an independent unit. First, one of the browned core boards is selected as the first core board, a receiving slot is opened on the first core board, and the circuit component is Place it in the receiving slot and use tape to fix it to prevent the circuit components from shifting during lamination and improve the manufacturing accuracy of the PCB. Then, multiple stranded leads are equally divided from both ends of the circuit assembly, and the leads are fixed on the first core board. Finally, the tape is removed, and the remaining core boards, the prepreg, and the first core board are sequentially stacked and laminated.
  • Figure 2 is a flow chart of a first method for realizing electrical connection between circuit components and multi-layer circuits in an embodiment of the present application
  • Figure 3 is a schematic structural diagram of the first core board in the embodiment of the present application.
  • Figure 4 is a flow chart of the second method for realizing electrical connection between circuit components and multi-layer circuits in the embodiment of the present application;
  • Figure 5 is a schematic diagram of the second method of realizing electrical connection between circuit components and multi-layer circuits in the embodiment of the present application;
  • Figure 6 is a flow chart of a third method for realizing electrical connection between circuit components and multi-layer circuits in an embodiment of the present application
  • FIG. 7 is a schematic diagram of the third method of realizing electrical connection between circuit components and multi-layer circuits in the embodiment of the present application.
  • connection should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection. Connection; can be mechanical or electrical. For those of ordinary skill in the art, the meanings of the above terms in this application can be understood according to the actual situation.
  • the term “above” or “below” a first feature on a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but passing between them. Additional feature touches.
  • the terms “above”, “above” and “above” a first feature on a second feature include the first feature being directly above and diagonally above the second feature, or simply mean that the first feature is higher in level than the second feature.
  • “Below”, “under” and “under” the first feature is the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature is less horizontally than the second feature.
  • this embodiment provides a PCB manufacturing method with embedded circuits and a PCB with embedded circuits, wherein the PCB manufacturing method with embedded circuits includes the following steps:
  • Multi-strand leads 5 are divided from both ends of the circuit assembly, and the leads 5 are fixed on the first core board 1; the tape is removed, and the remaining core boards, prepreg 2 and first core board 1 are laminated in sequence to form Multilayer board; electrically connect the lead 5 to the multilayer circuit of the multilayer board.
  • the above-mentioned PCB manufacturing method for buried circuits regards the circuit assembly as an independent unit, opening a receiving slot on the browned first core board 1, and then using the receiving slot 11 and tape to fix the circuit assembly to prevent the circuit assembly from being Offset during lamination improves PCB manufacturing accuracy.
  • the leads 5 are all electrically connected to the multi-layer circuits of the multi-layer board to realize the electrical connection between the circuit components and the multi-layer circuits, thereby generating a PCB with buried circuits and solving the problem of PCB problems occurring during the circuit etching process in related technologies.
  • the problem of processing tolerances and the increase in surface roughness of the circuit caused by browning the circuit components ensure that the insertion loss performance of the PCB meets the signal transmission requirements.
  • a branching slot 12 is provided on the first core board 1, the branching slot 12 is connected with the receiving slot 11, and the lead 5 is buried in the branching slot 12 to facilitate fixing the lead 5 to the first on core board 1.
  • the first core board 1 is provided with a plurality of wiring grooves 12 , and the wiring grooves 12 are arranged in one-to-one correspondence with the multi-stranded leads 5 .
  • Differential modules in related technologies are generally processed by etching, contour milling or punching, and are connected to the PCB in a plug-and-play manner.
  • the wiring density is low; on the other hand, there are processing accuracy errors, which affects the impedance of the PCB. /Insertion loss performance.
  • the shape of the circuit component should be designed according to the impedance and signal design requirements of the circuit component.
  • the accommodating groove 11 is opened according to the preset shape of the line assembly.
  • the line assembly includes a line body.
  • the line body is formed by bending and winding the wires along the groove wall of the accommodating groove 11 in the accommodating groove 11.
  • the line assembly also includes a shielding layer.
  • the shielding layer wraps the line body. There is no need to provide shielding layers on the upper and lower sides of the line assembly, thereby increasing the wiring density of the line assembly.
  • the structure of the above-mentioned circuit assembly determines that it is inconvenient to connect the lead 5 to the multi-layer circuit.
  • the electrical connection between the lead 5 and the multilayer circuit of the multilayer board is achieved through the following steps:
  • the first core board 1, the remaining core boards, and the prepreg 2 are sequentially stacked and laminated to form a multilayer board; a via hole 13 is opened at the pad 3 on the multilayer board, and the via hole 13 penetrates the multilayer board;
  • the above steps not only fix the lead 5 on the first core board 1 through the welding of the lead 5 and the pad 3, but also realize the electrical connection between the circuit component and the first core board 1.
  • a via hole 13 is opened at the pad 3 of the multilayer board, and the inner wall of the via hole 13 is metallized to realize the electrical connection between the first core board 1 and the multilayer circuit, thus realizing the connection between the circuit assembly and the multilayer circuit. Electrical connection.
  • the bonding pad 3 includes a first bonding pad 31 and a second bonding pad 32 , the first bonding pad 31 is electrically connected to the second bonding pad 32 , and the lead 5 is welded to the first bonding pad 31
  • the via hole 13 penetrates the second pad 32.
  • the arrangement of the first pad 31 and the second pad 32 increases the occupied area, the double pad 3 can ensure that the lead 5 is connected to the via.
  • the hole wall of hole 13 has sufficient connection area, which improves the reliability of the connection between the two.
  • the lead 5 is fixed on the first core board 1 by welding, and welding bumps are easily generated at the welding position 33, resulting in the first core board 1 not being connected to the remaining cores. After the boards are laminated, unevenness will occur at the welding position 33.
  • a through hole is provided on the first core board 1, and a bonding pad 3 is provided on the through hole. After the free end of the lead 5 passes through the bonding pad and the through hole in sequence, the lead 5 is tightened;
  • a plurality of remaining core boards, prepregs 2 and first core board 1 are sequentially stacked and laminated to form a multilayer board; an expanded hole 21 coaxial with the through hole is opened on the multilayer board, and the diameter of the expanded hole 21 is larger than the through hole. ;
  • the inner wall of the enlarged hole 21 is metallized.
  • Coaxial through holes are provided on each core board and prepreg 2, and the through holes of the first core board are provided with pads 3;
  • prepregs 2 and first core board 1 are stacked in sequence, multiple through holes form guide holes, and the free ends of the leads 5 pass through the pads and guide holes in sequence and then tightened;
  • the free end of lead 5 is electroplated and capped.
  • the above steps realize the fixation of the lead 5 on the first core board 1 by passing the free end of the lead 5 through the guide hole and then tightening it, and then laminate the stacked core boards so that the gap between the two adjacent core boards is The resin melts due to high temperature and flows into the guide hole to fix the lead 5 in the guide hole. Finally, the free end of the lead 5 is electroplated and capped, thus realizing the electrical connection between the circuit assembly and the multi-layer circuit and eliminating the need for metallization.
  • the design of the via hole effectively reduces the fluctuation of impedance value and interpolation, and improves the stability of the insertion loss performance test.
  • This embodiment also provides a PCB with embedded circuits, which is manufactured using the above-mentioned PCB manufacturing method with embedded circuits, which can avoid the browning treatment of the PCB, reduce the surface roughness of the circuit components, and can also avoid the processing of circuit etching.
  • the tolerances that arise during the process improve the insertion loss performance of the PCB.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本申请公开了一种埋设线路的PCB制作方法及埋设线路的PCB。该埋设线路的PCB制作方法将线路组件作为一个独立的单元，在棕化处理后的第一芯板上开设容纳槽，再利用容纳槽和胶带对线路组件进行固定，最后将引线均与多层板的多层线路电连接。

Description

埋设线路的PCB制作方法及埋设线路的PCB
本申请要求在2022年03月31日提交中国专利局、申请号为202210344145.8的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路板制作技术领域，例如一种埋设线路的PCB制作方法及埋设线路的PCB。
背景技术
近年来，随着电子产品的不断发展，对信号传输的完整性提出了更高的要求。信号传输越完整就意味着信号在传输过程中的损耗越小，因此PCB(Printed Circuit Boards，印制电路板)的插损性能对PCB是否满足信号传输要求至关重要。
相关技术中的PCB的线路主要通过在金属层上进行线路蚀刻，从而实现PCB的线路制作。但在传统方式制作的PCB过程中，为了提高层压过程的结合力，需要对PCB进行棕化的表面处理。蚀刻的线路直接制作在PCB上，会与PCB一起进行棕化处理，使得线路表面的粗糙度增加，而且蚀刻线路的过程中也会存在较大的加工公差，两者都将影响到PCB的插损性能，使其不能满足信号的传输要求。
发明内容
本申请提供一种埋设线路的PCB制作方法及埋设线路的PCB，能够解决相关技术中PCB在线路蚀刻的加工过程中出现公差的问题，并且避免了因对线路进行棕化处理带来的线路表面粗糙度增加的问题，从而保证PCB的插损性能满足信号的传输要求。
本申请提供
一种埋设线路的PCB制作方法，包括以下步骤：
对多个芯板进行棕化处理；
选取其中一个所述芯板作为第一芯板，在所述第一芯板上开设容纳槽，将线路组件放置于所述容纳槽内，并利用胶带进行固定；
所述线路组件的两端均分出多股引线，将所述引线固定在所述第一芯板上；撕掉所述胶带，将剩余所述芯板与半固化片、所述第一芯板依次叠合后层压，形成多层板；将所述引线与所述多层板的多层线路电连接。
作为上述埋设线路的PCB制作方法的一种可选方案，所述将所述引线与所述多层线路电连接，包括：
在所述第一芯板上设置焊盘，所述引线与所述焊盘焊接；
将所述第一芯板、所述半固化片与剩余所述芯板依次叠合后层压，形成所述多层板；在所述多层板上的所述焊盘处开设过孔，所述过孔贯穿所述多层板；
对所述过孔的内壁进行金属化。
作为上述埋设线路的PCB制作方法的一种可选方案，所述焊盘包括第一焊盘和第二焊盘，所述第一焊盘与所述第二焊盘电连接，所述引线焊接于所述第一焊盘上，经过层压形成所述多层板之后，所述过孔贯穿所述第二焊盘。
作为上述埋设线路的PCB制作方法的一种可选方案，所述将所述引线与所述多层板的所述多层线路电连接，包括：
所述第一芯板上开设有通孔，所述通孔上设有焊盘，所述引线的自由端依次穿过所述焊盘和所述通孔后，拉紧所述引线；
将多个剩余所述芯板、所述半固化片与所述第一芯板依次叠合后层压，形成多层板；所述多层板上开设与所述通孔同轴的扩孔，所述扩孔的直径大于所述通孔；
对所述扩孔的内壁进行金属化。
作为上述埋设线路的PCB制作方法的一种可选方案，所述将所述引线与所述多层板的多层线路电连接，包括：
在每个所述芯板和所述半固化片上均开设同轴通孔，所述第一芯板的通孔上设有焊盘；
将多个剩余所述芯板、所述半固化片与所述第一芯板依次叠合，多个所述通孔形成导向孔，所述引线的自由端依次穿过所述焊盘和所述导向孔后拉紧；
对叠合后的所述芯板进行层压，形成所述多层板；相邻两个所述芯板间的树脂向所述导向孔内流动，以将所述引线固定在所述导向孔内；
对所述引线的自由端进行电镀盖帽。
作为上述埋设线路的PCB制作方法的一种可选方案，所述第一芯板上开设分线槽，所述分线槽与所述容纳槽相连通，所述引线埋设于所述分线槽内。
作为上述埋设线路的PCB制作方法的一种可选方案，所述容纳槽可以根据所述线路组件的预设形状进行开设，所述线路组件包括线路本体，所述线路本体由导线在所述容纳槽内沿所述容纳槽的槽壁弯曲、绕圈而成。
作为上述埋设线路的PCB制作方法的一种可选方案，所述导线通过同一磨具拉制而成。
作为上述埋设线路的PCB制作方法的一种可选方案，所述线路组件还包括屏蔽层，所述屏蔽层包裹所述线路本体。
一种埋设线路的PCB，利用上述任一项方案中的埋设线路的PCB制作方法制作而成。
本申请所提供的埋设线路的PCB制作方法将线路组件作为一个独立的单元，先选取其中一个棕化处理后的芯板作为第一芯板，在第一芯板上开设容纳槽，将线路组件放置于容纳槽内，并利用胶带进行固定，以避免线路组件在层压时偏移，提高了PCB的制作精度。然后再从线路组件的两端均分出多股引线，将引线固定在第一芯板上。最后撕掉胶带，将多个剩余芯板与半固化片、第一芯板依次叠合后层压，形成多层板后，将引线均与多层板的多层线路电连接，以实现线路组件与多层线路的电连接，从而生成了埋设线路的PCB。上述制作方法解决了相关技术中PCB在线路蚀刻的加工过程中出现公差的问题，而且避免了因对线路组件进行棕化处理带来的线路组件表面粗糙度增加的问题，从而保证PCB的插损性能满足信号的传输要求。
本申请所提供的埋设线路的PCB利用上述埋设线路的PCB制作方法制作而成，能够避开相关技术中PCB在线路蚀刻的加工过程中出现的公差，和因对线路组件进行棕化处理带来的线路组件表面粗糙度增加的问题，进而提高了PCB的插损性能。
附图说明
图1为本申请实施例中埋设线路的PCB制作方法的流程图；
图2为本申请实施例中实现线路组件与多层线路的电连接的第一种方法的流程图；
图3为本申请实施例中第一芯板的结构示意图；
图4为本申请实施例中实现线路组件与多层线路的电连接的第二种方法流程图；
图5为本申请实施例中实现线路组件与多层线路的电连接的第二种方法的示意图；
图6为本申请实施例中实现线路组件与多层线路的电连接的第三种方法流程图；
图7为本申请实施例中实现线路组件与多层线路的电连接的第三种方法的示意图。
附图标记：
1、第一芯板；2、半固化片；3、焊盘；4、铜层；5、引线；
11、容纳槽；12、分线槽；13、过孔；
21、扩孔；
31、第一焊盘；32、第二焊盘；33、焊接位置。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本申请实施例的组件可以以多种不同的配置来布置和设计。
因此，以下对在附图中提供的本申请的实施例的详细描述仅仅表示本申请的选定实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行其他定义和解释。
在本申请的描述中，需要说明的是，术语“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该申请产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的工具台或元件必须具有特定的方位、以特定的方位构造和操作。此外，术语“第一”、“第 二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本申请的描述中，还需要说明的是，除非另有明确的规定，术语“设置”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接。对于本领域的普通技术人员而言，可以根据实际情况理解上述术语在本申请中的含义。
在本申请中，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下面详细描述本申请的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本申请。
如图1-图7所示，本实施例提供了一种埋设线路的PCB制作方法及埋设线路的PCB，其中埋设线路的PCB制作方法包括以下步骤：
对多个芯板进行棕化处理；
选取其中一个芯板作为第一芯板1，在第一芯板1上开设容纳槽11，将线路组件放置于容纳槽11内，并利用胶带进行固定；
线路组件的两端均分出多股引线5，将引线5固定在第一芯板1上；撕掉胶带，将剩余芯板、半固化片2与第一芯板1依次叠合后层压，形成多层板；将引线5与多层板的多层线路电连接。
上述埋设线路的PCB制作方法将线路组件作为一个独立的单元，在棕化处理后的第一芯板1上开设容纳槽，再利用容纳槽11和胶带对线路组件进行固定，以避免线路组件在层压时偏移，提高了PCB的制作精度。最后将引线5均与多层板的多层线路电连接，以实现线路组件与多层线路的电连接，从而生成了埋设线路的PCB，解决了相关技术中PCB在线路蚀刻的加工过程中出现加工公差的问题，和因对线路组件进行棕化处理带来的线路表面粗糙度增加的问题，从而保证PCB的插损性能满足信号的传输要求。
参考图3，可选地，第一芯板1上开设分线槽12，分线槽12与容纳槽11相连通，引线5埋设于分线槽12内，以便于将引线5固定于第一芯板1上。可选地，第一芯板1上设有多个分线槽12，分线槽12与多股引线5一一对应设置。
相关技术中的差分模块一般通过蚀刻、外形铣削或冲制等方式加工而成，以插拔的形式与PCB相连，一方面其布线密度低；另一方面存在加工精度误差，影响了PCB的阻抗/插损性能。而在本实施例中，为了提高埋设线路的PCB的插损性能，在预设线路组件的形状时，应该根据线路组件的阻抗和信号设计要求来进行设计。可选地，容纳槽11根据线路组件的预设形状进行开设，线路组件包括线路本体，线路本体由导线在容纳槽11内沿容纳槽11的槽壁弯曲、绕圈而成，一方面提高线路组件的布线密度，另一方面使得制作出的线路组件符合制作要求。可选地，容纳槽11通过激光、铣板或蚀刻等方式加工而成。可选地，导线通过同一磨具拉制而成，有效降低了导线之间的极差，提高了线路组件的加工精度。可选地，线路组件还包括屏蔽层，屏蔽层包裹线路本体，不需要再在线路组件的上下两侧设置屏蔽层，从而提高了线路组件的布线密度。
上述线路组件的结构决定了引线5与多层线路连接不便。可选地，结合图2，将引线5与多层板的多层线路电连接通过以下步骤实现：
在第一芯板1上设置焊盘3，所述引线5与所述焊盘3焊接；
将第一芯板1与剩余芯板、半固化片2依次叠合后层压，形成多层板；在多层板上的焊盘3处开设过孔13，过孔13贯穿多层板；
对过孔13的内壁进行金属化。
上述步骤通过引线5与焊盘3的焊接不仅将引线5固定在第一芯板1上，还实现了线路组件与第一芯板1的电连接。再在多层板的焊盘3处开设过孔13，并将过孔13的内壁金属化，实现了第一芯板1与多层线路的电连接，从而实现了线路组件与多层线路的电连接。
在其他实施例中，可选地，焊盘3包括第一焊盘31和第二焊盘32，第一焊盘31与第二焊盘32电连接，引线5焊接于第一焊盘31上，经过层压形成多层板之后，过孔13贯穿第二焊盘32，虽然第一焊盘31和第二焊盘32的设置增加了占用面积，但是双焊盘3可以保证引线5与过孔13的孔壁有足够的连接面积，提高了两者连接的可靠性。
上述步骤虽然解决了引线5与多层线路连接不便的问题，但利用焊接在第一芯板1上固定引线5，在焊接位置33容易产生焊接凸点，导致了第一芯板1与剩余芯板层压后会在焊接位置33处出现不平整的问题。
因此，或者可选地，如图4-图5所示，将引线5与多层线路电连接还通过以下步骤实现：
第一芯板1上开设有通孔，通孔上设有焊盘3，引线5的自由端依次穿过焊盘和通孔后，拉紧引线5；
将多个剩余芯板、半固化片2与第一芯板1依次叠合后层压，形成多层板；多层板上开设与通孔同轴的扩孔21，扩孔21的直径大于通孔；
对扩孔21的内壁进行金属化。
上述步骤通过引线5的自由端穿过通孔后拉紧实现了引线5在第一芯板1上的固定，再在通孔的基础上开设扩孔21，并将扩孔21的内壁金属化使得引线5的端部与金属化的扩孔21内壁相连接，从而实现了线路组件与多层线路的电连接，不仅解决了多层板在焊接位置33处可能会出现不平整的问题，还不需要考虑连接剂在高温高压的层压过程中的可靠性，简化了设计。
上述两种不同的步骤均是通过金属化孔壁解决了引线5与多层线路连接不便的问题，但金属化孔壁的设置会引起引线5的阻抗值和插损值发生波动，使得检测到的插损性能并不稳定。
因此，或者可选地，参考图6-图7，将引线5与多层线路电连接也可以通过以下步骤实现：
在每个芯板、半固化片2上均开设同轴通孔，第一芯板的通孔上设有焊盘3；
将多个剩余芯板、半固化片2与第一芯板1依次叠合，多个通孔形成导向孔，引线5的自由端依次穿过焊盘和导向孔后拉紧；
对叠合后的芯板进行层压，形成多层板；相邻两个芯板间的树脂向导向孔内流动，以将引线5固定在导向孔内；
对引线5的自由端进行电镀盖帽。
上述步骤通过引线5的自由端穿过导向孔后拉紧实现了引线5在第一芯板1上的固定，再对叠合后的芯板进行层压，使得相邻两个芯板之间的树脂因高温融化，向导向孔内流动，以将引线5固定在导向孔内，最后对引线5的自由端进行电镀盖帽，从而实现了线路组件与多层线路的电连接，取消了金属化过孔的设计，有效降低了阻抗值和插值的波动，提高了插损性能测试的稳定性。
本实施例还提供一种埋设线路的PCB，利用上述埋设线路的PCB制作方法制作而成，能够避开PCB的棕化处理，降低了线路组件的表面粗糙度，还可以避免在线路蚀刻的加工过程中出现的公差，进而提高了PCB的插损性能。

Claims (10)

  1. 一种埋设线路的PCB制作方法，包括：
    对多个芯板进行棕化处理；
    选取其中一个所述芯板作为第一芯板(1)，在所述第一芯板(1)上开设容纳槽(11)，将线路组件放置于所述容纳槽(11)内，并利用胶带进行固定；
    所述线路组件的两端均分出多股引线(5)，将所述引线(5)固定在所述第一芯板(1)上；撕掉所述胶带，将剩余所述芯板与半固化片(2)、所述第一芯板(1)依次叠合后层压，形成多层板；将所述引线(5)与所述多层板的多层线路电连接。
  2. 根据权利要求1所述的埋设线路的PCB制作方法，其中，所述将所述引线(5)与所述多层板的多层线路电连接，包括：
    在所述第一芯板(1)上设置焊盘(3)，所述引线(5)与所述焊盘(3)焊接；
    将所述第一芯板(1)、所述半固化片(2)与剩余所述芯板依次叠合后层压，形成所述多层板；在所述多层板上的所述焊盘(3)处开设过孔(13)，所述过孔(13)贯穿所述多层板；
    对所述过孔(13)的内壁进行金属化。
  3. 根据权利要求2所述的埋设线路的PCB制作方法，其中，所述焊盘(3)包括第一焊盘(31)和第二焊盘(32)，所述第一焊盘(31)与所述第二焊盘(32)电连接，所述引线(5)焊接于所述第一焊盘(31)上，经过层压形成所述多层板之后，所述过孔(13)贯穿所述第二焊盘(32)。
  4. 根据权利要求1所述的埋设线路的PCB制作方法，其中，所述将所述引线(5)与所述多层板的多层线路电连接，包括：
    所述第一芯板(1)上开设有通孔，所述通孔上设有焊盘(3)，所述引线(5)的自由端依次穿过所述焊盘(3)和所述通孔后，拉紧所述引线(5)；
    将多个剩余所述芯板、所述半固化片(2)与所述第一芯板(1)依次叠合后层压，形成所述多层板；所述多层板上开设与所述通孔同轴的扩孔(21)，所述扩孔(21)的直径大于所述通孔；
    对所述扩孔(21)的内壁进行金属化。
  5. 根据权利要求1所述的埋设线路的PCB制作方法，其中，所述将所述引线(5)与所述多层板的多层线路电连接，包括：
    在每个所述芯板和所述半固化片(2)上均开设同轴通孔，所述第一芯板(1)的通孔上设有焊盘(3)；
    将多个剩余所述芯板、所述半固化片(2)与所述第一芯板(1)依次叠合，多个 所述通孔形成导向孔，所述引线(5)的自由端依次穿过所述焊盘和所述导向孔后拉紧；
    对叠合后的所述芯板进行层压，形成所述多层板；相邻两个所述芯板间的树脂向所述导向孔内流动，以将所述引线(5)固定在所述导向孔内；
    对所述引线(5)的自由端进行电镀盖帽。
  6. 根据权利要求1所述的埋设线路的PCB制作方法，其中，所述第一芯板(1)上开设分线槽(12)，所述分线槽(12)与所述容纳槽(11)相连通，所述引线(5)埋设于所述分线槽(12)内。
  7. 根据权利要求1所述的埋设线路的PCB制作方法，其中，所述容纳槽(11)可以根据所述线路组件的预设形状进行开设，所述线路组件包括线路本体，所述线路本体由导线在所述容纳槽(11)内沿所述容纳槽(11)的槽壁弯曲、绕圈而成。
  8. 根据权利要求7所述的埋设线路的PCB制作方法，其中，所述导线通过同一磨具拉制而成。
  9. 根据权利要求7所述的埋设线路的PCB制作方法，其中，所述线路组件还包括屏蔽层，所述屏蔽层包裹所述线路本体。
  10. 一种埋设线路的PCB，利用如权利要求1-9中任一项所述的埋设线路的PCB制作方法制作而成。
PCT/CN2022/099872 2022-03-31 2022-06-20 埋设线路的pcb制作方法及埋设线路的pcb WO2023184729A1 (zh)

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