WO2023178791A1 - 一种信号采样电路以及半导体存储器 - Google Patents

一种信号采样电路以及半导体存储器 Download PDF

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Publication number
WO2023178791A1
WO2023178791A1 PCT/CN2022/089853 CN2022089853W WO2023178791A1 WO 2023178791 A1 WO2023178791 A1 WO 2023178791A1 CN 2022089853 W CN2022089853 W CN 2022089853W WO 2023178791 A1 WO2023178791 A1 WO 2023178791A1
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Prior art keywords
signal
clock
chip select
mode
odd
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PCT/CN2022/089853
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English (en)
French (fr)
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黄泽群
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长鑫存储技术有限公司
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Priority to EP22932848.9A priority Critical patent/EP4325501A4/en
Priority to US17/949,257 priority patent/US20230013811A1/en
Publication of WO2023178791A1 publication Critical patent/WO2023178791A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the field of integrated circuit technology, and in particular, to a signal sampling circuit and a semiconductor memory.
  • DDR Double Data Rate
  • the command address (Command/Address, CMD/ADD or CA for short) signal can be used as an address for sampling and as an instruction for sampling and decoding.
  • DRAM Dynamic Random Access Memory
  • the command address (Command/Address, CMD/ADD or CA for short) signal can be used as an address for sampling and as an instruction for sampling and decoding.
  • N MODE single-cycle mode
  • 2N MODE double-cycle mode
  • the pulse shapes of the chip select signals used by the 2T CMD signal and the NT ODT CMD signal are different, and the corresponding operating functions of the two are different. It's also different.
  • separate decoding circuits need to be set up for instruction signals in different modes. The circuit area is too large, and the signal decoding process of different instructions is prone to confusion, leading to decoding errors.
  • the present disclosure provides a signal sampling circuit and a semiconductor memory that can distinguish two instructions, 2T CMD and NT ODT CMD, in different cycle modes, and accurately decode them, while also saving circuit area and reducing power consumption.
  • inventions of the present disclosure provide a signal sampling circuit.
  • the signal sampling circuit includes a signal input circuit, a mode selection circuit, a first clock processing circuit, a second clock processing circuit and an instruction decoding circuit; wherein,
  • a signal input circuit for determining the instruction signal to be processed and the chip select signal to be processed based on the first clock signal, the first chip select signal and the first command address signal; wherein the clock cycle of the first clock signal is a preset clock cycle twice;
  • a mode selection circuit configured to select and process the first clock signal and the chip select signal to be processed according to the mode selection signal to obtain the target mode clock signal and the target mode chip select signal when the mode selection signal indicates the target mode;
  • the first clock processing circuit is used to perform sampling and logical operation processing on the chip select signal to be processed and the target mode chip select signal according to the target mode clock signal when the first chip select signal includes a pulse and the pulse width is a preset clock cycle, Get the first chip select clock signal;
  • the second clock processing circuit is used for when the first chip select signal includes one pulse and the pulse width is twice the preset clock period, or the first chip select signal includes 2 pulses and the pulse width is the preset clock period, according to
  • the target mode clock signal is sampled and logically processed by the chip select signal to be processed and the target mode chip select signal to obtain the second chip select clock signal;
  • the instruction decoding circuit is used to decode and sample the instruction signal to be processed according to the chip select signal to be processed and the first chip select clock signal to obtain the target instruction signal; or, to obtain the target instruction signal according to the chip select signal to be processed and the second chip select clock signal.
  • the signal is decoded and sampled to obtain the target instruction signal.
  • an embodiment of the present disclosure provides a semiconductor memory, including the signal sampling circuit of the first aspect.
  • the semiconductor memory is a dynamic random access memory DRAM chip and complies with DDR5 memory specifications.
  • Embodiments of the present disclosure provide a signal sampling circuit and a semiconductor memory. Based on the signal sampling circuit, a target mode clock signal and a target mode chip select signal are determined according to the periodic mode in order to provide first chip select signals with different pulse shapes. , obtain the corresponding first chip select clock signal and the second chip select clock signal, so as to correctly distinguish the two instructions 2T CMD and NT ODT CMD in different cycle modes and perform accurate decoding, which can avoid instruction decoding errors and It eliminates the problem of incorrect operations while saving circuit area and reducing power consumption.
  • Figure 1 is a schematic diagram of the decoding timing of different instruction signals in single-cycle mode
  • Figure 2 is a schematic diagram of the decoding timing of different instruction signals in dual-cycle mode
  • Figure 3 is a schematic structural diagram of a signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of another signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram of another signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 6A is a schematic structural diagram of a first decoding sampling circuit provided by an embodiment of the present disclosure.
  • Figure 6B is a schematic structural diagram of a second decoding sampling circuit provided by an embodiment of the present disclosure.
  • Figure 7 is a signal timing diagram of a signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 8 is a signal timing diagram of another signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 9 is a signal timing diagram of yet another signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 10 is a signal timing diagram of yet another signal sampling circuit provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first ⁇ second ⁇ third” Where permitted, the specific order or sequence may be interchanged so that the embodiments of the disclosure described herein can be practiced in an order other than that illustrated or described herein.
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • Command address input (Command/Address, CMD/ADD or CA for short)
  • Termination resistor On-Die Termination, ODT
  • DFF Data Flip-Flop or Delay Flip-Flop
  • NDT CMD Non-Target On-Die Termination Command
  • CA can be used as an address for sampling and as an instruction for sampling and decoding.
  • CA here is the collective name for various command address signals of DRAM, which can include row address strobe (RAS), column address strobe (Column Address Strobe, CAS), and write command (Write, WE).
  • RAS row address strobe
  • CAS Column address strobe
  • WE write command
  • Read, RD read command
  • the command address signal includes several address signals, which may be determined according to the specifications of the DRAM, and the embodiment of the present disclosure does not make any limitation.
  • the embodiments of this disclosure are related circuits for sampling and processing CA as an instruction. Therefore, the process of sampling and processing CA as an instruction is briefly described below.
  • CK_t and CK_c are a pair of input complementary clock signals, and the clock cycles of CK_t and CK_c are the preset clock cycles, and the phase difference is 180 degrees;
  • CA[13:0] is the CA signal input, here CA[13:0] represents a group of signals, the combined name of CA[0], CA[1],...,CA[13]; for 2T CMD signal, its corresponding chip select signal is represented by CS0_n; for NT ODT CMD signal, its corresponding chip select signal is represented by CS1_n;
  • CMD signal is the signal obtained after decoding the CA signal as an instruction.
  • the chip select signal is a signal indicating that the target chip is selected.
  • the CS0_n signal is an active low-level pulse signal.
  • the CS0_n signal includes a pulse, and the pulse width is the preset clock cycle;
  • the CA[13:0] signal Contains valid signals for two consecutive preset clock cycles.
  • the CA[4:0] signal of the first clock cycle needs to be sampled and decoded as a command to obtain a 2T CMD signal that lasts for two preset clock cycles.
  • CA[13:0] here represents a set of signals, which is CA The combined name of [0], CA[1],...,CA[13], CA[4:0] refers to CA[0], CA[1], CA[2], These five signals are CA[3] and CA[4].
  • the CS1_n signal is an active low-level pulse signal.
  • the CS1_n signal includes one pulse, and the pulse width is twice the preset clock period.
  • the CA[13:0] signal includes two consecutive preset clock periods. As a valid signal, the CA[4:0] signal of the first clock cycle needs to be sampled and decoded as a command signal to obtain the NT ODT CMD signal that lasts for two preset clock cycles.
  • the CS0_n signal is an active low-level pulse signal.
  • the CS0_n signal includes a pulse, and the pulse width is the preset clock period.
  • the CA[13:0] signal Including the valid signals of two non-consecutive preset clock cycles, the CA[4:0] signal of the first clock cycle also needs to be sampled and decoded as a command signal to obtain the 2T CMD signal.
  • CS1_n is a low-level active pulse signal.
  • CS1_n includes two pulses, and the pulse width is the preset clock period.
  • the CA[13:0] signal includes two discontinuous preset clock periods. Signal, CA[4:0] of the first clock cycle needs to be sampled and decoded as the command signal to obtain the NT ODT CMD signal.
  • the CA input needs to be decoded to obtain the 2T CMD signal; if there is a pulse in the CS_n signal and the pulse width is the preset clock cycle Assuming twice the clock period, then the CA input needs to be decoded to obtain the NT ODT CMD signal.
  • the CA input In dual-cycle mode, if there is one pulse in the CS_n signal and the pulse width is the preset clock period, then the CA input needs to be decoded to get the 2T CMD signal; if there are two pulses in the CS_n signal and the pulse width is the preset clock period, Then the CA input needs to be decoded to obtain the NT ODT CMD signal.
  • the 2T CMD signal and the NT ODT CMD signal are the same for decoding instructions such as read commands and write commands, the status of the CS_n signal is different and the operating functions of the two signals are different.
  • 2T The CMD signal requires a read operation, but the NT ODT CMD signal only needs an ODT operation that matches the read operation, and does not require a read operation. Therefore, in practical applications, it is necessary to distinguish between the decoding of 2T CMD signals and NT ODT CMD signals.
  • different cycle modes cause complex changes in the CS_n signals corresponding to different command signals, so the CA decoding circuit also becomes more complex.
  • a signal sampling circuit which includes a signal input circuit, a mode selection circuit, a first clock processing circuit, a second clock processing circuit and an instruction decoding circuit; wherein, the signal input circuit , used to determine the instruction signal to be processed and the chip select signal to be processed according to the first clock signal, the first chip select signal and the first command address signal; wherein the clock cycle of the first clock signal is twice the preset clock cycle ;
  • the mode selection circuit is used to select and process the first clock signal and the chip select signal to be processed according to the mode selection signal to obtain the target mode clock signal and the target mode chip select signal when the mode selection signal indicates the target mode;
  • a clock processing circuit configured to perform sampling and logic operation processing on the chip select signal to be processed and the target mode chip select signal according to the target mode clock signal when the first chip select signal includes a pulse and the pulse width is a preset clock cycle, to obtain The first chip select clock signal; the second clock processing circuit, used when the first chip select signal includes one pulse and the pulse width is twice the
  • the target mode clock signal and the target mode chip select signal are determined according to the periodic mode, so that the corresponding first chip select clock signal and the second chip select signal can be obtained for the first chip select signal with different pulse shapes.
  • Chip select clock signal so as to correctly distinguish 2T CMD and NT ODT CMD in different cycle modes, and perform correct decoding, which can avoid the problem of instruction decoding errors and wrong operations, and at the same time achieve the goal of saving circuit area and reducing power consumption. Purpose.
  • FIG. 3 shows a schematic structural diagram of a signal sampling circuit provided by an embodiment of the present disclosure.
  • the signal sampling circuit 30 may include a signal input circuit 31, a mode selection circuit 32, a first clock processing circuit 33, a second clock processing circuit 34 and an instruction decoding circuit 35; wherein,
  • the signal input circuit 31 is used to determine the instruction signal to be processed and the chip select signal to be processed according to the first clock signal, the first chip select signal and the first command address signal; wherein the clock cycle of the first clock signal is the preset clock twice the period;
  • the mode selection circuit 32 is configured to perform selection processing on the first clock signal and the chip select signal to be processed according to the mode selection signal when the mode selection signal indicates the target mode, to obtain the target mode clock signal and the target mode chip select signal;
  • the first clock processing circuit 33 is used to perform sampling and logical operation processing on the chip select signal to be processed and the target mode chip select signal according to the target mode clock signal when the first chip select signal includes a pulse and the pulse width is a preset clock cycle. , get the first chip select clock signal;
  • the second clock processing circuit 34 is used when the first chip select signal includes one pulse and the pulse width is twice the preset clock period, or the first chip select signal includes 2 pulses and the pulse width is the preset clock period, Perform sampling and logical operation processing on the chip select signal to be processed and the target mode chip select signal according to the target mode clock signal to obtain the second chip select clock signal;
  • the instruction decoding circuit 35 is used to decode and sample the instruction signal to be processed according to the chip select signal to be processed and the first chip select clock signal to obtain the target instruction signal; or, to obtain the target instruction signal according to the chip select signal to be processed and the second chip select signal.
  • the clock signal is decoded and sampled on the instruction signal to be processed to obtain the target instruction signal.
  • the signal sampling circuit 30 is used in the sampling and decoding process of address and instruction signals, and can be applied in various circuit scenarios.
  • the embodiments of the present disclosure will be explained and described later by using the CA signal in the DRAM chip to sample and decode addresses and instructions, but this does not constitute a relevant limitation.
  • the signal sampling circuit 30 is applied to a two-cycle command scenario.
  • the first command address signal here includes a valid signal of two preset clock cycles, and these two preset clock cycles may be continuous or discontinuous.
  • the CA[13:0] signal may be valid (Valid) in two consecutive preset clock cycles, or it may be valid in two discontinuous preset clock cycles.
  • the preset clock cycle here refers to the clock cycle of the CK_t/CK_c signal.
  • the target command signal can be the Command signal in the DDR5 DRAM chip. Since the effective pulse of this signal lasts for two clock cycles, it can be referred to as the 2T CMD signal here; where the 2T CMD signal can include the read command signal, Write command signal, refresh command signal, precharge command signal and activation command signal, etc.; alternatively, the target command signal can also be the Non-Target ODT Command signal in the DDR5DRAM chip, which can be referred to as the NT ODT CMD signal.
  • the embodiment of the present disclosure adds a mode selection circuit 32, and determines the target mode clock signal and the target mode chip select signal corresponding to the target mode through the mode selection circuit 32;
  • the embodiment of the present disclosure adds a first clock processing circuit 33 and a second clock processing circuit 34.
  • the first clock processing circuit 33 and the second clock processing circuit 34 each performs sampling and logical operation processing on the chip select signal to be processed according to the target mode clock signal and the target chip select signal, and obtains different first chip select clock signals and second chip select clock signals.
  • the first chip select clock signal and the second chip select clock signal is a valid signal and can indicate different instructions (2T CMD signal or NT ODT CMD signal).
  • the first chip select clock signal Perform a decoding and sampling process with the second chip select clock signal to obtain the target command signal.
  • the decoding of the two command signals 2T CMD and NT ODT CMD can be correctly distinguished in different cycle modes.
  • the single-cycle mode and the double-cycle mode share a set of decoding circuits, which not only saves circuit area and reduced power consumption.
  • the pulse width is twice the preset clock period
  • the pulse width specifically means that the deviation between the pulse width and twice the preset clock period is within the preset accuracy.
  • the descriptions in this disclosure involving the multiple relationship between the pulse width of other signals and the preset clock cycle can also be understood by reference.
  • the first clock processing circuit 33 is configured to, when the first chip select signal includes a pulse and the pulse width is a preset clock cycle, corresponding to the single-cycle mode.
  • the target mode clock signal is sampled and logically processed by the chip select signal to be processed and the target mode chip select signal corresponding to the single-cycle mode to obtain the first chip select clock signal; the second clock processing circuit 34 is used to select the first chip select signal.
  • the signal includes a pulse and the pulse width is twice the preset clock period
  • the chip select signal to be processed and the target mode chip select signal corresponding to the single cycle mode are sampled and logically processed according to the target mode clock signal corresponding to the single-cycle mode. Get the second chip select clock signal.
  • the first clock processing circuit 33 is configured to process the first chip select signal according to the two-period mode when the first chip select signal includes a pulse and the pulse width is a preset clock period.
  • the corresponding target mode clock signal is sampled and logically processed by the chip select signal to be processed and the target mode chip select signal corresponding to the dual-cycle mode to obtain the first chip select clock signal; the second clock processing circuit 34 is used to When the selection signal includes 2 pulses and the pulse width is the preset clock period, the chip select signal to be processed and the target mode chip select signal corresponding to the dual period mode are sampled and logically processed according to the target mode clock signal corresponding to the dual period mode, and the result is The second chip select clock signal.
  • the first chip select signal includes a pulse and the pulse width is a preset clock cycle
  • the first chip select clock signal obtained according to the first clock processing circuit 33 is valid at this time. signal
  • the second chip select clock signal obtained according to the second clock processing circuit 34 is an invalid signal.
  • the target command signal is the 2T CMD signal.
  • the first chip select signal includes one pulse and the pulse width is 2 preset clock cycles, or the first chip select signal includes 2 pulses and the pulse width is 2 preset clock cycles, period, at this time, the first chip select clock signal obtained according to the first clock processing circuit 33 is an invalid signal, and the second chip select clock signal obtained according to the second clock processing circuit 34 is a valid signal.
  • the target command signal is the NT ODT CMD signal.
  • the 2T CMD signal is decoded based on the first chip select clock signal, and the NT ODT CMD signal is decoded based on the second chip select clock signal, so Able to distinguish between different instructions.
  • the signal input circuit 31 may include a first receiving circuit 311, a second receiving circuit 312, a third receiving circuit 313 and an input Sampling circuit 314;
  • the first receiving circuit 311 is used to receive the initial command address signal and output the first command address signal
  • the second receiving circuit 312 is used to receive the initial chip select signal and output the first chip select signal
  • the third receiving circuit 313 is used to receive the initial clock signal, perform frequency division processing on the initial clock signal, and output the first odd clock signal and the first even clock signal;
  • the input sampling circuit 314 is used to sample the first chip select signal and the first command address signal according to the first clock signal to obtain the chip select signal to be processed and the command signal to be processed.
  • the clock period of the initial clock signal is a preset clock period
  • the first clock signal is composed of a first clock odd signal and a first clock even signal
  • the respective clock periods of the first clock odd signal and the first clock even signal are
  • the preset clock period is twice
  • the phase difference between the first clock odd signal and the first clock even signal is 180 degrees. That is to say, after frequency division processing, the initial clock signal obtains the first odd clock signal and the second even clock signal respectively.
  • first receiving circuit 311, the second receiving circuit 312 or the third receiving circuit 313 may be a receiver (denoted by Recevier) or a buffer (denoted by Buffer).
  • the initial command address signal here can be represented by CA[13:0], and the first command address signal is represented by CA; the initial chip select signal can be represented by CS_n, and the first chip select signal Represented by PCS; the initial clock signal can be represented by CK_t and CK_c, the first clock even signal is represented by PCLK_E, and the first clock odd signal is represented by PCLK_O.
  • VREFCA in Fig. 4 represents a reference signal.
  • the embodiment of the present disclosure needs to use the first clock signal to separately sample the first command address signal and the first chip select signal. Therefore, in some embodiments, based on the signal sampling circuit 30 shown in Figure 3, as shown in Figure 4, the input sampling circuit 314 includes a first sampling circuit 401, a second sampling circuit 402, a third sampling circuit 403 and The fourth sampling circuit 404; wherein,
  • the first sampling circuit 401 is used to sample the first command address signal according to the first clock signal to obtain the command signal to be processed;
  • the second sampling circuit 402 is used to sample the first command address signal according to the first clock odd signal to obtain the instruction odd signal to be processed;
  • the third sampling circuit 403 is used to sample and invert the first chip select signal according to the first clock even signal to obtain the chip select even signal to be processed;
  • the fourth sampling circuit 404 is used to sample and invert the first chip select signal according to the first clock odd signal to obtain the chip select odd signal to be processed.
  • the instruction signal to be processed may be composed of an even instruction signal to be processed and an odd instruction signal to be processed
  • the chip select signal to be processed may be composed of a chip select even signal to be processed and an odd chip select signal to be processed.
  • the even signal of the instruction to be processed is represented by CA[4:0]_1T_E
  • the odd signal of the instruction to be processed is represented by CA[4:0]_1T_O
  • the even signal of the chip select to be processed is represented by PCS_E
  • the odd signal of the chip select to be processed is represented Represented by PCS_O.
  • the first sampling circuit 401 may include a first flip-flop 504, and the first trigger The input terminal of the first flip-flop 504 is connected to the first command address signal, the clock terminal of the first flip-flop 504 is connected to the first clock signal, and the output terminal of the first flip-flop 504 is used to output the command signal to be processed;
  • the second sampling circuit 402 may include a second flip-flop 506, and the input terminal of the second flip-flop 506 is connected to the first command address signal, and the clock terminal of the second flip-flop 506 is connected to the first clock odd signal. The output end of 506 is used to output the odd signal of the pending instruction;
  • the third sampling circuit 403 includes a third flip-flop 508 and a first inverter 509, and the input terminal of the third flip-flop 508 is connected to the first chip select signal, and the clock terminal of the third flip-flop 508 is connected to the first clock even signal. Connect, the output terminal of the third flip-flop 508 is connected to the input terminal of the first inverter 509, and the output terminal of the first inverter 509 is used to output the chip selection signal to be processed;
  • the fourth sampling circuit 404 includes a fourth flip-flop 510 and a second inverter 511, and the input terminal of the fourth flip-flop 510 is connected to the first chip select signal, and the clock terminal of the fourth flip-flop 510 is connected to the first clock odd signal. connection, the output terminal of the fourth flip-flop 510 is connected to the input terminal of the second inverter 511, and the output terminal of the second inverter 511 is used to output the chip select odd signal to be processed.
  • CA[13:0]_1T_E is not a signal, but represents a set of command address signals, namely CA[0]_1T_E ⁇ CA[13]_1T_E, and the set of signals represented by CA[4:0]_1T_E
  • CA[13:0]_1T_O is not a signal, but represents a set of command address signals, namely CA[0]_1T_O ⁇ CA[13 ]_1T_O, and CA[4:0]_1T_O represents the five signals CA[0]_1T_O ⁇ CA[4]_1T_O in this group of signals.
  • first sampling circuit 401 or the second sampling circuit 402 since CA is not a signal, but a collective name for a group of signals, multiple first sampling circuits 401 may be included here, respectively for receiving Each CA signal in this group of CA signals; similarly, multiple second sampling circuits 402 may also be included for receiving each CA signal in this group of CA signals, and only one third sampling circuit is shown in the figure.
  • a sampling circuit 401 and a second sampling circuit 402 are shown as an illustration.
  • the first sampling circuit 401 may also include a first buffer 505.
  • the input terminal of the first buffer 505 is connected to the output terminal of the first flip-flop 504, and the first buffer 505
  • the output terminal is used to output the CA[4:0]_1T_E signal.
  • the second sampling circuit 402 may also include a second buffer 507.
  • the input terminal of the second buffer 507 is connected to the output terminal of the second flip-flop 506.
  • the output end of the second buffer 507 is used to output the CA[4:0]_1T_O signal. In this way, through the first buffer 505 and the second buffer 507, delay processing and drive enhancement processing are implemented during signal transmission.
  • the number of buffers is not limited to one, and may also be multiple.
  • the specific quantity can be set according to actual needs and is not specifically limited.
  • the third sampling circuit 403 uses the first clock even signal to sample and invert the first chip select signal to obtain the PCS_O signal; the fourth sampling circuit 404 uses the first clock odd signal to sample and invert the first chip select signal.
  • the PCS_E signal can be obtained by sampling and inverting the selected signal.
  • the first chip select signal is a low-level active pulse signal
  • the PCS_O signal or PCS_E signal can become a high-level active pulse. signal for subsequent logic operations.
  • the third sampling circuit 403 and the fourth sampling circuit 404 may not need to set the first inverter 509 and the second inverter 511, then the subsequent logical operations need to be adjusted accordingly. Thus the same effect can be achieved.
  • the mode selection circuit 32 may include a first selection circuit 321, a second selection circuit 322, a third selection circuit 323 and a third selection circuit 321.
  • the first selection circuit 321 is configured to select and process the first odd clock signal and the first even clock signal according to the mode selection signal to obtain the first mode clock signal among the target mode clock signals;
  • the second selection circuit 322 is used to select and process the first clock odd signal and the first clock even signal according to the mode selection signal to obtain the second mode clock signal among the target mode clock signals;
  • the third selection circuit 323 is used to perform selection processing on the chip select odd signal to be processed and the chip select even signal to be processed according to the mode selection signal to obtain the first mode chip select signal among the target mode chip select signals;
  • the fourth selection circuit 324 is used to perform selection processing on the chip select odd signal to be processed and the chip select even signal to be processed according to the mode selection signal to obtain the second mode chip select signal among the target mode chip select signals.
  • the first mode clock signal and the second mode clock signal constitute the target mode clock signal
  • the first mode chip select signal and the second mode chip select signal constitute the target mode chip select signal.
  • the mode selection signal can be represented by EN_1N
  • the first mode clock signal can be represented by PCLK_2NE_1NO
  • the second mode clock signal PCLK_2NO_1NE
  • the first mode chip select signal can be represented by PCS_2NE_1NO
  • the second mode chip The selection signal can be represented by PCS_2NO_1NE.
  • the target mode clock signal and the target mode chip select signal are adjusted accordingly, so that the decoding instruction can be subsequently determined to be the 2T CMD signal or the NT ODT CMD signal.
  • the mode selection circuit 32 when the mode selection signal indicates a single-cycle mode, is specifically configured to select the first clock odd signal to generate the first mode clock signal, and select the first clock even signal to generate the second mode clock signal.
  • the mode clock signal selects the odd chip select signal to be processed to generate the first mode chip select signal, and selects the even chip select signal to be processed to generate the second mode chip select signal.
  • the mode selection circuit 32 when the mode selection signal indicates the two-period mode, is specifically configured to select the first clock even signal to generate the first mode clock signal, and select the first clock odd signal to generate the first mode clock signal.
  • the two-mode clock signal selects the even chip select signal to be processed to generate the first mode chip select signal, and selects the odd chip select signal to be processed to generate the second mode chip select signal.
  • the decoding object is distinguished as the 2T CMD signal or the NT ODT CMD signal in different periodic modes.
  • the target mode is a single-cycle mode, it is determined that the mode selection signal is in a first level state; or, if the target mode is a dual-cycle mode, it is determined that the mode selection signal is in a second level state.
  • the first level state and the second level state are different.
  • the first level state is high level, and the second level state is low level; or, the first level state is low level, and the second level state is high level, and its specific value is It can be determined according to the actual application scenario, and is not limited in any way by the embodiment of the present disclosure.
  • the first selection circuit 321 includes a first multiplexer 513
  • the second selection circuit 322 includes a second Multiplexer 515
  • the third selection circuit 323 includes a third multiplexer 516
  • the fourth selection circuit 324 includes a fourth multiplexer 517;
  • the first input terminal of the first multiplexer 513 is connected to the first clock even signal, the second input terminal of the first multiplexer 513 is connected to the first clock odd signal, and the output terminal of the first multiplexer 513 Used to output the first mode clock signal;
  • the first input terminal of the second multiplexer 515 is connected to the first clock odd signal, the second input terminal of the second multiplexer 515 is connected to the first clock even signal, and the output terminal of the second multiplexer 515 Used to output the second mode clock signal;
  • the first input terminal of the third multiplexer 516 is connected to the chip select even signal to be processed, and the second input terminal of the third multiplexer 516 is connected to the odd chip select signal to be processed.
  • the output terminal is used to output the first mode chip select signal
  • the first input terminal of the fourth multiplexer 517 is connected to the chip select odd signal to be processed, the second input terminal of the fourth multiplexer 517 is connected to the chip select even signal to be processed, and the fourth multiplexer 517 The output terminal is used to output the second mode chip select signal;
  • the respective control terminals of the first multiplexer 513, the second multiplexer 515, the third multiplexer 516 and the fourth multiplexer 517 are connected to the mode selection signal.
  • the first selection circuit 321 may also include a third buffer 512.
  • the receiving end of the third buffer 512 is used to receive the first clock signal, and the output end of the third buffer 512 is connected to the first
  • the first input terminal of the multiplexer 513 is connected to the second input terminal of the second multiplexer 515 .
  • the second selection circuit 322 may also include a fourth buffer 514.
  • the receiving end of the fourth buffer 513 is used to receive the first clock odd signal.
  • the output end of the third buffer 513 is connected to the second end of the first multiplexer 513.
  • the input terminal is connected to the first input terminal of the second multiplexer 515 .
  • the third buffer 512 and the fourth buffer 514 delay processing and drive enhancement processing are implemented during signal transmission.
  • the number of buffers is not limited to one, and may also be multiple.
  • the specific quantity can be set according to actual needs and is not specifically limited.
  • the first clock processing circuit 33 may include a first logic circuit 331 and a second logic circuit 332.
  • the second clock processing circuit 34 may include a third logic circuit 341 and a fourth logic circuit 342; wherein,
  • the first logic circuit 331 is used to receive the first mode clock signal and the first mode chip select signal, and use the first mode clock signal to perform sampling and logical operation processing on the chip select even signal to be processed and the first mode chip select signal, to obtain The first chip select clock odd signal;
  • the second logic circuit 332 is used to receive the second mode clock signal and the second mode chip select signal, and use the second mode clock signal to perform sampling and logical operation processing on the chip select odd signal to be processed and the second mode chip select signal, to obtain The first chip select clock even signal;
  • the third logic circuit 341 is used to receive the first mode clock signal and the first mode chip select signal, and use the first mode clock signal to perform sampling and logical operation processing on the chip select even signal to be processed and the first mode chip select signal, to obtain The second chip select clock odd signal;
  • the fourth logic circuit 342 is used to receive the second mode clock signal and the second mode chip select signal for processing, and use the second mode clock signal to perform sampling and logical operations on the chip select odd signal to be processed and the second mode chip select signal to obtain The second chip select clock is even signal.
  • the first chip select clock signal is composed of the first chip select clock even signal and the first chip select clock odd signal
  • the second chip select clock signal is composed of the second chip select clock odd signal and the second chip select clock even signal.
  • signal composition In Figure 4 and Figure 5, the even signal of the first chip select clock can be represented by 2T_CLK_E, the odd signal of the first chip select clock can be represented by 2T_CLK_O, the even signal of the second chip select clock can be represented by NT_CLK_E, and the second chip select clock odd signal can be represented by NT_CLK_E.
  • the clock odd signal can be represented by NT_CLK_O.
  • the first logic circuit 331 includes a fifth sampling circuit 405, a first NOR gate 520, a first NOT Gate 521, sixth sampling circuit 406, first OR gate 523 and first AND gate 524; wherein,
  • the fifth sampling circuit 405 is used to use the first mode clock signal to sample and invert the chip select even signal to be processed to obtain the first intermediate sampled odd signal;
  • the first NOR gate 520 is used to perform a NOR operation on the first intermediate sampled odd signal and the first mode chip select signal to obtain the second intermediate sampled odd signal;
  • the first NOT gate 521 is used to perform a NOT operation on the first mode clock signal to obtain the first inverted clock odd signal;
  • the sixth sampling circuit 406 is used to perform sampling processing on the second intermediate sampling odd signal using the first inverted clock odd signal to obtain a third intermediate sampling odd signal;
  • the first OR gate 523 is used to perform an OR operation on the second intermediate sampled odd signal and the third intermediate sampled odd signal to obtain the fourth intermediate sampled odd signal;
  • the first AND gate 524 is used to perform an AND operation on the fourth intermediate sampled odd signal and the first mode clock signal to obtain the first chip select clock odd signal.
  • the fifth sampling circuit 405 may be composed of a fifth flip-flop 518 and a third inverter 519
  • the sixth sampling circuit 406 may be composed of a fifth flip-flop 518 and a third inverter 519 . It is composed of six flip-flops 522; among them, both the fifth flip-flop 518 and the sixth flip-flop 522 can be D-type flip-flops.
  • the third inverter 519 may not be provided, and then subsequent logical operations need to be adjusted accordingly, for example, the first NOR gate 520 may be adjusted to OR door, thus achieving the same effect.
  • each device of the first logic circuit 331 can be understood with reference to FIG. 4 and FIG. 5 .
  • the chip select even signal to be processed is represented by PCS_E; the first intermediate sample odd signal output by the fifth sampling circuit 405 can be represented by PCSB_O, and the second intermediate sample output by the first NOR gate 520
  • the odd signal can be represented by PCS_OEN1, the third intermediate sample odd signal output through the sixth sampling circuit 406 can be represented by PCS_OEN2, and the fourth intermediate sample odd signal output through the first OR gate 523 can be represented by PCS_OEN.
  • the first chip select clock odd signal output by 524 can be represented by 2T_CLK_O.
  • the first NOR gate 520 is used to screen the first chip select signal, and output the PCS_OEN1 signal with pulses according to the first chip select signal of the first type of pulse shape, and Mask the first chip select signal of other pulse shapes into the PCS_OEN1 signal that is always low, so that the 2T_CLK_O signal with pulses can be obtained later.
  • the fifth sampling circuit 405 is used to implement one level of rising edge sampling, while the first NOT gate 521 and the sixth sampling circuit 406 are used to implement one level of falling edge sampling.
  • the first type of pulse shape refers to that the first chip select signal changes to low level in even-numbered clock cycles and changes to high-level in adjacent odd-numbered clock cycles.
  • the periodic mode at this time can be a single periodic mode or a double periodic mode.
  • the even-numbered clock cycle refers to the clock cycle in which the rising edge of the first clock even signal PCLK_E is located
  • the odd-numbered clock cycle refers to the clock cycle in which the rising edge of the first clock odd signal PCLK_O is located.
  • the PCS_OEN1 signal and the PCS_OEN2 signal are obtained, and the PCS_OEN1 signal and the PCS_OEN2 signal are respectively Both are pulse signals with active high level, but the rising edge of the PCS_OEN2 signal is delayed by a preset clock cycle compared to the rising edge of the PCS_OEN1 signal.
  • the PCS_OEN1 signal and the PCS_OEN2 signal are ORed to broaden the pulse width, and the resulting pulse width of the PCS_OEN signal is 3 times the preset clock cycle; through the first AND gate 524, PCS_OEN The signal is ANDed with the PCLK_2NE_1NO (PCLK_O signal in single-cycle mode, PCLK_E signal in double-cycle mode) signal, so that the resulting 2T_CLK_O signal has two pulses, and the pulse width is the preset clock cycle.
  • PCLK_2NE_1NO PCLK_O signal in single-cycle mode, PCLK_E signal in double-cycle mode
  • the rising edge of the first pulse is used to generate the rising edge of the 2T CMD signal
  • the rising edge of the second pulse is used to generate the falling edge of the 2T CMD signal, which can ensure the reliability of the 2T CMD signal.
  • the pulse width is 2 preset clock cycles within the preset accuracy range to prevent the pulse width of the 2T CMD signal from being affected by the preparation process or environment and prevent signal failure.
  • the second logic circuit 332 may include a seventh sampling circuit 407, a second NOR gate 527, a second NOT gate 528, an eighth sampling circuit 408, a second OR Gate 530 and second AND gate 531; where,
  • the seventh sampling circuit 407 is used to use the second mode clock signal to sample and invert the chip select odd signal to be processed to obtain the first intermediate sampled even signal;
  • the second NOR gate 527 is used to perform a NOR operation on the first intermediate sampled even signal and the second mode chip select signal to obtain the second intermediate sampled even signal;
  • the second NOT gate 528 is used to perform a NOT operation on the second mode clock signal to obtain the first inverted clock even signal
  • the eighth sampling circuit 408 is used to perform sampling processing on the second intermediate sampled even signal using the first inverted clock even signal to obtain a third intermediate sampled even signal;
  • the second OR gate 530 is used to perform an OR operation on the second intermediate sampled even signal and the third intermediate sampled even signal to obtain a fourth intermediate sampled even signal;
  • the second AND gate 531 is used to perform an AND operation on the fourth intermediate sampled even signal and the second mode clock signal to obtain the first chip select clock even signal.
  • the seventh sampling circuit 407 may be composed of a seventh flip-flop 525 and a fourth inverter 526
  • the eighth sampling circuit 408 may be composed of a seventh flip-flop 525 and a fourth inverter 526 . It is composed of eight flip-flops 529; among them, the seventh flip-flop 525 and the eighth flip-flop 529 can both be D-type flip-flops.
  • the fourth inverter 526 may not be provided, and then the subsequent logical operations need to be adjusted accordingly, for example, the second NOR gate 527 is adjusted to OR door, thus achieving the same effect.
  • each device in the second logic circuit 332 can be understood with reference to FIG. 4 and FIG. 5 .
  • the chip select odd signal to be processed is represented by PCS_O; the first intermediate sample even signal output by the seventh sampling circuit 407 can be represented by PCSB_E, and the second intermediate sample output by the second NOR gate 527
  • the even signal can be represented by PCS_EEN1, the third intermediate sampled even signal output through the eighth sampling circuit 408 can be represented by PCS_EEN2, and the fourth intermediate sampled even signal output through the second OR gate 530 can be represented by PCS_EEN.
  • the first chip select clock even signal output by 531 can be represented by 2T_CLK_E.
  • the second NOR gate 527 is used to filter the first chip select signal and output the PCS_EEN1 signal with pulses according to the first chip select signal of the second type of pulse shape.
  • the first chip select signal of other pulse shapes is shielded as the always low-level PCS_EEN1 signal, so that the 2T_CLK_E signal with pulses can be obtained subsequently.
  • the seventh sampling circuit 407 is used to implement one level of rising edge sampling, while the second inverter 528 and the eighth sampling circuit 408 are used to implement one level of falling edge sampling.
  • the second type of pulse shape refers to that the first chip select signal changes to low level in odd clock cycles and changes to high level in adjacent even clock cycles.
  • the period mode at this time can be a single period mode or a double period mode.
  • the PCS_EEN 1 signal and the PCS_EEN 2 signal are obtained.
  • the PCS_EEN2 signal and the PCS_EEN2 signal are each high-level pulse signals, and the rising edge of the PCS_EEN 2 signal is delayed by a preset clock cycle compared to the rising edge of the PCS_EEN 1 signal.
  • the OR operation of the PCS_EEN 1 signal and the PCS_EEN 2 signal can broaden the pulse width, and the resulting pulse width of the PCS_EEN signal is 3 times the preset clock cycle;
  • the PCS_EEN signal and the PCLK_2NO_1NE signal are ANDed.
  • the resulting 2T_CLK_E signal has two pulses, and the pulse width is the preset clock cycle.
  • the rising edge of the first pulse is used to generate the rising edge of the 2T CMD signal
  • the rising edge of the second pulse is used to generate the falling edge of the 2T CMD signal, which can ensure the stability of the 2T CMD signal.
  • the pulse width clock is 2 preset clock cycles within the preset accuracy range, which can prevent the pulse width of the 2T CMD signal from being affected by the preparation process or environment and prevent signal failure.
  • the 2T_CLK_O signal and the 2T_CLK_E signal are at most There is only one valid signal, which has two pulses, and the pulse width of each pulse is 1 preset clock period.
  • the effective signal among the 2T_CLK_O signal and the 2T_CLK_E signal is subsequently used as the clock of the decoding process, and the target command signal obtained by decoding can be distinguished as the 2T CMD signal, and at the same time, the pulse width of the target command signal is guaranteed to be the preset accuracy range. Assume twice the clock period.
  • the third logic circuit 341 may include a ninth sampling circuit 409, a third NOT gate 534, a third NOR gate 535, a fourth NOT gate 536, a tenth Sampling circuit 410, third OR gate 538 and third AND gate 539; wherein,
  • the ninth sampling circuit 409 is used to use the first mode clock signal to sample and invert the chip select even signal to be processed to obtain the fifth intermediate sampling odd signal;
  • the third NOT gate 534 is used to perform a NOT operation on the first mode chip select signal to obtain the first mode chip select inverted signal;
  • the third NOR gate 535 is used to perform a NOR operation on the fifth intermediate sampled odd signal and the first mode chip select inverted signal to obtain the sixth intermediate sampled odd signal;
  • the fourth NOT gate 536 is used to perform a NOT operation on the first mode clock signal to obtain the first mode clock inversion signal
  • the tenth sampling circuit 410 is used to perform sampling processing on the sixth intermediate sampling odd signal using the first mode clock inverted signal to obtain the seventh intermediate sampling odd signal;
  • the third OR gate 538 is used to perform an OR operation on the sixth intermediate sampled odd signal and the seventh intermediate sampled odd signal to obtain the eighth intermediate sampled odd signal;
  • the third AND gate 539 is used to perform an AND operation on the eighth intermediate sampled odd signal and the first mode clock signal to obtain the second chip select clock odd signal.
  • the ninth sampling circuit 409 may be composed of a ninth flip-flop 421 and a fifth inverter 532
  • the tenth sampling circuit 410 may be composed of a ninth flip-flop 421 and a fifth inverter 532 . It is composed of ten flip-flops 537; among them, the ninth flip-flop 421 and the tenth flip-flop 537 can both be D-type flip-flops.
  • the fifth inverter 532 may not be provided, and subsequent logical operations need to be adjusted accordingly, for example, the third NOT gate 534 may be removed, and the third inverter 532 may be removed.
  • the three NOR gate 535 is adjusted to an OR gate, thereby achieving the same effect.
  • each device in the third logic circuit 341 can be understood with reference to FIG. 4 and FIG. 5 .
  • the chip select even signal to be processed is represented by PCS_E; the fifth intermediate sample odd signal output by the ninth sampling circuit 409 can be represented by PCSB_O, and the sixth intermediate sample output by the third NOR gate 535
  • the odd signal can be represented by NT_PCS_OEN1, the seventh intermediate sample odd signal output by the tenth sampling circuit 410 can be represented by NT_PCS_OEN2, and the eighth intermediate sample odd signal output by the third OR gate 538 can be represented by NT_PCS_OEN.
  • the second chip select clock odd signal output by 539 can be represented by NT_CLK_O.
  • the third NOT gate 534 and the third NOR gate 535 are used to filter the first chip select signal according to the first chip select signal of the third type of pulse shape. Output the NT_PCS_OEN1 signal with pulses, and mask the first chip select signal of other pulse shapes to the NT_PCS_OEN1 signal that is always low, so that the NT_CLK_O signal with pulses can be obtained subsequently.
  • the ninth sampling circuit 409 is used to implement one-level rising edge sampling, and the fourth NOT gate 536 and the tenth sampling circuit 410 are used to implement one level of falling edge sampling.
  • the third type of pulse shape refers to the first chip select signal changing to low level in even-numbered clock cycles in single-cycle mode and still being low-level in adjacent odd-numbered clock cycles, or the first chip select signal in dual-cycle mode changing to low level in the adjacent odd-numbered clock cycles.
  • the two adjacent even-numbered clock cycles change to low level and the middle odd-numbered clock cycle changes to high level.
  • the PCS_E signal is processed by using one level of rising edge sampling, NOT operation, NOR operation and one level of falling edge sampling to obtain the NT_PCS_OEN1 signal and NT_PCS_OEN2 signal.
  • the NT_PCS_OEN1 signal and the NT_PCS_OEN2 signal are each high-level pulse signals, and the rising edge of the NT_PCS_OEN2 signal is delayed by a preset clock cycle compared to the rising edge of the NT_PCS_OEN1 signal.
  • the OR operation of the NT_PCS_OEN1 signal and the NT_PCS_OEN2 signal can widen the pulse width.
  • the resulting pulse width of the NT_PCS_OEN signal is 3 times the preset clock period, and then the NT_PCS_OEN signal and the PCLK_2NE_1NO signal (PCLK_O signal in single-cycle mode, In the two-cycle mode, the PCLK_E signal is ANDed, and the resulting NT_CLK_O signal has two pulses, and the pulse width is the preset clock cycle.
  • the rising edge of the first pulse is used to generate the rising edge of the NT ODT CMD signal
  • the rising edge of the second pulse is used to generate the falling edge of the NT ODT CMD signal, which can ensure that the NT ODT
  • the pulse width clock of the CMD signal is 2 preset clock cycles within the preset accuracy range, which can prevent the pulse width of the NT ODT CMD signal from being affected by the preparation process or environment and prevent signal failure.
  • the fourth logic circuit 342 may include an eleventh sampling circuit 411 , a fifth NOT gate 542 , a fourth NOR gate 543 , a sixth NOT gate 544 , Twelve sampling circuit 412, fourth OR gate 546 and fourth AND gate 547; wherein,
  • the eleventh sampling circuit 411 is used to use the second mode clock signal to sample and invert the chip select odd signal to be processed to obtain the fifth intermediate sampled even signal;
  • the fifth NOT gate 542 is used to perform a NOT operation on the second mode chip select signal to obtain the second mode chip select inverted signal;
  • the fourth NOR gate 543 is used to perform a NOR operation on the fifth intermediate sampled even signal and the second mode chip select inverted signal to obtain the sixth intermediate sampled even signal;
  • the sixth NOT gate 544 is used to perform a NOT operation on the second mode clock signal to obtain the second mode clock inversion signal
  • the twelfth sampling circuit 412 is used to perform sampling processing on the sixth intermediate sampled even signal using the second mode clock inverted signal to obtain the seventh intermediate sampled even signal;
  • the fourth OR gate 546 is used to perform an OR operation on the sixth intermediate sampled even signal and the seventh intermediate sampled even signal to obtain the eighth intermediate sampled even signal;
  • the fourth AND gate 547 is used to perform an AND operation on the eighth intermediate sample even signal and the second mode clock signal to obtain the second chip select clock even signal.
  • the eleventh sampling circuit 411 may be composed of an eleventh flip-flop 540 and a sixth inverter 541
  • the twelfth sampling circuit 412 may be is composed of a twelfth flip-flop 545; wherein both the eleventh flip-flop 540 and the twelfth flip-flop 545 can be D-type flip-flops.
  • the sixth inverter 541 may not be provided, and the subsequent logical operations need to be adjusted accordingly, for example, the fifth NOT gate 542 may be removed, and the fifth inverter 541 may be removed.
  • the fourth NOR gate 543 is adjusted to an OR gate, so that the same effect can be achieved.
  • each device of the fourth logic circuit 342 can be understood with reference to FIG. 4 and FIG. 5 .
  • the chip select odd signal to be processed is represented by PCS_O; the fifth intermediate sampled even signal output by the eleventh sampling circuit 411 can be represented by PCSB_E, and the sixth intermediate sampled signal output by the fourth NOR gate 543 can be represented by PCSB_E.
  • the sampled even signal can be represented by NT_PCS_EEN1, the seventh intermediate sampled even signal output by the twelfth sampling circuit 412 can be represented by NT_PCS_EEN2, and the eighth intermediate sampled even signal output by the fourth OR gate 546 can be represented by NT_PCS_EEN.
  • the second chip select clock even signal output by AND gate 547 can be represented by NT_CLK_E.
  • the fifth NOT gate 542 and the fourth NOR gate 543 are used to filter the first chip select signal and output the first chip select signal according to the fourth type of pulse shape.
  • the eleventh sampling circuit 411 is used to implement a first-level rising edge sampling circuit
  • the sixth NOT gate 544 and the twelfth sampling circuit 412 are used to implement a first-level falling edge sampling circuit.
  • the fourth type of pulse shape refers to the first chip select signal changing to low level in odd-numbered clock cycles in single-cycle mode and remaining low level in adjacent even-numbered clock cycles, or the first chip select signal changing in phase in double-cycle mode.
  • the two adjacent odd-numbered clock cycles change to low level and the middle even-numbered clock cycle becomes high level.
  • the NT_PCS_EEN 1 signal and the NT_PCS_EEN 2 signal are each high-level pulse signals, and the rising edge of the NT_PCS_EEN 2 signal is delayed by a preset clock cycle compared to the rising edge of the NT_PCS_EEN 1 signal.
  • the OR operation of the NT_PCS_EEN 1 signal and the NT_PCS_EEN 2 signal can broaden the pulse width, and the resulting pulse width of the NT_PCS_EEN signal is 3 times the preset clock cycle; through the fourth AND gate 547 , perform an AND operation on the NT_PCS_EEN signal and the PCLK_2NO_1NE (PCLK_E in single-cycle mode, PCLK_O in two-cycle mode) signal.
  • the resulting NT_CLK_O signal has two pulses, and the pulse width is the preset clock cycle.
  • the rising edge of the first pulse is used to generate the rising edge of the NT ODT CMD signal
  • the rising edge of the second pulse is used to generate the falling edge of the NT ODT CMD signal, which can ensure that the NT ODT
  • the pulse width of the CMD signal is 2 preset clock cycles within the preset accuracy range, which can prevent the pulse width of the NT ODT CMD signal from being affected by the preparation process or environment and prevent signal failure.
  • the NT_CLK_O signal and the NT_CLK_E signal are different according to the pulse shape of the first chip select signal and the corresponding clock cycle parity when the level state change begins.
  • the valid signal has two pulses, and the pulse width of each pulse is 1 preset clock cycle.
  • the effective signal among the NT_CLK_O signal and the NT_CLK_E signal is subsequently used as the clock of the decoding process, and the target command signal obtained by decoding can be distinguished as the NT ODT CMD signal, while ensuring that the pulse width of the target command signal is 2 preset clock cycles. .
  • the target command signal decoded in different cycle modes is the NT ODT CMD signal or the 2T CMD signal, while ensuring that the pulse width of the target command signal is within the preset accuracy range of 2 preset clocks. cycle.
  • the instruction decoding circuit 35 may include a first instruction decoding circuit 351 and a second instruction decoding circuit 352; wherein,
  • the first instruction decoding circuit 351 is used to receive the first chip select clock signal, decode and sample the instruction signal to be processed according to the first chip select clock signal and the chip select signal to be processed, and obtain the first target instruction signal;
  • the second instruction decoding circuit 352 is configured to receive the second chip select clock signal, decode and sample the instruction signal to be processed according to the second chip select clock signal and the chip select signal to be processed, and obtain the second target instruction signal.
  • the initial chip select signal is a signal indicating that the target chip is selected, and the initial chip select signal is an active low-level pulse signal;
  • the first chip select clock signal is determined to be a valid signal
  • the first target command signal output through the first command decoding circuit is determined to be the target command signal
  • the second chip select clock signal is determined to be a valid signal
  • the second target command signal output via the second command decoding circuit is determined as the target command signal.
  • the first target command signal can be represented by the 2T CMD signal
  • the second target command signal can be represented by the NT ODT CMD signal.
  • the 2T CMD signal is output through the first command decoding circuit
  • the NT ODT CMD signal is output through the second command decoding circuit, which can avoid confusion. Distinguish between different types of command signals.
  • the first instruction decoding circuit 351 can It includes a first decoding sampling circuit 421 and a fifth OR gate 548; wherein,
  • the first decoding sampling circuit 421 is used to decode and sample the instruction even signal to be processed according to the first chip select clock odd signal and the chip select even signal to be processed, to obtain the first instruction even signal; and according to the first chip select The clock even signal and the chip select odd signal to be processed are decoded and sampled to obtain the first instruction odd signal;
  • the fifth OR gate 548 is used to perform an OR operation on the first instruction even signal and the first instruction odd signal to obtain the first target instruction signal;
  • the second instruction decoding circuit 352 includes a second decoding sampling circuit 422 and a sixth OR gate 549; wherein,
  • the second decoding sampling circuit 422 is used to decode and sample the instruction even signal to be processed according to the second chip select clock odd signal and the chip select even signal to be processed, to obtain the second instruction even signal; and according to the second chip select The clock even signal and the chip select odd signal to be processed are decoded and sampled to obtain the second instruction odd signal;
  • the sixth OR gate 549 is used to perform an OR operation on the second command even signal and the second command odd signal to obtain the second target command signal.
  • the first decoding sampling circuit 421 here can also be called the first instruction decoding flip-flop, represented by CMD DEC DFF1.
  • the output of the first decoding sampling circuit 421 includes the first command even signal and the first command odd signal; wherein, the first command even signal is represented by 2T_CMD_E, and the first command odd signal is represented by 2T_CMD_O; and then the 2T_CMD_E signal and the 2T_CMD_O signal are After performing the OR operation, the first target command signal is obtained and is represented by 2T CMD.
  • the second decoding sampling circuit 422 can also be called the second instruction decoding flip-flop, represented by CMD DEC DFF2.
  • the output of the second decoding sampling circuit includes the second command even signal and the second command odd signal; wherein, the second command even signal is represented by NT_CMD_E, and the second command odd signal is represented by NT_CMD_O; and then the NT_CMD_E signal and the NT_CMD_O signal are After the OR operation, the second target command signal is obtained and is represented by NT ODT CMD.
  • the first decoding sampling circuit 421 includes a first decoding circuit 550, a thirteenth sampling circuit 551, a second decoding circuit code circuit 552 and the fourteenth sampling circuit 553; among them,
  • the first decoding circuit 550 is used to decode the chip select even signal to be processed and the instruction even signal to be processed to obtain the first decoded even signal;
  • the thirteenth sampling circuit 551 is used to sample the first decoding even signal using the odd signal of the first chip select clock to obtain the first instruction even signal;
  • the second decoding circuit 552 is used to decode the chip select odd signal to be processed and the instruction odd signal to be processed to obtain the first decoded odd signal;
  • the fourteenth sampling circuit 553 is used to sample the first decoded odd signal using the first chip select clock even signal to obtain the first instruction odd signal.
  • the instruction signals to be processed may include five signals, including CA[0]_1T_E, CA[1]_1T_E, CA[2]_1T_E, CA[3]_1T_E, and CA[4]_1T_E.
  • the first decoding circuit 550 may be composed of a three-input NAND gate, a three-input NAND gate, and a two-input NOR gate.
  • PCS_E, CA[0]_1T_E and CA[1]_1T_E are input to the first three-input NAND gate
  • CA[2]_1T_E, CA[3]_1T_E and CA[4]_1T_E are input to the second three-input NAND gate.
  • NAND gate, then the output of the first three-input NAND gate is connected to one input of the two-input NOR gate, and the output of the second three-input NAND gate is connected to the other input of the two-input NOR gate.
  • the thirteenth sampling circuit 551 performs sampling output.
  • the thirteenth sampling circuit 551 can be a D-type flip-flop, the clock terminal of the D-type flip-flop is connected to the 2T_CLK_O signal, the input terminal of the D-type flip-flop is connected to the output terminal of the two-input NOR gate, and the D-type flip-flop The output terminal of the flip-flop is used to output the 2T_CMD_E signal.
  • the odd signal of instructions to be processed may include CA[0]_1T_O, CA[1]_1T_O, CA[2]_1T_O, CA[3]_1T_O, CA[4]_1T_O, etc. signal
  • the second decoding circuit 552 may be composed of a three-input NAND gate, a three-input NAND gate, and a two-input NOR gate.
  • PCS_O, CA[0]_1T_O and CA[1]_1T_O are input to the first three-input NAND gate
  • CA[2]_1T_O, CA[3]_1T_O and CA[4]_1T_O are input to the second three-input NAND gate.
  • NAND gate, then the output of the first three-input NAND gate is connected to one input of the two-input NOR gate, and the output of the second three-input NAND gate is connected to the other input of the two-input NOR gate.
  • the fourteenth sampling circuit 553 performs sampling output.
  • the fourteenth sampling circuit 553 can also be a D-type flip-flop.
  • the clock terminal of the D-type flip-flop is connected to the 2T_CLK_E signal.
  • the input terminal of the D-type flip-flop is connected to the output terminal of the two-input NOR gate.
  • D The output terminal of the flip-flop is used to output the 2T_CMD_O signal.
  • the second decoding sampling circuit 422 includes a third decoding circuit 554, a fifteenth sampling circuit 555, a fourth decoding circuit 556 and a tenth Six sampling circuit 557; among them,
  • the third decoding circuit 554 is used to decode the chip select even signal to be processed and the instruction even signal to be processed to obtain a second decoded even signal;
  • the fifteenth sampling circuit 555 is used to sample the second decoded even signal using the odd signal of the second chip select clock to obtain the second instruction even signal;
  • the fourth decoding circuit 556 is used to decode the chip select odd signal to be processed and the instruction odd signal to be processed to obtain a second decoded odd signal;
  • the sixteenth sampling circuit 557 is used to sample the second decoded odd signal using the even signal of the second chip select clock to obtain the second instruction odd signal.
  • the second decoding sampling circuit 422 and the first decoding sampling circuit 421 have the same circuit structure, but the signals received by some signal terminals are different, which can be compared with the first decoding sampling circuit 421 for reference and understanding. .
  • the design of these decoding circuits is specifically based on the instruction decoding. implemented by rules. For different products, different application scenarios, and different instructions, the decoding rules may be different, and the logic of the decoding circuit may also be adjusted accordingly, which is not specifically limited in the embodiments of this disclosure.
  • the mode selection circuit 32, the first clock processing circuit 33 and the second clock processing circuit 34 different first chip selection clock signals (using 2T_CLK_E/2T_CLK_O) and the second chip select clock signal (represented by NT_CLK_E/NT_CLK_O); in this way, when the initial chip select signal includes a pulse and the pulse width is the preset clock cycle (corresponding to the 2T CMD signal in single cycle mode or double 2T CMD signal in periodic mode), using the 2T_CLK_E/2T_CLK_O signal, the first target command signal obtained through the first command decoding circuit 351 is a valid signal (that is, a high-level active pulse signal), and through the second command decoding circuit 351 The second target command signal obtained by the code circuit 352 is an invalid signal (ie, a low level signal); on the contrary, when the initial chip select signal includes a pulse and the pulse width is twice the preset clock cycle (corresponding to NT in the single-cycle mode ODT CMD signal) or the initial chip
  • the signal processing process of the signal sampling circuit can be divided into three situations according to the periodic pattern and the pulse shape of the initial chip select signal.
  • Case 1 When the target mode is single-cycle mode or dual-cycle mode, and the initial chip select signal includes one pulse and the pulse width is the preset clock cycle, it is determined that the first chip select clock signal includes two pulses, and the pulse width of each pulse is The pulse width is the preset clock cycle.
  • the rising edge of the first pulse in the first chip select clock signal is used to generate the rising edge of the first target command signal.
  • the rising edge of the second pulse in the first chip select clock signal is used to generate the third A falling edge of the target command signal; and, determining that the second chip select clock signal maintains a constant level state, and the second target command signal maintains a constant level state.
  • Case 2 When the target mode is single-cycle mode, and the initial chip select signal includes one pulse and the pulse width is twice the preset clock cycle, it is determined that the first chip select clock signal maintains the level state unchanged, and the first target instruction The signal maintains the level state unchanged; and, it is determined that the second chip select clock signal includes two pulses, and the pulse width of each pulse is the preset clock period, and the rising edge of the first pulse in the second chip select clock signal is used for Generate the rising edge of the second target command signal, and the rising edge of the second pulse in the second chip select clock signal is used to generate the falling edge of the second target command signal;
  • Case 3 When the target mode is a two-cycle mode, and the initial chip select signal includes 2 pulses and the pulse width is the preset clock cycle, it is determined that the first target command signal maintains the level state unchanged; and, it is determined that the second chip select signal
  • the clock signal includes two pulses, and the pulse width of each pulse is a preset clock period.
  • the rising edge of the first pulse in the second chip select clock signal is used to generate the rising edge of the second target command signal.
  • the second chip select clock The rising edge of the second pulse in the signal is used to generate the falling edge of the second target command signal.
  • Situation 1 can be further divided into two specific situations for description. That is to say, when the target mode is single-cycle mode or dual-cycle mode, and the initial chip select signal includes one pulse and the pulse width is the preset clock cycle,
  • the odd signal of the first chip select clock is determined to be a valid signal, and the The odd signal of the chip select clock has two pulses; among them, the rising edge of the first pulse in the odd signal of the first chip select clock is used to generate the rising edge of the first target command signal, and the second pulse of the odd signal of the first chip select clock is used to generate the rising edge of the first target command signal. The rising edge of the pulse is used to generate the falling edge of the first target command signal;
  • the even signal of the first chip select clock is a valid signal
  • the The chip select clock even signal has two pulses; among them, the rising edge of the first pulse in the first chip select clock even signal is used to generate the rising edge of the first target command signal, and the second pulse in the first chip select clock even signal The rising edge of the pulse is used to generate the falling edge of the first target command signal.
  • the second situation can be further divided into two specific situations for description. That is, when the target mode is single-cycle mode and the initial chip select signal includes a pulse with a pulse width twice the preset clock period,
  • the odd signal of the second chip select clock is determined to be a valid signal
  • the second chip select clock odd signal has two pulses; among them, the rising edge of the first pulse in the second chip select clock odd signal is used to generate the rising edge of the second target command signal, and the second pulse in the second chip select clock odd signal is used to generate the rising edge of the second target command signal.
  • the rising edge of a pulse is used to generate the falling edge of the second target command signal;
  • the even signal of the second chip select clock is determined to be a valid signal
  • the second chip select clock even signal has two pulses; wherein, the rising edge of the first pulse in the second chip select clock even signal is used to generate the rising edge of the second target command signal, and the second pulse in the second chip select clock even signal is used to generate the rising edge of the second target command signal. The rising edge of a pulse is used to generate the falling edge of the second target command signal.
  • case three is further divided into two specific cases for description. That is to say, when the target mode is dual-cycle mode and the initial chip select signal includes 2 pulses and the pulse width is the preset clock cycle,
  • the second chip select signal is determined.
  • the clock odd signal is a valid signal
  • the second chip select clock odd signal has two pulses.
  • the rising edge of the first pulse in the second chip select clock odd signal is used to generate the rising edge of the second target command signal.
  • the second chip select The rising edge of the second pulse in the clock odd signal is used to generate the falling edge of the second target command signal;
  • the second chip select signal is determined.
  • the clock even signal is a valid signal
  • the second chip select clock even signal has two pulses; among them, the rising edge of the first pulse in the second chip select clock even signal is used to generate the rising edge of the second target command signal, and the second The rising edge of the second pulse in the chip select clock even signal is used to generate the falling edge of the second target command signal.
  • the embodiment of the present disclosure provides a signal sampling circuit.
  • the 2T CMD signal and the NT ODT CMD signal can be sampled and decoded through the aforementioned signal sampling circuit, and can clearly To distinguish the 2T CMD signal and the NT ODT CMD signal, there is no need to set up a separate decoding circuit for the dual-cycle mode, which not only saves the circuit area but also reduces the power consumption; on the other hand, according to the difference between the first chip select clock signal and the second chip select clock signal
  • the effective signal in the instruction decoding circuit outputs the target instruction signal through the corresponding instruction decoding circuit, which can distinguish the two instructions 2T CMD and NT ODT CMD and accurately decode them without affecting each other; on the other hand, due to the first chip select
  • the effective signal in the clock signal and the second chip select clock signal both includes two pulses, and the pulse width of each pulse is a preset clock cycle, and the rising edge of the first pulse is used to generate
  • the signal sampling circuit 30 may include a first receiver 501 , a second receiver 502 , a third receiver 503 , a first flip-flop 504 , and a first buffer 505 , the second flip-flop 506, the second buffer 507, the third flip-flop 508, the first inverter 509, the fourth flip-flop 510, the second inverter 511, the third buffer 512, the first multiplexer 513, the fourth buffer 514, the second multiplexer 515, the third multiplexer 516, the fourth multiplexer 517, the fifth flip-flop 518, the third inverter 519, the first NOR Gate 520, first NOT gate 521, sixth flip-flop 522, first OR gate 523, first AND gate 524, seventh flip-flop 525, fourth inverter 526, second NOR gate 527, second NOT Gate 528, eighth flip-flop 529, second OR gate 530, second AND gate 531, ninth flip-flop 5
  • the eighth flip-flop 529, the ninth flip-flop 532, the tenth flip-flop 537, the eleventh flip-flop 540, and the twelfth flip-flop 545 may all be D-type flip-flops.
  • the detailed structure of the first instruction decoding flip-flop 421 is shown in FIG. 6A
  • the detailed structure of the second instruction decoding flip-flop 422 is shown in FIG. 6B .
  • the circuit principle of Figure 5 can be referred to the foregoing description and will not be described in detail here.
  • the first command address signal is represented by CA, and CA can include Cy, Cz, C0, C1, C2 and C3;
  • the initial chip select signal is represented by CS_n, and is a signal used to indicate that the target chip is selected;
  • the first chip select signal It is represented by PCS.
  • the PCS signal is an active low-level pulse signal.
  • PCS is used to represent the signal that the target chip is selected; the initial clock signal is represented by CK_t, the first clock even signal is represented by PCLK_E, and the first clock odd signal is represented by PCLK_O. , and the clock cycle of the CK_t signal is the preset clock cycle, and the clock cycles of the PCLK_E signal and PCLK_O signal are twice the preset clock cycle.
  • the following is divided into four scenarios to specifically describe the signal timing of the signal sampling circuit 30 .
  • Scenario 1 As shown in Figure 7, assume that it is in single-cycle mode (1N MODE) and the first chip select signal is sampled as low on the rising edge of an even-numbered clock cycle and is sampled as high on the rising edge of the next adjacent odd-numbered clock cycle. level.
  • the CA signal is sampled through the PCLK_E signal to obtain the CA[4:0]_1T_E signal, which includes C0 and C2; the PCS signal is sampled and inverted through the PCLK_E signal to obtain the PCS_E signal, which is high A pulse signal with a valid level, and the pulse width is twice the preset clock period.
  • the PCS signal is sampled and inverted through the PCLK_O signal to obtain PCS_O (not shown in Figure 7, but its waveform can be referred to PCS_2NE_1NO), which is always a low-level signal.
  • the PCS_E signal is sampled and inverted through the PCLK_2NE_1NO signal (essentially the PCLK_O signal) to obtain the PCSB_O signal. It is an active low-level pulse signal, and the pulse width is twice the preset clock period, but Delayed by one preset clock cycle compared to the PCS_E signal. Perform a NOR operation on the PCSB_O signal and the PCS_2NE_1NO signal (essentially the PCS_O signal) to obtain the PCS_OEN1 signal, which is an active high-level pulse signal and the pulse width is twice the preset clock period.
  • the PCS_OEN1 signal is sampled through the falling edge of the PCLK_2NE_1NO signal (essentially the PCLK_O signal) to obtain the PCS_OEN2 signal. It is also a high-level active pulse signal, and the pulse width is twice the preset clock period, but it is delayed by one compared to the PCS_OEN1 signal. Default clock period. In this way, the PCS_OEN1 signal and the PCS_OEN2 signal are ORed to obtain the PCS_OEN signal, the pulse width of which is three times the preset clock period, that is, the first OR gate 523 plays a role in broadening the pulse width.
  • the PCS_OEN signal is ANDed with the PCLK_2NE_1NO signal (essentially the PCLK_O signal) to obtain the 2T_CLK_O signal, which includes 2 pulses and the pulse width is the preset clock cycle.
  • the 2T_CLK_E signal (not shown in Figure 7) is always a low-level invalid signal.
  • the 2T_CLK_O signal is used to decode and sample the CA[4:0]_1T_E signal to obtain the 2T CMD signal
  • the 2T CMD signal is a high-level pulse signal with a pulse width It is twice the preset clock period; among them, the rising edge of the first pulse in the 2T_CLK_O signal is used to generate the rising edge of the 2T CMD signal, and the rising edge of the second pulse in the 2T_CLK_O signal is used to generate the falling edge of the 2T CMD signal.
  • the essence of the PCLK_2NE_1NO signal is the PCLK_O signal, which means: the PCLK_2NE_1NO signal is derived from the PCLK_O signal, and the PCLK_2NE_1NO signal has the same waveform as the PCLK_O signal, but the PCLK_2NE_1NO signal may be slightly smaller than the PCLK_O signal (generated due to passing through the logic gate) Delay (not shown in this delay diagram).
  • the word "essence” in the embodiments of the present disclosure can be understood correspondingly with reference to this explanation.
  • the PCS_E signal is sampled and inverted through the PCLK_2NE_1NO signal (essentially the PCLK_O signal) to obtain the PCSB_O signal, which is an active low-level pulse signal, and the pulse width is twice the preset clock period. Since the inverted signal of PCS_2NE_1NO (essentially a PCS_O signal) is always a high-level signal, by performing a NOR operation on the PCSB_O signal and the inverted signal of PCS_2NE_1NO (essentially a PCS_O signal), we can obtain a signal that is always a low-level signal.
  • the NT_PCS_OEN1 signal and NT_PCS_OEN2 are always low-level signals, so the NT_CLK_O signal is always a low-level invalid signal.
  • the NT_CLK_E signal in this case is also a low-level invalid signal. Therefore, neither the NT_CLK_O signal nor the NT_CLK_E signal will result in effective decoding sampling, and the NT ODT CMD signal cannot be obtained.
  • the CS_n signal has only one low level of the preset clock cycle, which is sampled by the PCLK_E signal and becomes the PCS_E signal, and then in PCLK_2NE_1NO (in single In periodic mode, it is PCLK_O) and becomes the PCSB_O signal after sampling.
  • the PCSB_O signal and PCS_2NE_1NO perform NOR logic and then sample and generate PCS_OEN1/2 to cover the 2T_CLK_O signal.
  • the 2T_CLK_O signal samples the CA[4:0]_1T_E signal and the PCS_E signal and outputs the 2T CMD signal.
  • the other branch circuit is an inverted signal of the PCSB_O/E signal and the PCS_2NE_1NO/PCS_2NO_1NE signal, which causes the NT_PCS_OEN1/2 signal and the NT_PCS_EEN1/2 signal to be low level without covering the clock sampling, so there will be no Output NT ODT CMD signal.
  • the 2T_CLK_E signal includes two pulses, and the pulse The width is the preset clock cycle, but the 2T_CLK_O signal is always a low-level invalid signal.
  • the CA[4:0]_1T_O signal is decoded and sampled according to the 2T_CLK_E signal to obtain the 2T CMD signal.
  • the rising edge of the first pulse in the 2T_CLK_E signal is used to generate the rising edge of the 2T CMD signal
  • the rising edge of the second pulse in the 2T_CLK_E signal is used to generate the falling edge of the 2T CMD signal.
  • the NT_CLK_O signal and NT_CLK_E signal are both low-level invalid signals, so neither the NT_CLK_O signal nor the NT_CLK_E signal will trigger effective decoding sampling, and the NT ODT CMD signal cannot be obtained.
  • Scenario 2 As shown in Figure 8, assume that in single-cycle mode (1N MODE) and the first chip select signal is sampled as low level on the rising edge of an even-numbered clock cycle and is still sampled on the rising edge of the next adjacent odd-numbered clock cycle. low level.
  • the CA signal is sampled through the PCLK_E signal to obtain the CA[4:0]_1T_E signal, which includes C0 and C2; the PCS signal is sampled and inverted through the PCLK_E signal to obtain the PCS_E signal, which is high A pulse signal with a valid level, and the pulse width is twice the preset clock period.
  • the PCS signal is sampled and inverted by the PCLK_O signal to obtain the PCS_O signal (not shown in Figure 7, but its waveform can refer to PCS_2NE_1NO). It is a high-level pulse signal with a pulse width of two times the preset clock period. times. However, the rising edge of the PCS_O signal is delayed by a preset clock cycle compared to the rising edge of the PCS_E signal.
  • the PCS_E signal is sampled and inverted through the PCLK_2NE_1NO signal (essentially the PCLK_O signal) to obtain the PCSB_O signal. It is an active low-level pulse signal, and the pulse width is twice the preset clock period, but Delayed by one preset clock cycle compared to PCS_B. Perform a NOR operation on the PCSB_O signal and PCS_2NE_1NO (essentially the PCS_O signal), and cancel the two to obtain the PCS_OEN1 signal that is always low level, and then the 2T_CLK_O signal is always an invalid signal with low level.
  • the 2T_CLK_E signal in this case is always a low-level invalid signal. Therefore, neither the 2T_CLK_O signal nor the 2T_CLK_E signal will result in effective decoding sampling, and the 2T CMD signal cannot be obtained.
  • the PCS_E signal is sampled and inverted through the PCLK_2NE_1NO signal (essentially the PCLK_O signal) to obtain the PCSB_O signal, which is an active low-level pulse signal, and the pulse width is twice the preset clock period.
  • the NT_PCS_OEN1 signal is sampled through the falling edge of the PCLK_2NE_1NO signal to obtain the NT_PCS_OEN2 signal, which is also a high-level active pulse signal, and the pulse width is twice the preset clock cycle, but is delayed by one preset clock cycle compared to the NT_PCS_OEN1 signal.
  • the NT_PCS_OEN1 signal and the NT_PCS_OEN2 signal are ORed to obtain the NT_PCS_OEN signal, the pulse width of which is three times the preset clock period, that is, the third OR gate 538 plays a role in broadening the pulse width.
  • NT_PCS_OEN is ANDed with the PCLK_2NE_1NO signal to obtain NT_CLK_O, which includes 2 pulses and the pulse width is the preset clock cycle.
  • the NT_CLK_E signal in this case is always a low-level invalid signal.
  • the NT_CLK_O signal is used to decode and sample the CA[4:0]_1T_E signal to obtain the NT ODT CMD signal
  • the NT ODT CMD signal is a high-level active pulse signal
  • the pulse width is twice the preset clock period; among them, the rising edge of the first pulse in the NT_CLK_O signal is used to generate the rising edge of the NT ODT CMD signal, and the rising edge of the second pulse in the NT_CLK_O signal is used to generate the NT ODT CMD the falling edge of the signal.
  • the CS_n signal maintains a low level for 2 preset clock cycles. It is sampled by the PCLK_E/O signal and then becomes the PCS_E/O signal. Then the PCS_E/O signal is sampled by the PCLK_2NE_1NO/PCLK_2NO_1NE signal. After that, the PCSB_O/E signal, the PCSB_O/E signal and the PCS_2NE_1NO/PCS_2NO_1NE signal perform NOR logic. The obtained PCS_OEN1/2 signal and PCS_EEN1/2 signal are both low level, and the clock sampling is not covered, so the 2T CMD will not be output. Signal.
  • the other branch circuit is the inverted signal of the PCSB_O signal and the PCS_2NE_1NO signal for NOR logic, thereby generating NT_PCS_OEN1/2 to cover the NT_CLK_O signal with two pulses. Finally, this NT_CLK_O signal samples the CA[4:0]_1T_E signal and PCS_E signal output NT ODT CMD signal.
  • the NT_CLK_E signal consists of two pulses with a pulse width of It is the preset clock cycle, but the NT_CLK_O signal is always a low-level invalid signal.
  • the CA[4:0]_1T_O signal is decoded and sampled according to the NT_CLK_E signal to obtain the NT ODT CMD signal, and the NT ODT CMD signal is a high-level active pulse signal, and The pulse width is twice the preset clock period.
  • the rising edge of the first pulse in the NT_CLK_E signal is used to generate the rising edge of the NT ODT CMD signal
  • the rising edge of the second pulse in the NT_CLK_E signal is used to generate the falling edge of the NT ODT CMD signal.
  • the 2T_CLK_O signal and the 2T_CLK_E signal are always low-level invalid signals, so the 2T_CLK_O signal and the 2T_CLK_E signal will not trigger effective decoding sampling, and the 2T CMD signal cannot be obtained.
  • Scenario 3 As shown in Figure 9, assume that in the two-cycle mode (2N MODE) and the first chip select signal is sampled as low level on the rising edge of the even-numbered clock cycle and sampled as high on the rising edge of the next adjacent odd-numbered clock cycle level.
  • the CA signal is sampled through the PCLK_E signal to obtain the CA[4:0]_1T_E signal, which includes C0 and C2; the PCS signal is sampled and inverted through the PCLK_E signal to obtain the PCS_E signal, which is high A pulse signal with a valid level, and the pulse width is twice the preset clock period.
  • the PCS signal is sampled and inverted through the PCLK_O signal to obtain PCS_O (not shown in Figure 9), which is always a low-level signal.
  • the PCS_E signal is sampled and inverted through the PCLK_2NE_1NO signal (essentially the PCLK_E signal) to obtain the PCSB_O signal, which is an active low-level pulse signal, and the pulse width is twice the preset clock cycle.
  • the PCS_OEN1 signal is sampled through the falling edge of the PCLK_2NE_1NO signal to obtain the PCS_OEN2 signal, which is also a high-level active pulse signal, and the pulse width is twice the preset clock cycle, but is delayed by one preset clock cycle compared to the PCS_OEN1 signal.
  • the PCS_OEN1 signal and the PCS_OEN2 signal are ORed and then logically ANDed with the PCLK_2NE_1NO signal to obtain the 2T_CLK_O signal, which includes 2 pulses and the pulse width is the preset clock cycle.
  • the 2T_CLK_E signal in this case is always a low-level invalid signal.
  • the 2T_CLK_O signal is used to decode and sample the CA[4:0]_1T_E signal to obtain the 2T CMD signal
  • the 2T CMD signal is a high-level pulse signal with a pulse width It is twice the preset clock period; among them, the rising edge of the first pulse in the 2T_CLK_O signal is used to generate the rising edge of the 2T CMD signal, and the rising edge of the second pulse in the 2T_CLK_O signal is used to generate the falling edge of the 2T CMD signal.
  • the PCS_E signal is sampled and inverted through the PCLK_2NE_1NO signal to obtain the PCSB_O signal, which is an active low-level pulse signal, and the pulse width is twice the preset clock period.
  • the PCSB_O signal and the inverted signal of PCS_2NE_1NO are NOR-operated, and they are exactly offset, and the NT_PCS_OEN1 signal is always a low-level signal, and NT_PCS_OEN2 is always a low-level signal, so the NT_CLK_O signal is always low. Invalid signal level.
  • the NT_CLK_E signal in this case is always a low-level invalid signal. Therefore, neither the NT_CLK_O signal nor the NT_CLK_E signal will trigger effective decoding sampling, and the NT ODT CMD signal cannot be obtained.
  • the CS_n signal has only one low level of the preset clock cycle. It becomes the PCS_E signal after being sampled by the PCLK_E signal, and then becomes the PCLK_2NE_1NO signal after being sampled. is the PCSB_O signal. Among them, the PCSB_O signal and the PCS_2NE_1NO signal perform NOR logic and then sample and generate the PCS_OEN1/2 signal to cover the 2T_CLK_O signal. Finally, the 2T_CLK_O signal samples the CA[4:0]_1T_E signal and the PCS_E signal and outputs the 2T CMD signal.
  • the other branch circuit is an inverted signal of the PCSB_O/E signal and the PCS_2NE_1NO/PCS_2NO_1NE signal, which causes the NT_PCS_OEN1/2 signal and the NT_PCS_EEN1/2 signal to be low level without covering the clock sampling, so there will be no Output NT ODT CMD signal.
  • the 2T_CLK_E signal includes two pulses, each The width of the pulse is the preset clock period, but the 2T_CLK_O signal clock is a low-level invalid signal.
  • the CA[4:0]_1T_O signal is decoded and sampled according to the 2T_CLK_E signal to obtain the 2T CMD signal.
  • the rising edge of the first pulse in the 2T_CLK_E signal is used to generate the rising edge of the 2T CMD signal
  • the rising edge of the second pulse in the 2T_CLK_E signal is used to generate the falling edge of the 2T CMD signal.
  • the NT_CLK_O signal and NT_CLK_E signal are always low-level invalid signals, so neither the NT_CLK_O signal nor the NT_CLK_E signal will trigger effective decoding sampling, and the NT ODT CMD signal cannot be obtained.
  • Scenario 4 As shown in Figure 10, assume that in the two-cycle mode (2N MODE) and the first chip select signal is sampled as low level on the rising edge of two consecutive even-numbered clock cycles and between two consecutive even-numbered clock cycles. The rising edges of odd clock cycles are sampled as high.
  • the CA signal is sampled through the PCLK_E signal to obtain the CA[4:0]_1T_E signal, which includes C0 and C2; the PCS signal is sampled and inverted through the PCLK_E signal to obtain the PCS_E signal, which is high A pulse signal with a valid level, and the pulse width is 4 times the preset clock period.
  • the PCS signal is sampled and inverted through the PCLK_O signal to obtain the PCS_O signal (not shown in Figure 10), which is always low level.
  • the PCS_E signal is sampled and inverted through the PCLK_2NE_1NO signal (essentially the PCLK_E signal) to obtain the PCSB_O signal. It is an active low-level pulse signal, and the pulse width is 4 times the preset clock cycle.
  • PCS_OEN1 signal which is a high-level active pulse signal, but the rising edge of the PCS_OEN1 signal is later than the effective content of the CA[4:0]_1T_E signal C0
  • the PCS_OEN1 signal is sampled through the falling edge of the PCLK_2NE_1NO signal to obtain the PCS_OEN2 signal.
  • It is also a high-level active pulse signal, and the pulse width is twice the preset clock cycle, but it is delayed by one preset clock cycle compared to the PCS_OEN1 signal.
  • the PCS_OEN1 signal and the PCS_OEN2 signal are logically ANDed with the PCLK_2NE_1NO signal to obtain the 2T_CLK_O signal, which includes 2 pulses and the pulse width is the preset clock cycle, but the rising edge of the first pulse of the 2T_CLK_O signal is late. Due to the effective content C0 of the CA[4:0]_1T_E signal, the 2T_CLK_O signal does not result in effective decoding sampling, and the 2T CMD signal cannot be obtained. At the same time, the 2T_CLK_E signal in this case is always a low-level invalid signal. Therefore, the 2T_CLK_E signal will not result in effective decoding sampling, and the 2T CMD signal cannot be obtained.
  • the PCS_E signal is sampled and inverted through the PCLK_2NE_1NO signal (essentially the PCLK_E signal) to obtain the PCSB_O signal, which is an active low-level pulse signal and the pulse width is 4 times the preset clock cycle.
  • the PCS_OEN1 signal is sampled through the falling edge of the PCLK_2NE_1NO signal to obtain the NT_PCS_OEN2 signal, which is also a high-level active pulse signal, and the pulse width is twice the preset clock cycle, but is delayed by one preset clock cycle compared to the NT_PCS_OEN1 signal.
  • the NT_PCS_OEN1 signal and the NT_PCS_OEN2 signal are ORed and then logically ANDed with the PCLK_2NE_1NO signal to obtain NT_CLK_O, which includes 2 pulses and the pulse width is the preset clock cycle.
  • the NT_CLK_E signal in this case is always a low-level invalid signal.
  • the NT_CLK_O signal is used to decode and sample the CA[4:0]_1T_E signal to obtain the NT ODT CMD signal
  • the NT ODT CMD signal is a high-level active pulse signal
  • the pulse width is twice the preset clock period; among them, the rising edge of the first pulse in the NT_CLK_O signal is used to generate the rising edge of the NT ODT CMD signal, and the rising edge of the second pulse in the NT_CLK_O signal is used to generate the NT ODT CMD the falling edge of the signal.
  • the CS_n signal has a low level of 2 intervals, which is sampled by the PCLK_E/O signal and then becomes the PCS_E/O signal, and then the PCS_E signal is sampled by the PCLK_2NE_1NO signal.
  • the PCS_OEN1/2 signal is obtained, and the PCS_OEN1/2 signal is a high-level pulse signal, but the rising edge of the PCS_OEN1/2 signal is later than CA[4:0
  • the effective content of the ]_1T_E signal is C0, so the 2T_CLK_O signal will not cause effective decoding sampling, and the 2T CMD signal cannot be obtained; at the same time, the PCS_O signal becomes the PCSB_E signal after the PCLK_2NO_1NE signal is sampled, and the PCSB_E signal and the PCS_2NO_1NE signal are logically ORed.
  • the obtained PCS_EEN1/2 signal is always low level and does not cover the clock sampling, so the 2T CMD signal will not be output.
  • the other branch circuit is the inverted signal of the PCSB_O signal and the PCS_2NE_1NO signal for NOR logic, thereby generating NT_PCS_OEN1/2 to cover the NT_CLK_O signal with two pulses.
  • this NT_CLK_O signal samples the CA[4:0]_1T_E signal and PCS_E signal output NT ODT CMD signal.
  • the NT_CLK_E signal It includes two pulses, the width of each pulse is the preset clock period, but the NT_CLK_O signal clock is a low-level invalid signal.
  • the CA[4:0]_1T_O signal is decoded and sampled according to the NT_CLK_E signal to obtain the NT ODT CMD signal.
  • the rising edge of the first pulse in the NT_CLK_E signal is used to generate the rising edge of the NT ODT CMD signal
  • the rising edge of the second pulse in the NT_CLK_E signal is used to generate the falling edge of the NT ODT CMD signal.
  • the 2T_CLK_O signal is ultimately a low-level invalid signal.
  • the 2T_CLK_E signal has two pulses, its rising edge is later than the valid content of the CA[4:0]_1T_O signal, so the 2T_CLK_O signal is also an invalid signal.
  • the 2T_CLK_O signal and None of the 2T_CLK_E signals will result in effective decoding sampling, and the 2T CMD signal cannot be obtained.
  • the embodiment of the present disclosure provides a signal sampling circuit.
  • the specific implementation of the foregoing embodiment is described in detail through this embodiment. It can be seen that based on the technical solution of the embodiment of the present disclosure, through the signal sampling circuit of the embodiment of the present disclosure, 30.
  • the 2T CMD signal and the NT ODT CMD signal can be decoded separately in different periodic modes without affecting each other. There is no need to set up an independent decoding circuit for each periodic mode, saving circuit area and reducing power consumption.
  • FIG. 11 shows a schematic structural diagram of a semiconductor memory 110 provided by an embodiment of the present disclosure.
  • the semiconductor memory 110 may include the signal sampling circuit 30 of any of the foregoing embodiments.
  • the semiconductor memory 110 may be a DRAM chip.
  • the DRAM chip complies with DDR5 memory specifications.
  • the embodiments of the present disclosure mainly relate to circuits related to input signal sampling and instruction decoding in integrated circuit design, especially in DRAM chips, where the CA signal input in different cycle modes is used as instruction and address sampling and decoding respectively. Control and regulation circuit.
  • the technical solution of the embodiment of the present disclosure solves the problem of distinguishing 2T CMD and NT ODT CMD sampling and decoding in different periodic modes in DDR5. Instructions with different pulse shapes of the CS_n signal can be decoded into 2T CMD signals respectively. and NT ODT CMD signals, and do not affect each other.
  • the semiconductor memory 120 includes a signal sampling circuit 30. Therefore, based on the signal sampling circuit, the target mode clock signal and the target mode chip select signal are determined according to the periodic mode, In order to obtain the corresponding first chip select clock signal and the second chip select clock signal for the first chip select signal with different pulse shapes, so as to correctly distinguish 2T CMD and NT ODT CMD in different cycle modes, and perform correct decoding, It can avoid the problem of instruction decoding errors and wrong operations, while saving circuit area and reducing power consumption.
  • Embodiments of the present disclosure provide a signal sampling circuit and a semiconductor memory. Based on the signal sampling circuit, a target mode clock signal and a target mode chip select signal are determined according to the periodic mode in order to provide first chip select signals with different pulse shapes. , obtain the corresponding first chip select clock signal and the second chip select clock signal, so as to correctly distinguish the two instructions 2T CMD and NT ODT CMD in different cycle modes and perform accurate decoding, which can avoid instruction decoding errors and It eliminates the problem of incorrect operations while saving circuit area and reducing power consumption.

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Abstract

一种信号采样电路以及半导体存储器，该信号采样电路包括：信号输入电路，用于确定待处理指令信号和待处理片选信号；模式选择电路，用于根据模式选择信号确定目标模式时钟信号和目标模式片选信号；第一时钟处理电路，用于根据目标模式时钟信号对待处理片选信号和目标模式片选信号进行采样及逻辑运算处理，得到第一片选时钟信号；第二时钟处理电路，用于根据目标模式时钟信号对待处理片选信号和目标模式片选信号进行采样及逻辑运算处理，得到第二片选时钟信号；指令译码电路，用于确定目标指令信号。

Description

一种信号采样电路以及半导体存储器
相关的交叉引用
本公开基于申请号为202210292978.4、申请日为2022年03月23日、发明名称为“一种信号采样电路以及半导体存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种信号采样电路以及半导体存储器。
背景技术
随着半导体技术的不断发展，人们在制造和使用计算机等设备时，对数据的传输速度提出了越来越高的要求。为了获得更快的数据传输速度，应运而生了一系列可以双倍速率(Double Data Rate，DDR)传输的存储器等器件。
在动态随机存取存储器(Dynamic Random Access Memory，DRAM)芯片中，命令地址(Command/Address，CMD/ADD或简称为CA)信号既可以作为地址进行采样又可以作为指令进行采样译码。目前，DRAM中存在单周期模式(1N MODE)和双周期模式(2N MODE)，不同周期模式中2T CMD信号和NT ODT CMD信号所使用片选信号的脉冲形状不同，而且两者对应的操作功能也是不同的。但是现有的指令译码方案中，需要针对不同模式下的指令信号单独设置译码电路，电路面积过大，而且不同指令的信号译码过程还容易发生混淆而导致译码错误问题。
发明内容
本公开提供了一种信号采样电路以及半导体存储器，能够区分不同周期模式下2T CMD和NT ODT CMD这两种指令，并进行准确译码，同时还能够节省电路面积且降低功耗。
第一方面，本公开实施例提供了一种信号采样电路，信号采样电路包括信号输入电路、模式选择电路、第一时钟处理电路、第二时钟处理电路和指令译码电路；其中，
信号输入电路，用于根据第一时钟信号、第一片选信号和第一命令地址信号，确定待处理指令信号和待处理片选信号；其中，第一时钟信号的时钟周期为预设时钟周期的两倍；
模式选择电路，用于在模式选择信号指示目标模式的情况下，根据模式选择信号对第一时钟信号和待处理片选信号进行选择处理，得到目标模式时钟信号和目标模式片选信号；
第一时钟处理电路，用于当第一片选信号包括一个脉冲且脉冲宽度为预设时钟周期时，根据目标模式时钟信号对待处理片选信号和目标模式片选信号进行采样及逻辑运算处理，得到第一片选时钟信号；
第二时钟处理电路，用于当第一片选信号包括一个脉冲且脉冲宽度为预设时钟周期的两倍、或者第一片选信号包括2个脉冲且脉冲宽度为预设时钟周期时，根据目标模式时钟信号对待处理片选信号和目标模式片选信号进行采样及逻辑运算处理，得到第二片选时钟信号；
指令译码电路，用于根据待处理片选信号和第一片选时钟信号对待处理指令信号进行译码和采样处理，得到目标指令信号；或者，根据待处理片选信号和第二片选时钟信号对待处理指令信号进行译码和采样处理，得到目标指令信号。
第二方面，本公开实施例提供了一种半导体存储器，包括如第一方面的信号采样电路。
在一些实施例中，半导体存储器为动态随机存取存储器DRAM芯片，且符合DDR5内存规格。
本公开实施例提供了一种信号采样电路以及半导体存储器，基于该信号采样电路，根据所处的周期模式确定目标模式时钟信号和目标模式片选信号，以便针对不同脉冲形状的第一片选信号，获得相应的第一片选时钟信号和第二片选时钟信号，从而在不同周期模式下正确区分2T CMD和NT ODT CMD这两种指令并进行准确译码，能够避免出现指令译码错误而执行错误操作的问题，同时节省电路面积，降低功耗。
附图说明
图1为单周期模式中不同指令信号的译码时序示意图；
图2为双周期模式中不同指令信号的译码时序示意图；
图3为本公开实施例提供的一种信号采样电路的组成结构示意图；
图4为本公开实施例提供的另一种信号采样电路的组成结构示意图；
图5为本公开实施例提供的又一种信号采样电路的组成结构示意图；
图6A为本公开实施例提供的一种第一译码采样电路的组成结构示意图；
图6B为本公开实施例提供的一种第二译码采样电路的组成结构示意图；
图7为本公开实施例提供的一种信号采样电路的信号时序示意图；
图8为本公开实施例提供的另一种信号采样电路的信号时序示意图；
图9为本公开实施例提供的又一种信号采样电路的信号时序示意图；
图10为本公开实施例提供的再一种信号采样电路的信号时序示意图；
图11为本公开实施例提供的一种半导体存储器的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关公开，而非对该公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关公开相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
以下为本公开实施例中涉及到的专业名词解释以及部分名词的对应关系：
动态随机存取存储器(Dynamic Random Access Memory，DRAM)
同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)
双倍速率(Double Data Rate，DDR)
第四代DDR(4th DDR，DDR4)
第五代DDR(5th DDR，DDR5)
命令地址输入(Command/Address，CMD/ADD或简称为CA)
时钟输入(Clock Input，CLK)
片选输入(Chip Select Input，CS)
缓冲器(Buffer/Repeater，RPT)
终结电阻(On-Die Termination，ODT)
指令译码器(Command Decoder，CMD DEC)
D型触发器(Data Flip-Flop或Delay Flip-Flop，DFF)
工艺电压温度(Process Voltage Temperature，PVT)
两倍时钟周期的指令(2Tck Command，2T CMD)
非目标芯片终结电阻的指令(Non-Target On-Die Termination Command，NT ODT CMD)
可以理解，以DDR5DRAM设计为例，CA输入既可以作为地址进行采样又可以作为指令进行采样译码。其中，这里的CA是DRAM各种命令地址信号的统称，可以包括行地址选通脉冲(Row Address Strobe，RAS)、列地址选通脉冲(Column Address Strobe，CAS)、写命令(Write，WE)、读命令(Read，RD)等命令信号，以及还可以包括有A13～A0的地址信号等。另外，在实际应用中，该命令地址信号包括几位地址信号，具体可以是根据DRAM的规格确定，本公开实施例不作任何限定。
本公开实施例是针对CA作为指令进行采样和处理的相关电路，因此，以下对CA作为指令进行采样和处理的过程进行简要说明。
DDR5DRAM中存在单周期模式(用1N MODE表示)和双周期模式(用2N MODE表示)，且DDR5DRAM中存在两种指令信号：2T CMD信号和NT ODT CMD信号；其中中，2T CMD信号也可称为2-cycle Command信号。下面结合图1和图2分别对不同周期模式中2T CMD信号和NT ODT CMD信号的译码时序进行说明。
参见图1和图2，CK_t、CK_c为一对输入的互补时钟信号，且CK_t、CK_c的时钟周期为预设时钟周期，相位差为180度；CA[13:0]就是CA信号输入，这里的CA[13:0]表示一组信号，CA[0]、CA[1]、…、CA[13]的合并统称；对于2T CMD信号，其对应的片选信号用CS0_n表示；对于NT ODT CMD信号，其对应的片选信号用CS1_n表示；CMD信号为CA信号作为指令译码后得到的信号。在这里，片选信号是表征目标芯片被选中的信号。
如图1所示，在单周期模式中，对于2T CMD信号，CS0_n信号为低电平有效的脉冲信号，CS0_n信号包括一个脉冲，且脉冲宽度为预设时钟周期；CA[13:0]信号包括两个连续预设时钟周期的有效信号。第1个时钟周期的CA[4:0]信号需要作为指令进行采样和译码，得到持续两个预设时钟周期的2T CMD信号，这里的CA[13:0]表示一组信号，是CA[0]、CA[1]、…、CA[13]的合并统称，CA[4:0]是指CA[13:0]中的CA[0]、CA[1]、CA[2]、CA[3]和CA[4]这5个信号。对于NT ODT CMD信号，CS1_n信号为低电平有效的脉冲信号，CS1_n信号包括一个脉冲，且脉冲宽度为预设时钟周期的两倍，CA[13:0]信号包括两个连续预设时钟周期的有效信号，第1个时钟周期的CA[4:0]信号需要作为指令信号进行采样和译码，得到持续两个预设时钟周期的NT ODT CMD信号。
如图2所示，在双周期模式中，对于2T CMD信号，CS0_n信号为低电平有效的脉冲信号，CS0_n信号包括一个脉冲，且脉冲宽度为预设时钟周期，CA[13:0]信号包括非连续的两个预设时钟周期的有效信号，第1个时钟周期的CA[4:0]信号还需要作为指令信号进行采样和译码，得到2T CMD信号。对于NT ODT CMD信号，CS1_n为低电平有效的脉冲信号，CS1_n包括两个脉冲，且脉冲宽度为预设时钟周期，CA[13:0]信号包括非连续的两个预设时钟周期的有效信号，第1个时钟周期的CA[4:0]需要作为指令信号进行采样和译码，得到NT ODT CMD信号。
也就是说，在单周期模式下，如果CS_n信号存在一个脉冲且脉冲宽度为预设时钟周期时，那么需要对CA输入进行译码得到2T CMD信号；如果CS_n信号存在一个脉冲且脉冲宽度为预设时钟周期的两倍，那么需要对CA输入进行译码得到NT ODT CMD信号。在双周期模式下，如果CS_n信号存在一个脉冲且脉冲宽度为预设时钟周期，那么需要对CA输入进行译码得到2T CMD信号；如果CS_n信号存在两个脉冲且脉冲宽度为预设时钟周期，那么需要对CA输入进行译码得到NT ODT CMD信号。
虽然2T CMD信号和NT ODT CMD信号对于读命令、写命令等指令译码是相同的，但是由于CS_n信号的状态不一样，而且这两个信号的操作功能不同，比如对于读命令而言，2T CMD信号需要进行读操作，但是NT ODT CMD信号只需要进行和读操作匹配的ODT操作即可，不需要进行读操作。因此，在实际应用中需要对2T CMD信号和NT ODT CMD信号的译码进行区分。但是，不同的周期模式造成不同指令信号对应的CS_n信号具有复杂的变化，所以CA的译码电路也变得更为复杂。
基于此，本公开实施例提供了一种信号采样电路，该信号采样电路包括信号输入电路、模式选择电路、第一时钟处理电路、第二时钟处理电路和指令译码电路；其中，信号输入电路，用于根据第一时钟信号、第一片选信号和第一命令地址信号，确定待处理指令信号和待处理片选信号；其中，第一时钟信号的时钟周期为预设时钟周期的两倍；模式选择电路，用于在模式选择信号指示目标模式的情况下，根据模式选择信号对第一时钟信号和待处理片选信号进行选择处理，得到目标模式时钟信号和目标模式片选信号；第一时钟处理电路，用于当第一片选信号包括一个脉冲且脉冲宽度为预设时钟周期时，根据目标模式时钟信号对待处理片选信号和目标模式片选信号进行采样及逻辑运算处理，得到第一片选时钟信号；第二时钟处理电路，用于当第一片选信号包括一个脉冲且脉冲宽度为预设时钟周期的两倍、或者第一片选信号包括2个脉冲且脉冲宽度为预设时钟周期时，根据目标模式时钟信号对待处理片选信号和目标模式片选信号进行采样及逻辑运算处理，得到第二片选时钟信号；指令译码电路，用于根据待处理片选信号和第一片选时钟信号对待处理指令信号进行译码和采样处理，得到目标指令信号；或者，根据待处理片选信号和第二片选时钟信号对待处理指令信号进行译码和采样处理，得到目标指令信号。这样，基于该信号采样电路，根据所处的周期模式确定目标模式时钟信号和目标模式片选信号，以便针对不同脉冲形状的第一片选信号，获得相应的第一片选时钟信号和第二片选时钟信号，从而在不同周期模式下正确区分2T CMD和NT ODT CMD，并进行正确译码，能够避免出现指令译码错误而执行错误操作的问题，同时达到节省电路面积，降 低功耗的目的。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图3，其示出了本公开实施例提供的一种信号采样电路的组成结构示意图。如图3所示，该信号采样电路30可以包括信号输入电路31、模式选择电路32、第一时钟处理电路33、第二时钟处理电路34和指令译码电路35；其中，
信号输入电路31，用于根据第一时钟信号、第一片选信号和第一命令地址信号，确定待处理指令信号和待处理片选信号；其中，第一时钟信号的时钟周期为预设时钟周期的两倍；
模式选择电路32，用于在模式选择信号指示目标模式的情况下，根据模式选择信号对第一时钟信号和待处理片选信号进行选择处理，得到目标模式时钟信号和目标模式片选信号；
第一时钟处理电路33，用于当第一片选信号包括一个脉冲且脉冲宽度为预设时钟周期时，根据目标模式时钟信号对待处理片选信号和目标模式片选信号进行采样及逻辑运算处理，得到第一片选时钟信号；
第二时钟处理电路34，用于当第一片选信号包括一个脉冲且脉冲宽度为预设时钟周期的两倍、或者第一片选信号包括2个脉冲且脉冲宽度为预设时钟周期时，根据目标模式时钟信号对待处理片选信号和目标模式片选信号进行采样及逻辑运算处理，得到第二片选时钟信号；
指令译码电路35，用于根据待处理片选信号和第一片选时钟信号对待处理指令信号进行译码和采样处理，得到目标指令信号；或者，根据待处理片选信号和第二片选时钟信号对待处理指令信号进行译码和采样处理，得到目标指令信号。
需要说明的是，在本公开实施例中，信号采样电路30应用于地址和指令信号的采样和译码过程，具体可以应用在多种电路场景中。本公开实施例后续以DRAM芯片中的CA信号进行地址和指令的采样及译码进行解释和说明，但这并不构成相关限定。
还需要说明的是，在本公开实施例中，该信号采样电路30应用于两周期命令的场景。具体来说，在该场景下，这里的第一命令地址信号包括两个预设时钟周期的有效信号，这两个预设时钟周期可能是连续，也可能是不连续的。如图1和图2所示，CA[13:0]信号可能在连续的两个预设时钟周期中均是有效(Valid)的，也可能在不连续的两个预设时钟周期中均是有效(Valid)，这里的预设时钟周期是指CK_t/CK_c信号的时钟周期。
在本公开实施例中，目标指令信号可以为DDR5DRAM芯片中的Command信号，由于该信号的有效脉冲持续两个时钟周期，这里可简称为2T CMD信号；其中，2T CMD信号可以包括读命令信号、写命令信号、刷新命令信号、预充电命令信号和激活命令信号等；或者，目标指令信号也可以为DDR5DRAM芯片中的Non-Target ODT Command信号，这里可简称为NT ODT CMD信号。
在指令的采样译码中，为了区分单周期模式和双周期模式，本公开实施例增加模式选择电路32，通过模式选择电路32确定与目标模式对应的目标模式时钟信号和目标模式片选信号；另外，为了区分2T CMD信号和NT ODT CMD信号的采样译码过程，本公开实施例增加第一时钟处理电路33和第二时钟处理电路34，通过第一时钟处理电路33和第二时钟处理电路34各自根据目标模式时钟信号和目标片选信号对待处理片选信号进行采样及逻辑运算处理，得到不同的第一片选时钟信号和第二片选时钟信号。在这里，第一片选时钟信号和第二片选时钟信号之中至多只有一个为有效信号，而且能够指示不同的指令(2T CMD信号或者NT ODT CMD信号)，后续根据第一片选时钟信号和第二片选时钟信号进行译码采样过程，得到目标指令信号。这样，通过信号采样电路30，能够在不同周期模式中正确区分2T CMD和NT ODT CMD这两种指令信号的译码，同时单周期模式和双周期模式共用一套译码电路，不仅节省了电路面积而且降低了功耗。
需要说明的是，对于本公开实施例所述的脉冲宽度，“脉冲宽度为预设时钟周期的两倍”具体是指该脉冲宽度和预设时钟周期的两倍之间的偏差在预设精度范围内，本公开中涉及到其他信号的脉冲宽度和预设时钟周期之间倍数关系的说明也可参照理解。
在一种实现方式中，对于目标模式为单周期模式的情况，第一时钟处理电路33，用于当第一片选信号包括一个脉冲且脉冲宽度为预设时钟周期时，根据单周期模式对应的目标模式时钟信号对待处理片选信号和单周期模式对应的目标模式片选信号进行采样及逻辑运算处理，得到第一片选时钟信号；第二时钟处理电路34，用于当第一片选信号包括一个脉冲且脉冲宽度为预设时钟周期的两倍时，根据单周期模式对应的目标模式时钟信号对待处理片选信号和单周期模式对应的目标模式片选信号进行采样及逻辑运算处理，得到第二片选时钟信号。
在另一种实现方式中，对于目标模式为双周期模式的情况，第一时钟处理电路33，用于当第一片选信号包括一个脉冲且脉冲宽度为预设时钟周期时，根据双周期模式对应的目标模式时钟信号对 待处理片选信号和双周期模式对应的目标模式片选信号进行采样及逻辑运算处理，得到第一片选时钟信号；第二时钟处理电路34，用于当第一片选信号包括2个脉冲且脉冲宽度为预设时钟周期时，根据双周期模式对应的目标模式时钟信号对待处理片选信号和双周期模式对应的目标模式片选信号进行采样及逻辑运算处理，得到第二片选时钟信号。
需要说明的是，在本公开实施例中，当第一片选信号包括一个脉冲且脉冲宽度为预设时钟周期时，这时候根据第一时钟处理电路33得到的第一片选时钟信号为有效信号，而根据第二时钟处理电路34得到的第二片选时钟信号为无效信号。另外，在这种情况下，目标指令信号为2T CMD信号。
还需要说明的是，在本公开实施例中，当第一片选信号包括一个脉冲且脉冲宽度为2个预设时钟周期，或者第一片选信号包括2个脉冲且脉冲宽度为预设时钟周期时，这时候根据第一时钟处理电路33得到的第一片选时钟信号为无效信号，而根据第二时钟处理电路34得到的第二片选时钟信号为有效信号。另外，在这种情况下，目标指令信号为NT ODT CMD信号。
也就是说，无论是单周期模式还是双周期模式，2T CMD信号均是根据第一片选时钟信号译码得到的，NT ODT CMD信号均是根据第二片选时钟信号译码得到的，从而能够区分不同指令。
在一些实施例中，在图3所示信号采样电路30的基础上，如图4所示，信号输入电路31可以包括第一接收电路311、第二接收电路312、第三接收电路313和输入采样电路314；其中，
第一接收电路311，用于接收初始命令地址信号，输出第一命令地址信号；
第二接收电路312，用于接收初始片选信号，输出第一片选信号；
第三接收电路313，用于接收初始时钟信号，并对初始时钟信号进行分频处理，输出第一时钟奇信号和第一时钟偶信号；
输入采样电路314，用于根据第一时钟信号对第一片选信号和第一命令地址信号进行采样处理，得到待处理片选信号和待处理指令信号。
其中，初始时钟信号的时钟周期为预设时钟周期，第一时钟信号是由第一时钟奇信号和第一时钟偶信号组成，第一时钟奇信号和第一时钟偶信号各自的时钟周期均是预设时钟周期的两倍，且第一时钟奇信号和第一时钟偶信号之间的相位差为180度。也就是说，初始时钟信号在分频处理后分别得到第一时钟奇信号和第二时钟偶信号。
需要说明的是，无论是第一接收电路311，还是第二接收电路312或第三接收电路313，均可以是接收器(用Recevier表示)，或者也可以是缓冲器(用Buffer表示)。
还需要说明的是，在图4中，这里的初始命令地址信号可以用CA[13:0]表示，第一命令地址信号用CA表示；初始片选信号可以用CS_n表示，第一片选信号用PCS表示；初始时钟信号可以用CK_t和CK_c表示，第一时钟偶信号用PCLK_E表示，第一时钟奇信号用PCLK_O表示。另外，图4中的VREFCA表示参考信号。
还需要说明的是，在本公开实施例中，无论是初始命令地址信号还是第一命令地址信号，其并非是一个信号，而是代表一组命令地址信号，即CA[0]～CA[13]；因此，对于第一接收电路311而言，这里可以包括有14个接收电路，用于接收CA[0]、CA[1]、…、CA[13]等14个信号的，图中仅示出一个接收电路作为示意。
对于输入采样电路314而言，本公开实施例需要利用第一时钟信号分别对第一命令地址信号和第一片选信号进行采样处理。因此，在一些实施例中，在图3所示信号采样电路30的基础上，如图4所示，输入采样电路314包括第一采样电路401、第二采样电路402、第三采样电路403和第四采样电路404；其中，
第一采样电路401，用于根据第一时钟偶信号对第一命令地址信号进行采样处理，得到待处理指令偶信号；
第二采样电路402，用于根据第一时钟奇信号对第一命令地址信号进行采样处理，得到待处理指令奇信号；
第三采样电路403，用于根据第一时钟偶信号对第一片选信号进行采样及反相处理，得到待处理片选偶信号；
第四采样电路404，用于根据第一时钟奇信号对第一片选信号进行采样及反相处理，得到待处理片选奇信号。
在这里，待处理指令信号可以是由待处理指令偶信号和待处理指令奇信号组成，待处理片选信号可以是由待处理片选偶信号和待处理片选奇信号组成。
在图4中，待处理指令偶信号用CA[4:0]_1T_E表示，待处理指令奇信号用CA[4:0]_1T_O表示，待处理片选偶信号用PCS_E，待处理片选奇信号用PCS_O表示。
需要说明的是，在一种具体的实施例中，在图4所示信号采样电路30的基础上，如图5所示，第一采样电路401可以包括第一触发器504，且第一触发器504的输入端与第一命令地址信号连接，第一触发器504的时钟端与第一时钟偶信号连接，第一触发器504的输出端用于输出待处理指令偶信号；
第二采样电路402可以包括第二触发器506，且第二触发器506的输入端与第一命令地址信号连接，第二触发器506的时钟端与第一时钟奇信号连接，第二触发器506的输出端用于输出待处理指令奇信号；
第三采样电路403包括第三触发器508和第一反相器509，且第三触发器508的输入端与第一片选信号连接，第三触发器508的时钟端与第一时钟偶信号连接，第三触发器508的输出端与第一反相器509的输入端连接，第一反相器509的输出端用于输出待处理片选偶信号；
第四采样电路404包括第四触发器510和第二反相器511，且第四触发器510的输入端与第一片选信号连接，第四触发器510的时钟端与第一时钟奇信号连接，第四触发器510的输出端与第二反相器511的输入端连接，第二反相器511的输出端用于输出待处理片选奇信号。
在图4中，待处理命令地址偶信号用CA[13:0]_1T_E表示，待处理命令地址奇信号用CA[13:0]_1T_O表示。这里，CA[13:0]_1T_E并非是一个信号，而是代表一组命令地址信号，即CA[0]_1T_E～CA[13]_1T_E，而CA[4:0]_1T_E表示的这一组信号中的CA[0]_1T_E～CA[4]_1T_E这五个信号；CA[13:0]_1T_O也并非是一个信号，而是代表一组命令地址信号，即CA[0]_1T_O～CA[13]_1T_O，而CA[4:0]_1T_O表示的这一组信号中的CA[0]_1T_O～CA[4]_1T_O这五个信号。
可以理解地，对于第一采样电路401或者第二采样电路402来说，由于CA并非是一个信号，而是一组信号的统称；那么这里可以包括多个第一采样电路401，分别用于接收这一组CA信号中的每一个CA信号；同理，也可以包括多个第二采样电路402，分别用于接收这一组CA信号中的每一个CA信号，而图中仅示出一个第一采样电路401和一个第二采样电路402作为示意。
特别地，如图5所示，第一采样电路401还可以包括第一缓冲器505，此时第一缓冲器505的输入端与第一触发器504的输出端连接，且第一缓冲器505的输出端用于输出CA[4:0]_1T_E信号，第二采样电路402还可以包括第二缓冲器507，此时第二缓冲器507的输入端与第二触发器506的输出端连接，且第二缓冲器507的输出端用于输出CA[4:0]_1T_O信号。这样，通过第一缓冲器505和第二缓冲器507，在信号传输过程中实现延时处理和驱动增强处理。
在本公开实施例中，无论是第一缓冲器还是第二缓冲器，缓冲器个数并不局限于一个，也可以是多个。在这里，具体数量可以根据实际需求进行设置，并不作具体限定。
还需要说明的是，第三采样电路403是利用第一时钟偶信号对第一片选信号进行采样及反相处理，可以得到PCS_O信号；第四采样电路404是利用第一时钟奇信号对第一片选信号进行采样及反相处理，可以得到PCS_E信号。
在这里，因为第一片选信号为低电平有效的脉冲信号，所以增加第一反相器509或者第二反相器511之后，PCS_O信号或者PCS_E信号就可以变成高电平有效的脉冲信号，以便后续的逻辑运算。另外，对于不同的电路应用场景，第三采样电路403和第四采样电路404也可以不需要设置第一反相器509和第二反相器511，那么后续的逻辑运算则需进行相应调整，从而也可以达到相同效果。
在一些实施例中，在图3所示信号采样电路30的基础上，如图4所示，模式选择电路32可以包括第一选择电路321、第二选择电路322、第三选择电路323和第四选择电路324；其中，
第一选择电路321，用于根据模式选择信号对第一时钟奇信号和第一时钟偶信号进行选择处理，得到目标模式时钟信号中的第一模式时钟信号；
第二选择电路322，用于根据模式选择信号对第一时钟奇信号和第一时钟偶信号进行选择处理，得到目标模式时钟信号中的第二模式时钟信号；
第三选择电路323，用于根据模式选择信号对待处理片选奇信号和待处理片选偶信号进行选择处理，得到目标模式片选信号中的第一模式片选信号；
第四选择电路324，用于根据模式选择信号对待处理片选奇信号和待处理片选偶信号进行选择处理，得到目标模式片选信号中的第二模式片选信号。
在这里，第一模式时钟信号和第二模式时钟信号组成目标模式时钟信号，第一模式片选信号和第二模式片选信号组成目标模式片选信号。另外，在图4和图5中，模式选择信号可以用EN_1N表示，第一模式时钟信号可以用PCLK_2NE_1NO表示，第二模式时钟信号PCLK_2NO_1NE，第一模式片选信号可以用PCS_2NE_1NO表示，第二模式片选信号可以用PCS_2NO_1NE表示。
这样，针对不同的周期模式，目标模式时钟信号和目标模式片选信号存在相应调整，以便后续确定译码指令为2T CMD信号或者NT ODT CMD信号。
在一种可能的实现方式中，对于模式选择信号指示单周期模式的情况，模式选择电路32，具体用于选择第一时钟奇信号生成第一模式时钟信号，选择第一时钟偶信号生成第二模式时钟信号，选择待处理片选奇信号生成第一模式片选信号，选择待处理片选偶信号生成第二模式片选信号。
在另一种可能的实现方式中，对于模式选择信号指示双周期模式的情况，模式选择电路32，具体用于选择第一时钟偶信号生成第一模式时钟信号，选择第一时钟奇信号生成第二模式时钟信号，选择待处理片选偶信号生成第一模式片选信号，选择待处理片选奇信号生成第二模式片选信号。
这样，通过控制第一模式时钟信号/第二模式时钟信号、第一模式片选信号/第二模式片选信号的来源，可以区分单周期模式和双周期模式，可以在共用后续处理及译码电路的基础上，在不同周期模式下区分出译码对象为2T CMD信号或者NT ODT CMD信号。
在一些实施例中，若目标模式为单周期模式，则确定模式选择信号处于第一电平状态；或者，若目标模式为双周期模式，则确定模式选择信号处于第二电平状态。
在这里，第一电平状态和第二电平状态不同。示例性地，第一电平状态为高电平，第二电平状态为低电平；或者，第一电平状态为低电平，第二电平状态为高电平，其具体取值可以根据实际应用场景进行确定，本公开实施例不作任何限定。
在一种具体的实施例中，在图4所示信号采样电路30的基础上，如图5所示，第一选择电路321包括第一多路选择器513，第二选择电路322包括第二多路选择器515，第三选择电路323包括第三多路选择器516，第四选择电路324包括第四多路选择器517；其中，
第一多路选择器513的第一输入端与第一时钟偶信号连接，第一多路选择器513的第二输入端与第一时钟奇信号连接，第一多路选择器513的输出端用于输出第一模式时钟信号；
第二多路选择器515的第一输入端与第一时钟奇信号连接，第二多路选择器515的第二输入端与第一时钟偶信号连接，第二多路选择器515的输出端用于输出第二模式时钟信号；
第三多路选择器516的第一输入端与待处理片选偶信号连接，第三多路选择器516的第二输入端与待处理片选奇信号连接，第三多路选择器516的输出端用于输出第一模式片选信号；
第四多路选择器517的第一输入端与待处理片选奇信号连接，第四多路选择器517的第二输入端与待处理片选偶信号连接，第四多路选择器517的输出端用于输出第二模式片选信号；
第一多路选择器513、第二多路选择器515、第三多路选择器516和第四多路选择器517各自的控制端均与模式选择信号连接。
另外，如图5所示，第一选择电路321还可以包括第三缓冲器512，第三缓冲器512的接收端用于接收第一时钟偶信号，第三缓冲器512的输出端与第一多路选择器513的第一输入端和第二多路选择器515的第二输入端连接。第二选择电路322还可以包括第四缓冲器514，第四缓冲器513的接收端用于接收第一时钟奇信号，第三缓冲器513的输出端与第一多路选择器513的第二输入端和第二多路选择器515的第一输入端连接。这样，通过第三缓冲器512和第四缓冲器514，在信号传输过程中实现延时处理和驱动增强处理。在本公开实施例中，无论是第三缓冲器还是第四缓冲器，缓冲器个数并不局限于一个，也可以是多个。在这里，具体数量可以根据实际需求进行设置，并不作具体限定。
在一些实施例中，在图3所示信号采样电路30的基础上，如图4所示，第一时钟处理电路33可以包括第一逻辑电路331和第二逻辑电路332，第二时钟处理电路34可以包括第三逻辑电路341和第四逻辑电路342；其中，
第一逻辑电路331，用于接收第一模式时钟信号和第一模式片选信号，并利用第一模式时钟信号对待处理片选偶信号和第一模式片选信号进行采样及逻辑运算处理，得到第一片选时钟奇信号；
第二逻辑电路332，用于接收第二模式时钟信号和第二模式片选信号，并利用第二模式时钟信号对待处理片选奇信号和第二模式片选信号进行采样及逻辑运算处理，得到第一片选时钟偶信号；
第三逻辑电路341，用于接收第一模式时钟信号和第一模式片选信号，并利用第一模式时钟信号对待处理片选偶信号和第一模式片选信号进行采样及逻辑运算处理，得到第二片选时钟奇信号；
第四逻辑电路342，用于接收第二模式时钟信号和第二模式片选信号处理，并利用第二模式时钟信号对待处理片选奇信号和第二模式片选信号进行采样及逻辑运算，得到第二片选时钟偶信号。
在这里，第一片选时钟信号是由第一片选时钟偶信号和第一片选时钟奇信号组成，第二片选时钟信号是由第二片选时钟奇信号和第二片选时钟偶信号组成。在图4和图5中，这里的第一片选时钟偶信号可以用2T_CLK_E表示，第一片选时钟奇信号可以用2T_CLK_O表示，第二片选时钟偶信 号可以用NT_CLK_E表示，第二片选时钟奇信号可以用NT_CLK_O表示。
在一种具体的实施例中，在图3所示信号采样电路30的基础上，如图4所示，第一逻辑电路331包括第五采样电路405、第一或非门520、第一非门521、第六采样电路406、第一或门523和第一与门524；其中，
第五采样电路405，用于利用第一模式时钟信号对待处理片选偶信号进行采样及反相处理，得到第一中间采样奇信号；
第一或非门520，用于对第一中间采样奇信号和第一模式片选信号进行或非运算，得到第二中间采样奇信号；
第一非门521，用于对第一模式时钟信号进行非运算，得到第一反相时钟奇信号；
第六采样电路406，用于利用第一反相时钟奇信号对第二中间采样奇信号进行采样处理，得到第三中间采样奇信号；
第一或门523，用于对第二中间采样奇信号和第三中间采样奇信号进行或运算，得到第四中间采样奇信号；
第一与门524，用于对第四中间采样奇信号和第一模式时钟信号进行与运算，得到第一片选时钟奇信号。
需要说明的是，如图5所示，在第一逻辑电路331中，第五采样电路405可以是由第五触发器518和第三反相器519组成，第六采样电路406可以是由第六触发器522组成；其中，第五触发器518和第六触发器522均可以为D型触发器。另外，还需要注意的是，对于第五采样电路405而言，也可以不设置第三反相器519，那么后续的逻辑运算则需进行相应调整，例如将第一或非门520调整为或门，从而也能够达到相同效果。
第一逻辑电路331的各器件连接关系可以参照图4和图5来进行理解。在图4和图5中，待处理片选偶信号用PCS_E表示；经过第五采样电路405输出的第一中间采样奇信号可以用PCSB_O表示，经过第一或非门520输出的第二中间采样奇信号可以用PCS_OEN1表示，经过第六采样电路406输出的第三中间采样奇信号可以用PCS_OEN2表示，经过第一或门523输出的第四中间采样奇信号可以用PCS_OEN表示，经过第一与门524输出的第一片选时钟奇信号可以用2T_CLK_O表示。
需要说明的是，在第一逻辑电路331中，第一或非门520用于对第一片选信号进行筛选，根据第一类脉冲形状的第一片选信号输出存在脉冲的PCS_OEN1信号，并将其他脉冲形状的第一片选信号屏蔽为始终低电平的PCS_OEN1信号，以便于后续得到存在脉冲的2T_CLK_O信号。第五采样电路405用于实现一级上升沿采样，而第一非门521和第六采样电路406用于实现一级下降沿采样。第一类脉冲形状是指第一片选信号在偶数时钟周期变化为低电平且在相邻奇数时钟周期变化为高电平，此时的周期模式可以是单周期模式或者双周期模式。在这里，偶数时钟周期是指第一时钟偶信号PCLK_E的上升沿所在的时钟周期，奇数时钟周期是指第一时钟奇信号PCLK_O的上升沿所在的时钟周期。
这样，针对第一类脉冲形状的第一片选信号，通过对PCS_E信号进行一级上升沿采样、或非运算和一级下降沿采样，得到PCS_OEN1信号和PCS_OEN2信号，且PCS_OEN1信号和PCS_OEN2信号各自均为高电平有效的脉冲信号，但是PCS_OEN2信号的上升沿相比于PCS_OEN1信号的上升沿延迟一个预设时钟周期。在此基础上，通过第一或门523，PCS_OEN1信号和PCS_OEN2信号进行或运算能够拓宽脉冲宽度，所得到的PCS_OEN信号的脉冲宽度是预设时钟周期的3倍；通过第一与门524，PCS_OEN信号和PCLK_2NE_1NO(单周期模式中为PCLK_O信号，双周期模式中为PCLK_E信号)信号进行与运算，使所得到的2T_CLK_O信号具有两个脉冲，且脉冲宽度是预设时钟周期。这样，借助于具有两个脉冲的2T_CLK_O信号，利用第一个脉冲的上升沿产生2T CMD信号的上升沿，利用第二个脉冲的上升沿产生2T CMD信号的下降沿，能够保证2T CMD信号的脉冲宽度在预设精度范围内为2个预设时钟周期，避免2T CMD信号的脉冲宽度受到制备工艺或者环境的影响，防止信号失效。
在一种具体的实施例中，如图4所示，第二逻辑电路332可以包括第七采样电路407、第二或非门527、第二非门528、第八采样电路408、第二或门530和第二与门531；其中，
第七采样电路407，用于利用第二模式时钟信号对待处理片选奇信号进行采样及反相处理，得到第一中间采样偶信号；
第二或非门527，用于对第一中间采样偶信号和第二模式片选信号进行或非运算，得到第二中间采样偶信号；
第二非门528，用于对第二模式时钟信号进行非运算，得到第一反相时钟偶信号；
第八采样电路408，用于利用第一反相时钟偶信号对第二中间采样偶信号进行采样处理，得到第三中间采样偶信号；
第二或门530，用于对第二中间采样偶信号和第三中间采样偶信号进行或运算，得到第四中间采样偶信号；
第二与门531，用于对第四中间采样偶信号和第二模式时钟信号进行与运算，得到第一片选时钟偶信号。
需要说明的是，如图5所示，在第二逻辑电路332中，第七采样电路407可以是由第七触发器525和第四反相器526组成，第八采样电路408可以是由第八触发器529组成；其中，第七触发器525和第八触发器529均可以为D型触发器。另外，还需要注意的是，对于第七采样电路407而言，也可以不设置第四反相器526，那么后续的逻辑运算则需进行相应调整，例如将第二或非门527调整为或门，从而也能够达到相同效果。
第二逻辑电路332的各器件连接关系可以参照图4和图5来进行理解。在图4和图5中，待处理片选奇信号用PCS_O表示；经过第七采样电路407输出的第一中间采样偶信号可以用PCSB_E表示，经过第二或非门527输出的第二中间采样偶信号可以用PCS_EEN1表示，经过第八采样电路408输出的第三中间采样偶信号可以用PCS_EEN2表示，经过第二或门530输出的第四中间采样偶信号可以用PCS_EEN表示，经过第二与门531输出的第一片选时钟偶信号可以用2T_CLK_E表示。
需要说明的是，在第二逻辑电路332中，第二或非门527用于根据对第一片选信号进行筛选，根据第二类脉冲形状的第一片选信号输出存在脉冲的PCS_EEN1信号，并将其他脉冲形状的第一片选信号屏蔽为始终低电平的PCS_EEN1信号，以便于后续得到存在脉冲的2T_CLK_E信号。第七采样电路407用于实现一级上升沿采样，而第二非门528和第八采样电路408用于实现一级下降沿采样。第二类脉冲形状是指第一片选信号在奇数时钟周期变化为低电平且在相邻偶数时钟周期变化为高电平，此时的周期模式可以是单周期模式或者双周期模式。
这样，针对第二类脉冲形状的第一片选信号，通过对PCS_O信号进行一级上升沿采样、或非运算和一级下降沿采样，得到PCS_EEN 1信号和PCS_EEN 2信号，此时PCS_EEN 1信号和PCS_EEN2信号各自均为高电平有效的脉冲信号，且PCS_EEN 2信号的上升沿相比于PCS_EEN 1信号的上升沿延迟一个预设时钟周期。在此基础上，通过第二或门530，PCS_EEN 1信号和PCS_EEN 2信号进行或运算能够拓宽脉冲宽度，所得到的PCS_EEN信号的脉冲宽度是预设时钟周期的3倍；通过第二与门531，PCS_EEN信号和PCLK_2NO_1NE信号(单周期模式中为PCLK_E，双周期模式中为PCLK_O)进行与运算，所得到的2T_CLK_E信号具有两个脉冲，且脉冲宽度是预设时钟周期。这样，借助于具有两个脉冲的2T_CLK_E信号，利用第一个脉冲的上升沿产生2T CMD信号的上升沿，利用第二个脉冲的上升沿产生2T CMD信号的下降沿，能够保证2T CMD信号的脉冲宽度时钟在预设精度范围内为2个预设时钟周期，能够避免2T CMD信号的脉冲宽度受到制备工艺或者环境的影响，防止信号失效。
也就是说，在单周期模式或者双周期模式中，针对2T CMD信号，根据第一片选信号的脉冲形状以及开始发生电平状态变化时对应的时钟周期奇偶性不同，2T_CLK_O信号和2T_CLK_E信号至多仅存在一个有效信号，该有效信号存在两个脉冲，且每个脉冲的脉冲宽度为1个预设时钟周期。这样，后续利用2T_CLK_O信号和2T_CLK_E信号之中的有效信号作为译码过程的时钟，能够区分译码得到目标指令信号为2T CMD信号，同时在预设精度范围内保证目标指令信号的脉冲宽度为预设时钟周期的两倍。
在另一种具体的实施例中，如图4所示，第三逻辑电路341可以包括第九采样电路409、第三非门534、第三或非门535、第四非门536、第十采样电路410、第三或门538和第三与门539；其中，
第九采样电路409，用于利用第一模式时钟信号对待处理片选偶信号进行采样及反相处理，得到第五中间采样奇信；
第三非门534，用于对第一模式片选信号进行非运算，得到第一模式片选反相信号；
第三或非门535，用于对第五中间采样奇信号和第一模式片选反相信号进行或非运算，得到第六中间采样奇信号；
第四非门536，用于对第一模式时钟信号进行非运算，得到第一模式时钟反相信号；
第十采样电路410，用于利用第一模式时钟反相信号对第六中间采样奇信号进行采样处理，得到第七中间采样奇信号；
第三或门538，用于对第六中间采样奇信号和第七中间采样奇信号进行或运算，得到第八中间 采样奇信号；
第三与门539，用于对第八中间采样奇信号和第一模式时钟信号进行与运算，得到第二片选时钟奇信号。
需要说明的是，如图5所示，在第三逻辑电路341中，第九采样电路409可以是由第九触发器421和第五反相器532组成，第十采样电路410可以是由第十触发器537组成；其中，第九触发器421和第十触发器537均可以为D型触发器。另外，还需要注意的是，对于第九采样电路409而言，也可以不设置第五反相器532，那么后续的逻辑运算则需进行相应调整，例如去掉第三非门534，并将第三或非门535调整为或门，从而也能够达到相同效果。
第三逻辑电路341的各器件连接关系可以参照图4和图5来进行理解。在图4和图5中，待处理片选偶信号用PCS_E表示；经过第九采样电路409输出的第五中间采样奇信号可以用PCSB_O表示，经过第三或非门535输出的第六中间采样奇信号可以用NT_PCS_OEN1表示，经过第十采样电路410输出的第七中间采样奇信号可以用NT_PCS_OEN2表示，经过第三或门538输出的第八中间采样奇信号可以用NT_PCS_OEN表示，经过第三与门539输出的第二片选时钟奇信号可以用NT_CLK_O表示。
需要说明的是，在第三逻辑电路341中，第三非门534和第三或非门535，用于根据对第一片选信号进行筛选，根据第三类脉冲形状的第一片选信号输出存在脉冲的NT_PCS_OEN1信号，并将其他脉冲形状的第一片选信号屏蔽为始终低电平的NT_PCS_OEN1信号，以便于后续得到存在脉冲的NT_CLK_O信号。第九采样电路409用于实现一级上升沿采样，而第四非门536和第十采样电路410用于实现一级下降沿采样。第三类脉冲形状是指单周期模式中第一片选信号在偶数时钟周期变化为低电平且在相邻奇数时钟周期仍为低电平，或者双周期模式中第一片选信号在相邻两个偶数时钟周期变化为低电平且在中间奇数时钟周期为高电平。
这样，针对第三类脉冲形状的第一片选信号，通过采用一级上升沿采样、非运算、或非运算和一级下降沿采样对PCS_E信号进行处理，得到NT_PCS_OEN1信号和NT_PCS_OEN2信号，此时NT_PCS_OEN1信号和NT_PCS_OEN2信号各自均为高电平有效的脉冲信号，且NT_PCS_OEN2信号的上升沿相比于NT_PCS_OEN1信号的上升沿延迟一个预设时钟周期。在此基础上，NT_PCS_OEN1信号和NT_PCS_OEN2信号进行或运算能够拓宽脉冲宽度，所得到的NT_PCS_OEN信号的脉冲宽度是预设时钟周期的3倍，然后NT_PCS_OEN信号和PCLK_2NE_1NO信号(单周期模式中为PCLK_O信号，双周期模式中为PCLK_E信号)进行与运算，所得到的NT_CLK_O信号具有两个脉冲，且脉冲宽度是预设时钟周期。这样，借助于具有两个脉冲的NT_CLK_O信号，利用第一个脉冲的上升沿产生NT ODT CMD信号的上升沿，利用第二个脉冲的上升沿产生NT ODT CMD信号的下降沿，能够保证NT ODT CMD信号的脉冲宽度时钟在预设精度范围内为2个预设时钟周期，能够避免NT ODT CMD信号的脉冲宽度受到制备工艺或者环境的影响，防止信号失效。
在另一种具体的实施例中，如图4所示，第四逻辑电路342可以包括第十一采样电路411、第五非门542、第四或非门543、第六非门544、第十二采样电路412、第四或门546和第四与门547；其中，
第十一采样电路411，用于利用第二模式时钟信号对待处理片选奇信号进行采样及反相处理，得到第五中间采样偶信号；
第五非门542，用于对第二模式片选信号进行非运算，得到第二模式片选反相信号；
第四或非门543，用于对第五中间采样偶信号和第二模式片选反相信号进行或非运算，得到第六中间采样偶信号；
第六非门544，用于对第二模式时钟信号进行非运算，得到第二模式时钟反相信号；
第十二采样电路412，用于利用第二模式时钟反相信号对第六中间采样偶信号进行采样处理，得到第七中间采样偶信号；
第四或门546，用于对第六中间采样偶信号和第七中间采样偶信号进行或运算，得到第八中间采样偶信号；
第四与门547，用于对第八中间采样偶信号和第二模式时钟信号进行与运算，得到第二片选时钟偶信号。
需要说明的是，如图5所示，在第四逻辑电路342中，第十一采样电路411可以是由第十一触发器540和第六反相器541组成，第十二采样电路412可以是由第十二触发器545组成；其中，第十一触发器540和第十二触发器545均可以为D型触发器。另外，还需要注意的是，对于第十一采样电路411而言，也可以不设置第六反相器541，那么后续的逻辑运算则需进行相应调整，例如去 掉第五非门542，并将第四或非门543调整为或门，从而也能够达到相同效果。
第四逻辑电路342的各器件连接关系可以参照图4和图5来进行理解。在图4和图5中，待处理片选奇信号用PCS_O表示；经过第十一采样电路411输出的第五中间采样偶信号可以用PCSB_E表示，经过第四或非门543输出的第六中间采样偶信号可以用NT_PCS_EEN1表示，经过第十二采样电路412输出的第七中间采样偶信号可以用NT_PCS_EEN2表示，经过第四或门546输出的第八中间采样偶信号可以用NT_PCS_EEN表示，经过第四与门547输出的第二片选时钟偶信号可以用NT_CLK_E表示。
需要说明的是，在第四逻辑电路342中，第五非门542和第四或非门543用于根据对第一片选信号进行筛选，根据第四类脉冲形状的第一片选信号输出存在脉冲的NT_PCS_EEN1信号，并将其他脉冲形状的第一片选信号屏蔽为始终低电平的NT_PCS_EEN1信号，以便于后续得到存在脉冲的NT_CLK_E信号。第十一采样电路411用于实现一级上升沿采样电路，第六非门544和第十二采样电路412用于实现一级下降沿采样电路。第四类脉冲形状是指单周期模式中第一片选信号在奇数时钟周期变化为低电平且在相邻偶数时钟周期仍为低电平，或者双周期模式中第一片选信号在相邻两个奇数时钟周期变化为低电平且在中间偶数时钟周期为高电平。
这样，针对第四类脉冲形状的第一片选信号，通过采用一级上升沿采样电路、非运算电路、或非运算电路和一级下降沿采样电路对PCS_O信号进行处理，得到NT_PCS_EEN 1信号和NT_PCS_EEN 2信号，此时NT_PCS_EEN 1信号和NT_PCS_EEN 2信号各自均为高电平有效的脉冲信号，且NT_PCS_EEN 2信号的上升沿相比于NT_PCS_EEN 1信号的上升沿延迟一个预设时钟周期。在此基础上，通过第四或门546，NT_PCS_EEN 1信号和NT_PCS_EEN 2信号进行或运算能够拓宽脉冲宽度，所得到的NT_PCS_EEN信号的脉冲宽度是预设时钟周期的3倍；通过第四与门547，NT_PCS_EEN信号和PCLK_2NO_1NE(单周期模式中为PCLK_E，双周期模式中为PCLK_O)信号进行与运算，所得到的NT_CLK_O信号具有两个脉冲，且脉冲宽度是预设时钟周期。这样，借助于具有两个脉冲的NT_CLK_E信号，利用第一个脉冲的上升沿产生NT ODT CMD信号的上升沿，利用第二个脉冲的上升沿产生NT ODT CMD信号的下降沿，能够保证NT ODT CMD信号的脉冲宽度在预设精度范围内为2个预设时钟周期，能够避免NT ODT CMD信号的脉冲宽度受到制备工艺或者环境的影响，防止信号失效。
也就是说，在单周期模式或者双周期模式中，针对NT ODT CMD信号，根据第一片选信号的脉冲形状以及开始发生电平状态变化时对应的时钟周期奇偶性不同，NT_CLK_O信号和NT_CLK_E信号之中至多仅存在一个有效信号，该有效信号存在两个脉冲，且每个脉冲的脉冲宽度为1个预设时钟周期。这样，后续利用NT_CLK_O信号和NT_CLK_E信号之中的有效信号作为译码过程的时钟，能够区分译码得到目标指令信号为NT ODT CMD信号，同时保证目标指令信号的脉冲宽度为2个预设时钟周期。这样，通过上述电路，能够区分不同周期模式下译码得到的目标指令信号为NT ODT CMD信号或者为2T CMD信号，同时保证目标指令信号的脉冲宽度在预设精度范围内为2个预设时钟周期。
在一些实施例中，在图3所示信号采样电路30的基础上，如图4所示，指令译码电路35可以包括第一指令译码电路351和第二指令译码电路352；其中，
第一指令译码电路351，用于接收第一片选时钟信号，根据第一片选时钟信号和待处理片选信号对待处理指令信号进行译码和采样处理，得到第一目标指令信号；
第二指令译码电路352，用于接收第二片选时钟信号，根据第二片选时钟信号和待处理片选信号对待处理指令信号进行译码和采样处理，得到第二目标指令信号。
可以理解地，在一些实施例中，初始片选信号是表征目标芯片被选中的信号，且初始片选信号为低电平有效的脉冲信号；其中，
若初始片选信号包括一个脉冲且脉冲宽度为预设时钟周期，则确定第一片选时钟信号为有效信号，将经由第一指令译码电路输出的第一目标指令信号确定为目标指令信号；
若初始片选信号包括一个脉冲且脉冲宽度为预设时钟周期的两倍、或者初始片选信号包括2个脉冲且脉冲宽度为预设时钟周期，则确定第二片选时钟信号为有效信号，将经由第二指令译码电路输出的第二目标指令信号确定为目标指令信号。
需要说明的是，第一目标指令信号可以用2T CMD信号表示，第二目标指令信号可以用NT ODT CMD信号表示。这样，无论在单周期模式还是双周期模式中，2T CMD信号均是通过第一指令译码电路进行输出的，NT ODT CMD信号均是通过第二指令译码电路进行输出的，能够避免混淆，区别不同种类的指令信号。
在一种具体的实施例中，对于第一指令译码电路351而言，在图3所示信号采样电路30的基础上，如图4或者图5所示，第一指令译码电路351可以包括第一译码采样电路421和第五或门548；其中，
第一译码采样电路421，用于根据第一片选时钟奇信号和待处理片选偶信号对待处理指令偶信号进行译码和采样处理，得到第一指令偶信号；以及根据第一片选时钟偶信号和待处理片选奇信号对待处理指令奇信号进行译码和采样处理，得到第一指令奇信号；
第五或门548，用于对第一指令偶信号和第一指令奇信号进行或运算，得到第一目标指令信号；
第二指令译码电路352包括第二译码采样电路422和第六或门549；其中，
第二译码采样电路422，用于根据第二片选时钟奇信号和待处理片选偶信号对待处理指令偶信号进行译码和采样处理，得到第二指令偶信号；以及根据第二片选时钟偶信号和待处理片选奇信号对待处理指令奇信号进行译码和采样处理，得到第二指令奇信号；
第六或门549，用于对第二指令偶信号和第二指令奇信号进行或运算，得到第二目标指令信号。
需要说明的是，如图4或者图5所示，在本公开实施例中，这里的第一译码采样电路421又可称为第一指令译码触发器，用CMD DEC DFF1表示。第一译码采样电路421的输出包括第一指令偶信号和第一指令奇信号；其中，第一指令偶信号用2T_CMD_E表示，第一指令奇信号用2T_CMD_O表示；然后再对2T_CMD_E信号和2T_CMD_O信号进行或运算之后得到第一目标指令信号用2T CMD表示。
第二译码采样电路422也可称为第二指令译码触发器，用CMD DEC DFF2表示。第二译码采样电路的输出包括第二指令偶信号和第二指令奇信号；其中，第二指令偶信号用NT_CMD_E表示，第二指令奇信号用NT_CMD_O表示；然后再对NT_CMD_E信号和NT_CMD_O信号进行或运算之后得到第二目标指令信号用NT ODT CMD表示。
进一步地，在图4和图5所示信号采样电路30的基础上，如图6A所示，第一译码采样电路421包括第一译码电路550、第十三采样电路551、第二译码电路552和第十四采样电路553；其中，
第一译码电路550，用于对待处理片选偶信号和待处理指令偶信号进行译码处理，得到第一译码偶信号；
第十三采样电路551，用于利用第一片选时钟奇信号对第一译码偶信号进行采样处理，得到第一指令偶信号；
第二译码电路552，用于对待处理片选奇信号和待处理指令奇信号进行译码处理，得到第一译码奇信号；
第十四采样电路553，用于利用第一片选时钟偶信号对第一译码奇信号进行采样处理，得到第一指令奇信号。
需要说明的是，在图6A中，待处理指令偶信号可以包括CA[0]_1T_E、CA[1]_1T_E、CA[2]_1T_E、CA[3]_1T_E、CA[4]_1T_E等5个信号，而且第一译码电路550可以是由三输入与非门、三输入与非门和二输入或非门组成。其中，PCS_E、CA[0]_1T_E和CA[1]_1T_E输入到第一个三输入与非门，CA[2]_1T_E、CA[3]_1T_E和CA[4]_1T_E输入到第二个三输入与非门，然后第一个三输入与非门的输出端和二输入或非门的一个输入端连接，第二个三输入与非门的输出端和二输入或非门的另一个输入端连接，而二输入或非门的输出端用于输出第一译码偶信号，从而实现对待处理片选偶信号和待处理指令偶信号的译码；在得到第一译码偶信号后，利用第十三采样电路551进行采样输出。具体地，第十三采样电路551可以为一个D型触发器，该D型触发器的时钟端与2T_CLK_O信号连接，D型触发器的输入端与二输入或非门的输出端连接，D型触发器的输出端用于输出2T_CMD_E信号。
还需要说明的是，在图6A中，待处理指令奇信号可以包括CA[0]_1T_O、CA[1]_1T_O、CA[2]_1T_O、CA[3]_1T_O、CA[4]_1T_O等5个信号，而且第二译码电路552可以是由三输入与非门、三输入与非门和二输入或非门组成。其中，PCS_O、CA[0]_1T_O和CA[1]_1T_O输入到第一个三输入与非门，CA[2]_1T_O、CA[3]_1T_O和CA[4]_1T_O输入到第二个三输入与非门，然后第一个三输入与非门的输出端和二输入或非门的一个输入端连接，第二个三输入与非门的输出端和二输入或非门的另一个输入端连接，而二输入或非门的输出端用于输出第一译码奇信号，从而实现对待处理片选偶信号和待处理指令偶信号的译码；在得到第一译码奇信号后，利用第十四采样电路553进行采样输出。具体地，第十四采样电路553也可以为一个D型触发器，该D型触发器的时钟端与2T_CLK_E信号连接，D型触发器的输入端与二输入或非门的输出端连接，D型触发器的输出端用于输出2T_CMD_O信号。
还需要说明的是，在本公开实施例中，如图6B所示，第二译码采样电路422包括第三译码电路554、第十五采样电路555、第四译码电路556和第十六采样电路557；其中，
第三译码电路554，用于对待处理片选偶信号和待处理指令偶信号进行译码处理，得到第二译码偶信号；
第十五采样电路555，用于利用第二片选时钟奇信号对第二译码偶信号进行采样处理，得到第二指令偶信号；
第四译码电路556，用于对待处理片选奇信号和待处理指令奇信号进行译码处理，得到第二译码奇信号；
第十六采样电路557，用于利用第二片选时钟偶信号对第二译码奇信号进行采样处理，得到第二指令奇信号。
需要说明的是，在图6B中，第二译码采样电路422与第一译码采样电路421的电路结构相同，部分信号端接收的信号不同，可对比第一译码采样电路421进行参照理解。
另外，需要注意的是，无论是第一译码电路550、第二译码电路552，还是第三译码电路554、第四译码电路556，这些译码电路的设计具体是根据指令译码规则实现的。对于不同的产品，不同的应用场景，不同的指令，译码规则可能不同，那么译码电路的逻辑也可进行相应调整，本公开实施例不作具体限定。
这样，通过增加模式选择电路32、第一时钟处理电路33和第二时钟处理电路34，根据采用的周期模式以及第一片选信号的脉冲形状，可以输出不同的第一片选时钟信号(用2T_CLK_E/2T_CLK_O表示)和第二片选时钟信号(用NT_CLK_E/NT_CLK_O表示)；如此，当初始片选信号包括一个脉冲且脉冲宽度为预设时钟周期(对应单周期模式中的2T CMD信号或者双周期模式中的2T CMD信号)时，利用2T_CLK_E/2T_CLK_O信号，通过第一指令译码电路351得到的第一目标指令信号为有效信号(即高电平有效的脉冲信号)，通过第二指令译码电路352得到的第二目标指令信号为无效信号(即低电平信号)；反之，当初始片选信号包括一个脉冲且脉冲宽度为预设时钟周期的两倍(对应单周期模式中的NT ODT CMD信号)或者初始片选信号包括两个脉冲且脉冲宽度为预设时钟周期(对应双周期模式中的NT ODT CMD信号)时，利用NT_CLK_E/NT_CLK_O信号，通过第一指令译码电路351得到的第一目标指令信号为无效信号(即低电平信号)，通过第二指令译码电路352得到的第二目标指令信号为有效信号(即高电平有效的脉冲信号)；从而能够正确区分2T CMD和NT ODT CMD这两种信号并进行准确译码。
换句话说，根据周期模式和初始片选信号的脉冲形状，信号采样电路的信号处理过程可以分为三种情况。
情况一：当目标模式为单周期模式或者双周期模式，且初始片选信号包括一个脉冲且脉冲宽度为预设时钟周期时，确定第一片选时钟信号包括两个脉冲，且每一个脉冲的脉冲宽度为预设时钟周期，第一片选时钟信号中第一个脉冲的上升沿用于产生第一目标指令信号的上升沿，第一片选时钟信号中第二个脉冲的上升沿用于产生第一目标指令信号的下降沿；以及，确定第二片选时钟信号维持电平状态不变，第二目标指令信号维持电平状态不变。
情况二：当目标模式为单周期模式，且初始片选信号包括一个脉冲且脉冲宽度为预设时钟周期的两倍时，确定第一片选时钟信号维持电平状态不变，第一目标指令信号维持电平状态不变；以及，确定第二片选时钟信号包括两个脉冲，且每一个脉冲的脉冲宽度为预设时钟周期，第二片选时钟信号中第一个脉冲的上升沿用于产生第二目标指令信号的上升沿，第二片选时钟信号中第二个脉冲的上升沿用于产生第二目标指令信号的下降沿；
情况三：当目标模式为双周期模式，且初始片选信号包括2个脉冲且脉冲宽度为预设时钟周期时，确定第一目标指令信号维持电平状态不变；以及，确定第二片选时钟信号包括两个脉冲，且每一个脉冲的脉冲宽度为预设时钟周期，第二片选时钟信号中第一个脉冲的上升沿用于产生第二目标指令信号的上升沿，第二片选时钟信号中第二个脉冲的上升沿用于产生第二目标指令信号的下降沿。
在一种具体的实施例中，情况一可以进一步分为两种具体情况进行说明。也就是说，在目标模式为单周期模式或者双周期模式，且初始片选信号包括一个脉冲且脉冲宽度为预设时钟周期的情况下，
若第一片选信号在偶数时钟周期的上升沿采样为低电平且在下一相邻奇数时钟周期的上升沿采样为高电平，则确定第一片选时钟奇信号为有效信号，且第一片选时钟奇信号具有两个脉冲；其中，第一片选时钟奇信号中第一个脉冲的上升沿用于产生第一目标指令信号的上升沿，第一片选时钟奇信号中第二个脉冲的上升沿用于产生第一目标指令信号的下降沿；
若第一片选信号在奇数时钟周期的上升沿采样为低电平且在下一相邻偶数时钟周期的上升沿采样为高电平，则确定第一片选时钟偶信号为有效信号，且第一片选时钟偶信号具有两个脉冲；其中，第一片选时钟偶信号中第一个脉冲的上升沿用于产生第一目标指令信号的上升沿，第一片选时钟偶信号中第二个脉冲的上升沿用于产生第一目标指令信号的下降沿。
在一种具体的实施例中，情况二可以进一步分为两种具体情况进行说明。也就是说，在目标模式为单周期模式，且初始片选信号包括一个脉冲且脉冲宽度为预设时钟周期的两倍的情况下，
若第一片选信号在偶数时钟周期的上升沿采样为低电平且在下一相邻奇数时钟周期的上升沿采样仍为低电平，则确定第二片选时钟奇信号为有效信号，且第二片选时钟奇信号具有两个脉冲；其中，第二片选时钟奇信号中第一个脉冲的上升沿用于产生第二目标指令信号的上升沿，第二片选时钟奇信号中第二个脉冲的上升沿用于产生第二目标指令信号的下降沿；
若第一片选信号在奇数时钟周期的上升沿采样为低电平且在下一相邻偶数时钟周期的上升沿采样仍为低电平，则确定第二片选时钟偶信号为有效信号，且第二片选时钟偶信号具有两个脉冲；其中，第二片选时钟偶信号中第一个脉冲的上升沿用于产生第二目标指令信号的上升沿，第二片选时钟偶信号中第二个脉冲的上升沿用于产生第二目标指令信号的下降沿。
在一种具体的实施例中，情况三进一步分为两种具体情况进行说明。也就是说，在目标模式为双周期模式，且初始片选信号包括2个脉冲且脉冲宽度为预设时钟周期的情况下，
若第一片选信号在连续两个偶数时钟周期的上升沿采样为低电平且在连续两个偶数时钟周期之间的奇数时钟周期的上升沿采样为高电平，则确定第二片选时钟奇信号为有效信号，且第二片选时钟奇信号具有两个脉冲，第二片选时钟奇信号中第一个脉冲的上升沿用于产生第二目标指令信号的上升沿，第二片选时钟奇信号中第二个脉冲的上升沿用于产生第二目标指令信号的下降沿；
若第一片选信号在连续两个奇数时钟周期的上升沿采样为低电平且在连续两个奇数时钟周期之间的偶数时钟周期的上升沿采样为高电平，则确定第二片选时钟偶信号为有效信号，且第二片选时钟偶信号具有两个脉冲；其中，第二片选时钟偶信号中第一个脉冲的上升沿用于产生第二目标指令信号的上升沿，第二片选时钟偶信号中第二个脉冲的上升沿用于产生第二目标指令信号的下降沿。
本公开实施例提供了一种信号采样电路，一方面，无论是单周期模式和双周期模式，2T CMD信号和NT ODT CMD信号都可经由前述的信号采样电路进行采样译码处理，而且能够明确区分2T CMD信号和NT ODT CMD信号，无需为双周期模式单独设置译码电路，不仅节省电路面积而且降低了功耗；另一方面，根据第一片选时钟信号和第二片选时钟信号之中的有效信号，通过对应的指令译码电路输出目标指令信号，能够区分2T CMD和NT ODT CMD这两种指令并进行准确译码，两者互不影响；又一方面，由于第一片选时钟信号和第二片选时钟信号之中的有效信号均包括两个脉冲，且每个脉冲的脉冲宽度是一个预设时钟周期，且第一个脉冲的上升沿用于产生目标指令信号的上升沿，第二个脉冲的上升沿用于产生目标指令信号的下降沿，从而使得最终输出的目标指令信号的脉冲宽度可以满足在预设精度范围内为预设时钟周期的两倍，能够避免目标指令信号的脉冲宽度不确定的问题。
在本公开的另一实施例中，继续参见图5，信号采样电路30可以包括第一接收器501、第二接收器502、第三接收器503、第一触发器504、第一缓冲器505、第二触发器506、第二缓冲器507、第三触发器508、第一反相器509、第四触发器510、第二反相器511、第三缓冲器512、第一多路选择器513、第四缓冲器514、第二多路选择器515、第三多路选择器516、第四多路选择器517、第五触发器518、第三反相器519、第一或非门520、第一非门521、第六触发器522、第一或门523、第一与门524、第七触发器525、第四反相器526、第二或非门527、第二非门528、第八触发器529、第二或门530、第二与门531、第九触发器532、第五反相器533、第三非门534、第三或非门535、第四非门536、第十触发器537、第三或门538、第三与门539、第十一触发器540、第六反相器541、第五非门542、第四或非门543、第六非门544、第十二触发器545、第四或门546、第四与门547、第一指令译码触发器421、第五或门548、第二指令译码触发器422和第六或门549。其中，第一触发器504、第二触发器506、第三触发器508、第一反相器509、第四触发器510、第五触发器518、第六触发器522、第七触发器525、第八触发器529、第九触发器532、第十触发器537、第十一触发器540、第十二触发器545均可以为D型触发器。另外，第一指令译码触发器421的具体结构详见图6A所示，第二指令译码触发器422的具体结构详见图6B所示。
需要说明的是，图5的电路原理可参见前述，这里不再详述。基于图5所示的信号采样电路30，其对应的信号时序图如图7～10所示。第一命令地址信号用CA表示，且CA可以包括Cy、Cz、C0、C1、C2和C3；初始片选信号用CS_n表示，而且是用于表征目标芯片被选中的信号；第一片选信 号用PCS表示，PCS信号为低电平有效的脉冲信号，PCS用于表征目标芯片被选中的信号；初始时钟信号用CK_t表示，第一时钟偶信号用PCLK_E表示，第一时钟奇信号用PCLK_O表示，且CK_t信号的时钟周期为预设时钟周期，PCLK_E信号和PCLK_O信号的时钟周期均为预设时钟周期的两倍。以下分为四个场景，对信号采样电路30的信号时序进行具体说明。
场景一：如图7所示，假设在单周期模式(1N MODE)且第一片选信号在偶数时钟周期的上升沿采样为低电平且在下一相邻奇数时钟周期的上升沿采样为高电平。
此时，如图7所示，经PCLK_E信号对CA信号采样得到CA[4:0]_1T_E信号，其包括C0和C2；经PCLK_E信号对PCS信号采样及反相处理得到PCS_E信号，其为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍。经PCLK_O信号对PCS信号采样及反相处理得到PCS_O(图7未示出，但其波形可以参考PCS_2NE_1NO)，其始终为低电平信号。
在2T CLK电路中，经PCLK_2NE_1NO信号(本质为PCLK_O信号)对PCS_E信号采样及反相处理得到PCSB_O信号，其为低电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍，但是相比PCS_E信号延迟一个预设时钟周期。将PCSB_O信号和PCS_2NE_1NO信号(本质为PCS_O信号)进行或非运算，得到PCS_OEN1信号，其为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍。经PCLK_2NE_1NO信号(本质为PCLK_O信号)的下降沿对PCS_OEN1信号采样得到PCS_OEN2信号，其也为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍，但是相比PCS_OEN1信号延迟一个预设时钟周期。这样，PCS_OEN1信号和PCS_OEN2信号进行或运算得到PCS_OEN信号，其脉冲宽度为预设时钟周期的三倍，即第一或门523起到拓宽脉冲宽度的作用。PCS_OEN信号再与PCLK_2NE_1NO信号(本质为PCLK_O信号)进行与逻辑，得到2T_CLK_O信号，其包括2个脉冲，且脉冲宽度为预设时钟周期。同时，在本场景中，2T_CLK_E信号(图7中未示出)始终为低电平的无效信号。所以，通过第一指令译码触发器421，利用2T_CLK_O信号对CA[4:0]_1T_E信号进行译码采样，得到2T CMD信号，而且2T CMD信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍；其中，2T_CLK_O信号中的第一个脉冲的上升沿用于产生2T CMD信号的上升沿，2T_CLK_O信号中的第二个脉冲的上升沿用于产生2T CMD信号的下降沿。特别地，PCLK_2NE_1NO信号的本质为PCLK_O信号的含义是：PCLK_2NE_1NO信号来源于PCLK_O信号，PCLK_2NE_1NO信号和PCLK_O信号的波形一致，但是PCLK_2NE_1NO信号相比于PCLK_O信号可能存在(由于通过逻辑门而产生的)略微延时(该延时图中未示出)。本公开实施例中的“本质”一词均可参照该解释进行对应理解。
在NT ODT CLK电路中，经PCLK_2NE_1NO信号(本质为PCLK_O信号)对PCS_E信号采样及反相处理得到PCSB_O信号，其为低电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍。由于PCS_2NE_1NO(本质为PCS_O信号)的反相信号始终为高电平信号，所以通过将PCSB_O信号和PCS_2NE_1NO(本质为PCS_O信号)的反相信号进行或非运算，能够得到始终为低电平信号的NT_PCS_OEN1信号，进而NT_PCS_OEN2也始终为低电平信号，所以NT_CLK_O信号始终为低电平的无效信号。同时，本情况下的NT_CLK_E信号同样为低电平的无效信号。因此NT_CLK_O信号和NT_CLK_E信号均不会导致有效的译码采样，无法得到NT ODT CMD信号。
简单来说，在单周期模式下，如图7所示，对于2T CMD信号，CS_n信号只有一个预设时钟周期的低电平，被PCLK_E信号采样后变为PCS_E信号，然后在PCLK_2NE_1NO(在单周期模式中为PCLK_O)采样后变为PCSB_O信号。其中，PCSB_O信号和PCS_2NE_1NO(在单周期模式中为PCS_O)进行或非逻辑之后采样产生PCS_OEN1/2来覆盖产生2T_CLK_O信号。最后这个2T_CLK_O信号采样CA[4:0]_1T_E信号和PCS_E信号输出2T CMD信号。而另外一条分支电路是PCSB_O/E信号和PCS_2NE_1NO/PCS_2NO_1NE信号的反相信号进行或非逻辑，导致NT_PCS_OEN1/2信号和NT_PCS_EEN1/2信号均为低电平，而没有覆盖时钟采样，也就不会输出NT ODT CMD信号。
类似地，如果第一片选信号在奇数时钟周期的上升沿采样为低电平且在下一相邻偶数时钟周期的上升沿采样为高电平，此时，2T_CLK_E信号包括两个脉冲，且脉冲宽度为预设时钟周期，但是2T_CLK_O信号始终为低电平的无效信号。这样，通过第一指令译码触发器421，根据2T_CLK_E信号对CA[4:0]_1T_O信号进行译码采样，得到2T CMD信号。其中，2T_CLK_E信号中的第一个脉冲的上升沿用于产生2T CMD信号的上升沿，2T_CLK_E信号中的第二个脉冲的上升沿用于产生2T CMD信号的下降沿。另外，NT_CLK_O信号和NT_CLK_E信号均为低电平的无效信号，所以NT_CLK_O信号和NT_CLK_E信号均不会引发有效的译码采样，无法得到NT ODT CMD信号。
场景二：如图8所示，假设在单周期模式(1N MODE)且第一片选信号在偶数时钟周期的上升 沿采样为低电平且在下一相邻奇数时钟周期的上升沿采样仍为低电平。
此时，如图8所示，经PCLK_E信号对CA信号采样得到CA[4:0]_1T_E信号，其包括C0和C2；经PCLK_E信号对PCS信号采样及反相处理得到PCS_E信号，其为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍。经PCLK_O信号对PCS信号采样及反相处理得到PCS_O信号(图7中未示出，但其波形可参考PCS_2NE_1NO)，其为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍。但是PCS_O信号的上升沿相比于PCS_E信号的上升沿延迟一个预设时钟周期。
在2T CLK电路中，经PCLK_2NE_1NO信号(本质为PCLK_O信号)对PCS_E信号采样及反相处理得到PCSB_O信号，其为低电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍，但是相比于PCS_B延迟一个预设时钟周期。将PCSB_O信号和PCS_2NE_1NO(本质为PCS_O信号)进行或非运算，两者抵消，得到始终为低电平的PCS_OEN1信号，进而2T_CLK_O信号始终为低电平的无效信号。同时，本情况下的2T_CLK_E信号始终为低电平的无效信号。因此2T_CLK_O信号和2T_CLK_E信号均不会导致有效的译码采样，无法得到2T CMD信号。
在NT ODT CLK电路中，经PCLK_2NE_1NO信号(本质为PCLK_O信号)对PCS_E信号采样及反相处理得到PCSB_O信号，其为低电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍。将PCSB_O信号和PCS_2NE_1NO(本质为PCS_O信号)的反相信号进行或非运算，得到NT_PCS_OEN1信号，其为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍。经PCLK_2NE_1NO信号的下降沿对NT_PCS_OEN1信号采样得到NT_PCS_OEN2信号，其也为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍，但是相比NT_PCS_OEN1信号延迟一个预设时钟周期。这样，NT_PCS_OEN1信号和NT_PCS_OEN2信号进行或运算得到NT_PCS_OEN信号，其脉冲宽度为预设时钟周期的三倍，即第三或门538起到拓宽脉冲宽度的作用。NT_PCS_OEN信号再与PCLK_2NE_1NO信号进行与逻辑，得到NT_CLK_O，其包括2个脉冲，且脉冲宽度为预设时钟周期。同时，本情况下的NT_CLK_E信号始终为低电平的无效信号。所以，通过第二指令译码触发器422，利用NT_CLK_O信号对CA[4:0]_1T_E信号进行译码采样，得到NT ODT CMD信号，而且NT ODT CMD信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍；其中，NT_CLK_O信号中的第一个脉冲的上升沿用于产生NT ODT CMD信号的上升沿，NT_CLK_O信号中的第二个脉冲的上升沿用于产生NT ODT CMD信号的下降沿。
简单来说，如图8所示，CS_n信号具有维持2个预设时钟周期的低电平，分别被PCLK_E/O信号采样之后为PCS_E/O信号，然后PCS_E/O信号在PCLK_2NE_1NO/PCLK_2NO_1NE信号采样之后为PCSB_O/E信号，PCSB_O/E信号和PCS_2NE_1NO/PCS_2NO_1NE信号进行或非逻辑，得到的PCS_OEN1/2信号和PCS_EEN1/2信号均为低电平，没有覆盖时钟采样，也就不会输出2T CMD信号。而另外一条分支电路是PCSB_O信号和PCS_2NE_1NO信号的反相信号进行或非逻辑，从而产生NT_PCS_OEN1/2来覆盖产生具有两个脉冲的NT_CLK_O信号，最后这个NT_CLK_O信号采样CA[4:0]_1T_E信号和PCS_E信号输出NT ODT CMD信号。
类似地，如果第一片选信号在奇数时钟周期的上升沿采样为低电平且在下一相邻偶数时钟周期的上升沿采样仍为低电平，那么NT_CLK_E信号包括两个脉冲，且脉冲宽度为预设时钟周期，但是NT_CLK_O信号始终为低电平的无效信号。这样，通过第二指令译码触发器422，根据NT_CLK_E信号对CA[4:0]_1T_O信号进行译码采样，得到NT ODT CMD信号，而且NT ODT CMD信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍。其中，NT_CLK_E信号中的第一个脉冲的上升沿用于产生NT ODT CMD信号的上升沿，NT_CLK_E信号中的第二个脉冲的上升沿用于产生NT ODT CMD信号的下降沿。另外，2T_CLK_O信号和2T_CLK_E信号均始终为低电平的无效信号，所以2T_CLK_O信号和2T_CLK_E信号均不会引发有效的译码采样，无法得到2T CMD信号。
场景三：如图9所示，假设在双周期模式(2N MODE)且第一片选信号在偶数时钟周期的上升沿采样为低电平且在下一相邻奇数时钟周期的上升沿采样为高电平。
此时，如图9所示，经PCLK_E信号对CA信号采样得到CA[4:0]_1T_E信号，其包括C0和C2；经PCLK_E信号对PCS信号采样及反相处理得到PCS_E信号，其为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍。经PCLK_O信号对PCS信号采样及反相处理得到PCS_O(图9中未示出)，其始终为低电平信号。
在2T CLK电路中，经PCLK_2NE_1NO信号(本质为PCLK_E信号)对PCS_E信号采样及反相处理得到PCSB_O信号，其为低电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍。将PCSB_O信号和PCS_2NE_1NO(本质为PCS_E信号)进行或非运算，得到PCS_OEN1信号，其为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍。经PCLK_2NE_1NO信号的下降沿对 PCS_OEN1信号采样得到PCS_OEN2信号，其也为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍，但是相比PCS_OEN1信号延迟一个预设时钟周期。这样，PCS_OEN1信号和PCS_OEN2信号经过或逻辑后再与PCLK_2NE_1NO信号进行与逻辑，得到2T_CLK_O信号，其包括2个脉冲，且脉冲宽度为预设时钟周期。同时，本情况下的2T_CLK_E信号始终为低电平的无效信号。所以，通过第一指令译码触发器421，利用2T_CLK_O信号对CA[4:0]_1T_E信号进行译码采样，得到2T CMD信号，而且2T CMD信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍；其中，2T_CLK_O信号中的第一个脉冲的上升沿用于产生2T CMD信号的上升沿，2T_CLK_O信号中的第二个脉冲的上升沿用于产生2T CMD信号的下降沿。
在NT ODT CLK电路中，经PCLK_2NE_1NO信号对PCS_E信号采样及反相处理得到PCSB_O信号，其为低电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍。将PCSB_O信号和PCS_2NE_1NO(本质为PCS_E信号)的反相信号进行或非运算，刚好抵消，得到始终为低电平信号的NT_PCS_OEN1信号，进而NT_PCS_OEN2也始终为低电平信号，所以NT_CLK_O信号始终为低电平的无效信号。同时，本情况下的NT_CLK_E信号始终为低电平的无效信号。因此NT_CLK_O信号和NT_CLK_E信号均不会引发有效的译码采样，无法得到NT ODT CMD信号。
简单来说，在双周期模式下，对于2T CMD信号，如图9所示，CS_n信号只有一个预设时钟周期的低电平，被PCLK_E信号采样后变为PCS_E信号，然后在PCLK_2NE_1NO采样后变为PCSB_O信号。其中，PCSB_O信号和PCS_2NE_1NO信号进行或非逻辑之后采样产生PCS_OEN1/2信号来覆盖产生2T_CLK_O信号。最后这个2T_CLK_O信号采样CA[4:0]_1T_E信号和PCS_E信号输出2T CMD信号。而另外一条分支电路是PCSB_O/E信号和PCS_2NE_1NO/PCS_2NO_1NE信号的反相信号进行或非逻辑，导致NT_PCS_OEN1/2信号和NT_PCS_EEN1/2信号均为低电平，而没有覆盖时钟采样，也就不会输出NT ODT CMD信号。
类似地，如果第一片选信号在奇数时钟周期的上升沿采样为低电平且在下一相邻偶数时钟周期的上升沿采样为高电平，此时，2T_CLK_E信号包括两个脉冲，每个脉冲的宽度为预设时钟周期，但是2T_CLK_O信号时钟为低电平的无效信号。这样，通过第一指令译码触发器421，根据2T_CLK_E信号对CA[4:0]_1T_O信号进行译码采样，得到2T CMD信号。其中，2T_CLK_E信号中的第一个脉冲的上升沿用于产生2T CMD信号的上升沿，2T_CLK_E信号中的第二个脉冲的上升沿用于产生2T CMD信号的下降沿。另外，NT_CLK_O信号和NT_CLK_E信号均始终为低电平的无效信号，所以NT_CLK_O信号和NT_CLK_E信号均不会引发有效的译码采样，无法得到NT ODT CMD信号。
场景四：如图10所示，假设在双周期模式(2N MODE)且第一片选信号在连续两个偶数时钟周期的上升沿采样为低电平且在连续两个偶数时钟周期之间的奇数时钟周期的上升沿采样为高电平。
此时，如图10所示，经PCLK_E信号对CA信号采样得到CA[4:0]_1T_E信号，其包括C0和C2；经PCLK_E信号对PCS信号采样及反相处理得到PCS_E信号，其为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的4倍。经PCLK_O信号对PCS信号采样及反相处理得到PCS_O信号(图10未示出)，其始终为低电平。
在2T CLK电路中，经PCLK_2NE_1NO信号(本质为PCLK_E信号)对PCS_E信号采样及反相处理得到PCSB_O信号，其为低电平有效的脉冲信号，且脉冲宽度为预设时钟周期的4倍。将PCSB_O信号和PCS_2NE_1NO(本质为PCS_E信号)进行或非运算，得到PCS_OEN1信号，且其为高电平有效的脉冲信号，但是PCS_OEN1信号的上升沿迟于CA[4:0]_1T_E信号的有效内容C0，经PCLK_2NE_1NO信号的下降沿对PCS_OEN1信号采样得到PCS_OEN2信号，其也为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍，但是相比PCS_OEN1信号延迟一个预设时钟周期。这样，PCS_OEN1信号和PCS_OEN2信号经过或逻辑后再与PCLK_2NE_1NO信号进行与逻辑，得到2T_CLK_O信号，其包括2个脉冲，且脉冲宽度为预设时钟周期，但是2T_CLK_O信号的第一个脉冲的上升沿迟于CA[4:0]_1T_E信号的有效内容C0，所以2T_CLK_O信号并不会导致有效的译码采样，无法得到2T CMD信号。同时，本情况下的2T_CLK_E信号始终为低电平的无效信号。因此2T_CLK_E信号也不会导致有效的译码采样，无法得到2T CMD信号。
在NT ODT CLK电路中，经PCLK_2NE_1NO信号(本质为PCLK_E信号)对PCS_E信号采样及反相处理得到PCSB_O信号，其为低电平有效的脉冲信号，且脉冲宽度为预设时钟周期的4倍。将PCSB_O信号和PCS_2NE_1NO(本质为PCS_E信号)的反相信号进行或非运算，得到NT_PCS_OEN1信号，其为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍。经PCLK_2NE_1NO信号的下降沿对PCS_OEN1信号采样得到NT_PCS_OEN2信号，其也为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍，但是相比NT_PCS_OEN1信号延迟一个预设时 钟周期。这样，NT_PCS_OEN1信号和NT_PCS_OEN2信号经过或逻辑后再与PCLK_2NE_1NO信号进行与逻辑，得到NT_CLK_O，其包括2个脉冲，且脉冲宽度为预设时钟周期。同时，本情况下的NT_CLK_E信号始终为低电平的无效信号。所以，通过第二指令译码触发器422，利用NT_CLK_O信号对CA[4:0]_1T_E信号进行译码采样，得到NT ODT CMD信号，而且NT ODT CMD信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍；其中，NT_CLK_O信号中的第一个脉冲的上升沿用于产生NT ODT CMD信号的上升沿，NT_CLK_O信号中的第二个脉冲的上升沿用于产生NT ODT CMD信号的下降沿。
简单来说，对于NT ODT CMD信号，如图10所示，CS_n信号具有2个间隔周期的低电平，分别被PCLK_E/O信号采样之后为PCS_E/O信号，然后PCS_E信号在PCLK_2NE_1NO信号采样后为PCSB_O信号，PCSB_O信号和PCS_2NE_1NO信号进行或非逻辑后，得到PCS_OEN1/2信号，且PCS_OEN1/2信号为高电平有效的脉冲信号，但是PCS_OEN1/2信号的上升沿迟于CA[4:0]_1T_E信号的有效内容C0，所以2T_CLK_O信号并不会导致有效的译码采样，无法得到2T CMD信号；同时，PCS_O信号在PCLK_2NO_1NE信号采样后为PCSB_E信号，PCSB_E信号和PCS_2NO_1NE信号进行或非逻辑后，得到的PCS_EEN1/2信号始终为低电平，没有覆盖时钟采样，也就不会输出2T CMD信号。而另外一条分支电路是PCSB_O信号和PCS_2NE_1NO信号的反相信号进行或非逻辑，从而产生NT_PCS_OEN1/2来覆盖产生具有两个脉冲的NT_CLK_O信号，最后这个NT_CLK_O信号采样CA[4:0]_1T_E信号和PCS_E信号输出NT ODT CMD信号。
类似地，如果第一片选信号在连续两个奇数时钟周期的上升沿采样为低电平且在连续两个奇数时钟周期之间的偶数时钟周期的上升沿采样为高电平，那么NT_CLK_E信号包括两个脉冲，每个脉冲的宽度为预设时钟周期，但是NT_CLK_O信号时钟为低电平的无效信号。这样，通过第二指令译码触发器422，根据NT_CLK_E信号对CA[4:0]_1T_O信号进行译码采样，得到NT ODT CMD信号。其中，NT_CLK_E信号中的第一个脉冲的上升沿用于产生NT ODT CMD信号的上升沿，NT_CLK_E信号中的第二个脉冲的上升沿用于产生NT ODT CMD信号的下降沿。另外，2T_CLK_O信号终为低电平的无效信号，2T_CLK_E信号虽然存在2个脉冲，但其上升沿迟于CA[4:0]_1T_O信号的有效内容，所以2T_CLK_O信号同样为无效信号，2T_CLK_O信号和2T_CLK_E信号均不会导致有效的译码采样，无法得到2T CMD信号。
本公开实施例提供了一种信号采样电路，通过本实施例对前述实施例的具体实现进行详细阐述，从中可以看出，基于本公开实施例的技术方案，通过本公开实施例的信号采样电路30，能够在不同周期模式下对2T CMD信号和NT ODT CMD信号进行分别译码且相互不影响，无需为每种周期模式设置独立的译码电路，节省电路面积且降低功耗。
在本公开的又一实施例中，参见图11，其示出了本公开实施例提供的一种半导体存储器110的组成结构示意图。如图11所示，半导体存储器110可以包括前述实施例任一项的信号采样电路30。
在本公开实施例中，半导体存储器110可以为DRAM芯片。
进一步地，在一些实施例中，DRAM芯片符合DDR5内存规格。
需要说明的是，本公开实施例主要涉及集成电路设计中输入信号采样及指令译码的相关电路，特别涉及DRAM芯片中，不同周期模式下CA信号输入分别作为指令和地址采样和译码之后的控制调节电路。具体来说，本公开实施例的技术方案解决了DDR5中在不同周期模式中区分2T CMD和NT ODT CMD采样译码的难题，对于CS_n信号的脉冲形状不同的指令可以分别译码为2T CMD信号和NT ODT CMD信号，而且互相不影响。
另外，还需要说明的是，本公开实施例的技术方案可以应用于DRAM芯片中CA信号采样和译码的控制电路，但不局限于此范围，其他输入信号采样及指令译码的相关电路均可采用此设计。
这样，在本公开实施例中，对于半导体存储器120而言，其包括有信号采样电路30，因此，基于该信号采样电路，根据所处的周期模式确定目标模式时钟信号和目标模式片选信号，以便针对不同脉冲形状的第一片选信号，获得相应的第一片选时钟信号和第二片选时钟信号，从而在不同周期模式下正确区分2T CMD和NT ODT CMD，并进行正确译码，能够避免出现指令译码错误而执行错误操作的问题，同时节省电路面积，降低功耗。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句 “包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种信号采样电路以及半导体存储器，基于该信号采样电路，根据所处的周期模式确定目标模式时钟信号和目标模式片选信号，以便针对不同脉冲形状的第一片选信号，获得相应的第一片选时钟信号和第二片选时钟信号，从而在不同周期模式下正确区分2T CMD和NT ODT CMD这两种指令并进行准确译码，能够避免出现指令译码错误而执行错误操作的问题，同时节省电路面积，降低功耗。

Claims (22)

  1. 一种信号采样电路，所述信号采样电路包括信号输入电路、模式选择电路、第一时钟处理电路、第二时钟处理电路和指令译码电路；其中，
    所述信号输入电路，用于根据第一时钟信号、第一片选信号和第一命令地址信号，确定待处理指令信号和待处理片选信号；其中，所述第一时钟信号的时钟周期为预设时钟周期的两倍；
    所述模式选择电路，用于在模式选择信号指示目标模式的情况下，根据所述模式选择信号对所述第一时钟信号和所述待处理片选信号进行选择处理，得到目标模式时钟信号和目标模式片选信号；
    所述第一时钟处理电路，用于当所述第一片选信号包括一个脉冲且脉冲宽度为所述预设时钟周期时，根据所述目标模式时钟信号对所述待处理片选信号和所述目标模式片选信号进行采样及逻辑运算处理，得到第一片选时钟信号；
    所述第二时钟处理电路，用于当所述第一片选信号包括一个脉冲且脉冲宽度为所述预设时钟周期的两倍、或者所述第一片选信号包括2个脉冲且脉冲宽度为所述预设时钟周期时，根据所述目标模式时钟信号对所述待处理片选信号和所述目标模式片选信号进行采样及逻辑运算处理，得到第二片选时钟信号；
    所述指令译码电路，用于根据所述待处理片选信号和所述第一片选时钟信号对所述待处理指令信号进行译码和采样处理，得到目标指令信号；或者，根据所述待处理片选信号和所述第二片选时钟信号对所述待处理指令信号进行译码和采样处理，得到目标指令信号。
  2. 根据权利要求1所述的信号采样电路，其中，在所述目标模式为单周期模式的情况下，
    所述第一时钟处理电路，用于当所述第一片选信号包括一个脉冲且脉冲宽度为所述预设时钟周期时，根据所述单周期模式对应的目标模式时钟信号对所述待处理片选信号和所述单周期模式对应的目标模式片选信号进行采样及逻辑运算处理，得到所述第一片选时钟信号；
    所述第二时钟处理电路，用于当所述第一片选信号包括一个脉冲且脉冲宽度为所述预设时钟周期的两倍时，根据所述单周期模式对应的目标模式时钟信号对所述待处理片选信号和所述单周期模式对应的目标模式片选信号进行采样及逻辑运算处理，得到所述第二片选时钟信号；
    或者，在所述目标模式为双周期模式的情况下，
    所述第一时钟处理电路，用于当所述第一片选信号包括一个脉冲且脉冲宽度为所述预设时钟周期时，根据所述双周期模式对应的目标模式时钟信号对所述待处理片选信号和所述双周期模式对应的目标模式片选信号进行采样及逻辑运算处理，得到所述第一片选时钟信号；
    所述第二时钟处理电路，用于当第一片选信号包括2个脉冲且脉冲宽度为所述预设时钟周期时，根据所述双周期模式对应的目标模式时钟信号对所述待处理片选信号和所述双周期模式对应的目标模式片选信号进行采样及逻辑运算处理，得到所述第二片选时钟信号。
  3. 根据权利要求1所述的信号采样电路，其中，所述信号输入电路包括第一接收电路、第二接收电路、第三接收电路和输入采样电路；其中，
    所述第一接收电路，用于接收初始命令地址信号，输出所述第一命令地址信号；
    所述第二接收电路，用于接收初始片选信号，输出所述第一片选信号；
    所述第三接收电路，用于接收初始时钟信号，并对所述初始时钟信号进行分频处理，输出第一时钟奇信号和第一时钟偶信号；
    所述输入采样电路，用于根据所述第一时钟信号对所述第一片选信号和所述第一命令地址信号进行采样处理，得到所述待处理片选信号和所述待处理指令信号；
    其中，所述初始时钟信号的时钟周期为所述预设时钟周期，所述第一时钟信号是由所述第一时钟奇信号和所述第一时钟偶信号组成，所述第一时钟奇信号和所述第一时钟偶信号各自的时钟周期均是所述预设时钟周期的两倍，且所述第一时钟奇信号和所述第一时钟偶信号之间的相位差为180度。
  4. 根据权利要求3所述的信号采样电路，其中，所述输入采样电路包括第一采样电路、第二采样电路、第三采样电路和第四采样电路；其中，
    所述第一采样电路，用于根据所述第一时钟偶信号对所述第一命令地址信号进行采样处理，得到待处理指令偶信号；
    所述第二采样电路，用于根据所述第一时钟奇信号对所述第一命令地址信号进行采样处理，得到待处理指令奇信号；
    所述第三采样电路，用于根据所述第一时钟偶信号对所述第一片选信号进行采样及反相处理， 得到待处理片选偶信号；
    所述第四采样电路，用于根据所述第一时钟奇信号对所述第一片选信号进行采样及反相处理，得到待处理片选奇信号；
    其中，所述待处理指令信号是由所述待处理指令偶信号和所述待处理指令奇信号组成，所述待处理片选信号是由所述待处理片选偶信号和所述待处理片选奇信号组成。
  5. 根据权利要求4所述的信号采样电路，其中，
    所述第一采样电路包括第一触发器，且所述第一触发器的输入端与所述第一命令地址信号连接，所述第一触发器的时钟端与所述第一时钟偶信号连接，所述第一触发器的输出端用于输出所述待处理指令偶信号；
    所述第二采样电路包括第二触发器，且所述第二触发器的输入端与所述第一命令地址信号连接，所述第二触发器的时钟端与所述第一时钟奇信号连接，所述第二触发器的输出端用于输出所述待处理指令奇信号；
    所述第三采样电路包括第三触发器和第一反相器，且所述第三触发器的输入端与所述第一片选信号连接，所述第三触发器的时钟端与所述第一时钟偶信号连接，所述第三触发器的输出端与所述第一反相器的输入端连接，所述第一反相器的输出端用于输出所述待处理片选偶信号；
    所述第四采样电路包括第四触发器和第二反相器，且所述第四触发器的输入端与所述第一片选信号连接，所述第四触发器的时钟端与所述第一时钟奇信号连接，所述第四触发器的输出端与所述第二反相器的输入端连接，所述第二反相器的输出端用于输出所述待处理片选奇信号。
  6. 根据权利要求5所述的信号采样电路，其中，所述模式选择电路包括第一选择电路、第二选择电路、第三选择电路和第四选择电路；其中，
    所述第一选择电路，用于根据所述模式选择信号对所述第一时钟奇信号和所述第一时钟偶信号进行选择处理，得到所述目标模式时钟信号中的第一模式时钟信号；
    所述第二选择电路，用于根据所述模式选择信号对所述第一时钟奇信号和所述第一时钟偶信号进行选择处理，得到所述目标模式时钟信号中的第二模式时钟信号；
    所述第三选择电路，用于根据所述模式选择信号对所述待处理片选奇信号和所述待处理片选偶信号进行选择处理，得到所述目标模式片选信号中的第一模式片选信号；
    所述第四选择电路，用于根据所述模式选择信号对所述待处理片选奇信号和所述待处理片选偶信号进行选择处理，得到所述目标模式片选信号中的第二模式片选信号。
  7. 根据权利要求6所述的信号采样电路，其中，
    所述模式选择电路，具体用于在所述模式选择信号指示单周期模式的情况下，选择所述第一时钟奇信号生成所述第一模式时钟信号，选择所述第一时钟偶信号生成所述第二模式时钟信号，选择所述待处理片选奇信号生成所述第一模式片选信号，选择所述待处理片选偶信号生成所述第二模式片选信号；或者，
    所述模式选择电路，具体用于在所述模式选择信号指示双周期模式的情况下，选择所述第一时钟偶信号生成所述第一模式时钟信号，选择所述第一时钟奇信号生成所述第二模式时钟信号，选择所述待处理片选偶信号生成所述第一模式片选信号，选择所述待处理片选奇信号生成所述第二模式片选信号。
  8. 根据权利要求7所述的信号采样电路，其中，
    若所述目标模式为单周期模式，则确定所述模式选择信号处于第一电平状态；或者，
    若所述目标模式为双周期模式，则确定所述模式选择信号处于第二电平状态。
  9. 根据权利要求6所述的信号采样电路，其中，所述第一选择电路包括第一多路选择器，所述第二选择电路包括第二多路选择器，所述第三选择电路包括第三多路选择器，所述第四选择电路包括第四多路选择器；其中，
    所述第一多路选择器的第一输入端与所述第一时钟偶信号连接，所述第一多路选择器的第二输入端与所述第一时钟奇信号连接，所述第一多路选择器的输出端用于输出所述第一模式时钟信号；
    所述第二多路选择器的第一输入端与所述第一时钟奇信号连接，所述第二多路选择器的第二输入端与所述第一时钟偶信号连接，所述第二多路选择器的输出端用于输出所述第二模式时钟信号；
    所述第三多路选择器的第一输入端与所述待处理片选偶信号连接，所述第三多路选择器的第二输入端与所述待处理片选奇信号连接，所述第三多路选择器的输出端用于输出所述第一模式片选信号；
    所述第四多路选择器的第一输入端与所述待处理片选奇信号连接，所述第四多路选择器的第二 输入端与所述待处理片选偶信号连接，所述第四多路选择器的输出端用于输出所述第二模式片选信号；
    所述第一多路选择器、所述第二多路选择器、所述第三多路选择器和第四多路选择器各自的控制端均与所述模式选择信号连接。
  10. 根据权利要求6所述的信号采样电路，其中，所述第一时钟处理电路包括第一逻辑电路和第二逻辑电路，所述第二时钟处理电路包括第三逻辑电路和第四逻辑电路；其中，
    所述第一逻辑电路，用于接收所述第一模式时钟信号和所述第一模式片选信号，并利用所述第一模式时钟信号对所述待处理片选偶信号和所述第一模式片选信号进行采样及逻辑运算处理，得到第一片选时钟奇信号；
    所述第二逻辑电路，用于接收所述第二模式时钟信号和所述第二模式片选信号，并利用所述第二模式时钟信号对所述待处理片选奇信号和所述第二模式片选信号进行采样及逻辑运算处理，得到第一片选时钟偶信号；
    所述第三逻辑电路，用于接收所述第一模式时钟信号和所述第一模式片选信号，并利用所述第一模式时钟信号对所述待处理片选偶信号和所述第一模式片选信号进行采样及逻辑运算处理，得到第二片选时钟奇信号；
    所述第四逻辑电路，用于接收所述第二模式时钟信号和所述第二模式片选信号，并利用所述第二模式时钟信号对所述待处理片选奇信号和所述第二模式片选信号进行采样及逻辑运算处理，得到第二片选时钟偶信号；
    其中，所述第一片选时钟信号是由所述第一片选时钟偶信号和所述第一片选时钟奇信号组成，所述第二片选时钟信号是由所述第二片选时钟奇信号和所述第二片选时钟偶信号组成。
  11. 根据权利要求10所述的信号采样电路，其中，
    所述第一逻辑电路包括第五采样电路、第一或非门、第一非门、第六采样电路、第一或门和第一与门；其中，
    所述第五采样电路，用于利用所述第一模式时钟信号对所述待处理片选偶信号进行采样及反相处理，得到第一中间采样奇信号；
    所述第一或非门，用于对所述第一中间采样奇信号和所述第一模式片选信号进行或非运算，得到第二中间采样奇信号；
    所述第一非门，用于对所述第一模式时钟信号进行非运算，得到第一反相时钟奇信号；
    所述第六采样电路，用于利用所述第一反相时钟奇信号对所述第二中间采样奇信号进行采样处理，得到第三中间采样奇信号；
    所述第一或门，用于对所述第二中间采样奇信号和所述第三中间采样奇信号进行或运算，得到第四中间采样奇信号；
    所述第一与门，用于对所述第四中间采样奇信号和所述第一模式时钟信号进行与运算，得到所述第一片选时钟奇信号；
    所述第二逻辑电路包括第七采样电路、第二或非门、第二非门、第八采样电路、第二或门和第二与门；其中，
    所述第七采样电路，用于利用所述第二模式时钟信号对所述待处理片选奇信号进行采样及反相处理，得到第一中间采样偶信号；
    所述第二或非门，用于对所述第一中间采样偶信号和所述第二模式片选信号进行或非运算，得到第二中间采样偶信号；
    所述第二非门，用于对所述第二模式时钟信号进行非运算，得到第一反相时钟偶信号；
    所述第八采样电路，用于利用所述第一反相时钟偶信号对所述第二中间采样偶信号进行采样处理，得到第三中间采样偶信号；
    所述第二或门，用于对所述第二中间采样偶信号和所述第三中间采样偶信号进行或运算，得到第四中间采样偶信号；
    所述第二与门，用于对所述第四中间采样偶信号和所述第二模式时钟信号进行与运算，得到所述第一片选时钟偶信号。
  12. 根据权利要求10所述的信号采样电路，其中，
    所述第三逻辑电路包括第九采样电路、第三非门、第三或非门、第四非门、第十采样电路、第三或门和第三与门；其中，
    所述第九采样电路，用于利用所述第一模式时钟信号对所述待处理片选偶信号进行采样及反相 处理，得到第五中间采样奇信号；
    所述第三非门，用于对所述第一模式片选信号进行非运算，得到第一模式片选反相信号；
    所述第三或非门，用于对所述第五中间采样奇信号和所述第一模式片选反相信号进行或非运算，得到第六中间采样奇信号；
    所述第四非门，用于对所述第一模式时钟信号进行非运算，得到第一模式时钟反相信号；
    所述第十采样电路，用于利用所述第一模式时钟反相信号对所述第六中间采样奇信号进行采样处理，得到第七中间采样奇信号；
    所述第三或门，用于对所述第六中间采样奇信号和所述第七中间采样奇信号进行或运算，得到第八中间采样奇信号；
    所述第三与门，用于对所述第八中间采样奇信号和所述第一模式时钟信号进行与运算，得到所述第二片选时钟奇信号；
    所述第四逻辑电路包括第十一采样电路、第五非门、第四或非门、第六非门、第十二采样电路、第四或门和第四与门；其中，
    所述第十一采样电路，用于利用所述第二模式时钟信号对所述待处理片选奇信号进行采样及反相处理，得到第五中间采样偶信号；
    所述第五非门，用于对所述第二模式片选信号进行非运算，得到第二模式片选反相信号；
    所述第四或非门，用于对所述第五中间采样偶信号和所述第二模式片选反相信号进行或非运算，得到第六中间采样偶信号；
    所述第六非门，用于对所述第二模式时钟信号进行非运算，得到第二模式时钟反相信号；
    所述第十二采样电路，用于利用所述第二模式时钟反相信号对所述第六中间采样偶信号进行采样处理，得到第七中间采样偶信号；
    所述第四或门，用于对所述第六中间采样偶信号和所述第七中间采样偶信号进行或运算，得到第八中间采样偶信号；
    所述第四与门，用于对所述第八中间采样偶信号和所述第二模式时钟信号进行与运算，得到所述第二片选时钟偶信号。
  13. 根据权利要求10所述的信号采样电路，其中，所述指令译码电路包括第一指令译码电路和第二指令译码电路；其中，
    所述第一指令译码电路，用于接收所述第一片选时钟信号，根据所述第一片选时钟信号和所述待处理片选信号对所述待处理指令信号进行译码和采样处理，得到第一目标指令信号；
    所述第二指令译码电路，用于接收所述第二片选时钟信号，根据所述第二片选时钟信号和所述待处理片选信号对所述待处理指令信号进行译码和采样处理，得到第二目标指令信号。
  14. 根据权利要求13所述的信号采样电路，其中，所述第一指令译码电路包括第一译码采样电路和第五或门；其中，
    所述第一译码采样电路，用于根据所述第一片选时钟奇信号和所述待处理片选偶信号对所述待处理指令偶信号进行译码和采样处理，得到第一指令偶信号；以及根据所述第一片选时钟偶信号和所述待处理片选奇信号对所述待处理指令奇信号进行译码和采样处理，得到第一指令奇信号；
    所述第五或门，用于对所述第一指令偶信号和所述第一指令奇信号进行或运算，得到所述第一目标指令信号；
    所述第二指令译码电路包括第二译码采样电路和第六或门；其中，
    所述第二译码采样电路，用于根据所述第二片选时钟奇信号和所述待处理片选偶信号对所述待处理指令偶信号进行译码和采样处理，得到第二指令偶信号；以及根据所述第二片选时钟偶信号和所述待处理片选奇信号对所述待处理指令奇信号进行译码和采样处理，得到第二指令奇信号；
    所述第六或门，用于对所述第二指令偶信号和所述第二指令奇信号进行或运算，得到所述第二目标指令信号。
  15. 根据权利要求14所述的信号采样电路，其中，
    所述第一译码采样电路包括第一译码电路、第十三采样电路、第二译码电路和第十四采样电路；其中，
    所述第一译码电路，用于对所述待处理片选偶信号和所述待处理指令偶信号进行译码处理，得到第一译码偶信号；
    所述第十三采样电路，用于利用所述第一片选时钟奇信号对所述第一译码偶信号进行采样处理，得到所述第一指令偶信号；
    所述第二译码电路，用于对所述待处理片选奇信号和所述待处理指令奇信号进行译码处理，得到第一译码奇信号；
    所述第十四采样电路，用于利用所述第一片选时钟偶信号对所述第一译码奇信号进行采样处理，得到所述第一指令奇信号；
    所述第二译码采样电路包括第三译码电路、第十五采样电路、第四译码电路和第十六采样电路；其中，
    所述第三译码电路，用于对所述待处理片选偶信号和所述待处理指令偶信号进行译码处理，得到第二译码偶信号；
    所述第十五采样电路，用于利用所述第二片选时钟奇信号对所述第二译码偶信号进行采样处理，得到所述第二指令偶信号；
    所述第四译码电路，用于对所述待处理片选奇信号和所述待处理指令奇信号进行译码处理，得到第二译码奇信号；
    所述第十六采样电路，用于利用所述第二片选时钟偶信号对所述第二译码奇信号进行采样处理，得到所述第二指令奇信号。
  16. 根据权利要求13所述的信号采样电路，其中，所述初始片选信号是表征目标芯片被选中的信号，且所述初始片选信号为低电平有效的脉冲信号；其中，
    若所述初始片选信号包括一个脉冲且脉冲宽度为所述预设时钟周期，则确定所述第一片选时钟信号为有效信号，将经由所述第一指令译码电路输出的所述第一目标指令信号确定为所述目标指令信号；
    若所述初始片选信号包括一个脉冲且脉冲宽度为所述预设时钟周期的两倍、或者所述初始片选信号包括2个脉冲且脉冲宽度为所述预设时钟周期，则确定所述第二片选时钟信号为有效信号，将经由所述第二指令译码电路输出的所述第二目标指令信号确定为所述目标指令信号。
  17. 根据权利要求16所述的信号采样电路，其中，
    所述第一目标指令信号为DDR5 DRAM芯片中的Command信号；所述Command信号包括读命令信号，写命令信号，刷新命令信号，预充电命令信号，激活命令信号；
    所述第二目标指令信号为DDR5 DRAM芯片中的Non-Target ODT Command信号。
  18. 根据权利要求17所述的信号采样电路，其中，
    当所述目标模式为单周期模式或者双周期模式，且所述初始片选信号包括一个脉冲且脉冲宽度为所述预设时钟周期时，确定所述第一片选时钟信号包括两个脉冲，且每一个脉冲的脉冲宽度为所述预设时钟周期，所述第一片选时钟信号中第一个脉冲的上升沿用于产生所述第一目标指令信号的上升沿，所述第一片选时钟信号中第二个脉冲的上升沿用于产生所述第一目标指令信号的下降沿；以及，确定所述第二片选时钟信号维持电平状态不变，所述第二目标指令信号维持电平状态不变；
    当所述目标模式为单周期模式，且所述初始片选信号包括一个脉冲且脉冲宽度为所述预设时钟周期的两倍时，确定所述第一片选时钟信号维持电平状态不变，所述第一目标指令信号维持电平状态不变；以及，确定所述第二片选时钟信号包括两个脉冲，且每一个脉冲的脉冲宽度为所述预设时钟周期，所述第二片选时钟信号中第一个脉冲的上升沿用于产生所述第二目标指令信号的上升沿，所述第二片选时钟信号中第二个脉冲的上升沿用于产生所述第二目标指令信号的下降沿；
    当所述目标模式为双周期模式，且所述初始片选信号包括2个脉冲且脉冲宽度为所述预设时钟周期时，确定所述第一目标指令信号维持电平状态不变；以及，确定所述第二片选时钟信号包括两个脉冲，且每一个脉冲的脉冲宽度为所述预设时钟周期，所述第二片选时钟信号中第一个脉冲的上升沿用于产生所述第二目标指令信号的上升沿，所述第二片选时钟信号中第二个脉冲的上升沿用于产生所述第二目标指令信号的下降沿。
  19. 根据权利要求18所述的信号采样电路，其中，在所述目标模式为单周期模式或者双周期模式，且所述初始片选信号包括一个脉冲且脉冲宽度为所述预设时钟周期的情况下，
    若所述第一片选信号在偶数时钟周期的上升沿采样为低电平且在下一相邻奇数时钟周期的上升沿采样为高电平，则确定所述第一片选时钟奇信号为有效信号，且所述第一片选时钟奇信号具有两个脉冲；其中，所述第一片选时钟奇信号中第一个脉冲的上升沿用于产生所述第一目标指令信号的上升沿，所述第一片选时钟奇信号中第二个脉冲的上升沿用于产生所述第一目标指令信号的下降沿；
    若所述第一片选信号在奇数时钟周期的上升沿采样为低电平且在下一相邻偶数时钟周期的上升沿采样为高电平，则确定所述第一片选时钟偶信号为有效信号，且所述第一片选时钟偶信号具有两个脉冲；其中，所述第一片选时钟偶信号中第一个脉冲的上升沿用于产生所述第一目标指令信号的 上升沿，所述第一片选时钟偶信号中第二个脉冲的上升沿用于产生所述第一目标指令信号的下降沿。
  20. 根据权利要求19所述的信号采样电路，其中，在所述目标模式为单周期模式，且初始片选信号包括一个脉冲且脉冲宽度为所述预设时钟周期的两倍的情况下，
    若所述第一片选信号在偶数时钟周期的上升沿采样为低电平且在下一相邻奇数时钟周期的上升沿采样仍为低电平，则确定所述第二片选时钟奇信号为有效信号，且所述第二片选时钟奇信号具有两个脉冲；其中，所述第二片选时钟奇信号中第一个脉冲的上升沿用于产生所述第二目标指令信号的上升沿，所述第二片选时钟奇信号中第二个脉冲的上升沿用于产生所述第二目标指令信号的下降沿；
    若所述第一片选信号在奇数时钟周期的上升沿采样为低电平且在下一相邻偶数时钟周期的上升沿采样仍为低电平，则确定所述第二片选时钟偶信号为有效信号，且所述第二片选时钟偶信号具有两个脉冲；其中，所述第二片选时钟偶信号中第一个脉冲的上升沿用于产生所述第二目标指令信号的上升沿，所述第二片选时钟偶信号中第二个脉冲的上升沿用于产生所述第二目标指令信号的下降沿；
    在所述目标模式为双周期模式，且所述初始片选信号包括2个脉冲且脉冲宽度为所述预设时钟周期的情况下，
    若所述第一片选信号在连续两个偶数时钟周期的上升沿采样为低电平且在所述连续两个偶数时钟周期之间的奇数时钟周期的上升沿采样为高电平，则确定所述第二片选时钟奇信号为有效信号，且所述第二片选时钟奇信号具有两个脉冲，所述第二片选时钟奇信号中第一个脉冲的上升沿用于产生所述第二目标指令信号的上升沿，所述第二片选时钟奇信号中第二个脉冲的上升沿用于产生所述第二目标指令信号的下降沿；
    若所述第一片选信号在连续两个奇数时钟周期的上升沿采样为低电平且在所述连续两个奇数时钟周期之间的偶数时钟周期的上升沿采样为高电平，则确定所述第二片选时钟偶信号为有效信号，且所述第二片选时钟偶信号具有两个脉冲；其中，所述第二片选时钟偶信号中第一个脉冲的上升沿用于产生所述第二目标指令信号的上升沿，所述第二片选时钟偶信号中第二个脉冲的上升沿用于产生所述第二目标指令信号的下降沿。
  21. 一种半导体存储器，包括如权利要求1至20任一项所述的信号采样电路。
  22. 根据权利要求21所述的半导体存储器，其中，所述半导体存储器为动态随机存取存储器DRAM芯片，且符合DDR5内存规格。
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