WO2023178805A1 - 一种信号采样电路以及半导体存储器 - Google Patents

一种信号采样电路以及半导体存储器 Download PDF

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WO2023178805A1
WO2023178805A1 PCT/CN2022/091428 CN2022091428W WO2023178805A1 WO 2023178805 A1 WO2023178805 A1 WO 2023178805A1 CN 2022091428 W CN2022091428 W CN 2022091428W WO 2023178805 A1 WO2023178805 A1 WO 2023178805A1
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signal
clock
chip select
odd
sampling circuit
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PCT/CN2022/091428
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English (en)
French (fr)
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黄泽群
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长鑫存储技术有限公司
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Priority to EP22932862.0A priority Critical patent/EP4328916A4/en
Priority to US17/934,185 priority patent/US12080335B2/en
Publication of WO2023178805A1 publication Critical patent/WO2023178805A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the field of integrated circuit technology, and in particular, to a signal sampling circuit and a semiconductor memory.
  • DDR Double Data Rate
  • the command address (Command/Address, CMD/ADD or CA for short) signal can be used as an address for sampling and as an instruction for sampling and decoding.
  • the chip select signals used by the two have different pulse widths, and their corresponding operating functions are also different; however, in the existing instruction decoding scheme These two instructions are prone to confusion, leading to decoding errors.
  • the present disclosure provides a signal sampling circuit and a semiconductor memory that can distinguish between two instructions, 2T CMD and NT ODT CMD, and perform accurate decoding, thereby avoiding the problem of incorrect operation due to instruction decoding errors.
  • embodiments of the present disclosure provide a signal sampling circuit, which includes a signal input circuit, a first instruction sampling circuit, a second instruction sampling circuit and an instruction decoding circuit; wherein,
  • the signal input circuit is used to determine the instruction signal to be processed and the chip select signal to be processed according to the first clock signal, the first chip select signal and the first command address signal; wherein the clock cycle of the first clock signal is Twice the default clock period;
  • the first instruction sampling circuit is configured to perform two-stage sampling on the chip select signal to be processed according to the first clock signal when the pulse width of the first chip select signal is the preset clock cycle. Logic operation processing to obtain the first chip select clock signal;
  • the second instruction sampling circuit is configured to perform two operations on the chip select signal to be processed according to the first clock signal when the pulse width of the first chip select signal is twice the preset clock cycle. stage sampling and logical operation processing to obtain the second chip select clock signal;
  • the instruction decoding circuit is used to decode and sample the instruction signal to be processed according to the chip select signal to be processed and the first chip select clock signal to obtain a target instruction signal; or, according to the The chip select signal to be processed and the second chip select clock signal decode and sample the instruction signal to be processed to obtain a target instruction signal.
  • an embodiment of the present disclosure provides a semiconductor memory, which includes the signal sampling circuit as described in the first aspect.
  • Embodiments of the present disclosure provide a signal sampling circuit and a semiconductor memory. Based on the signal sampling circuit, when the pulse width of the first chip select signal is different, according to the obtained first chip select clock signal and the second chip select clock signal, the two instructions 2T CMD and NT ODT CMD can be correctly distinguished and decoded accurately without affecting each other, thereby avoiding the problem of instruction decoding errors and incorrect operations.
  • Figure 1 is a schematic diagram of the signal timing of the two clock cycle commands
  • Figure 2 is a schematic structural diagram of a signal sampling circuit
  • Figure 3 is a schematic structural diagram of an instruction decoder
  • Figure 4 is a comparison diagram of two chip select signals with different pulse widths
  • Figure 5A is a signal timing diagram of a signal sampling circuit
  • Figure 5B is a signal timing diagram of another signal sampling circuit
  • Figure 6 is a schematic structural diagram of a signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram of another signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 8A is a schematic structural diagram of a first decoding sampling circuit provided by an embodiment of the present disclosure.
  • Figure 8B is a schematic structural diagram of a second decoding sampling circuit provided by an embodiment of the present disclosure.
  • Figure 9 is a detailed structural diagram of a signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 10 is a signal timing diagram of a signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 11 is a signal timing diagram of another signal sampling circuit provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first ⁇ second ⁇ third” Where permitted, the specific order or sequence may be interchanged so that the embodiments of the disclosure described herein can be practiced in an order other than that illustrated or described herein.
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • Command address input (Command/Address, CMD/ADD or CA for short)
  • Termination resistor On-Die Termination, ODT
  • DFF Data Flip-Flop or Delay Flip-Flop
  • NDT CMD Non-Target On-Die Termination Command
  • CA can be used as an address for sampling and as an instruction for sampling and decoding.
  • CA here is the collective name for various command address signals of DRAM, which can include row address strobe (RAS), column address strobe (Column Address Strobe, CAS), and write command (Write, WE).
  • RAS row address strobe
  • CAS Column address strobe
  • WE write command
  • activation command active, ACT
  • other command signals and may also include address signals from A13 to A0, etc.
  • the command address signal includes several address signals, which may be determined according to the specifications of the DRAM, and the embodiment of the present disclosure does not make any limitation.
  • FIG. 1 shows the signal timing diagram of the two clock cycle commands.
  • CK_t and CK_c are a pair of input complementary clock signals
  • CA[13:0] is the CA signal input
  • CMD is the command signal obtained after decoding the CA signal
  • CS_n is the chip select signal indicating that the CA signal is valid.
  • CA[13:0] is a signal that lasts for two clock cycles.
  • the CA of the first clock cycle and the CA of the second clock cycle need to be sampled as address signals.
  • the CA of the first clock cycle CA also needs to be sampled and decoded as a command signal.
  • CA[4:0] of the first clock cycle is sampled and decoded as the command signal.
  • the signal sampling circuit 10 may include a first receiver 101, a second receiver 102, a third receiver 103, a first sampling circuit 104, a second sampling circuit 105, a third sampling circuit 106, Four sampling circuits 107, fifth sampling circuit 108, sixth sampling circuit 109, first buffer 110, first AND gate 111, second buffer 112, second AND gate 113, instruction decoder 114 and OR gate 115 .
  • the first sampling circuit 104, the second sampling circuit 105, the fifth sampling circuit 108 and the sixth sampling circuit 109 may be composed of D-type flip-flops
  • the third sampling circuit 106 and the fourth sampling circuit 107 may be composed of D-type flip-flops. Composed of flip-flop and inverter.
  • the input signal of the first receiver 101 is the initial command address signal (represented by CA[13:0]) and the reference signal (represented by VREFCA), and the output signal is the first command address signal (represented by CA) ;
  • the input signal of the second receiver 102 is the initial chip select signal (represented by CS_n) and the reference signal (represented by VREFCA), and the output signal is the first chip select signal (represented by PCS);
  • the input signal of the third receiver 103 is a pair of input complementary clock signals (represented by CK_t and CK_c), and the output signal is the first clock even signal (represented by PCLK_E) and the first clock odd signal (represented by PCLK_O). It should be noted that the third receiver 103 also has frequency division processing capability.
  • the respective frequencies of the PCLK_E signal and the PCLK_O signal are half of the frequency of the CK_t signal or the CK_c signal, that is, the respective clocks of the PCLK_E signal and the PCLK_O signal.
  • the period is twice the clock period of the CK_t signal or CK_c signal, and the phase difference is 180 degrees.
  • CA[13:0] here represents a group of signals, the combined collective name of CA[0], CA[1],..., CA[13].
  • the first receiver 101 actually includes 14 receiving circuits, as well as output lines, and even the subsequent sampling circuit. There are also 14 long wiring paths, and CA[0], CA[1],..., CA[13] has a one-to-one correspondence.
  • the PCLK_E signal is used to sample the first command address signal to obtain a second address even signal (represented by CA[13:0]_1T_E), and the second address even signal includes the instruction to be processed.
  • Even signal represented by CA[4:0]_1T_E
  • the PCLK_O signal is used to sample the first command address signal to obtain a second address odd signal (represented by CA[13:0]_1T_O ), and the second address odd signal includes the instruction odd signal to be processed (represented by CA[4:0]_1T_O);
  • the PCLK_E signal is used to sample and invert the first chip select signal, and we obtain The chip select even signal to be processed (represented by PCS_E);
  • the fourth sampling circuit 107 the PCLK_O signal is used to sample and invert the first chip select signal to obtain the odd chip select signal to be processed (represented by PCS_O); and then Through the fifth sampling circuit 108,
  • the instruction decoder 114 it can also be called an instruction decoding flip-flop, represented by CMD DEC DFF.
  • the instruction decoder may include a first instruction decoding circuit a and a second instruction decoding circuit b. Both the first instruction decoding circuit a and the second instruction decoding circuit b are composed of two inputs. It consists of logic components such as NAND gate, three-input NAND gate, two-input NOR gate, D-type flip-flop and AND gate. The details are shown in Figure 3.
  • the initial clock signal (represented by CK_t/CK_c) is divided into PCLK_E signal and PCLK_O signal after the receiver, and then the CA signal is sampled. Since 2T CMD in DDR5 needs to use the CA signal of the first clock cycle as the instruction and address, and then use the CA signal of the second clock cycle as the remaining address. Therefore, the DDR5 design requires two levels of sampling, which are then used as addresses for two clock cycles respectively. For instructions, the first-level CA signal needs to be used for combinational logic, and then the second-level sampling is performed to align with the sampling address signal of the second cycle. Since the command signal needs to maintain a pulse width, the CMD_E/O signal can be generated by using the PCS_OD/ED signal obtained after two-stage sampling to perform an AND logic operation, and then the CMD signal can be obtained after an OR operation.
  • the 2T CMD signal can also be called the 2-cycle Command signal.
  • the corresponding chip select signal is represented by CS0_n, and its pulse width is the preset clock cycle
  • the corresponding chip select signal is represented by CS1_n, and its pulse width is twice the preset clock period. The decoding timing of these two signals will be described below in conjunction with the signal sampling circuit 10.
  • the first command address signal is represented by CA, and CA can include Cy, Cz, C0, C1, C2 and C3;
  • the initial chip select signal is represented by CS_n, and the first chip select signal is represented by PCS , the CS_n signal is an active low-level pulse signal, and is used to represent the signal that the target chip is selected;
  • the initial clock signal is represented by CK_t, the clock period of the CK_t signal is equal to the preset clock period, that is, 1Tck, and the PCLK_E signal and PCLK_O signal
  • the clock cycles are twice the preset clock cycle, that is, 2Tck.
  • the pulse width of the PCS signal at this time is the preset clock cycle. After sampling and inverting the PCS signal using the rising edge of the PCLK_E signal, the PCS_E signal is active at high level.
  • the pulse signal, and the pulse width is twice the preset clock period; after using the rising edge of the PCLK_O signal to sample and invert the PCS signal, the PCS_O signal is obtained as a low-level signal; at the same time, the PCLK_O signal is used to After sampling processing, the PCS_OD signal is obtained as a high-level pulse signal, and the pulse width is twice the preset clock period; however, after sampling the PCS_O signal using the PCLK_E signal, the PCS_ED signal is obtained as a low-level signal; After logical operations such as the first buffer 110, the first AND gate 111, the second buffer 112, and the second AND gate 113, it is obtained that the CS_CLK_E signal is a low-level signal and the CS_CLK_O signal is a high-level active pulse signal.
  • the pulse width is a preset clock cycle; then use the rising edge of the PCLK_E signal to sample the CA signal, and get the CA[4:0]_1T_E signal including C0 and C2; since the CS_CLK_E signal and PCS_ED signal are low-level signals , then the CMD_E signal obtained by decoding is also a low-level signal; only after using the CS_CLK_O signal, PCS_OD signal and CA[4:0]_1T_E signal for sampling and decoding processing, the CMD_O signal obtained is the CMD signal, and The CMD signal is an active high-level pulse signal.
  • the pulse width of the PCS signal at this time is twice the preset clock period.
  • PCS_E is obtained /PCS_O signals are high-level active pulse signals, and the pulse width is twice the preset clock cycle, but the PCS_O signal is delayed by one preset clock cycle compared to the PCS_E signal;
  • the PCS_OD/PCS_ED signals obtained after further sampling and processing are also Both are high-level pulse signals, and the pulse width is twice the preset clock cycle, but the PCS_ED signal is delayed by one preset clock cycle compared to the PCS_OD signal; then the CS_CLK_O/CS_CLK_E signals obtained through logical operations are also high.
  • a pulse signal with a valid level, and the pulse width is a preset clock cycle, but the CS_CLK_E signal is delayed by a preset clock cycle compared to the CS_CLK_O signal.
  • the CA[4:0]_1T_E signal includes C0 and C2
  • the CA[4:0]_1T_O signal includes C1 and C3. At this time, not only the C0 sampled by the CS_CLK_O signal needs to be decoded, but also the C1 sampled by the CS_CLK_E signal.
  • the signal sampling circuit includes a signal input circuit, a first instruction sampling circuit, a second instruction sampling circuit and an instruction decoding circuit; wherein the signal input circuit is used according to The first clock signal, the first chip select signal and the first command address signal determine the instruction signal to be processed and the chip select signal to be processed.
  • the clock period of the first clock signal is twice the preset clock period;
  • the first instruction sampling circuit used when the pulse width of the first chip select signal is the preset clock cycle, perform two-level sampling and logical operation processing on the chip select signal to be processed according to the first clock signal, and obtain the first chip select clock signal;
  • the second instruction sampling A circuit for, when the pulse width of the first chip select signal is twice the preset clock period, perform two-level sampling and logical operation processing on the chip select signal to be processed based on the first clock signal to obtain the second chip select clock signal;
  • the instruction decoding circuit is used to decode and sample the instruction signal to be processed according to the chip select signal to be processed and the first chip select clock signal to obtain the target instruction signal; or, to obtain the target instruction signal according to the chip select signal to be processed and the second chip select clock signal.
  • the signal is decoded and sampled to obtain the target instruction signal.
  • the 2T CMD and NT ODT CMD can be correctly distinguished.
  • the two instructions are decoded accurately and do not affect each other, thereby avoiding the problem of instruction decoding errors and incorrect operations.
  • FIG. 6 shows a schematic structural diagram of a signal sampling circuit provided by an embodiment of the present disclosure.
  • the signal sampling circuit 60 may include a signal input circuit 61, a first instruction sampling circuit 62, a second instruction sampling circuit 63 and an instruction decoding circuit 64; wherein,
  • the signal input circuit 61 is used to determine the instruction signal to be processed and the chip select signal to be processed according to the first clock signal, the first chip select signal and the first command address signal; wherein the clock cycle of the first clock signal is the preset clock twice the period;
  • the first instruction sampling circuit 62 is used to perform two-level sampling and logical operation processing on the chip select signal to be processed according to the first clock signal when the pulse width of the first chip select signal is a preset clock period to obtain the first chip select clock. Signal;
  • the second instruction sampling circuit 63 is used to perform two-level sampling and logical operation processing on the chip select signal to be processed according to the first clock signal when the pulse width of the first chip select signal is twice the preset clock period to obtain the second Chip select clock signal;
  • the instruction decoding circuit 64 is used to decode and sample the instruction signal to be processed according to the chip select signal to be processed and the first chip select clock signal to obtain the target instruction signal; or, to obtain the target instruction signal according to the chip select signal to be processed and the second chip select signal.
  • the clock signal is decoded and sampled on the instruction signal to be processed to obtain the target instruction signal.
  • the signal sampling circuit 60 is used in the sampling and decoding process of address and instruction signals, and can be applied in various circuit scenarios.
  • the embodiments of the present disclosure will be explained and described later by using the CA signal in the DRAM chip to sample and decode addresses and instructions, but this does not constitute a relevant limitation.
  • the signal sampling circuit 60 can be applied to the 2T CMD scenario.
  • the first command address signal here includes a valid signal for two preset clock cycles, and the valid pulse of the target command signal (represented by CMD) also lasts for two preset clock cycles.
  • the CS_n signal is an active low-level pulse signal, and the CA[13:0] signals corresponding to the current clock cycle and the adjacent next clock cycle are both valid (Valid); among them, the current clock cycle is The CS_n signal is the clock period corresponding to the low-level pulse.
  • the preset clock cycle here refers to the clock cycle of the CK_t/CK_c signal
  • the CS_n signal represents the signal that the target chip is selected
  • CA[13:0] is not a signal, but represents A set of command address signals, namely CA[0] ⁇ CA[13], a total of 14 signals.
  • the target command signal can be the Command signal in the DDR5 DRAM chip. Since the effective pulse of this signal lasts for two clock cycles, it can be referred to as the 2T CMD signal here; where, the Command signal can Including read command signal, write command signal, refresh command signal, precharge command signal and activation command signal, etc.; alternatively, the target command signal can also be the Non-Target ODT Command signal in the DDR5DRAM chip, which can be referred to as the NT ODT CMD signal. .
  • the embodiment of the present disclosure adds a first instruction sampling circuit 62 and a second instruction sampling circuit 63. Since the two use The pulse width of the first chip select signal is different, and different first chip select clock signals and second chip select clock signals can be output; in this way, for the 2T CMD signal, the target command signal obtained by using the first chip select clock signal is A valid signal, while the target command signal obtained by using the second chip select clock signal is an invalid signal (i.e., a low level signal); for the NT ODT CMD signal, the target command signal obtained by using the first chip select clock signal is an invalid signal. (i.e., low level signal), and the target command signal obtained by using the second chip select clock signal is a valid signal, so that the two command signals of 2T CMD and NT ODT CMD can be correctly distinguished and accurately decoded.
  • the target command signal includes a pulse, and the pulse width of the pulse is twice the preset clock cycle;
  • the first chip select clock signal When the pulse width of the first chip select signal is the preset clock cycle, the first chip select clock signal includes two pulses, and the pulse width of each pulse is the preset clock cycle, and the second chip select clock signal maintains The level state remains unchanged; among them, the rising edge of the first pulse in the first chip select clock signal is used to generate the rising edge of the target command signal, and the rising edge of the second pulse in the first chip select clock signal is used to generate the target command signal. falling edge.
  • the pulse width of the first chip select signal is the preset clock cycle
  • the first chip select clock signal obtained according to the first instruction sampling circuit 62 is a valid signal
  • the first chip select clock signal obtained according to the second instruction sampling circuit 63 is The second chip select clock signal is an invalid signal.
  • the target command signal is the 2T CMD signal; and the rising edge of the target command signal is generated by the rising edge of the first pulse in the first chip select clock signal, and the falling edge of the target command signal is generated by the rising edge of the first pulse in the first chip select clock signal. The rising edge of the second pulse in the chip select clock signal is generated.
  • the pulse width is twice the preset clock period
  • the pulse width and twice the preset clock period specifically refers to the pulse width and twice the preset clock period. The deviation between them is within the preset accuracy range, and the pulse width descriptions of other signals in this disclosure can also be understood by reference.
  • the target command signal includes a pulse, and the pulse width of the pulse is twice the preset clock cycle;
  • the pulse width of the first chip select signal is twice the preset clock period
  • the first chip select clock signal maintains the level state unchanged
  • the second chip select clock signal includes two pulses, and each pulse The pulse width is the preset clock cycle; among them, the rising edge of the first pulse in the second chip select clock signal is used to generate the rising edge of the target command signal, and the rising edge of the second pulse in the second chip select clock signal is used to generate The falling edge of the target command signal.
  • the pulse width of the first chip select signal is twice the preset clock period
  • the first chip select clock signal obtained by the first instruction sampling circuit 62 is an invalid signal at this time
  • the first chip select clock signal obtained by the second instruction sampling circuit 62 is an invalid signal.
  • the second chip select clock signal obtained by circuit 63 is a valid signal.
  • the target command signal is the NT ODT CMD signal; and the rising edge of the target command signal is generated by the rising edge of the first pulse in the second chip select clock signal, and the falling edge of the target command signal is generated by The rising edge of the second pulse in the second chip select clock signal is generated.
  • the two command signals 2T CMD and NT ODT CMD can also be used to generate the rise of the target command signal edge and falling edge, so that the pulse width of the target command signal is always twice the preset clock cycle within the preset accuracy range, avoiding the problem of uncertainty in the pulse width of the target command signal.
  • the signal input circuit 61 may include a receiving circuit 611 and an input sampling circuit 612; wherein,
  • the receiving circuit 611 is used to receive the initial command address signal, the initial chip select signal and the initial clock signal, and output the first command address signal, the first chip select signal and the first clock signal;
  • the input sampling circuit 612 is used to sample the first chip select signal and the first command address signal according to the first clock signal to obtain the chip select signal to be processed and the command signal to be processed.
  • the clock period of the initial clock signal is a preset clock period
  • the clock period of the first clock signal is twice the preset clock period. That is to say, the first clock signal is obtained by dividing the initial clock signal.
  • the receiving circuit 611 may include a first receiving circuit 451, a second receiving circuit 452 and a third receiving circuit 453; wherein,
  • the first receiving circuit 451 is used to receive the initial command address signal and output the first command address signal
  • the second receiving circuit 452 is used to receive the initial chip select signal and output the first chip select signal
  • the third receiving circuit 453 is used to receive the initial clock signal, perform frequency division processing on the initial clock signal, and output the first odd clock signal and the first even clock signal.
  • the first clock signal may be composed of a first clock odd signal and a first clock even signal, the respective clock periods of the first clock odd signal and the first clock even signal are twice the preset clock period, and the The phase difference between the first clock odd signal and the first clock even signal is 180 degrees.
  • the initial command address signal here can be represented by CA[13:0], and the first command address signal can be represented by CA; the initial chip select signal can be represented by CS_n, and the first chip select signal can be represented by CS_n.
  • the selection signal is represented by PCS; the initial clock signal can be represented by CK_t and CK_c, the first clock even signal is represented by PCLK_E, and the first clock odd signal is represented by PCLK_O.
  • the clock period of the PCLK_E signal is twice the preset clock period
  • the clock period of the PCLK_O signal is also twice the preset clock period
  • the phase difference between the PCLK_E signal and the PCLK_O signal is 180 degrees.
  • the embodiment of the present disclosure not only needs to use the first clock signal to sample the first command address signal, but also needs to use the first clock signal to sample the first chip select signal. Therefore, in some embodiments, as shown in Figure 7, the input sampling circuit 612 may include a first sampling circuit 461, a second sampling circuit 462, a third sampling circuit 463 and a fourth sampling circuit 464; wherein,
  • the first sampling circuit 461 is used to sample the first command address signal according to the first clock signal to obtain the command signal to be processed;
  • the second sampling circuit 462 is used to sample the first command address signal according to the first clock odd signal to obtain the instruction odd signal to be processed;
  • the third sampling circuit 463 is used to sample and invert the first chip select signal according to the first clock even signal to obtain the chip select even signal to be processed;
  • the fourth sampling circuit 464 is used to sample and invert the first chip select signal according to the first clock odd signal to obtain the chip select odd signal to be processed.
  • the instruction signal to be processed may be composed of an even instruction signal to be processed and an odd instruction signal to be processed
  • the chip select signal to be processed may be composed of a chip select even signal to be processed and an odd chip select signal to be processed.
  • the first sampling circuit 461 may include a first flip-flop, and the input terminal of the first flip-flop is connected to the first command address signal, and the clock terminal of the first flip-flop is connected to the first command address signal.
  • the first clock signal is connected, and the output end of the first flip-flop is used to output the instruction signal to be processed;
  • the second sampling circuit 462 may include a second flip-flop, and the input end of the second flip-flop is connected to the first command address signal.
  • the third sampling circuit 463 may include a third flip-flop and a first inverter, And the input terminal of the third flip-flop is connected to the first chip select signal, the clock terminal of the third flip-flop is connected to the first clock even signal, the output terminal of the third flip-flop is connected to the input terminal of the first inverter, and the third flip-flop is connected to the input terminal of the first inverter.
  • the fourth sampling circuit 464 may include a fourth flip-flop and a second inverter, and the input end of the fourth flip-flop is connected to the first chip select signal. , the clock terminal of the fourth flip-flop is connected to the first clock odd signal, the output terminal of the fourth flip-flop is connected to the input terminal of the second inverter, and the output terminal of the second inverter is used to output the chip select odd signal to be processed. Signal.
  • the command address signal to be processed may be composed of an even signal of the command address to be processed and an odd signal of the command address to be processed
  • the instruction signal to be processed may be an even signal of the instruction to be processed. It is composed of the odd signal of the instruction to be processed.
  • the command address even signal to be processed includes the instruction even signal to be processed, and the command address even signal to be processed is represented by CA[13:0]_1T_E, and the instruction even signal to be processed is represented by CA[4:0]_1T_E; the command to be processed is
  • the odd address signal includes the odd signal of the instruction to be processed, and the odd signal of the command address to be processed is represented by CA[13:0]_1T_O, and the odd signal of the instruction to be processed is represented by CA[4:0]_1T_O.
  • CA[13:0]_1T_E is not a signal, but represents a set of command address signals, namely CA[0]_1T_E ⁇ CA[13]_1T_E, and CA[4:0] _1T_E represents five signals including CA[0]_1T_E ⁇ CA[4]_1T_E in this group of signals;
  • CA[13:0]_1T_O is not a signal, but represents a group of command address signals, namely CA[ 0]_1T_O ⁇ CA[13]_1T_O, and CA[4:0]_1T_O represents five signals including CA[0]_1T_O ⁇ CA[4]_1T_O in this group of signals.
  • the chip select signal to be processed may be composed of an even chip select signal to be processed and an odd chip select signal to be processed.
  • the first chip select signal is represented by PCS
  • the even chip select signal to be processed is represented by PCS_E
  • the odd chip select signal to be processed is represented by PCS_O.
  • PCS is an active low-level pulse signal
  • the PCS_O signal or PCS_E signal can be turned into a high-level active pulse signal for subsequent logic operations.
  • the third sampling circuit 463 and the fourth sampling circuit 464 may not need to set the first inverter and the second inverter, and then the subsequent logical operations need to be adjusted accordingly, thereby also The same effect can be achieved.
  • the first flip-flop, the second flip-flop, the third flip-flop and the fourth flip-flop may all be D-type flip-flops.
  • the clock terminal of the D-type flip-flop is connected to the PCLK_E signal
  • the input terminal of the D-type flip-flop is connected to the CA signal
  • the D-type flip-flop is connected to the CA signal.
  • the output end of the device is used to output the CA[13:0]_1T_E signal
  • the CA[4:0]_1T_E signal constitutes the instruction signal to be processed.
  • the clock terminal of the D-type flip-flop is connected to the PCLK_O signal
  • the input terminal of the D-type flip-flop is connected to the CA signal
  • the output terminal of the D-type flip-flop is used to output the CA[13:0]_1T_O signal
  • the CA[4:0]_1T_O signal constitutes the odd signal of the instruction to be processed.
  • first sampling circuit 461 or the second sampling circuit 462 since CA is not a signal, but a collective name for a group of signals; then multiple first sampling circuits 461 can be included here, are respectively used to receive each CA signal in this group of CA signals; similarly, multiple second sampling circuits 462 may also be included, respectively used to receive each CA signal in this group of CA signals; in the figure, only A first sampling circuit 461 and a second sampling circuit 462 are shown as an illustration.
  • the PCLK_E signal, PCLK_O signal, PCS_E signal, PCS_O signal, CA[4:0]_1T_E signal and CA[4:0]_1T_O signal can be obtained; and then further use different
  • the first chip select signal of the pulse width and the different command sampling circuits can obtain different first chip select clock signals and second chip select clock signals, so that Correctly distinguish between the two instructions 2T CMD and NT ODT CMD, and decode them accurately without affecting each other.
  • the signal sampling circuit 60 may also include a first buffer 65 and a second buffer 66; wherein,
  • the first buffer 65 is used to delay the first clock even signal to obtain the first clock delayed even signal
  • the second buffer 66 is used to delay the first clock odd signal to obtain the first clock delayed odd signal.
  • the first clock even signal and the first clock odd signal need to be delayed before being input to the first command sampling circuit 62 and the second command sampling circuit 63 .
  • the first clock even signal is represented by PCLK_E
  • the first clock delayed even signal is represented by PCLK_EE
  • the first clock odd signal is represented by PCLK_O
  • the first clock delayed odd signal is represented by PCLK_OO.
  • the buffer whether it is the first buffer 65 or the second buffer 66, it not only has a delay function, but also has the function of enhancing the signal driving capability. Specifically, for the first clock-delayed even signal and the first clock-delayed even signal, the first clock-delayed even signal not only has a time delay compared to the first clock-delayed even signal, but also has a driving capability of the first clock-delayed even signal. Stronger; similarly, for the first clock delayed odd signal and the first clock odd signal, the first clock delayed odd signal has a delay compared to the first clock odd signal, and the first clock delayed odd signal Stronger driving ability.
  • the number of buffers is not limited to one, and may also be multiple.
  • the specific quantity can be set according to actual needs and is not specifically limited.
  • the first instruction sampling circuit 62 may include a first logic circuit 621 and a second logic circuit 622; wherein,
  • the first logic circuit 621 is used to receive the first clock delayed odd signal and the chip select even signal to be processed, and use the first clock delayed odd signal to perform two-level sampling and logical operations on the chip select even signal to be processed, to obtain the first Chip select clock odd signal;
  • the second logic circuit 622 is used to receive the first clock delayed even signal and the chip select odd signal to be processed, and use the first clock delayed even signal to perform two-level sampling and logical operations on the chip select odd signal to be processed to obtain the first Chip select clock even signal.
  • the first chip select clock signal may be composed of a first chip select clock even signal and a first chip select clock odd signal.
  • the even signal of the first chip select clock can be represented by 2T_CLK_E
  • the odd signal of the first chip select clock can be represented by 2T_CLK_O.
  • the first logic circuit 621 may include a fifth sampling circuit 465, a first NOR gate 466, a first NOT gate 467, a sixth sampling circuit 468, a first OR Gate 469 and the first AND gate 470;
  • the fifth sampling circuit 465 is used to use the first clock delayed odd signal to sample and invert the chip select even signal to be processed to obtain the first intermediate sampled odd signal;
  • the first NOR gate 466 is used to perform a NOR operation on the first intermediate sampled odd signal and the chip select odd signal to be processed to obtain the second intermediate sampled odd signal;
  • the first NOT gate 467 is used to perform a NOT operation on the first clock delayed odd signal to obtain the first inverted clock odd signal;
  • the sixth sampling circuit 468 is used to perform sampling processing on the second intermediate sampling odd signal using the first inverted clock odd signal to obtain a third intermediate sampling odd signal;
  • the first OR gate 469 is used to perform an OR operation on the second intermediate sampled odd signal and the third intermediate sampled odd signal to obtain the fourth intermediate sampled odd signal;
  • the first AND gate 470 is used to perform an AND operation on the fourth intermediate sample odd signal and the first clock delay odd signal to obtain the first chip select clock odd signal.
  • the fifth sampling circuit 465 may be composed of a fifth flip-flop and a third inverter
  • the sixth sampling circuit 468 may be composed of a sixth flip-flop; wherein, the fifth sampling circuit 465 may be composed of a fifth flip-flop and a third inverter.
  • Both the fifth flip-flop and the sixth flip-flop can be D-type flip-flops.
  • the third inverter may not be provided, and subsequent logical operations need to be adjusted accordingly, such as adjusting the first NOR gate 466 to an OR gate. , thus achieving the same effect.
  • the input terminal of the fifth flip-flop is connected to the chip select even signal to be processed, the clock terminal of the fifth flip-flop is connected to the first clock delay odd signal, and the output terminal of the fifth flip-flop is connected to The input terminal of the third inverter is connected, and the output terminal of the third inverter is used to output the first intermediate sampling odd signal; an input terminal of the first NOR gate 466 is connected to the output terminal of the third inverter, and the The other input terminal of a NOR gate 466 is used to receive the chip select odd signal to be processed, the output terminal of the first NOR gate 466 is used to output the second intermediate sample odd signal, and the output terminal of the first NOR gate 466 is ANDed.
  • the input terminal of the sixth flip-flop is connected, and the clock terminal of the sixth flip-flop is connected with the output terminal of the first NOT gate 467.
  • the input terminal of the first NOT gate 467 is used to receive the first clock delay odd signal; the sixth flip-flop
  • the output terminal is used to output the third intermediate sample odd signal, and the output terminal of the sixth flip-flop is connected to one input terminal of the first OR gate 469, and the other input terminal of the first OR gate 469 is used to receive the second intermediate sample.
  • the output terminal of the first OR gate 469 is used to output the fourth intermediate sample odd signal, and the output terminal of the first OR gate 469 is connected to one input terminal of the first AND gate 470, and the other input terminal of the first AND gate 470 The input terminal is used to receive the first clock delay odd signal, and the output terminal of the first AND gate 470 is used to output the first chip select clock odd signal.
  • the chip select even signal to be processed is represented by PCS_E; the first intermediate sampled odd signal output through the fifth sampling circuit 465 can be represented by PCSB_O, and is output through the first NOR gate 466
  • the second intermediate sampling odd signal of can be represented by PCS_OEN1
  • the third intermediate sampling odd signal output by the sixth sampling circuit 468 can be represented by PCS_OEN2
  • the fourth intermediate sampling odd signal output by the first OR gate 469 can be represented by PCS_OEN
  • the odd signal of the first chip select clock output through the first AND gate 470 can be represented by 2T_CLK_O.
  • the second logic circuit 622 may include a seventh sampling circuit 471, a second NOR gate 472, a second NOT gate 473, an eighth sampling circuit 474, a second OR gate 475 and second AND gate 476;
  • the seventh sampling circuit 471 is used to use the first clock delayed even signal to sample and invert the chip select odd signal to be processed to obtain the first intermediate sampled even signal;
  • the second NOR gate 472 is used to perform a NOR operation on the first intermediate sampled even signal and the chip select even signal to be processed to obtain the second intermediate sampled even signal;
  • the second NOT gate 473 is used to perform a NOT operation on the first clock delay even signal to obtain the first inverted clock even signal;
  • the eighth sampling circuit 474 is used to perform sampling processing on the second intermediate sampled even signal using the first inverted clock even signal to obtain a third intermediate sampled even signal;
  • the second OR gate 475 is used to perform an OR operation on the second intermediate sampled even signal and the third intermediate sampled even signal to obtain a fourth intermediate sampled even signal;
  • the second AND gate 476 is used to perform an AND operation on the fourth intermediate sample even signal and the first clock delay even signal to obtain the first chip select clock even signal.
  • the seventh sampling circuit 471 may be composed of a seventh flip-flop and a fourth inverter
  • the eighth sampling circuit 474 may be composed of an eighth flip-flop; wherein, the Both the seventh flip-flop and the eighth flip-flop can be D-type flip-flops.
  • the fourth inverter may not be provided, and subsequent logical operations need to be adjusted accordingly, for example, the second NOR gate 472 may be adjusted to an OR gate. , thus achieving the same effect.
  • the input terminal of the seventh flip-flop is connected to the chip select odd signal to be processed, the clock terminal of the seventh flip-flop is connected to the first clock delay even signal, and the output terminal of the seventh flip-flop is connected to The input terminal of the fourth inverter is connected, and the output terminal of the fourth inverter is used to output the first intermediate sampling even signal; an input terminal of the second NOR gate 472 is connected to the output terminal of the fourth inverter, and the first The other input terminal of the two NOR gate 472 is used to receive the chip select even signal to be processed, the output terminal of the second NOR gate 472 is used to output the second intermediate sample even signal, and the output terminal of the second NOR gate 472 is AND The input terminal of the eighth flip-flop is connected, the clock terminal of the eighth flip-flop is connected to the output terminal of the second NOT gate 473, and the input terminal of the second NOT gate 473 is used to receive the first clock delay even signal; the eighth flip-flop The output terminal is used to output the third intermediate sample even signal
  • the output end of the second OR gate 475 is used to output the fourth intermediate sample even signal, and the output end of the second OR gate 475 is connected to one input end of the second AND gate 476, and the other end of the second AND gate 476
  • the input terminal is used to receive the first clock delay even signal, and the output terminal of the second AND gate 476 is used to output the first chip select clock even signal.
  • the chip select odd signal to be processed is represented by PCS_O; the first intermediate sampled even signal output through the seventh sampling circuit 471 can be represented by PCSB_E, and is output through the second NOR gate 472
  • the second intermediate sampled even signal of can be represented by PCS_EEN1
  • the third intermediate sampled even signal output by the eighth sampling circuit 474 can be represented by PCS_EEN2
  • the fourth intermediate sampled even signal output by the second OR gate 475 can be represented by PCS_EEN
  • the first chip select clock even signal output through the second AND gate 476 can be represented by 2T_CLK_E.
  • the fifth sampling circuit 465 can be regarded as a rising edge sampling circuit, that is, the rising edge of the odd signal is delayed by the first clock to perform sampling processing; while the first NOT gate 467 and the sixth The sampling circuit 468 can be regarded as a falling edge sampling circuit, that is, the falling edge of the first clock delay odd signal is used for sampling processing; for the second logic circuit 622, the seventh sampling circuit 471 can be regarded as a rising edge sampling circuit, that is, The first clock is used to delay the rising edge of the even signal for sampling processing; the second NOT gate 473 and the eighth sampling circuit 474 can be regarded as falling edge sampling circuits, that is, the first clock is used to delay the falling edge of the even signal for sampling processing. .
  • the PCS_E/PCS_O signal is continuously sampled by using a first-level rising edge sampling circuit and a first-level falling edge sampling circuit, and then increasing the high-level pulse width of the chip select signal through OR logic, thereby A 2T_CLK_O/2T_CLK_E signal with two pulses can be generated.
  • the first OR gate 469 and the second OR gate 475 both have the function of broadening the signal pulse width.
  • the pulse width of the PCS_OEN1 signal is twice the preset clock period
  • the pulse width of the PCS_OEN2 signal is also twice the preset clock period, but is delayed by one preset clock compared to the PCS_OEN1 signal.
  • the PCS_OEN1 signal and the PCS_OEN2 signal are ORed through the first OR gate 469 to obtain the PCS_OEN signal, and the pulse width is three times the preset clock cycle; then the PCS_OEN signal and the PCLK_OO signal are coupled through the first AND gate 470 By performing an AND operation, a 2T_CLK_O signal with two pulses can be obtained, and the pulse width of each pulse is a preset clock cycle.
  • the second OR gate 475 outputs the PCS_EEN signal, and the pulse width is also three times the preset clock cycle; then the second AND gate 476 performs an AND operation on the PCS_EEN signal and the PCLK_EE signal to obtain a signal with two pulses. 2T_CLK_E signal, and the pulse width of each pulse is a preset clock cycle.
  • the first logic circuit 621 performs two-level sampling and logic operation processing on the PCS_E signal to obtain the 2T_CLK_O signal; through the second logic circuit 622
  • the PCS_O signal undergoes two-level sampling and logical operation processing to obtain the 2T_CLK_E signal; then based on the 2T_CLK_O signal and the 2T_CLK_E signal, the corresponding decoded target command signal is the 2T CMD signal.
  • the second instruction sampling circuit 63 may include a third logic circuit 631 and a fourth logic circuit 632; wherein,
  • the third logic circuit 631 is used to receive the first clock delayed odd signal and the chip select even signal to be processed, and use the first clock delayed odd signal to perform two-level sampling and logical operations on the chip select even signal to be processed, to obtain the second Chip select clock odd signal;
  • the fourth logic circuit 632 is used to receive the first clock delayed even signal and the chip select odd signal to be processed, and use the first clock delayed even signal to perform two-level sampling and logical operations on the chip select odd signal to be processed to obtain the second Chip select clock even signal;
  • the second chip select clock signal may be composed of a second chip select clock even signal and a second chip select clock odd signal.
  • the even signal of the second chip select clock can be represented by NT_CLK_E
  • the odd signal of the second chip select clock can be represented by NT_CLK_O.
  • the third logic circuit 631 may include a ninth sampling circuit 477, a third NOT gate 478, a third NOR gate 479, a fourth NOT gate 480, a tenth sampling circuit circuit 481, the third OR gate 482 and the third AND gate 483; wherein,
  • the ninth sampling circuit 477 is used to use the first clock delayed odd signal to sample and invert the chip select even signal to be processed to obtain the fifth intermediate sampled odd signal;
  • the third NOT gate 478 is used to perform a NOT operation on the chip select odd signal to be processed to obtain the second chip select inverted odd signal;
  • the third NOR gate 479 is used to perform a NOR operation on the fifth intermediate sampled odd signal and the second chip select inverted odd signal to obtain the sixth intermediate sampled odd signal;
  • the fourth NOT gate 480 is used to perform a NOT operation on the first clock delayed odd signal to obtain the second inverted clock odd signal;
  • the tenth sampling circuit 481 is used to perform sampling processing on the sixth intermediate sampling odd signal using the second inverted clock odd signal to obtain the seventh intermediate sampling odd signal;
  • the third OR gate 482 is used to perform an OR operation on the sixth intermediate sample odd signal and the seventh intermediate sample odd signal to obtain the eighth intermediate sample odd signal;
  • the third AND gate 483 is used to perform an AND operation on the eighth intermediate sample odd signal and the first clock delay odd signal to obtain the second chip select clock odd signal.
  • the ninth sampling circuit 477 may be composed of a ninth flip-flop and a fifth inverter, and the tenth sampling circuit 481 may be composed of a tenth flip-flop; wherein, the Both the ninth flip-flop and the tenth flip-flop can be D-type flip-flops.
  • the ninth sampling circuit 477 the fifth inverter does not need to be provided, and the subsequent logical operations need to be adjusted accordingly, for example, the third NOT gate 478 is removed, and the third inverter is replaced.
  • the NOR gate 479 is adjusted to an OR gate, so that the same effect can be achieved.
  • the input terminal of the ninth flip-flop is connected to the chip select even signal to be processed, the clock terminal of the ninth flip-flop is connected to the first clock delay odd signal, and the output terminal of the ninth flip-flop is connected to The input terminal of the fifth inverter is connected, and the output terminal of the fifth inverter is used to output the fifth intermediate sampling odd signal; an input terminal of the third NOR gate 479 is connected to the output terminal of the fifth inverter, and the The other input end of the three NOR gate 479 is connected to the output end of the third NOR gate 478. The input end of the third NOR gate 478 is used to receive the chip select odd signal to be processed.
  • the output end of the third NOR gate 479 is used to The sixth intermediate sample odd signal is output, and the output terminal of the third NOR gate 479 is connected to the input terminal of the tenth flip-flop, the clock terminal of the tenth flip-flop is connected to the output terminal of the fourth NOT gate 480, and the fourth NOT gate 480
  • the input terminal of 480 is used to receive the first clock delay odd signal; the output terminal of the tenth flip-flop is used to output the seventh intermediate sampling odd signal, and the output terminal of the tenth flip-flop is connected to an input terminal of the third OR gate 482 connection, the other input terminal of the third OR gate 482 is used to receive the sixth intermediate sample odd signal, the output terminal of the third OR gate 482 is used to output the eighth intermediate sample odd signal, and the output terminal of the third OR gate 482 is with One input terminal of the third AND gate 483 is connected, the other input terminal of the third AND gate 483 is used to receive the first clock delay odd signal, and the output terminal of the third AND gate 483 is used
  • the chip select even signal to be processed is represented by PCS_E; the fifth intermediate sampled odd signal output through the ninth sampling circuit 477 can be represented by PCSB_O, and is output through the third NOR gate 479
  • the sixth intermediate sampling odd signal can be represented by NT_PCS_OEN1
  • the seventh intermediate sampling odd signal output by the tenth sampling circuit 481 can be represented by NT_PCS_OEN2
  • the eighth intermediate sampling odd signal output by the third OR gate 482 can be represented by NT_PCS_OEN
  • the odd signal of the second chip select clock output through the third AND gate 483 can be represented by NT_CLK_O.
  • the fourth logic circuit 632 may include an eleventh sampling circuit 484, a fifth NOT gate 485, a fourth NOR gate 486, a sixth NOT gate 487, Twelve sampling circuit 488, fourth OR gate 489 and fourth AND gate 490; wherein,
  • the eleventh sampling circuit 484 is used to use the first clock delayed even signal to sample and invert the chip select odd signal to be processed to obtain the fifth intermediate sampled even signal;
  • the fifth NOT gate 485 is used to perform a NOT operation on the chip select even signal to be processed to obtain the second chip select inverted even signal;
  • the fourth NOR gate 486 is used to perform a NOR operation on the fifth intermediate sampled even signal and the second chip select inverted even signal to obtain the sixth intermediate sampled even signal;
  • the sixth NOT gate 487 is used to perform a NOT operation on the first clock delay even signal to obtain the second inverted clock even signal;
  • the twelfth sampling circuit 488 is used to perform sampling processing on the sixth intermediate sampled even signal using the second inverted clock even signal to obtain the seventh intermediate sampled even signal;
  • the fourth OR gate 489 is used to perform an OR operation on the sixth intermediate sampled even signal and the seventh intermediate sampled even signal to obtain the eighth intermediate sampled even signal;
  • the fourth AND gate 490 is used to perform an AND operation on the eighth intermediate sample even signal and the first clock delay even signal to obtain the second chip select clock even signal.
  • the eleventh sampling circuit 484 may be composed of an eleventh flip-flop and a sixth inverter
  • the twelfth sampling circuit 488 may be composed of a twelfth flip-flop. ; Among them, both the eleventh flip-flop and the twelfth flip-flop can be D-type flip-flops.
  • the sixth inverter may not be provided, and subsequent logical operations need to be adjusted accordingly, such as removing the fifth NOT gate 485 and replacing the fifth inverter with the sixth inverter.
  • the four NOR gate 486 is adjusted to an OR gate, so that the same effect can be achieved.
  • the input terminal of the eleventh flip-flop is connected to the chip select odd signal to be processed, the clock terminal of the eleventh flip-flop is connected to the first clock delay even signal, and the The output terminal is connected to the input terminal of the sixth inverter, and the output terminal of the sixth inverter is used to output the fifth intermediate sampling even signal; an input terminal of the fourth NOR gate 486 is connected to the output terminal of the sixth inverter.
  • the other input terminal of the fourth NOR gate 486 is connected to the output terminal of the fifth NOT gate 485, the input terminal of the fifth NOT gate 485 is used to receive the chip selection signal to be processed, and the output of the fourth NOR gate 486 terminal is used to output the sixth intermediate sampling even signal, and the output terminal of the fourth NOR gate 486 is connected to the input terminal of the twelfth flip-flop, and the clock terminal of the twelfth flip-flop is connected to the output terminal of the sixth NOT gate 487 , the input terminal of the sixth NOT gate 487 is used to receive the first clock delayed even signal; the output terminal of the twelfth flip-flop is used to output the seventh intermediate sampled even signal, and the output terminal of the twelfth flip-flop is connected to the fourth One input terminal of the OR gate 489 is connected, the other input terminal of the fourth OR gate 489 is used to receive the sixth intermediate sample even signal, the output terminal of the fourth OR gate 489 is used to output the eighth intermediate sample even signal, and the fourth The output
  • the chip select odd signal to be processed is represented by PCS_O; the fifth intermediate sampled even signal output through the eleventh sampling circuit 484 can be represented by PCSB_E, and passes through the fourth NOR gate 486
  • the output sixth intermediate sample even signal can be represented by NT_PCS_EEN1, the seventh intermediate sample even signal output by the twelfth sampling circuit 488 can be represented by NT_PCS_EEN2, and the eighth intermediate sample even signal output by the fourth OR gate 489 can be represented by NT_PCS_EEN.
  • the second chip select clock even signal output by the fourth AND gate 490 can be represented by NT_CLK_E.
  • the ninth sampling circuit 477 can be regarded as a rising edge sampling circuit, that is, the rising edge of the odd signal is delayed by the first clock to perform sampling processing; and the fourth NOT gate 480 and the third The ten sampling circuit 481 can be regarded as a falling edge sampling circuit, that is, the falling edge of the first clock delay odd signal is used for sampling processing; for the fourth logic circuit 632, the eleventh sampling circuit 484 can be regarded as a rising edge sampling circuit , that is, the first clock is used to delay the rising edge of the even signal for sampling processing; and the sixth NOT gate 487 and the twelfth sampling circuit 488 can be regarded as a falling edge sampling circuit, that is, the first clock is used to delay the falling edge of the even signal.
  • the PCS_E/PCS_O signal is continuously sampled by using a first-level rising edge sampling circuit and a first-level falling edge sampling circuit, and then increasing the high-level pulse width of the chip select signal through OR logic, thereby
  • the NT_CLK_O/NT_CLK_E signal can be generated with two pulses.
  • the third OR gate 482 and the fourth OR gate 489 both have the function of broadening the signal pulse width.
  • the pulse width of the NT_PCS_OEN1 signal is twice the preset clock period
  • the pulse width of the NT_PCS_OEN2 signal is also twice the preset clock period, but is delayed by one preset clock compared to the NT_PCS_OEN1 signal.
  • the NT_PCS_OEN1 signal and the NT_PCS_OEN2 signal are ORed through the third OR gate 482 to obtain the NT_PCS_OEN signal, and the pulse width is three times the preset clock cycle; then the NT_PCS_OEN signal and the PCLK_OO signal are paired through the third AND gate 483 Performing an AND operation, you can get the NT_CLK_O signal with two pulses, and the pulse width of each pulse is a preset clock cycle.
  • the fourth OR gate 489 outputs the NT_PCS_EEN signal, and the pulse width is also three times the preset clock cycle; then the fourth AND gate 490 performs an AND operation on the NT_PCS_EEN signal and the PCLK_EE signal to obtain an output signal with two pulses.
  • NT_CLK_E signal, and the pulse width of each pulse is a preset clock cycle.
  • the third logic circuit 631 performs two-level sampling and logic operation processing on the PCS_E signal to obtain the NT_CLK_O signal; through the fourth logic circuit 631 Circuit 632 performs two-level sampling and logical operation processing on the PCS_O signal to obtain the NT_CLK_E signal; then based on the NT_CLK_O signal and the NT_CLK_E signal, the target command signal that can be correspondingly decoded is the NT ODT CMD signal.
  • the instruction decoding circuit 64 may include a first instruction decoding circuit 641 and a second instruction decoding circuit 642; wherein,
  • the first instruction decoding circuit 641 is used to receive the first chip select clock signal, decode and sample the instruction signal to be processed according to the first chip select clock signal and the chip select signal to be processed, and obtain the first target instruction signal;
  • the second instruction decoding circuit 642 is configured to receive the second chip select clock signal, decode and sample the instruction signal to be processed according to the second chip select clock signal and the chip select signal to be processed, and obtain the second target instruction signal.
  • the first target command signal is the Command signal in the DDR5 DRAM chip. Since the effective pulse of this signal lasts for two clock cycles, it can be referred to as the 2T CMD signal.
  • the Command signal includes a read command signal and a write command. signal, refresh command signal, precharge command signal and activation command signal;
  • the second target command signal is the Non-Target ODT Command signal in the DDR5DRAM chip, which can be referred to as the NT ODT CMD signal.
  • the initial chip select signal may be a signal indicating that the target chip is selected, and the initial chip select signal is an active low-level pulse signal; wherein, if the pulse width of the initial chip select signal is a predetermined Assuming the clock cycle, the first chip select clock signal is determined to be a valid pulse signal, and the first target command signal output through the first command decoding circuit is determined to be the target command signal; if the pulse width of the initial chip select signal is the preset clock twice the period, the second chip select clock signal is determined to be a valid pulse signal, and the second target command signal output through the second command decoding circuit is determined to be the target command signal.
  • the first chip select clock signal is determined at this time, specifically including the 2T_CLK_E signal and the 2T_CLK_O signal; and then using 2T_CLK_E signal/2T_CLK_O signal, through the first command decoding circuit 641, the first target command signal can be obtained as the 2T CMD signal.
  • the second chip select clock signal is determined at this time, specifically including the NT_CLK_E signal and NT_CLK_O signal; then using the NT_CLK_E signal/NT_CLK_O signal, the second target command signal can be obtained through the second command decoding circuit 642 as the NT ODT CMD signal.
  • the first instruction decoding circuit 641 may include a first decoding sampling circuit 491 and a fifth OR gate 492; wherein ,
  • the first decoding sampling circuit 491 is used to decode and sample the instruction even signal to be processed according to the first chip select clock odd signal and the chip select even signal to be processed, to obtain the first instruction even signal; and according to the first chip select The clock even signal and the chip select odd signal to be processed are decoded and sampled to obtain the first instruction odd signal;
  • the fifth OR gate 492 is used to perform an OR operation on the first command even signal and the first command odd signal to obtain the first target command signal.
  • the first decoding sampling circuit 491 here can also be called an instruction decoding flip-flop, represented by CMD DEC DFF.
  • the output of the first decoding sampling circuit includes the first command even signal and the first command odd signal; wherein the first command even signal is represented by 2T_CMD_E, and the first command odd signal is represented by 2T_CMD_O; and then the 2T_CMD_E signal and the 2T_CMD_O signal are After the OR operation, the first target command signal is obtained as the 2T CMD signal.
  • the first decoding sampling circuit 491 may include a first decoding circuit 811, a thirteenth sampling circuit 812, a second decoding circuit 813 and a third Fourteen sampling circuits 814; among which,
  • the first decoding circuit 811 is used to decode the chip select signal to be processed and the instruction signal to be processed to obtain the first decoded signal;
  • the thirteenth sampling circuit 812 is used to sample the first decoded even signal using the odd signal of the first chip select clock to obtain the first instruction even signal;
  • the second decoding circuit 813 is used to decode the chip select odd signal to be processed and the instruction odd signal to be processed to obtain the first decoded odd signal;
  • the fourteenth sampling circuit 814 is used to sample the first decoded odd signal using the first chip select clock even signal to obtain the first instruction odd signal.
  • the instruction signals to be processed may include five signals, including CA[0]_1T_E, CA[1]_1T_E, CA[2]_1T_E, CA[3]_1T_E, and CA[4]_1T_E.
  • the first decoding circuit 811 may be composed of a three-input NAND gate, a three-input NAND gate, and a two-input NOR gate.
  • PCS_E, CA[0]_1T_E and CA[1]_1T_E are input to the first three-input NAND gate
  • CA[2]_1T_E, CA[3]_1T_E and CA[4]_1T_E are input to the second three-input NAND gate.
  • NAND gate, then the output of the first three-input NAND gate is connected to one input of the two-input NOR gate, and the output of the second three-input NAND gate is connected to the other input of the two-input NOR gate.
  • the thirteenth sampling circuit 812 performs sampling output.
  • the thirteenth sampling circuit 812 may be a D-type flip-flop.
  • the clock terminal of the D-type flip-flop is connected to the 2T_CLK_O signal.
  • the input terminal of the D-type flip-flop is connected to the output terminal of the two-input NOR gate.
  • the output terminal of the flip-flop is used to output the 2T_CMD_E signal.
  • the odd signal of instructions to be processed may include CA[0]_1T_O, CA[1]_1T_O, CA[2]_1T_O, CA[3]_1T_O, CA[4]_1T_O, etc. signal
  • the second decoding circuit 813 may be composed of a three-input NAND gate, a three-input NAND gate, and a two-input NOR gate.
  • PCS_O, CA[0]_1T_O and CA[1]_1T_O are input to the first three-input NAND gate
  • CA[2]_1T_O, CA[3]_1T_O and CA[4]_1T_O are input to the second three-input NAND gate.
  • NAND gate, then the output of the first three-input NAND gate is connected to one input of the two-input NOR gate, and the output of the second three-input NAND gate is connected to the other input of the two-input NOR gate.
  • the fourteenth sampling circuit 814 performs sampling output.
  • the fourteenth sampling circuit 814 can also be a D-type flip-flop.
  • the clock terminal of the D-type flip-flop is connected to the 2T_CLK_E signal.
  • the input terminal of the D-type flip-flop is connected to the output terminal of the two-input NOR gate.
  • D The output terminal of the flip-flop is used to output the 2T_CMD_O signal.
  • the second instruction decoding circuit 642 may include a second decoding sampling circuit 493 and a sixth OR gate 494; in,
  • the second decoding sampling circuit 493 is used to decode and sample the instruction even signal to be processed according to the second chip select clock odd signal and the chip select even signal to be processed, to obtain the second instruction even signal; and according to the second chip select The clock even signal and the chip select odd signal to be processed are decoded and sampled to obtain the second instruction odd signal;
  • the sixth OR gate 494 is used to perform an OR operation on the second command even signal and the second command odd signal to obtain the second target command signal.
  • the second decoding sampling circuit 493 here can also be called an instruction decoding flip-flop, represented by CMD DEC DFF.
  • the output of the second decoding sampling circuit includes the second command even signal and the second command odd signal; wherein, the second command even signal is represented by NT_CMD_E, and the second command odd signal is represented by NT_CMD_O; and then the NT_CMD_E signal and the NT_CMD_O signal are After the OR operation, the second target command signal is obtained as the NT ODT CMD signal.
  • the second decoding sampling circuit 493 may include a third decoding circuit 815, a fifteenth sampling circuit 816, a fourth decoding circuit 817 and a third decoding circuit 817. Sixteen sampling circuits 818; among them,
  • the third decoding circuit 815 is used to decode the chip select even signal to be processed and the instruction even signal to be processed to obtain a second decoded even signal;
  • the fifteenth sampling circuit 816 is used to sample the second decoded even signal using the second chip select clock odd signal to obtain the second instruction even signal;
  • the fourth decoding circuit 817 is used to decode the chip select odd signal to be processed and the instruction odd signal to be processed to obtain a second decoded odd signal;
  • the sixteenth sampling circuit 818 is used to sample the second decoded odd signal using the second chip select clock even signal to obtain the second instruction odd signal.
  • the input signals of the third decoding circuit 815 and the first decoding circuit 811 are the same.
  • the fifteenth sampling circuit is used to 816 for sampling output.
  • the fifteenth sampling circuit 816 can be a D-type flip-flop.
  • the clock terminal of the D-type flip-flop is connected to the NT_CLK_O signal.
  • the input terminal of the D-type flip-flop is connected to the output terminal of the two-input NOR gate.
  • the output terminal of the flip-flop is used to output the NT_CMD_E signal.
  • the sixteenth sample is used Circuit 818 performs sample output.
  • the sixteenth sampling circuit 818 can also be a D-type flip-flop.
  • the clock terminal of the D-type flip-flop is connected to the NT_CLK_E signal.
  • the input terminal of the D-type flip-flop is connected to the output terminal of the two-input NOR gate.
  • D The output terminal of the type flip-flop is used to output the NT_CMD_O signal.
  • the design of these decoding circuits is specifically based on the instruction decoding. implemented by rules. For different products, different application scenarios, and different instructions, the decoding rules may be different, and the logic of the decoding circuit may also be adjusted accordingly, which is not specifically limited in the embodiments of this disclosure.
  • the first command sampling circuit 62 and the second command sampling circuit 63 since the pulse widths of the first chip select signals used by the two are different, the 2T_CLK_E/2T_CLK_O signal or the NT_CLK_E/NT_CLK_O signal can be output; thus, when the first When the pulse width of the chip select signal is the preset clock cycle, using the 2T_CLK_E/2T_CLK_O signal, the first target command signal obtained through the first command decoding circuit 641 is a valid signal (that is, a high-level active pulse signal), and the first target command signal is obtained through the first command decoding circuit 641.
  • the second target command signal obtained by the second command decoding circuit 642 is an invalid signal (ie, a low level signal); conversely, when the pulse width of the first chip select signal is twice the preset clock cycle, the NT_CLK_E/NT_CLK_O signal is used , the first target command signal obtained through the first command decoding circuit 641 is an invalid signal (ie, low level signal), and the second target command signal obtained through the second command decoding circuit 642 is a valid signal (ie, high level signal). Effective pulse signal); thus being able to correctly distinguish the two signals 2T CMD and NT ODT CMD and perform accurate decoding.
  • the pulse width of the initial chip select signal is the preset clock cycle
  • the first chip select signal is sampled as low level on the rising edge of the even clock cycle and is sampled as low level on the next phase If the rising edge sample of the adjacent odd-numbered clock cycle is high level, it is determined that the first chip select clock odd signal is a high-level active pulse signal, and the first chip select clock odd signal has two pulses; among them, the first chip select clock odd signal
  • the rising edge of the first pulse in the odd clock signal is used to generate the rising edge of the first target command signal
  • the rising edge of the second pulse in the first chip select clock odd signal is used to generate the falling edge of the first target command signal.
  • the first chip select signal is sampled as a low level on the rising edge of an odd-numbered clock cycle and is sampled as a high level on the rising edge of the next adjacent even-numbered clock cycle, then it is determined that the first chip select signal is low level.
  • the select clock even signal is a high-level active pulse signal, and the first chip select clock even signal has two pulses; among them, the rising edge of the first pulse in the first chip select clock even signal is used to generate the first target command signal The rising edge of the second pulse in the first chip select clock even signal is used to generate the falling edge of the first target command signal.
  • the pulse width of the initial chip select signal is twice the preset clock period, then in a possible implementation, if the first chip select signal is sampled as low level on the rising edge of the even clock period and is sampled as low level on the next adjacent If the rising edge sampling of the odd clock cycle is still low level, it is determined that the second chip select clock odd signal is a high-level active pulse signal, and the second chip select clock odd signal has two pulses; among them, the second chip select clock odd signal The rising edge of the first pulse in the odd clock signal is used to generate the rising edge of the second target command signal, and the rising edge of the second pulse in the second chip select clock odd signal is used to generate the falling edge of the second target command signal.
  • the second chip select clock even signal is a high-level active pulse signal, and the second chip select clock even signal has two pulses; among them, the rising edge of the first pulse in the second chip select clock even signal is used to generate the second target instruction The rising edge of the signal, the rising edge of the second pulse in the second chip select clock even signal is used to generate the falling edge of the second target command signal.
  • the even clock cycle or the odd clock cycle refers to the clock cycle of the initial clock signal (expressed by CK_t/CK_c).
  • the PCLK_E signal and the PCLK_O signal can be obtained; then the clock cycle where the rising edge of the PCLK_E signal is located is regarded as the even clock cycle, and the clock cycle where the rising edge of the PCLK_O signal is located is regarded as Odd clock cycles.
  • the pulse width is a preset clock period
  • the pulse width is twice the preset clock period
  • the preset accuracy range which can be the pulse width and a
  • the deviation between the preset clock periods is within the preset accuracy range, or the deviation between the pulse width and twice the preset clock period is within the preset accuracy range.
  • either the 2T_CLK_E signal or the 2T_CLK_O signal includes two pulses, and the pulse width of each pulse is a preset clock cycle, and the rising edge of the first pulse is used to generate the rising edge of the first target command signal.
  • the rising edge of the second pulse is used to generate the falling edge of the first target command signal, so that the pulse width of the final output first target command signal can meet twice the preset clock cycle; in addition, since neither the NT_CLK_E signal nor NT_CLK_O signal, which includes two pulses, and the pulse width of each pulse is a preset clock cycle, and the rising edge of the first pulse is used to generate the rising edge of the second target command signal, and the rising edge of the second pulse is used In order to generate the falling edge of the second target command signal, the pulse width of the final output second target command signal can also meet twice the preset clock cycle; in this way, it can not only avoid the problem of uncertainty in the pulse width of the target command signal , and can also distinguish between the two instructions 2T CMD and NT ODT CMD and accurately decode them without affecting each other.
  • Embodiments of the present disclosure provide a signal sampling circuit.
  • the signal sampling circuit can be used according to the required pulse width.
  • the obtained first chip select clock signal and the second chip select clock signal can also distinguish between the two instructions 2T CMD and NT ODT CMD and accurately decode them without affecting each other, thereby avoiding instruction decoding errors and execution errors. Operational issues.
  • the signal sampling circuit 60 may include a first receiver 911, a second receiver 912, a third receiver 913, a first flip-flop 914, a second flip-flop 915, a third flip-flop 916, a first Inverter 917, fourth flip-flop 918, second inverter 919, first buffer 920, second buffer 921, fifth flip-flop 922, third inverter 923, first NOR gate 924, The first NOT gate 925, the sixth flip-flop 926, the first OR gate 927, the first AND gate 928, the seventh flip-flop 929, the fourth inverter 930, the second NOR gate 931, the second NOT gate 932, The eighth flip-flop 933, the second OR gate 934, the second AND gate 935, the ninth flip-flop 936, the first NOT gate 925, the sixth flip-flop 926, the first OR gate 927, the first AND gate 928, the seventh flip-flop 929, the fourth inverter 930, the second NOR gate 931, the second NOT
  • the ninth flip-flop 936, the tenth flip-flop 941, the eleventh flip-flop 944, and the twelfth flip-flop 949 may all be D-type flip-flops.
  • the detailed structure of the first instruction decoding flip-flop 952 is shown in FIG. 8A
  • the detailed structure of the second instruction decoding flip-flop 954 is shown in FIG. 8B .
  • the PCLK_OO signal is used to perform rising edge sampling processing on the PCS_E signal through the fifth flip-flop 922, and then the PCSB_O signal can be obtained through the third inverter 923; and then the PCSB_O signal is obtained through the first NOR gate 924
  • the signal and the PCS_O signal are NOR-operated to obtain the PCS_OEN1 signal; through the first NOT gate 925 and the sixth flip-flop 926, the PCLK_OO signal is used to perform falling edge sampling processing on the PCS_OEN1 signal to obtain the PCS_OEN2 signal; through the first OR gate 927, the PCS_OEN1 signal is obtained
  • the signal is ORed with the PCS_OEN2 signal to obtain PCS_OEN; the PCS_OEN signal and the PCLK_OO signal are ANDed through the first AND gate 928 to obtain the 2T_CLK_O signal; similarly, through the seventh flip-flop 929, the PCLK_EE signal is used
  • the PCLK_OO signal is used to perform rising edge sampling processing on the PCS_E signal through the ninth flip-flop 936, and then the PCSB_O signal can be obtained through the fifth inverter 937; the PCS_O signal is then processed through the third NOT gate 938 NAND operation is performed to obtain the second chip select inverted odd signal, and then NOR operation is performed on the PCSB_O signal and the second chip select inverted odd signal through the third NOR gate 939 to obtain the NT_PCS_OEN1 signal; through the fourth NOT gate 940 and the The ten flip-flop 941 uses the PCLK_OO signal to perform falling edge sampling processing on the NT_PCS_OEN1 signal to obtain the NT_PCS_OEN2 signal; the third OR gate 942 performs an OR operation on the NT_PCS_OEN1 signal and the NT_PCS_OEN2 signal to obtain the NT_PCS_OEN signal; the third AND gate 943 performs an OR operation on
  • the PCLK_EE signal is used to perform rising edge sampling processing on the PCS_O signal, and then the PCSB_E signal can be obtained through the sixth inverter 945; and then through the fifth NOT gate 946 and the fourth NOR gate 947, the sixth NOT gate 948, the twelfth flip-flop 949, the fourth OR gate 950, and the fourth AND gate 951, the NT_CLK_E signal can be obtained.
  • the NT_CLK_E signal there is at most one valid signal among the NT_CLK_O signal and the NT_CLK_E signal.
  • the 2T_CLK_O signal and the 2T_CLK_E signal are used to decode and sample the CA[4:0]_1T_E signal, CA[4:0]_1T_O signal, PCS_E signal, and PCS_O signal, and obtain 2T_CMD_E signal and 2T_CMD_O signal, and then perform an OR logic operation on the 2T_CMD_E signal and 2T_CMD_O signal through the fifth OR gate 953 to obtain the 2T CMD signal.
  • the NT_CLK_O signal and the NT_CLK_E signal are used to decode and sample the CA[4:0]_1T_E signal, CA[4:0]_1T_O signal, PCS_E signal, and PCS_O signal to obtain the NT_CMD_E signal and the NT_CMD_O signal, and then perform an OR logic operation on the NT_CMD_E signal and the NT_CMD_O signal through the sixth OR gate 955 to obtain the NT ODT CMD signal.
  • the embodiment of the present disclosure continuously samples the PCS_E signal/PCS_O signal by using a first-level rising edge flip-flop and a first-level falling edge flip-flop, and then increases the high-level pulse width of the chip select signal through OR logic, and then combines it with PLCK_OO
  • the /PLCK_EE signal is ANDed to generate a chip select clock signal with two pulses to sample the target instruction.
  • both the first chip select clock signal and the second chip select clock signal include two pulses, and the pulse width of each pulse is a preset clock cycle, and then the chip select clock signal is used to sample the decoded instructions.
  • the embodiment of the present disclosure determines that the CS_n signal of the first clock cycle and the second clock cycle is low level and high level respectively by performing NOR logic on the PCSB_O signal and the PCS_O signal.
  • the instruction for sampling decoding is 2T CMD, and then the 2T_CLK_O signal/2T_CLK_E signal covered by this logic is used to perform instruction sampling decoding and output the 2T_CMD signal.
  • the embodiment of the present disclosure determines that the CS_n signal of the first clock cycle and the second clock cycle is both low level by performing a non-logical or non-logical process of the PCSB_O signal and the PCS_O signal, and can determine that the sample to be sampled is decoded.
  • the instruction of the code is NT ODT CMD, and then the NT_CLK_O signal/NT_CLK_E signal covered by this logic is used to perform instruction sampling and decoding, and the NT ODT CMD signal is output.
  • the first command address signal is represented by CA
  • CA can include Cy, Cz, C0, C1, C2 and C3
  • the initial chip select signal is represented by CS_n
  • the first chip select signal is represented by PCS.
  • the CS_n signal is an active low-level pulse signal, and is a signal used to represent the target chip being selected; the initial clock signal is represented by CK_t, the first clock even signal is represented by PCLK_E, the first clock odd signal is represented by PCLK_O, and CK_t
  • the clock cycle of the signal is the preset clock cycle, and the clock cycles of the PCLK_E signal and PCLK_O signal are twice the preset clock cycle.
  • Figure 10 shows A signal timing diagram of a signal sampling circuit provided by an embodiment of the present disclosure. As shown in Figure 10, in the 2T CLK circuit, after using the rising edge of the PCLK_E signal to sample the CA signal, the CA[4:0]_1T_E signal including C0 and C2 is obtained.
  • the PCS_E signal After using the rising edge of the PCLK_E signal to sample and invert the PCS signal, the PCS_E signal is a high-level active pulse signal, and the pulse width is twice the preset clock period; at this time, the rising edge of the PCLK_O signal is used After sampling and inverting the PCS signal on the rising edge, the PCS_O signal is obtained as a low-level signal; then, after sampling and inverting the PCS_E signal on the rising edge through the fifth flip-flop 922 and the third inverter 923, we obtain The PCSB_O signal is an active low-level pulse signal, and the pulse width is twice the preset clock cycle, but is delayed by one preset clock cycle compared to the PCS_E signal; then the PCSB_O signal and the PCS_O signal are paired through the first NOR gate 924 After performing the NOR operation, the PCS_OEN1 signal is obtained as a high-level pulse signal, and the pulse width is twice the preset clock period; then the falling
  • the function of the first OR gate 927 is to broaden the pulse width of the signal; and then The first AND gate 928 performs an AND operation on the PCS_OEN signal and the PCLK_OO signal to obtain the 2T_CLK_O signal including two pulses, and the pulse width of each pulse is the preset clock cycle; at this time, the 2T_CLK_O signal is used to perform the CA[4:0]_1T_E signal
  • the 2T CMD signal can be obtained, and the 2T CMD signal is a high-level effective pulse signal, and the pulse width is twice the preset clock period within the preset accuracy range; among them, the first of the 2T_CLK_O signals
  • the rising edge of the first pulse is used to generate the rising edge of the 2T CMD signal
  • the rising edge of the second pulse in the 2T_CLK_O signal is used to generate the falling edge of the 2T CMD signal.
  • the PCS_E signal is a high-level active pulse signal, and the pulse width is the preset clock cycle twice; after using the rising edge of the PCLK_O signal to sample and invert the PCS signal, the PCS_O signal is obtained as a low-level signal; then the PCS_E signal is processed through the ninth flip-flop 936 and the fifth inverter 937 After rising edge sampling and inversion processing, the PCSB_O signal is a low-level active pulse signal, and the pulse width is twice the preset clock period; however, after the logical inversion of the PCSB_O signal and PCS_O through the third NOR gate 939 After performing the NOR operation on the signal, the NT_PCS_OEN1 signal is obtained as a low-level signal, and then after the falling edge sampling processing of the NT_PCS_OEN1 signal is performed through the first NOT gate
  • FIG. 11 shows that a PCS signal provided by an embodiment of the present disclosure is sampled as low level on the rising edge of the even clock period and is sampled as low level on the adjacent odd-numbered clock period.
  • the corresponding signal timing diagram when the rising edge of the clock cycle is sampled as low level.
  • the CA[4:0]_1T_E signal including C0 and C2 is obtained.
  • the PCS_E signal After using the rising edge of the PCLK_E signal to sample and invert the PCS signal, the PCS_E signal is a high-level active pulse signal, and the pulse width is twice the preset clock period; using the rising edge of the PCLK_O signal to After the PCS signal is sampled and inverted, the PCS_O signal is a high-level active pulse signal, and the pulse width is twice the preset clock cycle, but it is delayed by one preset clock cycle compared to the PCS_E signal; then after the first After the fifth flip-flop 922 and the third inverter 923 perform rising edge sampling and inversion processing on the PCS_E signal, the PCSB_O signal is a low-level active pulse signal, and the PCS_O signal is an inverted signal of each other; then, through the third After a NOR gate 924 performs a NOR operation on the PCSB_O signal and the PCS_O signal, the PCS_OEN1 signal is obtained as a low level signal; and then the PC
  • the PCS_OEN2 signal is obtained as a low-level signal; in this way, after the logical operation of the first OR gate 927 and the first AND gate 928, the 2T_CLK_O signal is also a low-level signal, and the 2T_CLK_O signal cannot be used to pair CA[4: 0]_1T_E signal is decoded and sampled, and the 2T CMD signal will not be output at this time.
  • the CA[4:0]_1T_E signal is obtained including C0 and C2.
  • the PCS_E signal After using the rising edge of the PCLK_E signal to sample and invert the PCS signal, the PCS_E signal is a high-level active pulse signal, and the pulse width is twice the preset clock period; using the rising edge of the PCLK_O signal to After the PCS signal is sampled and inverted, the PCS_O signal is a high-level active pulse signal, and the pulse width is twice the preset clock cycle, but it is delayed by one preset clock cycle compared to the PCS_E signal; then after the first After the nine flip-flops 936 and the fifth inverter 937 perform rising edge sampling and inversion processing on the PCS_E signal, the PCSB_O signal is a low-level active pulse signal, and is an inverted signal with the PCS_O signal; however, after passing through the third After the three NOR gate 939 performs a NOR operation on the PCSB_O signal and the logical inverse signal of PCS_O, it obtains that the NT_PCS_OEN1 signal
  • the function of the first OR gate 927 is to broaden the pulse width of the signal. ;
  • the third AND gate 943 performs an AND operation on the NT_PCS_OEN signal and the PCLK_OO signal to obtain the NT_CLK_O signal including two pulses, and the pulse width of each pulse is the preset clock cycle; at this time, the NT_CLK_O signal is used to CA[4:0 ]_1T_E signal is decoded and sampled to obtain the NT ODT CMD signal, and the NT ODT CMD signal is a high-level active pulse signal, and the pulse width is twice the preset clock cycle within the preset accuracy range; among them, NT_CLK_O
  • the rising edge of the first pulse in the signal is used to generate the rising edge of the NT ODT CMD signal
  • the rising edge of the second pulse in the NT_CLK_O signal is used to generate the falling edge of the NT ODT CMD signal, so that 2T CMD and NT can also be correctly
  • the 2T CMD signal and the NT ODT CMD signal can be decoded separately without affecting each other.
  • the CS_n signal has only one low level of the preset clock cycle, which becomes the PCS_E signal after being sampled by the PCLK_E signal, and then becomes the PCSB_O signal after being sampled by PCLK_O.
  • the PCSB_O signal and the PCS_O signal are NORed and then sampled to generate PCS_OEN1/2 to cover the 2T_CLK_O signal.
  • the 2T_CLK_O signal samples the CA[4:0]_1T_E signal and the PCS_E signal and outputs the 2T CMD signal.
  • the other branch circuit is the PCSB_O signal and (the non-logical logic of the PCS_O signal, which is high level) or the non-logical logic, causing NT_PCS_OEN1/2 to be low level, and no sampling clock is generated, so NT ODT CMD will not be output. Signal.
  • the CS_n signal has a low level of 2 preset clock cycles, which is the PCS_E/O signal after being sampled by PCLK_E/O, and then the PCS_E signal is the PCSB_O signal after being sampled by PCLK_O.
  • the NOR logic of the PCSB_O signal and the PCS_O signal exactly cancels each other out, causing PCS_OEN1/2 to be low level, and no sampling clock is generated, so the 2T CMD signal will not be output.
  • the other branch circuit is the NOR logic of the PCSB_O signal and (the non-logic of the PCS_O signal, which is low level), thereby generating PCS_OEN1/2 to cover the NT_CLK_O signal with two pulses. Finally, this NT_CLK_O signal samples CA[4 :0]_1T_E signal and PCS_E signal output NT ODT CMD signal.
  • the timing waveforms provided in FIG. 10 and FIG. 11 are both cases where the first chip select signal starts from an even clock cycle.
  • Figure 10 shows that the first chip select signal is sampled as low level on the rising edge of the even clock cycle and is sampled as low level on the next adjacent odd clock cycle.
  • Figure 11 shows the first chip select signal is sampled as low level on the rising edge of an even clock cycle And the sampling on the rising edge of the next adjacent odd-numbered clock cycle is still low level.
  • the situation for odd clock cycles is similar and will not be described in detail here.
  • the embodiment of the present disclosure provides a signal sampling circuit.
  • the specific implementation of the foregoing embodiment is described in detail through this embodiment. It can be seen that the technical solution based on the embodiment of the present disclosure can not only avoid the pulse width of the target command signal. Uncertain problem, and when the pulse width of the first chip select signal is different, according to the obtained first chip select clock signal and the second chip select clock signal, the two instructions 2T CMD and NT ODT CMD can also be distinguished , and perform accurate decoding without affecting each other, thereby avoiding the problem of instruction decoding errors and incorrect operations.
  • FIG. 12 shows a schematic structural diagram of a semiconductor memory 120 provided by an embodiment of the present disclosure.
  • the semiconductor memory 120 may include the signal sampling circuit 60 described in any of the previous embodiments.
  • the semiconductor memory 120 may be a DRAM chip.
  • the DRAM chip complies with DDR5 memory specifications.
  • the embodiments of the present disclosure mainly relate to circuits related to input signal sampling and instruction decoding in integrated circuit design, and particularly to DRAM chips in which the CA signal input is used as a control and adjustment circuit after instruction and address sampling and decoding respectively.
  • the technical solution of the embodiment of the present disclosure solves the problem of distinguishing 2T CMD and NT ODT CMD sampling and decoding in DDR5, so that the 2T CMD signal and the NT ODT CMD signal can be distinguished according to the different pulse widths of the CS_n signal, and the Decode accurately and do not affect each other.
  • the semiconductor memory 120 includes the signal sampling circuit 60. Therefore, not only can the problem of uncertain pulse width of the target command signal be avoided, but also the problem of uncertainty in the pulse width of the first chip select signal can be avoided. Under different circumstances, according to the obtained first chip select clock signal and the second chip select clock signal, the two instructions 2T CMD and NT ODT CMD can also be distinguished and accurately decoded without affecting each other, thereby avoiding the occurrence of instructions. The problem of incorrect operation due to decoding errors.
  • Embodiments of the present disclosure provide a signal sampling circuit and a semiconductor memory. Based on the signal sampling circuit, when the pulse width of the first chip select signal is different, according to the obtained first chip select clock signal and the second chip select clock signal, the two instructions 2T CMD and NT ODT CMD can be correctly distinguished and decoded accurately without affecting each other, thereby avoiding the problem of instruction decoding errors and incorrect operations.

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Abstract

本公开实施例提供了一种信号采样电路以及半导体存储器，该信号采样电路包括：信号输入电路，用于确定待处理指令信号和待处理片选信号；第一指令采样电路，用于根据第一时钟信号对待处理片选信号进行两级采样及逻辑运算处理，得到第一片选时钟信号；第二指令采样电路，用于根据第一时钟信号对待处理片选信号进行两级采样及逻辑运算处理，得到第二片选时钟信号；指令译码电路，用于根据待处理片选信号和第一片选时钟信号对待处理指令信号进行译码和采样处理，得到目标指令信号；或者，根据待处理片选信号和第二片选时钟信号对待处理指令信号进行译码和采样处理，得到目标指令信号。

Description

一种信号采样电路以及半导体存储器
相关的交叉引用
本公开基于申请号为202210294955.7、申请日为2022年03月23日、发明名称为“一种信号采样电路以及半导体存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种信号采样电路以及半导体存储器。
背景技术
随着半导体技术的不断发展，人们在制造和使用计算机等设备时，对数据的传输速度提出了越来越高的要求。为了获得更快的数据传输速度，应运而生了一系列数据可以双倍速率(Double Data Rate，DDR)传输的存储器等器件。
在动态随机存取存储器(Dynamic Random Access Memory，DRAM)芯片中，命令地址(Command/Address，CMD/ADD或简称为CA)信号既可以作为地址进行采样又可以作为指令进行采样译码。目前，对于DRAM芯片中的2T CMD信号和NT ODT CMD信号来说，两者所使用片选信号的脉冲宽度不同，而且两者对应的操作功能也是不同的；但是在现有的指令译码方案中这两种指令容易发生混淆而导致译码错误问题。
发明内容
本公开提供了一种信号采样电路以及半导体存储器，能够区分2T CMD和NT ODT CMD这两种指令，并进行准确译码，从而避免出现指令译码错误而执行错误操作的问题。
第一方面，本公开实施例提供了一种信号采样电路，所述信号采样电路包括信号输入电路、第一指令采样电路、第二指令采样电路和指令译码电路；其中，
所述信号输入电路，用于根据第一时钟信号、第一片选信号和第一命令地址信号，确定待处理指令信号和待处理片选信号；其中，所述第一时钟信号的时钟周期为预设时钟周期的两倍；
所述第一指令采样电路，用于当所述第一片选信号的脉冲宽度为所述预设时钟周期时，根据所述第一时钟信号对所述待处理片选信号进行两级采样及逻辑运算处理，得到第一片选时钟信号；
所述第二指令采样电路，用于当所述第一片选信号的脉冲宽度为所述预设时钟周期的两倍时，根据所述第一时钟信号对所述待处理片选信号进行两级采样及逻辑运算处理，得到第二片选时钟信号；
所述指令译码电路，用于根据所述待处理片选信号和所述第一片选时钟信号对所述待处理指令信号进行译码和采样处理，得到目标指令信号；或者，根据所述待处理片选信号和所述第二片选时钟信号对所述待处理指令信号进行译码和采样处理，得到目标指令信号。
第二方面，本公开实施例提供了一种半导体存储器，该半导体存储器包括如第一方面所述的信号采样电路。
本公开实施例提供了一种信号采样电路以及半导体存储器，基于该信号采样电路，在第一片选信号的脉冲宽度不同情况下，根据所得到的第一片选时钟信号和第二片选时钟信号，就可以正确区分2T CMD和NT ODT CMD这两种指令，并进行准确译码，而且互不影响，从而避免出现指令译码错误而执行错误操作的问题。
附图说明
图1为两个时钟周期命令的信号时序示意图；
图2为一种信号采样电路的组成结构示意图；
图3为一种指令译码器的组成结构示意图；
图4为脉冲宽度不同的两个片选信号对比示意图；
图5A为一种信号采样电路的信号时序示意图；
图5B为另一种信号采样电路的信号时序示意图；
图6为本公开实施例提供的一种信号采样电路的组成结构示意图；
图7为本公开实施例提供的另一种信号采样电路的组成结构示意图；
图8A为本公开实施例提供的一种第一译码采样电路的组成结构示意图；
图8B为本公开实施例提供的一种第二译码采样电路的组成结构示意图；
图9为本公开实施例提供的一种信号采样电路的详细结构示意图；
图10为本公开实施例提供的一种信号采样电路的信号时序示意图；
图11为本公开实施例提供的另一种信号采样电路的信号时序示意图；
图12为本公开实施例提供的一种半导体存储器的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关公开，而非对该公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关公开相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
以下为本公开实施例中涉及到的专业名词解释以及部分名词的对应关系：
动态随机存取存储器(Dynamic Random Access Memory，DRAM)
同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)
双倍速率(Double Data Rate，DDR)
第四代DDR(4th DDR，DDR4)
第五代DDR(5th DDR，DDR5)
命令地址输入(Command/Address，CMD/ADD或简称为CA)
时钟输入(Clock Input，CLK)
片选输入(Chip Select Input，CS)
缓冲器(Buffer/Repeater，RPT)
终结电阻(On-Die Termination，ODT)
指令译码器(Command Decoder，CMD DEC)
D型触发器(Data Flip-Flop或Delay Flip-Flop，DFF)
工艺、电压、温度(Process、Voltage、Temperature，PVT)
两倍时钟周期的指令(2Tck Command，2T CMD)
非目标芯片终结电阻的指令(Non-Target On-Die Termination Command，NT ODT CMD)
可以理解，以DDR5DRAM设计为例，CA输入既可以作为地址进行采样又可以作为指令进行采样译码。其中，这里的CA是DRAM各种命令地址信号的统称，可以包括行地址选通脉冲(Row Address Strobe，RAS)、列地址选通脉冲(Column Address Strobe，CAS)、写命令(Write，WE)、激活命令(Active，ACT)等命令信号，以及还可以包括有A13～A0的地址信号等。另外，在实际应用中，该命令地址信号包括几位地址信号，具体可以是根据DRAM的规格确定，本公开实施例不作任何限定。
在DDR5DRAM的2T CMD模式下，参见图1，其示出了两个时钟周期命令的信号时序示意图。在图1中，CK_t、CK_c为一对输入的互补时钟信号，CA[13:0]就是CA信号输入，CMD为CA信号译码后得到的指令信号，CS_n为指示CA信号有效的片选信号。如图1所示，CA[13:0]为持续两个时钟周期的信号，第1个时钟周期的CA和第2个时钟周期的CA需要作为地址信号进行采样，同时第1个时钟周期的CA还需要作为指令信号进行采样和译码。具体地，在DDR5DRAM中，第1个时钟周期的CA[4:0]是作为指令信号进行采样和译码的。
示例性地，参见图2，其示出了一种信号采样电路的组成结构示意图。如图2所示，该信号采样电路10可以包括第一接收器101、第二接收器102、第三接收器103、第一采样电路104、第二采样电路105、第三采样电路106、第四采样电路107、第五采样电路108、第六采样电路109、第一缓冲器110、第一与门111、第二缓冲器112、第二与门113、指令译码器114和或门115。其中，第一采样电路104、第二采样电路105、第五采样电路108和第六采样电路109可以是由D型触发器组成，第三采样电路106和第四采样电路107可以是由D型触发器和反相器组成。
在图2中，第一接收器101的输入信号为初始命令地址信号(用CA[13:0]表示)和参考信号(用VREFCA表示)，输出信号为第一命令地址信号(用CA表示)；第二接收器102的输入信号为初始片选信号(用CS_n表示)和参考信号(用VREFCA表示)，输出信号为第一片选信号(用PCS表示)；第三接收器103的输入信号为一对输入的互补时钟信号(用CK_t和CK_c表示)，输出信号为第一时钟偶信号(用PCLK_E表示)和第一时钟奇信号(用PCLK_O表示)。需要注意的是，第三接收器103还具有分频处理能力，因此，PCLK_E信号和PCLK_O信号各自的频率为CK_t信号或者CK_c信号的频率的二分之一，即PCLK_E信号和PCLK_O信号各自的时钟周期为CK_t信号或者CK_c信号的时钟周期的两倍，且相位差为180度。另外，还需要注意的是，这里的CA[13:0]表示一组信号，CA[0]、CA[1]、…、CA[13]的合并统称。相应的，第一接收器101中其实包括有14个接收电路，以及输出的线路，甚至包括后面的采样电路，长走线路径也是14根，与CA[0]、CA[1]、…、CA[13]是一一对应的。
然后，通过第一采样电路104，利用PCLK_E信号对第一命令地址信号进行采样处理，得到第二地址偶信号(用CA[13:0]_1T_E表示)，且第二地址偶信号包括待处理指令偶信号(用CA[4:0]_1T_E表示)；通过第二采样电路105，利用PCLK_O信号对第一命令地址信号进行采样处理，得到第二地址奇信号(用CA[13:0]_1T_O表示)，且第二地址奇信号包括待处理指令奇信号(用CA[4:0]_1T_O表示)；通过第三采样电路106，利用PCLK_E信号对第一片选信号进行采样及反相处理，得到待处理片选偶信号(用PCS_E表示)；通过第四采样电路107，利用PCLK_O信号对第一片选信号进行采样及反相处理，得到待处理片选奇信号(用PCS_O表示)；然后再通过第五采样电路108，利用PCLK_O信号对PCS_E信号进行采样 处理，得到目标片选奇信号(用PCS_OD表示)；以及通过第六采样电路109，利用PCLK_E信号对PCS_O信号进行采样处理，得到目标片选偶信号(用PCS_ED表示)；再利用第一缓冲器110和第一与门111对PCLK_E信号和PCS_ED信号进行逻辑运算，得到片选时钟偶信号(用CS_CLK_E表示)；利用第二缓冲器112和第二与门113对PCLK_O信号和PCS_OD信号进行逻辑运算，得到片选时钟奇信号(用CS_CLK_O表示)；紧接着，再通过指令译码器114，利用CS_CLK_E信号和CS_CLK_O信号对CA[4:0]_1T_E、CA[4:0]_1T_O、PCS_OD和PCS_ED进行译码及采样处理，得到指令偶信号(用CMD_E表示)和指令奇信号(用CMD_O表示)；最后，通过或门115对CMD_E信号和CMD_O信号进行或逻辑运算，得到目标指令信号(用CMD表示)。另外，还需要注意的是，CA[13:0]_1T_E信号并非是一个信号，而是代表一组信号，即CA[13]_1T_E～CA[0]_1T_E，而CA[4:0]_1T_E信号则是CA[13:0]_1T_E信号中的CA[0]_1T_E、CA[1]_1T_E、CA[2]_1T_E、CA[3]_1T_E、CA[4]_1T_E这5个信号；CA[13:0]_1T_O信号也并非是一个信号，而是代表一组信号，即CA[13]_1T_O～CA[0]_1T_O，而CA[4:0]_1T_O信号则是CA[13:0]_1T_O信号中的CA[0]_1T_O、CA[1]_1T_O、CA[2]_1T_O、CA[3]_1T_O、CA[4]_1T_O这5个信号。
还需要说明的是，对于指令译码器114而言，其也可以称为指令译码触发器，用CMD DEC DFF表示。参见图3，指令译码器可以包括第一指令译码电路a和第二指令译码电路b，而无论是第一指令译码电路a还是第二指令译码电路b，均是由二输入与非门、三输入与非门、二输入或非门、D型触发器和与门等逻辑部件组成，具体详见图3所示。
这样，以DDR5DRAM为例，初始时钟信号(用CK_t/CK_c表示)在接收器之后分频处理为PCLK_E信号和PCLK_O信号，然后去采样CA信号。由于DDR5中2T CMD需要用第一个时钟周期的CA信号作为指令和地址，然后用第二个时钟周期的CA信号作为剩下的地址。因此，DDR5设计需要两级采样，然后分别作为两个时钟周期的地址。对于指令来说，需要用第一级的CA信号进行组合逻辑，然后进行第二级采样来和第二个周期的采样地址信号对齐。由于指令信号需要保持一个脉冲宽度，这样利用两级采样后得到的PCS_OD/ED信号进行与逻辑运算，可以产生CMD_E/O信号，然后再经过或运算后即可得到CMD信号。
然而，在DDR5中存在两种指令信号：2T CMD信号和NT ODT CMD信号。其中，2T CMD信号也可称为2-cycle Command信号。如图4所示，对于2T CMD信号，其对应的片选信号用CS0_n表示，其脉冲宽度为预设时钟周期；对于NT ODT CMD信号，其对应的片选信号用CS1_n表示，其脉冲宽度为预设时钟周期的两倍。下面将结合信号采样电路10对这两种信号的译码时序进行描述。
参见图5A和图5B，其示出了上述信号采样电路10对应的信号时序示意图。如图5A和图5B所示，第一命令地址信号用CA表示，且CA可以包括Cy、Cz、C0、C1、C2和C3；初始片选信号用CS_n表示，第一片选信号用PCS表示，CS_n信号为低电平有效的脉冲信号，而且用于表征目标芯片被选中的信号；初始时钟信号用CK_t表示，CK_t信号的时钟周期等于预设时钟周期，即1Tck，而PCLK_E信号和PCLK_O信号的时钟周期均为预设时钟周期的两倍，即2Tck。
针对2T CMD信号，如图5A所示，这时候PCS信号的脉冲宽度为预设时钟周期，在利用PCLK_E信号的上升沿对PCS信号进行采样及反相处理后，得到PCS_E信号为高电平有效的脉冲信号，而且脉冲宽度为预设时钟周期的两倍；在利用PCLK_O信号的上升沿对PCS信号进行采样及反相处理后，得到PCS_O信号为低电平信号；同时利用PCLK_O信号对PCS_E信号进行采样处理后，得到PCS_OD信号为高电平有效的脉冲信号，而且脉冲宽度为预设时钟周期的两倍；但是利用PCLK_E信号对PCS_O信号进行采样处理后，得到PCS_ED信号为低电平信号；在经过第一缓冲器110、第一与门111、第二缓冲器112、第二与门113等逻辑运算后，得到CS_CLK_E信号为低电平信号，CS_CLK_O信号为高电平有效的脉冲信号，而且脉冲宽度为一个预设时钟周期；然后利用PCLK_E信号的上升沿对CA信号进行采样处理后，得到CA[4:0]_1T_E信号包括C0和C2；由于CS_CLK_E信号和PCS_ED信号为低电平信号，那么译码得到的CMD_E信号也为低电平信号；只有利用CS_CLK_O信号、PCS_OD信号和CA[4:0]_1T_E信号进行采样及译码处理后，所得到的CMD_O信号即为CMD信号，而且CMD信号为高电平有效的脉冲信号，脉冲宽度为预设时钟周期的两倍与延时的差值，该延时指的是CS_CLK_O信号的上升沿与PCS_OD信号的上升沿之间的延时；也即CMD信号的脉冲宽度＝(2Tck-延时)。
针对NT ODT CMD信号，如图5B所示，这时候PCS信号的脉冲宽度为预设时钟周期的两倍，在利用PCLK_E/PCLK_O信号的上升沿对PCS信号进行采样及反相处理后，得到PCS_E/PCS_O信号均为高电平有效的脉冲信号，而且脉冲宽度为预设时钟周期的两倍，但是PCS_O信号相比PCS_E信号延迟一个预设时钟周期；进一步采样处理后得到的PCS_OD/PCS_ED信号也均为高电平有效的脉冲信号，而且脉冲宽度为预设时钟周期的两倍，但是PCS_ED信号相比PCS_OD信号延迟一个预设时钟周期；然后经过逻辑运算得到的CS_CLK_O/CS_CLK_E信号也均为高电平有效的脉冲信号，而且脉冲宽度为一个预设时钟周期，但是CS_CLK_E信号相比CS_CLK_O信号延迟一个预设时钟周期。其中，CA[4:0]_1T_E信号包括C0和C2，CA[4:0]_1T_O信号包括C1和C3，这时候不仅CS_CLK_O信号采样到的C0需进行译码，而且CS_CLK_E信号采样到的C1也需进行译码，使得最终产生的CMD信号脉冲宽度为预设时钟周期的三倍与延时的差值，即CMD信号的脉冲宽度＝(3Tck-延时)；而且CMD信号中不仅有C0的译码信息，还有C1的译码信息，如此没有正确译码出NT ODT CMD信号。
也就是说，通过应用简单的PCS_ED/PCS_OD和PCLK_E/PCLK_O组合逻辑产生的CS_CLK_O/CS_CLK_E信号进行指令采样，然后再和PCS_ED/PCS_OD进行与逻辑，从而可以产生一个脉冲的CMD信号。但是2T CMD信号和NT ODT CMD信号的区别是CS_n信号为低电平的脉冲宽度不同，如果直接采用上述信号采样电路10，NT ODT CMD信号会被错误的解析成2T CMD信号。然而，这两个命令信号的操作功能是不同的。因此，在实际应用中需要对2T CMD信号和NT ODT CMD信号进行区分，并 且正确译码。
基于此，本公开实施例提供了一种信号采样电路，该信号采样电路包括信号输入电路、第一指令采样电路、第二指令采样电路和指令译码电路；其中，信号输入电路，用于根据第一时钟信号、第一片选信号和第一命令地址信号，确定待处理指令信号和待处理片选信号，第一时钟信号的时钟周期为预设时钟周期的两倍；第一指令采样电路，用于当第一片选信号的脉冲宽度为预设时钟周期时，根据第一时钟信号对待处理片选信号进行两级采样及逻辑运算处理，得到第一片选时钟信号；第二指令采样电路，用于当第一片选信号的脉冲宽度为预设时钟周期的两倍时，根据第一时钟信号对待处理片选信号进行两级采样及逻辑运算处理，得到第二片选时钟信号；指令译码电路，用于根据待处理片选信号和第一片选时钟信号对待处理指令信号进行译码和采样处理，得到目标指令信号；或者，根据待处理片选信号和第二片选时钟信号对待处理指令信号进行译码和采样处理，得到目标指令信号。这样，基于该信号采样电路，在第一片选信号的脉冲宽度不同情况下，根据所得到的第一片选时钟信号和第二片选时钟信号，就可以正确区分2T CMD和NT ODT CMD这两种指令，并进行准确译码，而且互不影响，从而避免出现指令译码错误而执行错误操作的问题。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图6，其示出了本公开实施例提供的一种信号采样电路的组成结构示意图。如图6所示，该信号采样电路60可以包括信号输入电路61、第一指令采样电路62、第二指令采样电路63和指令译码电路64；其中，
信号输入电路61，用于根据第一时钟信号、第一片选信号和第一命令地址信号，确定待处理指令信号和待处理片选信号；其中，第一时钟信号的时钟周期为预设时钟周期的两倍；
第一指令采样电路62，用于当第一片选信号的脉冲宽度为预设时钟周期时，根据第一时钟信号对待处理片选信号进行两级采样及逻辑运算处理，得到第一片选时钟信号；
第二指令采样电路63，用于当第一片选信号的脉冲宽度为预设时钟周期的两倍时，根据第一时钟信号对待处理片选信号进行两级采样及逻辑运算处理，得到第二片选时钟信号；
指令译码电路64，用于根据待处理片选信号和第一片选时钟信号对待处理指令信号进行译码和采样处理，得到目标指令信号；或者，根据待处理片选信号和第二片选时钟信号对待处理指令信号进行译码和采样处理，得到目标指令信号。
需要说明的是，在本公开实施例中，信号采样电路60应用于地址和指令信号的采样和译码过程，具体可以应用在多种电路场景中。本公开实施例后续以DRAM芯片中的CA信号进行地址和指令的采样及译码进行解释和说明，但这并不构成相关限定。
还需要说明的是，在本公开实施例中，该信号采样电路60可以应用于2T CMD场景。具体来说，在该场景下，这里的第一命令地址信号包括两个预设时钟周期的有效信号，同时目标指令信号(用CMD表示)的有效脉冲也持续两个预设时钟周期，详见图1所示。在图1中，CS_n信号为低电平有效的脉冲信号，当前时钟周期和相邻的下一个时钟周期对应的CA[13:0]信号均是有效(Valid)的；其中，当前时钟周期为CS_n信号为低电平脉冲对应的时钟周期。另外，需要注意的是，这里的预设时钟周期是指CK_t/CK_c信号的时钟周期，CS_n信号则是表征目标芯片被选中的信号，而且CA[13:0]并非是一个信号，而是代表一组命令地址信号，即CA[0]～CA[13]共14个信号。
还需要说明的是，在本公开实施例中，目标指令信号可以为DDR5DRAM芯片中的Command信号，由于该信号的有效脉冲持续两个时钟周期，这里可简称为2T CMD信号；其中，Command信号可以包括读命令信号、写命令信号、刷新命令信号、预充电命令信号和激活命令信号等；或者，目标指令信号也可以为DDR5DRAM芯片中的Non-Target ODT Command信号，这里可简称为NT ODT CMD信号。
在指令的采样译码中，为了解决区分2T CMD信号和NT ODT CMD信号采样译码的难题，本公开实施例通过增加第一指令采样电路62和第二指令采样电路63，由于两者使用的第一片选信号的脉冲宽度不同，可以输出不同的第一片选时钟信号和第二片选时钟信号；这样，对于2T CMD信号而言，利用第一片选时钟信号得到的目标指令信号为有效信号，而利用第二片选时钟信号得到的目标指令信号为无效信号(即低电平信号)；对于NT ODT CMD信号而言，利用第一片选时钟信号得到的目标指令信号为无效信号(即低电平信号)，而利用第二片选时钟信号得到的目标指令信号为有效信号，从而能够正确区分2T CMD和NT ODT CMD这两种指令信号，并进行准确译码。
在一些实施例中，对于目标指令信号而言，目标指令信号包括一个脉冲，且脉冲的脉冲宽度为预设时钟周期的两倍；其中，
在第一片选信号的脉冲宽度为预设时钟周期的情况下，第一片选时钟信号包括两个脉冲，且每一个脉冲的脉冲宽度为预设时钟周期，以及第二片选时钟信号维持电平状态不变；其中，第一片选时钟信号中第一个脉冲的上升沿用于产生目标指令信号的上升沿，第一片选时钟信号中第二个脉冲的上升沿用于产生目标指令信号的下降沿。
也就是说，当第一片选信号的脉冲宽度为预设时钟周期时，这时候根据第一指令采样电路62得到的第一片选时钟信号为有效信号，而根据第二指令采样电路63得到的第二片选时钟信号为无效信号。另外，在这种情况下，目标指令信号为2T CMD信号；而且目标指令信号的上升沿是由第一片选时钟信号中第一个脉冲的上升沿产生，目标指令信号的下降沿是由第一片选时钟信号中第二个脉冲的上升沿产生。
需要说明的是，对于本公开实施例所述的脉冲宽度，以目标指令信号为例，“脉冲宽度为预设时钟周期的两倍”具体是指该脉冲宽度和预设时钟周期的两倍之间的偏差在预设精度范围内，本公开中涉及到其他信号的脉冲宽度说明也可参照理解。
在一些实施例中，对于目标指令信号而言，目标指令信号包括一个脉冲，且脉冲的脉冲宽度为预设时钟周期的两倍；其中，
在第一片选信号的脉冲宽度为预设时钟周期的两倍的情况下，第一片选时钟信号维持电平状态不变；以及第二片选时钟信号包括两个脉冲，且每一个脉冲的脉冲宽度为预设时钟周期；其中，第二片选时钟信号中第一个脉冲的上升沿用于产生目标指令信号的上升沿，第二片选时钟信号中第二个脉冲的上升沿用于产生目标指令信号的下降沿。
也就是说，当第一片选信号的脉冲宽度为预设时钟周期的两倍时，这时候根据第一指令采样电路62得到的第一片选时钟信号为无效信号，而根据第二指令采样电路63得到的第二片选时钟信号为有效信号。另外，在这种情况下，目标指令信号为NT ODT CMD信号；而且目标指令信号的上升沿是由第二片选时钟信号中第一个脉冲的上升沿产生，目标指令信号的下降沿是由第二片选时钟信号中第二个脉冲的上升沿产生。
这样，根据第一片选时钟信号和第二片选时钟信号，不仅能够正确区分2T CMD和NT ODT CMD这两种指令信号，并进行准确译码；而且还可以用来产生目标指令信号的上升沿和下降沿，使得目标指令信号的脉冲宽度在预设精度范围内始终为预设时钟周期的两倍，避免目标指令信号的脉冲宽度不确定问题。
在一些实施例中，在图6所示信号采样电路60的基础上，如图7所示，信号输入电路61可以包括接收电路611和输入采样电路612；其中，
接收电路611，用于接收初始命令地址信号、初始片选信号和初始时钟信号，输出第一命令地址信号、第一片选信号和第一时钟信号；
输入采样电路612，用于根据第一时钟信号对第一片选信号和第一命令地址信号进行采样处理，得到待处理片选信号和待处理指令信号。
在这里，初始时钟信号的时钟周期为预设时钟周期，第一时钟信号的时钟周期为预设时钟周期的两倍。也就是说，第一时钟信号是通过对初始时钟信号进行分频处理得到的。
在一种具体的实施例中，如图7所示，接收电路611可以包括第一接收电路451、第二接收电路452和第三接收电路453；其中，
第一接收电路451，用于接收初始命令地址信号，输出第一命令地址信号；
第二接收电路452，用于接收初始片选信号，输出第一片选信号；
第三接收电路453，用于接收初始时钟信号，并对初始时钟信号进行分频处理，输出第一时钟奇信号和第一时钟偶信号。
在这里，第一时钟信号可以是由第一时钟奇信号和第一时钟偶信号组成，第一时钟奇信号和第一时钟偶信号各自的时钟周期均是预设时钟周期的两倍，而且第一时钟奇信号和第一时钟偶信号之间的相位差为180度。
另外，需要说明的是，在本公开实施例中，无论是第一接收电路451，还是第二接收电路452或第三接收电路453，均可以是接收器(用Recevier表示)，或者也可以是缓冲器(用Buffer表示)。
还需要说明的是，在本公开实施例中，这里的初始命令地址信号可以用CA[13:0]表示，第一命令地址信号用CA表示；初始片选信号可以用CS_n表示，第一片选信号用PCS表示；初始时钟信号可以用CK_t和CK_c表示，第一时钟偶信号用PCLK_E表示，第一时钟奇信号用PCLK_O表示。其中，对于PCLK_E信号和PCLK_O信号而言，PCLK_E信号的时钟周期是预设时钟周期的两倍，PCLK_O信号的时钟周期也是预设时钟周期的两倍，而且PCLK_E信号和PCLK_O信号之间的相位差为180度。
还需要说明的是，在本公开实施例中，无论是初始命令地址信号还是第一命令地址信号，其并非是一个信号，而是代表一组命令地址信号，即CA[0]～CA[13]；因此，对于第一接收电路451而言，这里可以包括有14个接收电路，分别用于接收CA[0]、CA[1]、…、CA[13]等14个信号，图中仅示出一个接收电路作为示意。
进一步地，对于输入采样电路612而言，本公开实施例不仅需要利用第一时钟信号对第一命令地址信号进行采样处理，还需要利用第一时钟信号对第一片选信号进行采样处理。因此，在一些实施例中，如图7所示，输入采样电路612可以包括第一采样电路461、第二采样电路462、第三采样电路463和第四采样电路464；其中，
第一采样电路461，用于根据第一时钟偶信号对第一命令地址信号进行采样处理，得到待处理指令偶信号；
第二采样电路462，用于根据第一时钟奇信号对第一命令地址信号进行采样处理，得到待处理指令奇信号；
第三采样电路463，用于根据第一时钟偶信号对第一片选信号进行采样及反相处理，得到待处理片选偶信号；
第四采样电路464，用于根据第一时钟奇信号对第一片选信号进行采样及反相处理，得到待处理片选奇信号。
在这里，待处理指令信号可以是由待处理指令偶信号和待处理指令奇信号组成，待处理片选信号可以是由待处理片选偶信号和待处理片选奇信号组成。
需要说明的是，在一种具体的实施例中，第一采样电路461可以包括第一触发器，且第一触发器的输入端与第一命令地址信号连接，第一触发器的时钟端与第一时钟偶信号连接，第一触发器的输出端用于输出待处理指令偶信号；第二采样电路462可以包括第二触发器，且第二触发器的输入端与第一命令地址信号连接，第二触发器的时钟端与第一时钟奇信号连接，第二触发器的输出端用于输出待处理指令奇信号；第三采样电路463可以包括第三触发器和第一反相器，且第三触发器的输入端与第一片选信号连接，第三触发器的时钟端与第一时钟偶信号连接，第三触发器的输出端与第一反相器的输入端连接，第一反相器的输出端用于输出待处理片选偶信号；第四采样电路464可以包括第四触发器和第二反相器， 且第四触发器的输入端与第一片选信号连接，第四触发器的时钟端与第一时钟奇信号连接，第四触发器的输出端与第二反相器的输入端连接，第二反相器的输出端用于输出待处理片选奇信号。
对于第一采样电路461和第二采样电路462而言，待处理命令地址信号可以是由待处理命令地址偶信号和待处理命令地址奇信号组成，待处理指令信号可以是由待处理指令偶信号和待处理指令奇信号组成。其中，待处理命令地址偶信号包括待处理指令偶信号，且待处理命令地址偶信号用CA[13:0]_1T_E表示，待处理指令偶信号用CA[4:0]_1T_E表示；待处理命令地址奇信号包括待处理指令奇信号，且待处理命令地址奇信号用CA[13:0]_1T_O表示，待处理指令奇信号用CA[4:0]_1T_O表示。在这里，需要注意的是，CA[13:0]_1T_E也并非是一个信号，而是代表一组命令地址信号，即CA[0]_1T_E～CA[13]_1T_E，而CA[4:0]_1T_E表示的这一组信号中的CA[0]_1T_E～CA[4]_1T_E等五个信号；CA[13:0]_1T_O也并非是一个信号，而是代表一组命令地址信号，即CA[0]_1T_O～CA[13]_1T_O，而CA[4:0]_1T_O表示的这一组信号中的CA[0]_1T_O～CA[4]_1T_O等五个信号。
对于第三采样电路463和第四采样电路464而言，待处理片选信号可以是由待处理片选偶信号和待处理片选奇信号组成。其中，第一片选信号用PCS表示，待处理片选偶信号用PCS_E表示，待处理片选奇信号用PCS_O表示。
还需要说明的是，在本公开实施例中，因为PCS为低电平有效的脉冲信号，对于第三采样电路463和第四采样电路464，增加第一反相器或者第二反相器之后，PCS_O信号或者PCS_E信号就可以变成高电平有效的脉冲信号，以便后续的逻辑运算。但是，对于后续不同的逻辑运算，第三采样电路463和第四采样电路464也可以不需要设置第一反相器和第二反相器，那么后续的逻辑运算则需进行相应调整，从而也可以达到相同效果。
在一些实施例中，第一触发器、第二触发器、第三触发器和第四触发器均可以为D型触发器。以第一采样电路461和第二采样电路462为例，在第一采样电路461中，D型触发器的时钟端与PCLK_E信号连接，D型触发器的输入端与CA信号连接，D型触发器的输出端用于输出CA[13:0]_1T_E信号，且其中的CA[4:0]_1T_E信号组成待处理指令偶信号。在第二采样电路462中，D型触发器的时钟端与PCLK_O信号连接，D型触发器的输入端与CA信号连接，D型触发器的输出端用于输出CA[13:0]_1T_O信号，且其中的CA[4:0]_1T_O信号组成待处理指令奇信号。在这里，需要注意的是，对于第一采样电路461或者第二采样电路462来说，由于CA并非是一个信号，而是一组信号的统称；那么这里可以包括多个第一采样电路461，分别用于接收这一组CA信号中的每一个CA信号；同理，也可以包括多个第二采样电路462，分别用于接收这一组CA信号中的每一个CA信号；而图中仅示出一个第一采样电路461和一个第二采样电路462作为示意。
这样，在经过接收电路611和输入采样电路612之后，可以获得PCLK_E信号、PCLK_O信号、PCS_E信号、PCS_O信号、CA[4:0]_1T_E信号和CA[4:0]_1T_O信号；然后进一步利用不同脉冲宽度的第一片选信号以及不同的指令采样电路(第一指令采样电路62和第二指令采样电路63)，可以得到不同的第一片选时钟信号和第二片选时钟信号，从而可以正确区分2T CMD和NT ODT CMD这两种指令，并且进行准确译码，而且互不影响。
在一些实施例中，在图6所示信号采样电路60的基础上，如图7所示，信号采样电路60还可以包括第一缓冲器65和第二缓冲器66；其中，
第一缓冲器65，用于对第一时钟偶信号进行延时处理，得到第一时钟延时偶信号；
第二缓冲器66，用于对第一时钟奇信号进行延时处理，得到第一时钟延时奇信号。
需要说明的是，在本公开实施例中，第一时钟偶信号和第一时钟奇信号在输入第一指令采样电路62和第二指令采样电路63之前还需要先进行延时处理。这里，第一时钟偶信号用PCLK_E表示，第一时钟延时偶信号用PCLK_EE表示；第一时钟奇信号用PCLK_O表示，第一时钟延时奇信号用PCLK_OO表示。
还需要说明的是，对于缓冲器而言，无论是第一缓冲器65还是第二缓冲器66，不仅具有延时功能，而且还可以具有增强信号驱动能力的作用。具体地，对于第一时钟延时偶信号与第一时钟偶信号而言，第一时钟延时偶信号相比第一时钟偶信号不仅存在时延，而且第一时钟延时偶信号的驱动能力更强；同理，对于第一时钟延时奇信号与第一时钟奇信号而言，第一时钟延时奇信号相比第一时钟奇信号存在时延，而且第一时钟延时奇信号的驱动能力更强。
在本公开实施例中，无论是第一缓冲器65还是第二缓冲器66，缓冲器个数并不局限于一个，也可以是多个。在这里，具体数量可以根据实际需求进行设置，并不作具体限定。
在一些实施例中，在图6所示信号采样电路60的基础上，如图7所示，第一指令采样电路62可以包括第一逻辑电路621和第二逻辑电路622；其中，
第一逻辑电路621，用于接收第一时钟延时奇信号和待处理片选偶信号，并利用第一时钟延时奇信号对待处理片选偶信号进行两级采样及逻辑运算，得到第一片选时钟奇信号；
第二逻辑电路622，用于接收第一时钟延时偶信号和待处理片选奇信号，并利用第一时钟延时偶信号对待处理片选奇信号进行两级采样及逻辑运算，得到第一片选时钟偶信号。
在这里，第一片选时钟信号可以是由第一片选时钟偶信号和第一片选时钟奇信号组成。其中，第一片选时钟偶信号可以用2T_CLK_E表示，第一片选时钟奇信号可以用2T_CLK_O表示。
在一种具体的实施例中，如图7所示，第一逻辑电路621可以包括第五采样电路465、第一或非门466、第一非门467、第六采样电路468、第一或门469和第一与门470；其中，
第五采样电路465，用于利用第一时钟延时奇信号对待处理片选偶信号进行采样及反相处理，得到第一中间采样奇信号；
第一或非门466，用于对第一中间采样奇信号和待处理片选奇信号进行或非运算，得到第二中间采 样奇信号；
第一非门467，用于对第一时钟延时奇信号进行非运算，得到第一反相时钟奇信号；
第六采样电路468，用于利用第一反相时钟奇信号对第二中间采样奇信号进行采样处理，得到第三中间采样奇信号；
第一或门469，用于对第二中间采样奇信号和第三中间采样奇信号进行或运算，得到第四中间采样奇信号；
第一与门470，用于对第四中间采样奇信号和第一时钟延时奇信号进行与运算，得到第一片选时钟奇信号。
需要说明的是，在第一逻辑电路621中，第五采样电路465可以是由第五触发器和第三反相器组成，第六采样电路468可以是由第六触发器组成；其中，第五触发器和第六触发器均可以为D型触发器。另外，还需要注意的是，对于第五采样电路465而言，也可以不设置第三反相器，那么后续的逻辑运算则需进行相应调整，例如将第一或非门466调整为或门，从而也能够达到相同效果。
具体来说，在图7中，第五触发器的输入端与待处理片选偶信号连接，第五触发器的时钟端与第一时钟延时奇信号连接，第五触发器的输出端与第三反相器的输入端连接，第三反相器的输出端用于输出第一中间采样奇信号；第一或非门466的一个输入端与第三反相器的输出端连接，第一或非门466的另一个输入端用于接收待处理片选奇信号，第一或非门466的输出端用于输出第二中间采样奇信号，而且第一或非门466的输出端与第六触发器的输入端连接，第六触发器的时钟端与第一非门467的输出端连接，第一非门467的输入端用于接收第一时钟延时奇信号；第六触发器的输出端用于输出第三中间采样奇信号，而且第六触发器的输出端与第一或门469的一个输入端连接，第一或门469的另一个输入端用于接收第二中间采样奇信号，第一或门469的输出端用于输出第四中间采样奇信号，而且第一或门469的输出端与第一与门470的一个输入端连接，第一与门470的另一个输入端用于接收第一时钟延时奇信号，第一与门470的输出端用于输出第一片选时钟奇信号。
还需要说明的是，在本公开实施例中，待处理片选偶信号用PCS_E表示；经过第五采样电路465输出的第一中间采样奇信号可以用PCSB_O表示，经过第一或非门466输出的第二中间采样奇信号可以用PCS_OEN1表示，经过第六采样电路468输出的第三中间采样奇信号可以用PCS_OEN2表示，经过第一或门469输出的第四中间采样奇信号可以用PCS_OEN表示，经过第一与门470输出的第一片选时钟奇信号可以用2T_CLK_O表示。
在另一种具体的实施例中，如图7所示，第二逻辑电路622可以包括第七采样电路471、第二或非门472、第二非门473、第八采样电路474、第二或门475和第二与门476；其中，
第七采样电路471，用于利用第一时钟延时偶信号对待处理片选奇信号进行采样及反相处理，得到第一中间采样偶信号；
第二或非门472，用于对第一中间采样偶信号和待处理片选偶信号进行或非运算，得到第二中间采样偶信号；
第二非门473，用于对第一时钟延时偶信号进行非运算，得到第一反相时钟偶信号；
第八采样电路474，用于利用第一反相时钟偶信号对第二中间采样偶信号进行采样处理，得到第三中间采样偶信号；
第二或门475，用于对第二中间采样偶信号和第三中间采样偶信号进行或运算，得到第四中间采样偶信号；
第二与门476，用于对第四中间采样偶信号和第一时钟延时偶信号进行与运算，得到第一片选时钟偶信号。
需要说明的是，在第二逻辑电路622中，第七采样电路471可以是由第七触发器和第四反相器组成，第八采样电路474可以是由第八触发器组成；其中，第七触发器和第八触发器均可以为D型触发器。另外，还需要注意的是，对于第七采样电路471而言，也可以不设置第四反相器，那么后续的逻辑运算则需进行相应调整，例如将第二或非门472调整为或门，从而也能够达到相同效果。
具体来说，在图7中，第七触发器的输入端与待处理片选奇信号连接，第七触发器的时钟端与第一时钟延时偶信号连接，第七触发器的输出端与第四反相器的输入端连接，第四反相器的输出端用于输出第一中间采样偶信号；第二或非门472的一个输入端与第四反相器的输出端连接，第二或非门472的另一个输入端用于接收待处理片选偶信号，第二或非门472的输出端用于输出第二中间采样偶信号，而且第二或非门472的输出端与第八触发器的输入端连接，第八触发器的时钟端与第二非门473的输出端连接，第二非门473的输入端用于接收第一时钟延时偶信号；第八触发器的输出端用于输出第三中间采样偶信号，而且第八触发器的输出端与第二或门475的一个输入端连接，第二或门475的另一个输入端用于接收第二中间采样偶信号，第二或门475的输出端用于输出第四中间采样偶信号，而且第二或门475的输出端与第二与门476的一个输入端连接，第二与门476的另一个输入端用于接收第一时钟延时偶信号，第二与门476的输出端用于输出第一片选时钟偶信号。
还需要说明的是，在本公开实施例中，待处理片选奇信号用PCS_O表示；经过第七采样电路471输出的第一中间采样偶信号可以用PCSB_E表示，经过第二或非门472输出的第二中间采样偶信号可以用PCS_EEN1表示，经过第八采样电路474输出的第三中间采样偶信号可以用PCS_EEN2表示，经过第二或门475输出的第四中间采样偶信号可以用PCS_EEN表示，经过第二与门476输出的第一片选时钟偶信号可以用2T_CLK_E表示。
可以理解，对于第一逻辑电路621而言，第五采样电路465可以看作上升沿采样电路，即利用第一时钟延时奇信号的上升沿进行采样处理；而第一非门467和第六采样电路468可以看作下降沿采样电路，即利用第一时钟延时奇信号的下降沿进行采样处理；对于第二逻辑电路622而言，第七采样电路471可 以看作上升沿采样电路，即利用第一时钟延时偶信号的上升沿进行采样处理；而第二非门473和第八采样电路474可以看作下降沿采样电路，即利用第一时钟延时偶信号的下降沿进行采样处理。也就是说，在本公开实施例中，通过采用一级上升沿采样电路和一级下降沿采样电路连续采样PCS_E/PCS_O信号，然后通过或逻辑来增加片选信号的高电平脉冲宽度，从而可以产生具有两个脉冲的2T_CLK_O/2T_CLK_E信号。
具体来说，在本公开实施例中，第一或门469、第二或门475均具有拓宽信号脉冲宽度的作用。其中，以第一或门469为例，PCS_OEN1信号的脉冲宽度为预设时钟周期的两倍，PCS_OEN2信号的脉冲宽度也为预设时钟周期的两倍，但是相比PCS_OEN1信号延迟一个预设时钟周期；这样，通过第一或门469对PCS_OEN1信号和PCS_OEN2信号进行或运算，可以得到PCS_OEN信号，而且脉冲宽度为预设时钟周期的三倍；然后通过第一与门470对PCS_OEN信号和PCLK_OO信号进行与运算，可以得到具有两个脉冲的2T_CLK_O信号，而且每个脉冲的脉冲宽度为一个预设时钟周期。同理，第二或门475输出的PCS_EEN信号，而且脉冲宽度也为预设时钟周期的三倍；然后通过第二与门476对PCS_EEN信号和PCLK_EE信号进行与运算，可以得到具有两个脉冲的2T_CLK_E信号，而且每个脉冲的脉冲宽度为一个预设时钟周期。
这样，当第一片选信号的脉冲宽度为预设时钟周期时，这时候通过第一逻辑电路621对PCS_E信号进行两级采样和逻辑运算处理，可以得到2T_CLK_O信号；通过第二逻辑电路622对PCS_O信号进行两级采样和逻辑运算处理，可以得到2T_CLK_E信号；然后根据2T_CLK_O信号和2T_CLK_E信号，能够对应译码的目标指令信号为2T CMD信号。
在一些实施例中，在图6所示信号采样电路60的基础上，如图7所示，第二指令采样电路63可以包括第三逻辑电路631和第四逻辑电路632；其中，
第三逻辑电路631，用于接收第一时钟延时奇信号和待处理片选偶信号，并利用第一时钟延时奇信号对待处理片选偶信号进行两级采样及逻辑运算，得到第二片选时钟奇信号；
第四逻辑电路632，用于接收第一时钟延时偶信号和待处理片选奇信号，并利用第一时钟延时偶信号对待处理片选奇信号进行两级采样及逻辑运算，得到第二片选时钟偶信号；
在这里，第二片选时钟信号可以是由第二片选时钟偶信号和第二片选时钟奇信号组成。其中，第二片选时钟偶信号可以用NT_CLK_E表示，第二片选时钟奇信号可以用NT_CLK_O表示。
在一种具体的实施例中，如图7所示，第三逻辑电路631可以包括第九采样电路477、第三非门478、第三或非门479、第四非门480、第十采样电路481、第三或门482和第三与门483；其中，
第九采样电路477，用于利用第一时钟延时奇信号对待处理片选偶信号进行采样及反相处理，得到第五中间采样奇信号；
第三非门478，用于对待处理片选奇信号进行非运算，得到第二片选反相奇信号；
第三或非门479，用于对第五中间采样奇信号和第二片选反相奇信号进行或非运算，得到第六中间采样奇信号；
第四非门480，用于对第一时钟延时奇信号进行非运算，得到第二反相时钟奇信号；
第十采样电路481，用于利用第二反相时钟奇信号对第六中间采样奇信号进行采样处理，得到第七中间采样奇信号；
第三或门482，用于对第六中间采样奇信号和第七中间采样奇信号进行或运算，得到第八中间采样奇信号；
第三与门483，用于对第八中间采样奇信号和第一时钟延时奇信号进行与运算，得到第二片选时钟奇信号。
需要说明的是，在第三逻辑电路631中，第九采样电路477可以是由第九触发器和第五反相器组成，第十采样电路481可以是由第十触发器组成；其中，第九触发器和第十触发器均可以为D型触发器。另外，还需要注意的是，对于第九采样电路477而言，也可以不设置第五反相器，那么后续的逻辑运算则需进行相应调整，例如去掉第三非门478，并将第三或非门479调整为或门，从而也能够达到相同效果。
具体来说，在图7中，第九触发器的输入端与待处理片选偶信号连接，第九触发器的时钟端与第一时钟延时奇信号连接，第九触发器的输出端与第五反相器的输入端连接，第五反相器的输出端用于输出第五中间采样奇信号；第三或非门479的一个输入端与第五反相器的输出端连接，第三或非门479的另一个输入端与第三非门478的输出端连接，第三非门478的输入端用于接收待处理片选奇信号，第三或非门479的输出端用于输出第六中间采样奇信号，而且第三或非门479的输出端与第十触发器的输入端连接，第十触发器的时钟端与第四非门480的输出端连接，第四非门480的输入端用于接收第一时钟延时奇信号；第十触发器的输出端用于输出第七中间采样奇信号，而且第十触发器的输出端与第三或门482的一个输入端连接，第三或门482的另一个输入端用于接收第六中间采样奇信号，第三或门482的输出端用于输出第八中间采样奇信号，而且第三或门482的输出端与第三与门483的一个输入端连接，第三与门483的另一个输入端用于接收第一时钟延时奇信号，第三与门483的输出端用于输出第二片选时钟奇信号。
还需要说明的是，在本公开实施例中，待处理片选偶信号用PCS_E表示；经过第九采样电路477输出的第五中间采样奇信号可以用PCSB_O表示，经过第三或非门479输出的第六中间采样奇信号可以用NT_PCS_OEN1表示，经过第十采样电路481输出的第七中间采样奇信号可以用NT_PCS_OEN2表示，经过第三或门482输出的第八中间采样奇信号可以用NT_PCS_OEN表示，经过第三与门483输出的第二片选时钟奇信号可以用NT_CLK_O表示。
在另一种具体的实施例中，如图7所示，第四逻辑电路632可以包括第十一采样电路484、第五非门485、第四或非门486、第六非门487、第十二采样电路488、第四或门489和第四与门490；其中，
第十一采样电路484，用于利用第一时钟延时偶信号对待处理片选奇信号进行采样及反相处理，得到第五中间采样偶信号；
第五非门485，用于对待处理片选偶信号进行非运算，得到第二片选反相偶信号；
第四或非门486，用于对第五中间采样偶信号和第二片选反相偶信号进行或非运算，得到第六中间采样偶信号；
第六非门487，用于对第一时钟延时偶信号进行非运算，得到第二反相时钟偶信号；
第十二采样电路488，用于利用第二反相时钟偶信号对第六中间采样偶信号进行采样处理，得到第七中间采样偶信号；
第四或门489，用于对第六中间采样偶信号和第七中间采样偶信号进行或运算，得到第八中间采样偶信号；
第四与门490，用于对第八中间采样偶信号和第一时钟延时偶信号进行与运算，得到第二片选时钟偶信号。
需要说明的是，在第四逻辑电路632中，第十一采样电路484可以是由第十一触发器和第六反相器组成，第十二采样电路488可以是由第十二触发器组成；其中，第十一触发器和第十二触发器均可以为D型触发器。另外，还需要注意的是，对于第十一采样电路484而言，也可以不设置第六反相器，那么后续的逻辑运算则需进行相应调整，例如去掉第五非门485，并将第四或非门486调整为或门，从而也能够达到相同效果。
具体来说，在图7中，第十一触发器的输入端与待处理片选奇信号连接，第十一触发器的时钟端与第一时钟延时偶信号连接，第十一触发器的输出端与第六反相器的输入端连接，第六反相器的输出端用于输出第五中间采样偶信号；第四或非门486的一个输入端与第六反相器的输出端连接，第四或非门486的另一个输入端与第五非门485的输出端连接，第五非门485的输入端用于接收待处理片选偶信号，第四或非门486的输出端用于输出第六中间采样偶信号，而且第四或非门486的输出端与第十二触发器的输入端连接，第十二触发器的时钟端与第六非门487的输出端连接，第六非门487的输入端用于接收第一时钟延时偶信号；第十二触发器的输出端用于输出第七中间采样偶信号，而且第十二触发器的输出端与第四或门489的一个输入端连接，第四或门489的另一个输入端用于接收第六中间采样偶信号，第四或门489的输出端用于输出第八中间采样偶信号，而且第四或门489的输出端与第四与门490的一个输入端连接，第四与门490的另一个输入端用于接收第一时钟延时偶信号，第四与门490的输出端用于输出第二片选时钟偶信号。
还需要说明的是，在本公开实施例中，待处理片选奇信号用PCS_O表示；经过第十一采样电路484输出的第五中间采样偶信号可以用PCSB_E表示，经过第四或非门486输出的第六中间采样偶信号可以用NT_PCS_EEN1表示，经过第十二采样电路488输出的第七中间采样偶信号可以用NT_PCS_EEN2表示，经过第四或门489输出的第八中间采样偶信号可以用NT_PCS_EEN表示，经过第四与门490输出的第二片选时钟偶信号可以用NT_CLK_E表示。
还可以理解，对于第三逻辑电路631而言，第九采样电路477可以看作上升沿采样电路，即利用第一时钟延时奇信号的上升沿进行采样处理；而第四非门480和第十采样电路481可以看作下降沿采样电路，即利用第一时钟延时奇信号的下降沿进行采样处理；对于第四逻辑电路632而言，第十一采样电路484可以看作上升沿采样电路，即利用第一时钟延时偶信号的上升沿进行采样处理；而第六非门487和第十二采样电路488可以看作下降沿采样电路，即利用第一时钟延时偶信号的下降沿进行采样处理。也就是说，在本公开实施例中，通过采用一级上升沿采样电路和一级下降沿采样电路连续采样PCS_E/PCS_O信号，然后通过或逻辑来增加片选信号的高电平脉冲宽度，从而可以产生具有两个脉冲的NT_CLK_O/NT_CLK_E信号。
也就是说，第三或门482、第四或门489均具有拓宽信号脉冲宽度的作用。其中，以第三或门482为例，NT_PCS_OEN1信号的脉冲宽度为预设时钟周期的两倍，NT_PCS_OEN2信号的脉冲宽度也为预设时钟周期的两倍，但是相比NT_PCS_OEN1信号延迟一个预设时钟周期；这样，通过第三或门482对NT_PCS_OEN1信号和NT_PCS_OEN2信号进行或运算，可以得到NT_PCS_OEN信号，而且脉冲宽度为预设时钟周期的三倍；然后通过第三与门483对NT_PCS_OEN信号和PCLK_OO信号进行与运算，可以得到具有两个脉冲的NT_CLK_O信号，而且每个脉冲的脉冲宽度为一个预设时钟周期。同理，第四或门489输出的NT_PCS_EEN信号，而且脉冲宽度也为预设时钟周期的三倍；然后通过第四与门490对NT_PCS_EEN信号和PCLK_EE信号进行与运算，可以得到具有两个脉冲的NT_CLK_E信号，而且每个脉冲的脉冲宽度为一个预设时钟周期。
这样，当第一片选信号的脉冲宽度为预设时钟周期的两倍时，这时候通过第三逻辑电路631对PCS_E信号进行两级采样和逻辑运算处理，可以得到NT_CLK_O信号；通过第四逻辑电路632对PCS_O信号进行两级采样和逻辑运算处理，可以得到NT_CLK_E信号；然后根据NT_CLK_O信号和NT_CLK_E信号，能够对应译码的目标指令信号为NT ODT CMD信号。
在一些实施例中，在图6所示信号采样电路60的基础上，如图7所示，指令译码电路64可以包括第一指令译码电路641和第二指令译码电路642；其中，
第一指令译码电路641，用于接收第一片选时钟信号，根据第一片选时钟信号和待处理片选信号对待处理指令信号进行译码和采样处理，得到第一目标指令信号；
第二指令译码电路642，用于接收第二片选时钟信号，根据第二片选时钟信号和待处理片选信号对待处理指令信号进行译码和采样处理，得到第二目标指令信号。
在本公开实施例中，第一目标指令信号为DDR5DRAM芯片中的Command信号，由于该信号的有效脉冲持续两个时钟周期，可简称为2T CMD信号；其中，Command信号包括读命令信号、写命令信号、 刷新命令信号、预充电命令信号和激活命令信号；第二目标指令信号为DDR5DRAM芯片中的Non-Target ODT Command信号，可简称为NT ODT CMD信号。
可以理解地，在一些实施例中，初始片选信号可以是表征目标芯片被选中的信号，且初始片选信号为低电平有效的脉冲信号；其中，若初始片选信号的脉冲宽度为预设时钟周期，则确定第一片选时钟信号为有效脉冲信号，将经由第一指令译码电路输出的第一目标指令信号确定为目标指令信号；若初始片选信号的脉冲宽度为预设时钟周期的两倍，则确定第二片选时钟信号为有效脉冲信号，将经由第二指令译码电路输出的第二目标指令信号确定为目标指令信号。
需要说明的是，在本公开实施例中，当初始片选信号的脉冲宽度为预设时钟周期时，这时候确定出的是第一片选时钟信号，具体包括2T_CLK_E信号和2T_CLK_O信号；然后利用2T_CLK_E信号/2T_CLK_O信号，通过第一指令译码电路641可以得到第一目标指令信号为2T CMD信号。
还需要说明的是，在本公开实施例中，当初始片选信号的脉冲宽度为预设时钟周期的两倍时，这时候确定出的是第二片选时钟信号，具体包括NT_CLK_E信号和NT_CLK_O信号；然后利用NT_CLK_E信号/NT_CLK_O信号，通过第二指令译码电路642可以得到第二目标指令信号为NT ODT CMD信号。
在一种具体的实施例中，对于第一指令译码电路641而言，如图7所示，第一指令译码电路641可以包括第一译码采样电路491和第五或门492；其中，
第一译码采样电路491，用于根据第一片选时钟奇信号和待处理片选偶信号对待处理指令偶信号进行译码和采样处理，得到第一指令偶信号；以及根据第一片选时钟偶信号和待处理片选奇信号对待处理指令奇信号进行译码和采样处理，得到第一指令奇信号；
第五或门492，用于对第一指令偶信号和第一指令奇信号进行或运算，得到第一目标指令信号。
需要说明的是，在本公开实施例中，这里的第一译码采样电路491又可称为指令译码触发器，用CMD DEC DFF表示。第一译码采样电路的输出包括第一指令偶信号和第一指令奇信号；其中，第一指令偶信号用2T_CMD_E表示，第一指令奇信号用2T_CMD_O表示；然后再对2T_CMD_E信号和2T_CMD_O信号进行或运算之后得到第一目标指令信号为2T CMD信号。
还需要说明的是，在本公开实施例中，如图8A所示，第一译码采样电路491可以包括第一译码电路811、第十三采样电路812、第二译码电路813和第十四采样电路814；其中，
第一译码电路811，用于对待处理片选偶信号和待处理指令偶信号进行译码处理，得到第一译码偶信号；
第十三采样电路812，用于利用第一片选时钟奇信号对第一译码偶信号进行采样处理，得到第一指令偶信号；
第二译码电路813，用于对待处理片选奇信号和待处理指令奇信号进行译码处理，得到第一译码奇信号；
第十四采样电路814，用于利用第一片选时钟偶信号对第一译码奇信号进行采样处理，得到第一指令奇信号。
需要说明的是，在图8A中，待处理指令偶信号可以包括CA[0]_1T_E、CA[1]_1T_E、CA[2]_1T_E、CA[3]_1T_E、CA[4]_1T_E等5个信号，而且第一译码电路811可以是由三输入与非门、三输入与非门和二输入或非门组成。其中，PCS_E、CA[0]_1T_E和CA[1]_1T_E输入到第一个三输入与非门，CA[2]_1T_E、CA[3]_1T_E和CA[4]_1T_E输入到第二个三输入与非门，然后第一个三输入与非门的输出端和二输入或非门的一个输入端连接，第二个三输入与非门的输出端和二输入或非门的另一个输入端连接，而二输入或非门的输出端用于输出第一译码偶信号，从而实现对待处理片选偶信号和待处理指令偶信号的译码；在得到第一译码偶信号后，利用第十三采样电路812进行采样输出。具体地，第十三采样电路812可以为一个D型触发器，该D型触发器的时钟端与2T_CLK_O信号连接，D型触发器的输入端与二输入或非门的输出端连接，D型触发器的输出端用于输出2T_CMD_E信号。
还需要说明的是，在图8A中，待处理指令奇信号可以包括CA[0]_1T_O、CA[1]_1T_O、CA[2]_1T_O、CA[3]_1T_O、CA[4]_1T_O等5个信号，而且第二译码电路813可以是由三输入与非门、三输入与非门和二输入或非门组成。其中，PCS_O、CA[0]_1T_O和CA[1]_1T_O输入到第一个三输入与非门，CA[2]_1T_O、CA[3]_1T_O和CA[4]_1T_O输入到第二个三输入与非门，然后第一个三输入与非门的输出端和二输入或非门的一个输入端连接，第二个三输入与非门的输出端和二输入或非门的另一个输入端连接，而二输入或非门的输出端用于输出第一译码奇信号，从而实现对待处理片选偶信号和待处理指令偶信号的译码；在得到第一译码奇信号后，利用第十四采样电路814进行采样输出。具体地，第十四采样电路814也可以为一个D型触发器，该D型触发器的时钟端与2T_CLK_E信号连接，D型触发器的输入端与二输入或非门的输出端连接，D型触发器的输出端用于输出2T_CMD_O信号。
在另一种具体的实施例中，对于第二指令译码电路642而言，如图7所示，第二指令译码电路642可以包括第二译码采样电路493和第六或门494；其中，
第二译码采样电路493，用于根据第二片选时钟奇信号和待处理片选偶信号对待处理指令偶信号进行译码和采样处理，得到第二指令偶信号；以及根据第二片选时钟偶信号和待处理片选奇信号对待处理指令奇信号进行译码和采样处理，得到第二指令奇信号；
第六或门494，用于对第二指令偶信号和第二指令奇信号进行或运算，得到第二目标指令信号。
需要说明的是，在本公开实施例中，这里的第二译码采样电路493也可称为指令译码触发器，用CMD DEC DFF表示。第二译码采样电路的输出包括第二指令偶信号和第二指令奇信号；其中，第二指令偶信号用NT_CMD_E表示，第二指令奇信号用NT_CMD_O表示；然后再对NT_CMD_E信号和NT_CMD_O信号进行或运算之后得到第二目标指令信号为NT ODT CMD信号。
还需要说明的是，在本公开实施例中，如图8B所示，第二译码采样电路493可以包括第三译码电 路815、第十五采样电路816、第四译码电路817和第十六采样电路818；其中，
第三译码电路815，用于对待处理片选偶信号和待处理指令偶信号进行译码处理，得到第二译码偶信号；
第十五采样电路816，用于利用第二片选时钟奇信号对第二译码偶信号进行采样处理，得到第二指令偶信号；
第四译码电路817，用于对待处理片选奇信号和待处理指令奇信号进行译码处理，得到第二译码奇信号；
第十六采样电路818，用于利用第二片选时钟偶信号对第二译码奇信号进行采样处理，得到第二指令奇信号。
需要说明的是，在图8B中，第三译码电路815与第一译码电路811的输入信号相同，根据第三译码电路815得到第二译码偶信号后，利用第十五采样电路816进行采样输出。具体地，第十五采样电路816可以为一个D型触发器，该D型触发器的时钟端与NT_CLK_O信号连接，D型触发器的输入端与二输入或非门的输出端连接，D型触发器的输出端用于输出NT_CMD_E信号。
还需要说明的是，在图8B中，第四译码电路817与第二译码电路813的输入信号相同，根据第四译码电路817得到第二译码奇信号后，利用第十六采样电路818进行采样输出。具体地，第十六采样电路818也可以为一个D型触发器，该D型触发器的时钟端与NT_CLK_E信号连接，D型触发器的输入端与二输入或非门的输出端连接，D型触发器的输出端用于输出NT_CMD_O信号。
另外，需要注意的是，无论是第一译码电路811、第二译码电路813，还是第三译码电路815、第四译码电路817，这些译码电路的设计具体是根据指令译码规则实现的。对于不同的产品，不同的应用场景，不同的指令，译码规则可能不同，那么译码电路的逻辑也可进行相应调整，本公开实施例不作具体限定。
这样，通过增加第一指令采样电路62和第二指令采样电路63，由于两者使用的第一片选信号的脉冲宽度不同，可以输出2T_CLK_E/2T_CLK_O信号或者NT_CLK_E/NT_CLK_O信号；如此，当第一片选信号的脉冲宽度为预设时钟周期时，利用2T_CLK_E/2T_CLK_O信号，通过第一指令译码电路641得到的第一目标指令信号为有效信号(即高电平有效的脉冲信号)，通过第二指令译码电路642得到的第二目标指令信号为无效信号(即低电平信号)；反之，当第一片选信号的脉冲宽度为预设时钟周期的两倍时，利用NT_CLK_E/NT_CLK_O信号，通过第一指令译码电路641得到的第一目标指令信号为无效信号(即低电平信号)，通过第二指令译码电路642得到的第二目标指令信号为有效信号(即高电平有效的脉冲信号)；从而能够正确区分2T CMD和NT ODT CMD这两种信号，并进行准确译码。
也就是说，如果初始片选信号的脉冲宽度为预设时钟周期，那么在一种可能的实现方式中，若第一片选信号在偶数时钟周期的上升沿采样为低电平且在下一相邻奇数时钟周期的上升沿采样为高电平，则确定第一片选时钟奇信号为高电平有效的脉冲信号，且第一片选时钟奇信号具有两个脉冲；其中，第一片选时钟奇信号中第一个脉冲的上升沿用于产生第一目标指令信号的上升沿，第一片选时钟奇信号中第二个脉冲的上升沿用于产生第一目标指令信号的下降沿。
在另一种可能的实现方式中，若第一片选信号在奇数时钟周期的上升沿采样为低电平且在下一相邻偶数时钟周期的上升沿采样为高电平，则确定第一片选时钟偶信号为高电平有效的脉冲信号，且第一片选时钟偶信号具有两个脉冲；其中，第一片选时钟偶信号中第一个脉冲的上升沿用于产生第一目标指令信号的上升沿，第一片选时钟偶信号中第二个脉冲的上升沿用于产生第一目标指令信号的下降沿。
如果初始片选信号的脉冲宽度为预设时钟周期的两倍，那么在一种可能的实现方式中，若第一片选信号在偶数时钟周期的上升沿采样为低电平且在下一相邻奇数时钟周期的上升沿采样仍为低电平，则确定第二片选时钟奇信号为高电平有效的脉冲信号，且第二片选时钟奇信号具有两个脉冲；其中，第二片选时钟奇信号中第一个脉冲的上升沿用于产生第二目标指令信号的上升沿，第二片选时钟奇信号中第二个脉冲的上升沿用于产生第二目标指令信号的下降沿。
在另一种可能的实现方式中，若第一片选信号在奇数时钟周期的上升沿采样为低电平且在下一相邻偶数时钟周期的上升沿采样仍为低电平，则确定第二片选时钟偶信号为高电平有效的脉冲信号，且第二片选时钟偶信号具有两个脉冲；其中，第二片选时钟偶信号中第一个脉冲的上升沿用于产生第二目标指令信号的上升沿，第二片选时钟偶信号中第二个脉冲的上升沿用于产生第二目标指令信号的下降沿。
在这里，偶数时钟周期或者奇数时钟周期是指初始时钟信号(用CK_t/CK_c表示)的时钟周期。具体来说，经过第三接收电路453的分频处理之后，可以得到PCLK_E信号和PCLK_O信号；然后将PCLK_E信号的上升沿所在的时钟周期作为偶数时钟周期，PCLK_O信号的上升沿所在的时钟周期作为奇数时钟周期。另外，还需要注意的是，这里的“脉冲宽度为一个预设时钟周期”或者“脉冲宽度为预设时钟周期的两倍”均是指预设精度范围内，具体可以为该脉冲宽度和一个预设时钟周期之间的偏差在预设精度范围内，或者该脉冲宽度和预设时钟周期的两倍之间的偏差在预设精度范围内。
这样，由于无论是2T_CLK_E信号还是2T_CLK_O信号，其均包括两个脉冲，且每个脉冲的脉冲宽度是一个预设时钟周期，且第一个脉冲的上升沿用于产生第一目标指令信号的上升沿，第二个脉冲的上升沿用于产生第一目标指令信号的下降沿，从而使得最终输出的第一目标指令信号的脉冲宽度可以满足预设时钟周期的两倍；另外，由于无论是NT_CLK_E信号还是NT_CLK_O信号，其均包括两个脉冲，且每个脉冲的脉冲宽度是一个预设时钟周期，且第一个脉冲的上升沿用于产生第二目标指令信号的上升沿，第二个脉冲的上升沿用于产生第二目标指令信号的下降沿，从而使得最终输出的第二目标指令信号的脉冲宽度也可以满足预设时钟周期的两倍；如此，不仅能够避免目标指令信号的脉冲宽度不确定的问题，而且还能够区分2T CMD和NT ODT CMD这两种指令并进行准确译码，两者互不影响。
本公开实施例提供了一种信号采样电路，这样，基于该信号采样电路，不仅能够避免目标指令信号 的脉冲宽度不确定的问题，而且在第一片选信号的脉冲宽度不同情况下，根据所得到的第一片选时钟信号和第二片选时钟信号，还可以区分2T CMD和NT ODT CMD这两种指令并进行准确译码，而且互不影响，从而避免出现指令译码错误而执行错误操作的问题。
在本公开的另一实施例中，基于前述实施例所述的信号采样电路60，参见图9，其示出了本公开实施例提供的一种信号采样电路的详细结构示意图。如图9所示，信号采样电路60可以包括第一接收器911、第二接收器912、第三接收器913、第一触发器914、第二触发器915、第三触发器916、第一反相器917、第四触发器918、第二反相器919、第一缓冲器920、第二缓冲器921、第五触发器922、第三反相器923、第一或非门924、第一非门925、第六触发器926、第一或门927、第一与门928、第七触发器929、第四反相器930、第二或非门931、第二非门932、第八触发器933、第二或门934、第二与门935、第九触发器936、第五反相器937、第三非门938、第三或非门939、第四非门940、第十触发器941、第三或门942、第三与门943、第十一触发器944、第六反相器945、第五非门946、第四或非门947、第六非门948、第十二触发器949、第四或门950、第四与门951、第一指令译码触发器952、第五或门953、第二指令译码触发器954和第六或门955。其中，第一触发器914、第二触发器915、第三触发器916、第四触发器918、第五触发器922、第六触发器926、第七触发器929、第八触发器933、第九触发器936、第十触发器941、第十一触发器944、第十二触发器949均可以为D型触发器。另外，第一指令译码触发器952的具体结构详见图8A所示，第二指令译码触发器954的具体结构详见图8B所示。
需要说明的是，图9的组成结构与图7类似，故针对图9的描述可以参见前述图7的相关描述，这里不再详述。
其中，在2T CLK电路中，通过第五触发器922，利用PCLK_OO信号对PCS_E信号进行上升沿采样处理，然后经过第三反相器923可以得到PCSB_O信号；再通过第一或非门924对PCSB_O信号和PCS_O信号进行或非运算，得到PCS_OEN1信号；通过第一非门925和第六触发器926，利用PCLK_OO信号对PCS_OEN1信号进行下降沿采样处理，得到PCS_OEN2信号；通过第一或门927对PCS_OEN1信号和PCS_OEN2信号进行或运算，得到PCS_OEN；通过第一与门928对PCS_OEN信号和PCLK_OO信号进行与运算，得到2T_CLK_O信号；同理，通过第七触发器929，利用PCLK_EE信号对PCS_O信号进行上升沿采样处理，然后再经过第四反相器930、第二或非门931、第二非门932、第八触发器933以及第二或门934、第二与门935，可以得到2T_CLK_E信号。在这里，2T_CLK_O信号和2T_CLK_E信号之中至多存在一个有效信号。
在NT ODT CLK电路中，通过第九触发器936，利用PCLK_OO信号对PCS_E信号进行上升沿采样处理，然后经过第五反相器937可以得到PCSB_O信号；再通过第三非门938对PCS_O信号进行非运算，得到第二片选反相奇信号，然后通过第三或非门939对PCSB_O信号和第二片选反相奇信号进行或非运算，得到NT_PCS_OEN1信号；通过第四非门940和第十触发器941，利用PCLK_OO信号对NT_PCS_OEN1信号进行下降沿采样处理，得到NT_PCS_OEN2信号；通过第三或门942对NT_PCS_OEN1信号和NT_PCS_OEN2信号进行或运算，得到NT_PCS_OEN信号；通过第三与门943对NT_PCS_OEN信号和PCLK_OO信号进行与运算，得到NT_CLK_O信号。同理，通过第十一触发器944，利用PCLK_EE信号对PCS_O信号进行上升沿采样处理，然后经过第六反相器945可以得到PCSB_E信号；然后再通过第五非门946、第四或非门947、第六非门948和第十二触发器949以及第四或门950、第四与门951，可以得到NT_CLK_E信号。在这里，NT_CLK_O信号和NT_CLK_E信号之中至多存在一个有效信号。
最后，通过第一指令译码触发器952，利用2T_CLK_O信号和2T_CLK_E信号对CA[4:0]_1T_E信号、CA[4:0]_1T_O信号、PCS_E信号、PCS_O信号进行译码及采样处理，得到2T_CMD_E信号和2T_CMD_O信号，再通过第五或门953对2T_CMD_E信号和2T_CMD_O信号进行或逻辑运算，得到2T CMD信号。通过第二指令译码触发器954，利用NT_CLK_O信号和NT_CLK_E信号对CA[4:0]_1T_E信号、CA[4:0]_1T_O信号、PCS_E信号、PCS_O信号进行译码及采样处理，得到NT_CMD_E信号和NT_CMD_O信号，再通过第六或门955对NT_CMD_E信号和NT_CMD_O信号进行或逻辑运算，得到NT ODT CMD信号。
也就是说，本公开实施例通过采用一级上升沿触发器和一级下降沿触发器连续采样PCS_E信号/PCS_O信号，然后通过或逻辑来增加片选信号的高电平脉冲宽度，再与PLCK_OO/PLCK_EE信号进行与逻辑来产生具有两个脉冲的片选时钟信号，从而进行目标指令的采样。通过该信号采样电路60，无论是第一片选时钟信号还是第二片选时钟信号均包含了两个脉冲，且每个脉冲的脉冲宽度为一个预设时钟周期，然后利用该片选时钟信号来采样译码之后的指令。其中，一种情况下，本公开实施例通过对PCSB_O信号和PCS_O信号的或非逻辑来确定第一个时钟周期和第二个时钟周期的CS_n信号分别为低电平和高电平，可以确定待采样译码的指令为2T CMD，然后利用此逻辑覆盖的2T_CLK_O信号/2T_CLK_E信号进行指令采样译码，输出2T_CMD信号。另一种情况下，本公开实施例通过PCSB_O信号和PCS_O信号的非逻辑进行或非逻辑来确定第一个时钟周期和第二个时钟周期的CS_n信号都为低电平，可以确定待采样译码的指令为NT ODT CMD，然后利用此逻辑覆盖的NT_CLK_O信号/NT_CLK_E信号进行指令采样译码，输出NT ODT CMD信号。
基于图9所示的信号采样电路60，其对应的信号时序图如图10和图11所示。在图10和图11中，第一命令地址信号用CA表示，且CA可以包括Cy、Cz、C0、C1、C2和C3；初始片选信号用CS_n表示，第一片选信号用PCS表示，CS_n信号为低电平有效的脉冲信号，而且是用于表征目标芯片被选中的信号；初始时钟信号用CK_t表示，第一时钟偶信号用PCLK_E表示，第一时钟奇信号用PCLK_O表示，且CK_t信号的时钟周期为预设时钟周期，PCLK_E信号和PCLK_O信号的时钟周期均为预设时钟周期的两倍。
以PCLK_E信号的上升沿所在的时钟周期作为偶数时钟周期、以PCLK_O信号的上升沿所在的时钟周期作为奇数时钟周期为例，当PCS信号的脉冲宽度为预设时钟周期时，图10示出了本公开实施例提供的一种信号采样电路的信号时序示意图。如图10所示，在2T CLK电路中，利用PCLK_E信号的上升沿对CA信号进行采样处理后，得到CA[4:0]_1T_E信号包括C0和C2。在利用PCLK_E信号的上升沿对PCS信号进行采样及反相处理后，得到PCS_E信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍；这时候在利用PCLK_O信号的上升沿对PCS信号进行采样及反相处理后，得到PCS_O信号为低电平信号；然后在经过第五触发器922和第三反相器923对PCS_E信号进行上升沿采样及反相处理后，得到PCSB_O信号为低电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍，但是相比PCS_E信号延迟一个预设时钟周期；然后在通过第一或非门924对PCSB_O信号和PCS_O信号进行或非运算后，得到PCS_OEN1信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍；然后再通过第一非门925和第六触发器926对PCS_OEN1信号进行下降沿采样处理后，得到PCS_OEN2信号也为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍，但是相比PCS_OEN1信号延迟一个预设时钟周期；这样，通过第一或门927对PCS_OEN1信号和PCS_OEN2信号进行或运算，得到PCS_OEN信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的三倍，即第一或门927的作用是拓宽信号的脉冲宽度；然后再由第一与门928对PCS_OEN信号和PCLK_OO信号进行与运算，得到2T_CLK_O信号包括两脉冲，且每个脉冲的脉冲宽度为预设时钟周期；此时利用2T_CLK_O信号对CA[4:0]_1T_E信号进行译码采样，可以得到2T CMD信号，而且2T CMD信号为高电平有效的脉冲信号，且脉冲宽度为在预设精度范围内预设时钟周期的两倍；其中，2T_CLK_O信号中的第一个脉冲的上升沿用于产生2T CMD信号的上升沿，2T_CLK_O信号中的第二个脉冲的上升沿用于产生2T CMD信号的下降沿。然而，这种情况在NT ODT CLK电路中，在利用PCLK_E信号的上升沿对PCS信号进行采样及反相处理后，得到PCS_E信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍；在利用PCLK_O信号的上升沿对PCS信号进行采样及反相处理后，得到PCS_O信号为低电平信号；然后在经过第九触发器936和第五反相器937对PCS_E信号进行上升沿采样及反相处理后，得到PCSB_O信号为低电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍；但是在通过第三或非门939对PCSB_O信号和PCS_O的逻辑反信号进行或非运算后，得到NT_PCS_OEN1信号为低电平信号，然后在通过第一非门925和第六触发器926对NT_PCS_OEN1信号进行下降沿采样处理后，得到NT_PCS_OEN2信号也为低电平信号；这样，在通过第三或门942和第三与门943的逻辑运算后，得到NT_CLK_O信号为低电平信号，也就无法利用NT_CLK_O信号对CA[4:0]_1T_E信号进行译码采样，此时不会输出NT ODT CMD信号，从而可以区分2T CMD和NT ODT CMD这两种指令，并进行准确译码。
当PCS信号的脉冲宽度为预设时钟周期的两倍时，图11示出了本公开实施例提供的一种PCS信号在偶数时钟周期的上升沿采样为低电平且在相邻下一奇数时钟周期的上升沿采样为低电平时对应的信号时序示意图。如图11所示，在2T CLK电路中，利用PCLK_E信号的上升沿对CA信号进行采样处理后，得到CA[4:0]_1T_E信号包括C0和C2。在利用PCLK_E信号的上升沿对PCS信号进行采样及反相处理后，得到PCS_E信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍；在利用PCLK_O信号的上升沿对PCS信号进行采样及反相处理后，得到PCS_O信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍，但是相比PCS_E信号延迟一个预设时钟周期；然后在经过第五触发器922和第三反相器923对PCS_E信号进行上升沿采样及反相处理后，得到PCSB_O信号为低电平有效的脉冲信号，且与PCS_O信号互为反相信号；然后在通过第一或非门924对PCSB_O信号和PCS_O信号进行或非运算后，得到PCS_OEN1信号为低电平信号；然后再通过第一非门925和第六触发器926对PCS_OEN1信号进行下降沿采样处理后，得到PCS_OEN2信号为低电平信号；这样，在通过第一或门927和第一与门928的逻辑运算后，得到2T_CLK_O信号也为低电平信号，也就无法利用2T_CLK_O信号对CA[4:0]_1T_E信号进行译码采样，此时不会输出2T CMD信号。然而，这种情况在NT ODT CLK电路中，利用PCLK_E信号的上升沿对CA信号进行采样处理后，得到CA[4:0]_1T_E信号包括C0和C2。在利用PCLK_E信号的上升沿对PCS信号进行采样及反相处理后，得到PCS_E信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍；在利用PCLK_O信号的上升沿对PCS信号进行采样及反相处理后，得到PCS_O信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍，但是相比PCS_E信号延迟一个预设时钟周期；然后在经过第九触发器936和第五反相器937对PCS_E信号进行上升沿采样及反相处理后，得到PCSB_O信号为低电平有效的脉冲信号，且与PCS_O信号互为反相信号；但是在通过第三或非门939对PCSB_O信号和PCS_O的逻辑反信号进行或非运算后，得到NT_PCS_OEN1信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍，而且与PCS_O信号相比存在有少许延迟(该延迟是由第三非门938、第三或非门939等逻辑器件导致的，可忽略不计)；然后在通过第一非门925和第六触发器926对NT_PCS_OEN1信号进行下降沿采样处理后，得到NT_PCS_OEN2信号为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的两倍，但是相比NT_PCS_OEN1信号延迟一个预设时钟周期；这样，在通过第三或门942对NT_PCS_OEN1信号和NT_PCS_OEN2信号进行或运算，得到NT_PCS_OEN信号也为高电平有效的脉冲信号，且脉冲宽度为预设时钟周期的三倍，即第一或门927的作用是拓宽信号的脉冲宽度；然后再由第三与门943对NT_PCS_OEN信号和PCLK_OO信号进行与运算，得到NT_CLK_O信号包括两脉冲，且每个脉冲的脉冲宽度为预设时钟周期；此时利用NT_CLK_O信号对CA[4:0]_1T_E信号进行译码采样，可以得到NT ODT CMD信号，而且NT ODT CMD信号为高电平有效的脉冲信号，且脉冲宽度在预设精度范围内为预设时钟周期的两倍；其中，NT_CLK_O信号中的第一个脉冲的上升沿用于产生NT ODT CMD信号的上升沿，NT_CLK_O信号中的第二个脉冲的上升沿用于产生NT ODT CMD信号的下降沿，从而也可以正确区分2T CMD和NT ODT CMD这两种指令，并进行准确译码。
简单来说，通过本公开实施例所述的信号采样电路60，2T CMD信号和NT ODT CMD信号可以分别译码且相互不影响。其中，对于2T CMD信号，CS_n信号只有一个预设时钟周期的低电平，被PCLK_E信号采样后变为PCS_E信号，然后在PCLK_O采样后变为PCSB_O信号。其中，PCSB_O信号和PCS_O信号进行或非逻辑之后采样产生PCS_OEN1/2来覆盖产生2T_CLK_O信号。最后这个2T_CLK_O信号采样CA[4:0]_1T_E信号和PCS_E信号输出2T CMD信号。而另外一条分支电路是PCSB_O信号和(PCS_O信号的非逻辑，为高电平)进行或非逻辑，导致NT_PCS_OEN1/2均为低电平，而没有产生采样时钟，也就不会输出NT ODT CMD信号。
对于NT ODT CMD信号，CS_n信号具有2个预设时钟周期的低电平，分别被PCLK_E/O采样之后为PCS_E/O，然后PCS_E信号在PCLK_O采样之后为PCSB_O信号。PCSB_O信号和PCS_O信号进行或非逻辑正好相互抵消，导致PCS_OEN1/2均为低电平，而没有产生采样时钟，也就不会输出2T CMD信号。而另外一条分支电路是PCSB_O信号和(PCS_O信号的非逻辑，为低电平)进行或非逻辑，从而产生PCS_OEN1/2来覆盖产生具有两个脉冲的NT_CLK_O信号，最后这个NT_CLK_O信号采样CA[4:0]_1T_E信号和PCS_E信号输出NT ODT CMD信号。
此外，在本公开实施例中，图10和图11所提供的时序波形都是第一片选信号从偶数时钟周期开始的情况。具体来说，在初始片选信号的脉冲宽度为预设时钟周期的情况下，图10为第一片选信号在偶数时钟周期的上升沿采样为低电平且在下一相邻奇数时钟周期的上升沿采样为高电平的情况；在初始片选信号的脉冲宽度为预设时钟周期的两倍的情况下，图11为第一片选信号在偶数时钟周期的上升沿采样为低电平且在下一相邻奇数时钟周期的上升沿采样仍为低电平的情况。同理，奇数时钟周期的情况类似，这里不作详述。
本公开实施例提供了一种信号采样电路，通过本实施例对前述实施例的具体实现进行详细阐述，从中可以看出，基于本公开实施例的技术方案，不仅能够避免目标指令信号的脉冲宽度不确定的问题，而且在第一片选信号的脉冲宽度不同情况下，根据所得到的第一片选时钟信号和第二片选时钟信号，还可以区分2T CMD和NT ODT CMD这两种指令，并进行准确译码，而且互不影响，从而避免出现指令译码错误而执行错误操作的问题。
在本公开的又一实施例中，参见图12，其示出了本公开实施例提供的一种半导体存储器120的组成结构示意图。如图12所示，半导体存储器120可以包括前述实施例任一项所述的信号采样电路60。
在本公开实施例中，半导体存储器120可以为DRAM芯片。
进一步地，在一些实施例中，DRAM芯片符合DDR5内存规格。
需要说明的是，本公开实施例主要涉及集成电路设计中输入信号采样及指令译码的相关电路，特别涉及DRAM芯片中，CA信号输入分别作为指令和地址采样和译码之后的控制调节电路。具体来说，本公开实施例的技术方案解决了DDR5中区分2T CMD和NT ODT CMD采样译码的难题，使得可以根据CS_n信号的脉冲宽度不同来区分2T CMD信号和NT ODT CMD信号，并进行准确译码，而且互相不影响。
另外，还需要说明的是，本公开实施例的技术方案可以应用于DRAM芯片中CA信号采样和译码的控制电路，但不局限于此范围，其他输入信号采样及指令译码的相关电路均可采用此设计。
这样，在本公开实施例中，对于半导体存储器120而言，其包括有信号采样电路60，因此，不仅能够避免目标指令信号的脉冲宽度不确定的问题，而且在第一片选信号的脉冲宽度不同情况下，根据所得到的第一片选时钟信号和第二片选时钟信号，还可以区分2T CMD和NT ODT CMD这两种指令并进行准确译码，而且互不影响，从而避免出现指令译码错误而执行错误操作的问题。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种信号采样电路以及半导体存储器，基于该信号采样电路，在第一片选信号的脉冲宽度不同情况下，根据所得到的第一片选时钟信号和第二片选时钟信号，就可以正确区分2T CMD和NT ODT CMD这两种指令，并进行准确译码，而且互不影响，从而避免出现指令译码错误而执行错误操作的问题。

Claims (20)

  1. 一种信号采样电路，所述信号采样电路包括信号输入电路、第一指令采样电路、第二指令采样电路和指令译码电路；其中，
    所述信号输入电路，用于根据第一时钟信号、第一片选信号和第一命令地址信号，确定待处理指令信号和待处理片选信号；其中，所述第一时钟信号的时钟周期为预设时钟周期的两倍；
    所述第一指令采样电路，用于当所述第一片选信号的脉冲宽度为所述预设时钟周期时，根据所述第一时钟信号对所述待处理片选信号进行两级采样及逻辑运算处理，得到第一片选时钟信号；
    所述第二指令采样电路，用于当所述第一片选信号的脉冲宽度为所述预设时钟周期的两倍时，根据所述第一时钟信号对所述待处理片选信号进行两级采样及逻辑运算处理，得到第二片选时钟信号；
    所述指令译码电路，用于根据所述待处理片选信号和所述第一片选时钟信号对所述待处理指令信号进行译码和采样处理，得到目标指令信号；或者，根据所述待处理片选信号和所述第二片选时钟信号对所述待处理指令信号进行译码和采样处理，得到目标指令信号。
  2. 根据权利要求1所述的信号采样电路，其中，所述目标指令信号包括一个脉冲，且所述脉冲的脉冲宽度为所述预设时钟周期的两倍；其中，
    在所述第一片选信号的脉冲宽度为所述预设时钟周期的情况下，所述第一片选时钟信号包括两个脉冲，且每一个脉冲的脉冲宽度为所述预设时钟周期，以及所述第二片选时钟信号维持电平状态不变；其中，所述第一片选时钟信号中第一个脉冲的上升沿用于产生所述目标指令信号的上升沿，所述第一片选时钟信号中第二个脉冲的上升沿用于产生所述目标指令信号的下降沿；
    在所述第一片选信号的脉冲宽度为所述预设时钟周期的两倍的情况下，所述第一片选时钟信号维持电平状态不变；以及所述第二片选时钟信号包括两个脉冲，且每一个脉冲的脉冲宽度为所述预设时钟周期；其中，所述第二片选时钟信号中第一个脉冲的上升沿用于产生所述目标指令信号的上升沿，所述第二片选时钟信号中第二个脉冲的上升沿用于产生所述目标指令信号的下降沿。
  3. 根据权利要求1所述的信号采样电路，其中，所述信号输入电路包括接收电路和输入采样电路；其中，
    所述接收电路，用于接收初始命令地址信号、初始片选信号和初始时钟信号，输出所述第一命令地址信号、所述第一片选信号和所述第一时钟信号；
    所述输入采样电路，用于根据所述第一时钟信号对所述第一片选信号和所述第一命令地址信号进行采样处理，得到所述待处理片选信号和所述待处理指令信号；其中，所述初始时钟信号的时钟周期为所述预设时钟周期。
  4. 根据权利要求3所述的信号采样电路，其中，所述接收电路包括第一接收电路、第二接收电路和第三接收电路；其中，
    所述第一接收电路，用于接收所述初始命令地址信号，输出所述第一命令地址信号；
    所述第二接收电路，用于接收所述初始片选信号，输出所述第一片选信号；
    所述第三接收电路，用于接收所述初始时钟信号，并对所述初始时钟信号进行分频处理，输出第一时钟奇信号和第一时钟偶信号；其中，所述第一时钟信号是由所述第一时钟奇信号和所述第一时钟偶信号组成，所述第一时钟奇信号和所述第一时钟偶信号各自的时钟周期均是所述预设时钟周期的两倍，且所述第一时钟奇信号和所述第一时钟偶信号之间的相位差为180度。
  5. 根据权利要求4所述的信号采样电路，其中，所述输入采样电路包括第一采样电路、第二采样电路、第三采样电路和第四采样电路；其中，
    所述第一采样电路，用于根据所述第一时钟偶信号对所述第一命令地址信号进行采样处理，得到待处理指令偶信号；
    所述第二采样电路，用于根据所述第一时钟奇信号对所述第一命令地址信号进行采样处理，得到待处理指令奇信号；
    所述第三采样电路，用于根据所述第一时钟偶信号对所述第一片选信号进行采样及反相处理，得到待处理片选偶信号；
    所述第四采样电路，用于根据所述第一时钟奇信号对所述第一片选信号进行采样及反相处理，得到待处理片选奇信号；
    其中，所述待处理指令信号是由所述待处理指令偶信号和所述待处理指令奇信号组成，所述待处理片选信号是由所述待处理片选偶信号和所述待处理片选奇信号组成。
  6. 根据权利要求5所述的信号采样电路，其中，
    所述第一采样电路包括第一触发器，且所述第一触发器的输入端与所述第一命令地址信号连接，所述第一触发器的时钟端与所述第一时钟偶信号连接，所述第一触发器的输出端用于输出所述待处理指令偶信号；
    所述第二采样电路包括第二触发器，且所述第二触发器的输入端与所述第一命令地址信号连接，所述第二触发器的时钟端与所述第一时钟奇信号连接，所述第二触发器的输出端用于输出所述待处理指令奇信号；
    所述第三采样电路包括第三触发器和第一反相器，且所述第三触发器的输入端与所述第一片选信号连接，所述第三触发器的时钟端与所述第一时钟偶信号连接，所述第三触发器的输出端与所述第一反相器的输入端连接，所述第一反相器的输出端用于输出所述待处理片选偶信号；
    所述第四采样电路包括第四触发器和第二反相器，且所述第四触发器的输入端与所述第一片选信号连接，所述第四触发器的时钟端与所述第一时钟奇信号连接，所述第四触发器的输出端与所述第二反相器的输入端连接，所述第二反相器的输出端用于输出所述待处理片选奇信号。
  7. 根据权利要求5所述的信号采样电路，其中，所述信号采样电路还包括第一缓冲器和第二缓冲器；其中，
    所述第一缓冲器，用于对所述第一时钟偶信号进行延时处理，得到第一时钟延时偶信号；
    所述第二缓冲器，用于对所述第一时钟奇信号进行延时处理，得到第一时钟延时奇信号。
  8. 根据权利要求7所述的信号采样电路，其中，所述第一指令采样电路包括第一逻辑电路和第二逻辑电路；其中，
    所述第一逻辑电路，用于接收所述第一时钟延时奇信号和所述待处理片选偶信号，并利用所述第一时钟延时奇信号对所述待处理片选偶信号进行两级采样及逻辑运算，得到第一片选时钟奇信号；
    所述第二逻辑电路，用于接收所述第一时钟延时偶信号和所述待处理片选奇信号，并利用所述第一时钟延时偶信号对所述待处理片选奇信号进行两级采样及逻辑运算，得到第一片选时钟偶信号；
    其中，所述第一片选时钟信号是由所述第一片选时钟偶信号和所述第一片选时钟奇信号组成。
  9. 根据权利要求8所述的信号采样电路，其中，
    所述第一逻辑电路包括第五采样电路、第一或非门、第一非门、第六采样电路、第一或门和第一与门；其中，
    所述第五采样电路，用于利用所述第一时钟延时奇信号对所述待处理片选偶信号进行采样及反相处理，得到第一中间采样奇信号；
    所述第一或非门，用于对所述第一中间采样奇信号和所述待处理片选奇信号进行或非运算，得到第二中间采样奇信号；
    所述第一非门，用于对所述第一时钟延时奇信号进行非运算，得到第一反相时钟奇信号；
    所述第六采样电路，用于利用所述第一反相时钟奇信号对所述第二中间采样奇信号进行采样处理，得到第三中间采样奇信号；
    所述第一或门，用于对所述第二中间采样奇信号和所述第三中间采样奇信号进行或运算，得到第四中间采样奇信号；
    所述第一与门，用于对所述第四中间采样奇信号和所述第一时钟延时奇信号进行与运算，得到所述第一片选时钟奇信号；
    所述第二逻辑电路包括第七采样电路、第二或非门、第二非门、第八采样电路、第二或门和第二与门；其中，
    所述第七采样电路，用于利用所述第一时钟延时偶信号对所述待处理片选奇信号进行采样及反相处理，得到第一中间采样偶信号；
    所述第二或非门，用于对所述第一中间采样偶信号和所述待处理片选偶信号进行或非运算，得到第二中间采样偶信号；
    所述第二非门，用于对所述第一时钟延时偶信号进行非运算，得到第一反相时钟偶信号；
    所述第八采样电路，用于利用所述第一反相时钟偶信号对所述第二中间采样偶信号进行采样处理，得到第三中间采样偶信号；
    所述第二或门，用于对所述第二中间采样偶信号和所述第三中间采样偶信号进行或运算，得到第四中间采样偶信号；
    所述第二与门，用于对所述第四中间采样偶信号和所述第一时钟延时偶信号进行与运算，得到所述第一片选时钟偶信号。
  10. 根据权利要求8所述的信号采样电路，其中，所述第二指令采样电路包括第三逻辑电路和第四逻辑电路；其中，
    所述第三逻辑电路，用于接收所述第一时钟延时奇信号和所述待处理片选偶信号，并利用所述第一时钟延时奇信号对所述待处理片选偶信号进行两级采样及逻辑运算，得到第二片选时钟奇信号；
    所述第四逻辑电路，用于接收所述第一时钟延时偶信号和所述待处理片选奇信号，并利用所述第一时钟延时偶信号对所述待处理片选奇信号进行两级采样及逻辑运算，得到第二片选时钟偶信号；
    其中，所述第二片选时钟信号是由所述第二片选时钟偶信号和所述第二片选时钟奇信号组成。
  11. 根据权利要求10所述的信号采样电路，其中，
    所述第三逻辑电路包括第九采样电路、第三非门、第三或非门、第四非门、第十采样电路、第三或门和第三与门；其中，
    所述第九采样电路，用于利用所述第一时钟延时奇信号对所述待处理片选偶信号进行采样及反相处理，得到第五中间采样奇信号；
    所述第三非门，用于对所述待处理片选奇信号进行非运算，得到第二片选反相奇信号；
    所述第三或非门，用于对所述第五中间采样奇信号和所述第二片选反相奇信号进行或非运算， 得到第六中间采样奇信号；
    所述第四非门，用于对所述第一时钟延时奇信号进行非运算，得到第二反相时钟奇信号；
    所述第十采样电路，用于利用所述第二反相时钟奇信号对所述第六中间采样奇信号进行采样处理，得到第七中间采样奇信号；
    所述第三或门，用于对所述第六中间采样奇信号和所述第七中间采样奇信号进行或运算，得到第八中间采样奇信号；
    所述第三与门，用于对所述第八中间采样奇信号和所述第一时钟延时奇信号进行与运算，得到所述第二片选时钟奇信号；
    所述第四逻辑电路包括第十一采样电路、第五非门、第四或非门、第六非门、第十二采样电路、第四或门和第四与门；其中，
    所述第十一采样电路，用于利用所述第一时钟延时偶信号对所述待处理片选奇信号进行采样及反相处理，得到第五中间采样偶信号；
    所述第五非门，用于对所述待处理片选偶信号进行非运算，得到第二片选反相偶信号；
    所述第四或非门，用于对所述第五中间采样偶信号和所述第二片选反相偶信号进行或非运算，得到第六中间采样偶信号；
    所述第六非门，用于对所述第一时钟延时偶信号进行非运算，得到第二反相时钟偶信号；
    所述第十二采样电路，用于利用所述第二反相时钟偶信号对所述第六中间采样偶信号进行采样处理，得到第七中间采样偶信号；
    所述第四或门，用于对所述第六中间采样偶信号和所述第七中间采样偶信号进行或运算，得到第八中间采样偶信号；
    所述第四与门，用于对所述第八中间采样偶信号和所述第一时钟延时偶信号进行与运算，得到所述第二片选时钟偶信号。
  12. 根据权利要求10所述的信号采样电路，其中，所述指令译码电路包括第一指令译码电路和第二指令译码电路；其中，
    所述第一指令译码电路，用于接收所述第一片选时钟信号，根据所述第一片选时钟信号和所述待处理片选信号对所述待处理指令信号进行译码和采样处理，得到第一目标指令信号；
    所述第二指令译码电路，用于接收所述第二片选时钟信号，根据所述第二片选时钟信号和所述待处理片选信号对所述待处理指令信号进行译码和采样处理，得到第二目标指令信号。
  13. 根据权利要求12所述的信号采样电路，其中，
    所述第一指令译码电路包括第一译码采样电路和第五或门；其中，
    所述第一译码采样电路，用于根据所述第一片选时钟奇信号和所述待处理片选偶信号对所述待处理指令偶信号进行译码和采样处理，得到第一指令偶信号；以及根据所述第一片选时钟偶信号和所述待处理片选奇信号对所述待处理指令奇信号进行译码和采样处理，得到第一指令奇信号；
    所述第五或门，用于对所述第一指令偶信号和所述第一指令奇信号进行或运算，得到所述第一目标指令信号；
    所述第二指令译码电路包括第二译码采样电路和第六或门；其中，
    所述第二译码采样电路，用于根据所述第二片选时钟奇信号和所述待处理片选偶信号对所述待处理指令偶信号进行译码和采样处理，得到第二指令偶信号；以及根据所述第二片选时钟偶信号和所述待处理片选奇信号对所述待处理指令奇信号进行译码和采样处理，得到第二指令奇信号；
    所述第六或门，用于对所述第二指令偶信号和所述第二指令奇信号进行或运算，得到所述第二目标指令信号。
  14. 根据权利要求13所述的信号采样电路，其中，
    所述第一译码采样电路包括第一译码电路、第十三采样电路、第二译码电路和第十四采样电路；其中，
    所述第一译码电路，用于对所述待处理片选偶信号和所述待处理指令偶信号进行译码处理，得到第一译码偶信号；
    所述第十三采样电路，用于利用所述第一片选时钟奇信号对所述第一译码偶信号进行采样处理，得到所述第一指令偶信号；
    所述第二译码电路，用于对所述待处理片选奇信号和所述待处理指令奇信号进行译码处理，得到第一译码奇信号；
    所述第十四采样电路，用于利用所述第一片选时钟偶信号对所述第一译码奇信号进行采样处理，得到所述第一指令奇信号；
    所述第二译码采样电路包括第三译码电路、第十五采样电路、第四译码电路和第十六采样电路；其中，
    所述第三译码电路，用于对所述待处理片选偶信号和所述待处理指令偶信号进行译码处理，得到第二译码偶信号；
    所述第十五采样电路，用于利用所述第二片选时钟奇信号对所述第二译码偶信号进行采样处理，得到所述第二指令偶信号；
    所述第四译码电路，用于对所述待处理片选奇信号和所述待处理指令奇信号进行译码处理，得到第二译码奇信号；
    所述第十六采样电路，用于利用所述第二片选时钟偶信号对所述第二译码奇信号进行采样处理，得到所述第二指令奇信号。
  15. 根据权利要求12所述的信号采样电路，其中，所述初始片选信号是表征目标芯片被选中的信号，且所述初始片选信号为低电平有效的脉冲信号；其中，
    若所述初始片选信号的脉冲宽度为所述预设时钟周期，则确定所述第一片选时钟信号为有效脉冲信号，将经由所述第一指令译码电路输出的所述第一目标指令信号确定为所述目标指令信号；
    若所述初始片选信号的脉冲宽度为所述预设时钟周期的两倍，则确定所述第二片选时钟信号为有效脉冲信号，将经由所述第二指令译码电路输出的所述第二目标指令信号确定为所述目标指令信号。
  16. 根据权利要求15所述的信号采样电路，其中，
    所述第一目标指令信号为DDR5 DRAM芯片中的Command信号；所述Command信号包括读命令信号，写命令信号，刷新命令信号，预充电命令信号，激活命令信号；
    所述第二目标指令信号为DDR5 DRAM芯片中的Non-Target ODT Command信号。
  17. 根据权利要求15所述的信号采样电路，其中，在所述初始片选信号的脉冲宽度为所述预设时钟周期的情况下，
    若所述第一片选信号在偶数时钟周期的上升沿采样为低电平且在下一相邻奇数时钟周期的上升沿采样为高电平，则确定所述第一片选时钟奇信号为高电平有效的脉冲信号，且所述第一片选时钟奇信号具有两个脉冲；其中，所述第一片选时钟奇信号中第一个脉冲的上升沿用于产生所述第一目标指令信号的上升沿，所述第一片选时钟奇信号中第二个脉冲的上升沿用于产生所述第一目标指令信号的下降沿；
    若所述第一片选信号在奇数时钟周期的上升沿采样为低电平且在下一相邻偶数时钟周期的上升沿采样为高电平，则确定所述第一片选时钟偶信号为高电平有效的脉冲信号，且所述第一片选时钟偶信号具有两个脉冲；其中，所述第一片选时钟偶信号中第一个脉冲的上升沿用于产生所述第一目标指令信号的上升沿，所述第一片选时钟偶信号中第二个脉冲的上升沿用于产生所述第一目标指令信号的下降沿。
  18. 根据权利要求15所述的信号采样电路，其中，在所述初始片选信号的脉冲宽度为所述预设时钟周期的两倍的情况下，
    若所述第一片选信号在偶数时钟周期的上升沿采样为低电平且在下一相邻奇数时钟周期的上升沿采样仍为低电平，则确定所述第二片选时钟奇信号为高电平有效的脉冲信号，且所述第二片选时钟奇信号具有两个脉冲；其中，所述第二片选时钟奇信号中第一个脉冲的上升沿用于产生所述第二目标指令信号的上升沿，所述第二片选时钟奇信号中第二个脉冲的上升沿用于产生所述第二目标指令信号的下降沿；
    若所述第一片选信号在奇数时钟周期的上升沿采样为低电平且在下一相邻偶数时钟周期的上升沿采样仍为低电平，则确定所述第二片选时钟偶信号为高电平有效的脉冲信号，且所述第二片选时钟偶信号具有两个脉冲；其中，所述第二片选时钟偶信号中第一个脉冲的上升沿用于产生所述第二目标指令信号的上升沿，所述第二片选时钟偶信号中第二个脉冲的上升沿用于产生所述第二目标指令信号的下降沿。
  19. 一种半导体存储器，包括如权利要求1至18任一项所述的信号采样电路。
  20. 根据权利要求19所述的半导体存储器，其中，所述半导体存储器为动态随机存取存储器DRAM芯片，且符合DDR5内存规格。
PCT/CN2022/091428 2022-03-23 2022-05-07 一种信号采样电路以及半导体存储器 WO2023178805A1 (zh)

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