WO2023178803A1 - 一种信号采样电路以及半导体存储器 - Google Patents

一种信号采样电路以及半导体存储器 Download PDF

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Publication number
WO2023178803A1
WO2023178803A1 PCT/CN2022/091111 CN2022091111W WO2023178803A1 WO 2023178803 A1 WO2023178803 A1 WO 2023178803A1 CN 2022091111 W CN2022091111 W CN 2022091111W WO 2023178803 A1 WO2023178803 A1 WO 2023178803A1
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Prior art keywords
signal
clock
chip select
odd
sampling
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PCT/CN2022/091111
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English (en)
French (fr)
Inventor
黄泽群
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长鑫存储技术有限公司
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Priority to US17/954,664 priority Critical patent/US20230017682A1/en
Publication of WO2023178803A1 publication Critical patent/WO2023178803A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/42—Out-of-phase gating or clocking signals applied to counter stages
    • H03K23/44—Out-of-phase gating or clocking signals applied to counter stages using field-effect transistors

Definitions

  • the present disclosure relates to the field of integrated circuit technology, and in particular, to a signal sampling circuit and a semiconductor memory.
  • DDR Double Data Rate
  • the input command address signal can be used as an address for sampling and as an instruction for sampling and decoding.
  • DRAM Dynamic Random Access Memory
  • the input command address signal is used as a command, sampling and decoding is required to obtain the decoded signal.
  • pulse width of the decoded signal may cause data failure and affect the performance of the semiconductor.
  • the present disclosure provides a signal sampling circuit and a semiconductor memory, which can improve the problem of uncertainty in the signal pulse width and improve the quality of the target command signal.
  • embodiments of the present disclosure provide a signal sampling circuit, which includes a signal input circuit, a clock receiving circuit, a sampling logic circuit and a decoding circuit; wherein,
  • the signal input circuit is used to determine the instruction signal to be processed and the chip select signal to be processed
  • the clock receiving circuit is used to receive an initial clock signal and perform frequency division processing on the initial clock signal to obtain a first clock signal; wherein the clock cycle of the initial clock signal is a preset clock cycle, and the third The clock period of a clock signal is twice the preset clock period;
  • the sampling logic circuit is used to perform two-level sampling processing and logical operation processing on the chip select signal to be processed according to the first clock signal to obtain a chip select clock signal; wherein the chip select clock signal includes two Pulse, and the width of each pulse is the preset clock period;
  • the decoding circuit is used to decode and sample the instruction signal to be processed according to the chip select signal to be processed and the chip select clock signal to obtain a target instruction signal.
  • the target command signal includes a pulse, and the width of the pulse is 2 times the preset clock cycle; wherein the rising edge of the first pulse in the chip select clock signal is used to generate The rising edge of the target command signal and the rising edge of the second pulse in the chip select clock signal are used to generate the falling edge of the target command signal.
  • the first clock signal includes an odd clock signal and an even clock signal; wherein,
  • the clock cycles of the odd clock signal and the even clock signal are both twice the preset clock cycle, and the phase difference between the odd clock signal and the even clock signal is 180 degrees.
  • the signal input circuit includes a first input circuit and a second input circuit; wherein,
  • the first input circuit is used to receive an initial command signal and output an intermediate command signal
  • the second input circuit is used to receive the initial chip select signal and output the intermediate chip select signal
  • the odd clock signal is used to perform sampling processing and inversion processing on the intermediate chip select signal to obtain an odd chip select signal to be processed
  • the even clock signal is used to perform sampling processing and inversion processing on the intermediate chip select signal. , get the chip selection signal to be processed
  • the instruction odd signal to be processed and the even instruction signal to be processed constitute the instruction signal to be processed
  • the chip select odd signal to be processed and the chip select even signal to be processed constitute the chip select signal to be processed.
  • the sampling logic circuit includes a first sampling circuit, a second sampling circuit, a first logic circuit and a second logic circuit; wherein,
  • the first sampling circuit is configured to use the odd clock signal to perform first-level sampling processing on the chip select even signal to be processed to obtain a first chip select sampling odd signal; and use the clock odd signal to The first chip selects and samples the odd signal for second-level sampling processing to obtain the second chip selects and samples the odd signal;
  • the second sampling circuit is configured to use the clock even signal to perform first-level sampling processing on the chip select odd signal to be processed to obtain a first chip select sampling even signal; and use the clock even signal to perform a first-level sampling process on the chip select odd signal to be processed.
  • the first chip selects and samples the even signal for the second level sampling processing to obtain the second chip selects and samples the even signal;
  • the first logic circuit is used to perform logical operations on the clock odd signal, the first chip select sample odd signal and the second chip select sample odd signal to obtain a chip select clock odd signal;
  • the second logic circuit is used to perform logical operations on the clock even signal, the first chip select sample even signal and the second chip select sample even signal to obtain a chip select clock even signal;
  • the chip select clock even signal and the chip select clock odd signal constitute the chip select clock signal.
  • the first-level sampling processing refers to rising edge sampling processing
  • the second-level sampling processing refers to falling edge sampling processing
  • the first sampling circuit includes a first flip-flop, a first NOT gate and a second flip-flop; wherein,
  • the input terminal of the first flip-flop is connected to the even selection signal of the chip to be processed, the clock terminal of the first flip-flop is connected to the odd clock signal, and the input terminal of the second flip-flop is connected to the third
  • the output terminal of a flip-flop is connected, the input terminal of the first NOT gate is connected to the clock odd signal, the output terminal of the first NOT gate is connected to the clock terminal of the second flip-flop, and the second The output terminal of the flip-flop is used to output the second chip selection odd signal.
  • the second sampling circuit includes a third flip-flop, a second NOT gate and a fourth flip-flop; wherein,
  • the input terminal of the third flip-flop is connected to the chip select odd signal to be processed, the clock terminal of the third flip-flop is connected to the clock even signal, and the input terminal of the fourth flip-flop is connected to the third flip-flop.
  • the output terminals of the three flip-flops are connected, the input terminal of the second NOT gate is connected with the clock even signal, the output terminal of the second NOT gate is connected with the clock terminal of the fourth flip-flop, and the fourth The output terminal of the flip-flop is used to output the second chip selection sampling even signal.
  • the first logic circuit includes a first OR gate and a first AND gate; wherein,
  • the first OR gate is used to perform an OR operation on the first chip selection sampling odd signal and the second chip selection sampling odd signal to obtain an intermediate odd signal;
  • the first AND gate is used to perform an AND operation on the intermediate odd signal and the clock odd signal to obtain the chip select clock odd signal.
  • the second logic circuit includes a second OR gate and a second AND gate; wherein,
  • the second OR gate is used to perform an OR operation on the first chip selection sampling even signal and the second chip selection sampling even signal to obtain an intermediate even signal;
  • the second AND gate is used to perform an AND operation on the intermediate even signal and the clock even signal to obtain the chip select clock even signal.
  • the decoding circuit includes a first instruction decoding circuit, a second instruction decoding circuit, and a third OR gate; wherein,
  • the first instruction decoding circuit is used to decode and sample the instruction even signal to be processed according to the chip select even signal to be processed and the chip select clock odd signal to obtain an instruction even signal;
  • the second instruction decoding circuit is used to decode and sample the instruction odd signal to be processed according to the chip select odd signal to be processed and the chip select clock even signal to obtain an instruction odd signal;
  • the third OR gate is used to perform an OR operation on the instruction even signal and the instruction odd signal to obtain the target instruction signal.
  • the first instruction decoding circuit includes a first decoding circuit and a third sampling circuit; wherein,
  • the first decoding circuit is used to decode the instruction even signal to be processed and the chip select even signal to be processed to obtain an instruction decoding even signal;
  • the third sampling circuit is used to sample the instruction decoding even signal according to the chip select clock odd signal to obtain the instruction even signal.
  • the second instruction decoding circuit includes a second decoding circuit and a fourth sampling circuit; wherein,
  • the second decoding circuit is used to decode the instruction odd signal to be processed and the chip select odd signal to be processed to obtain an instruction decoding odd signal;
  • the fourth sampling circuit is configured to perform sampling processing on the instruction decoding odd signal according to the even signal of the chip select clock to obtain the instruction odd signal.
  • the initial chip select signal is a signal indicating that the target chip is selected, and the initial chip select signal is an active low-level pulse signal;
  • the chip select even signal to be processed is a pulse signal with an active high level
  • the rising edge of the first pulse in the chip select clock odd signal is used to generate the rising edge of the target command signal, and the rising edge of the second pulse in the chip select clock odd signal is used to generate the falling edge of the target command signal. along.
  • the odd chip select signal to be processed is an active high level pulse signal
  • the rising edge of the first pulse in the chip select clock even signal is used to generate the rising edge of the target command signal, and the rising edge of the second pulse in the chip select clock even signal is used to generate the falling edge of the target command signal.
  • an embodiment of the present disclosure provides a semiconductor memory, including the signal sampling circuit as described in any one of the first aspects.
  • the semiconductor memory is a dynamic random access memory DRAM chip.
  • Embodiments of the present disclosure provide a signal sampling circuit and a semiconductor memory.
  • the signal sampling circuit includes a signal input circuit, a clock receiving circuit, a sampling logic circuit and a decoding circuit; wherein the signal input circuit is used to determine the instruction signal to be processed and The chip select signal to be processed; the clock receiving circuit is used to receive the initial clock signal and perform frequency division processing on the initial clock signal to obtain the first clock signal; wherein the clock cycle of the initial clock signal is the preset clock cycle, and the first clock The clock cycle of the signal is twice the preset clock cycle; the sampling logic circuit is used to perform two-level sampling processing and logical operation processing on the chip select signal to be processed according to the first clock signal to obtain the chip select clock signal; wherein, the chip select clock The signal includes two pulses, and the width of each pulse is a preset clock cycle; the decoding circuit is used to decode and sample the instruction signal to be processed according to the chip select signal to be processed and the chip select clock signal to obtain the target command signal.
  • the chip select clock signal after processing by the signal sampling circuit, includes two pulses, and the width of each pulse is a preset clock cycle, so that the pulse width of the target command signal after decoding and sampling will not follow the process, Changes in voltage, temperature, etc. produce deviations, which improves the problem of uncertain pulse width of the target command signal and prevents data failure.
  • Figure 1 is a schematic diagram of the signal timing of the two clock cycle commands
  • Figure 2 is a schematic structural diagram of a signal sampling circuit
  • Figure 3 is a schematic structural diagram of an instruction decoder
  • Figure 4 is a signal timing diagram of a signal sampling circuit
  • Figure 5 is a schematic structural diagram of a signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of another signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram of another signal sampling circuit provided by an embodiment of the present disclosure.
  • FIG. 8A is a schematic structural diagram of the first instruction decoding circuit provided by an embodiment of the present disclosure.
  • Figure 8B is a schematic structural diagram of the second instruction decoding circuit provided by an embodiment of the present disclosure.
  • Figure 9 is a detailed structural diagram of a signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 10 is a signal timing diagram of a signal sampling circuit provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that the terms “first ⁇ second ⁇ third” Where permitted, the specific order or sequence may be interchanged so that the embodiments of the disclosure described herein can be practiced in an order other than that illustrated or described herein.
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • Command address input (Command/Address, CMD/ADD or CA for short)
  • DFF Data Flip-Flop or Delay Flip-Flop
  • CA can be used as an address for sampling and as an instruction for sampling and decoding.
  • CA here is the collective name for various command address signals of DRAM, which can include row address strobe (RAS), column address strobe (Column Address Strobe, CAS), and write command (Write, WE).
  • RAS row address strobe
  • CAS Column address strobe
  • WE write command
  • ACT activation command
  • ACT Active
  • other command signals and may also include address signals from A13 to A0, etc.
  • the command address signal includes several address signals, which may be determined according to the specifications of the DRAM, and the embodiment of the present disclosure does not make any limitation.
  • CK_t and CK_c are a pair of complementary clock signals
  • CA[13:0] is the CA input
  • CMD is the command signal obtained after CA decoding
  • CS_n is the chip select signal indicating that CA is valid.
  • CA[13:0] is a signal that lasts for two clock cycles.
  • CA[13:0] of the first clock cycle and CA[13:0] of the second clock cycle need to be used as address signals.
  • CA[4:0] of the first clock cycle also needs to be sampled and decoded as a command signal.
  • the clock cycle refers to the clock cycle of CK_t/CK_c.
  • the part where CA is used as an instruction signal for sampling and decoding is mainly involved, and the part where CA is used for sampling and outputting an address signal is omitted, and no further description will be given.
  • the signal sampling decoding circuit includes a first receiver 101, a second receiver 102, a third receiver 103, a first flip-flop 104, a second flip-flop 105, a third flip-flop 106, An inverter 107, fourth flip-flop 108, second inverter 109, fifth flip-flop 110, sixth flip-flop 111, first buffer 112, first AND gate 113, second buffer 114, Two AND gate 115, instruction decoder 116 and OR gate 117.
  • the first flip-flop 104, the second flip-flop 105, the third flip-flop 106, the fourth flip-flop 108, the fifth flip-flop 110, and the sixth flip-flop 111 can all be composed of D-type flip-flops; for instruction translation
  • the encoder 116 may be composed of a three-input NAND gate, a two-input NOR gate, a buffer and other logical components, as shown in Figure 3 for details.
  • the input signals of the first receiver 101 are the initial command address signal (represented by CA[13:0]) and the reference signal (represented by VREFCA), and the output signal is the intermediate command address signal (represented by CA);
  • the input signals of the second receiver 102 are the initial chip select signal (represented by CS_n) and the reference signal (represented by VREFCA), and the output signal is the intermediate chip select signal (represented by PCS);
  • the input signal of the third receiver 103 is the initial The clock signal (including the CK_t signal and the CK_c signal) is divided into an even clock signal (represented by PCLK_E) and an odd clock signal (represented by PCLK_O) after frequency division processing.
  • CK_t/CK_c is a pair of complementary signals with a phase difference of 180°
  • the clock cycle of CK_t/CK_c is the preset clock cycle
  • the clock cycle of PCLK_E/PCLK_O is 2 times the preset clock cycle
  • the phase difference is 180°.
  • CA[13:0] here represents a set of signals, which is the combined collective name of CA[0], CA[1],..., CA[13].
  • the first receiver 101 actually includes 14 receiving circuits, as well as output lines, and even the following sampling circuits, there are 14, and CA[0], CA[1],...,CA[13] There is a one-to-one correspondence.
  • CA[13:0], CA[0], CA[1], CA[2], CA[3] and CA[4] are used to decode to form the instruction signal, expressed as CA[4:0 ]. Therefore, through the first flip-flop 104, the odd clock signal PCLK_O is used to perform one-level sampling processing on the intermediate command address signal CA to obtain the odd signal of the instruction to be processed (represented by CA[4:0]_1T_O); through the second flip-flop 105 , use the clock even signal PCLK_E to perform one-level sampling processing on the intermediate command address signal CA, and obtain the instruction even signal to be processed (represented by CA[4:0]_1T_E).
  • the intermediate command address signal CA will actually be sampled and output as an address signal, but this part of the circuit has nothing to do with the embodiment of the present disclosure and has been omitted, and will not be described here.
  • the clock even signal PCLK_E is used to sample and invert the intermediate chip select signal PCS to obtain the chip select even signal to be processed (represented by PCS_E).
  • the flip-flop 110 uses the clock odd signal PCLK_O to sample the chip select even signal PCS_E to be processed, and obtains the first chip select sampling odd signal (represented by PCS_OD); similarly, through the fourth flip-flop 108 and the second inverter 109 , use the odd clock signal PCLK_O to sample and invert the intermediate chip select signal PCS to obtain the odd chip select signal to be processed (represented by PCS_O), use the even clock signal PCLK_E to sample the odd chip select signal PCS_O to be processed, and obtain the odd chip select signal PCS_O to be processed.
  • a piece of selected sampling even signal represented by PCS_ED).
  • the initial chip select signal CS_n is an active low-level pulse signal
  • the intermediate chip select signal PCS is at a low level on the rising edge of an even clock cycle
  • the sampling odd signal PCS_OD is valid
  • the pending chip select odd signal PCS_O and the first chip select sampling odd signal PCS_ED are valid.
  • the even clock period or the odd clock period refers to the clock period of the initial clock signal CK_t/CK_c.
  • the odd clock signal PCLK_E and the even clock signal PCLK_O can be obtained; then the clock cycle in which the rising edge of the even clock signal PCLK_E is located is regarded as the even clock cycle, and the odd clock signal PCLK_E is The clock cycle where the rising edge of PCLK_O is located is regarded as the odd clock cycle.
  • the clock even signal PCLK_E and the first chip select sample even signal PCS_ED are input to the first AND gate 113, thereby calculating the chip select clock even signal (represented by CS_CLK_E), and the clock odd signal PCLK_O is After passing through the second buffer 114 and the first chip select sample odd signal PCS_OD, it is input to the second AND gate 115, thereby calculating the chip select clock odd signal (represented by CS_CLK_O).
  • the chip select clock odd signal CS_CLK_O/chip select clock even signal CS_CLK_E is used to process the instruction even signal CA[4:0]_1T_E/the instruction odd signal to be processed CA[4:0]_1T_O
  • the first chip selection sampling odd signal PCS_OD/the first chip selection sampling even signal PCS_ED are decoded and sampled to obtain the instruction even signal (represented by CMD_E) and the instruction odd signal (represented by CMD_O); finally, through the OR gate 117
  • the command even signal CMD_E and the command odd signal CMD_O perform an OR logic operation to obtain the target command signal (represented by CMD), so that the target command signal CMD can enter the subsequent module for the next application.
  • the corresponding signal timing diagram is shown in Figure 4.
  • the initial clock signal is represented by CK_t/CK_c
  • the even clock signal is represented by PCLK_E
  • the odd clock signal is represented by PCLK_O.
  • the clock cycle of CK_t/CK_c is the preset clock cycle
  • the clock cycles of PCLK_E/PCLK_O are both preset clock cycles.
  • the intermediate command address signal is represented by CA, and CA can include Cy, Cz, C0, C1, C2 and C3;
  • the initial chip select signal is represented by CS_n, and the intermediate chip select signal is represented by PCS, and PCS is An active low-level pulse signal, PCS is used to represent the signal that the target chip is selected. Please see Figure 2 for the meaning and origin of other signals.
  • the intermediate command address signal CA whose content is C0 and C2 and the low-level intermediate chip select signal PCS are sampled by the clock even signal PCLK_E to generate the instruction even signal CA[4:0 ]_1T_E and the valid chip select even signal PCS_E to be processed; then, the chip select even signal PCS_E to be processed is sampled twice by the clock odd signal PCLK_O to obtain the first chip select sampled odd signal PCS_OD, and the first chip select sampled odd signal PCS_OD After operating with the clock odd signal PCLK_O, the effective chip select clock odd signal CS_CLK_O is obtained.
  • the effective first chip select sample odd signal PCS_OD and the effective chip select clock odd signal CS_CLK_O are used to decode and sample the instruction even signal CA[4:0]_1T_E to be processed to obtain the target instruction signal.
  • the intermediate command address signal CA whose content is C1 and C3 and the high-level intermediate chip select signal PCS are sampled by the odd clock signal PCLK_O, resulting in CA[4:0]_1T_O (not shown) and invalid
  • the middle chip select odd signal PCS_O, and the middle chip select odd signal PCS_O is sampled twice by the clock even signal PCLK_E, resulting in an invalid first chip select sampling even signal PCS_ED, and the first chip select sampling even signal PCS_ED and the clock even signal PCLK_E
  • an invalid chip select clock even signal CS_CLK_E is obtained. Then, using the invalid first chip select sample even signal PCS_ED and the invalid chip select clock even signal CS_CLK_E to decode and sample the
  • the odd clock signal PCLK_O/the even clock signal PCLK_E is shielded by the first chip select sampling odd signal PCS_OD/the first chip select sampling even signal PCS_ED, so that the chip select clock odd signal CS_CLK_O/chip select clock even signal CS_CLK_E will only A valid signal is retained, and the valid signal in the chip select clock odd signal CS_CLK_O/chip select clock even signal CS_CLK_E includes a pulse whose pulse width is the preset clock cycle.
  • the preset clock cycle refers to the clock cycle of the initial clock signal CK_t/CK_c.
  • the chip select clock odd signal CS_CLK_O includes a pulse
  • the pulse width is a preset clock period
  • the first chip select sampling odd signal PCS_OD includes a pulse
  • the pulse width is a preset clock period. 2 times.
  • the chip select clock odd signal CS_CLK_O is used to generate the rising edge of CMD
  • the first chip select sampling odd signal PCS_OD is used to generate the falling edge of CMD.
  • the chip select clock odd signal CS_CLK_O is obtained by ANDing the first chip select sampling odd signal PCS_OD and the clock odd signal PCLK_O, so the rising edge of the chip select clock odd signal CS_CLK_O is the same as the first chip odd signal PCS_OD.
  • the rising edge of the chip select clock odd signal CS_CLK_O is the same as the first chip odd signal PCS_OD.
  • the odd-sampling signal PCS_OD the first chip select sampling odd signal PCS_OD signal will last for two preset clock cycles, due to the gap between the rising edge of the chip select clock odd signal CS_CLK_O and the rising edge of the first chip select sampling odd signal PCS_OD There is a delay.
  • the pulse width of the target command signal CMD is not twice the preset clock cycle, but the difference between 2 times the preset clock cycle and the delay.
  • the delay refers to the odd chip select clock.
  • the delay between the rising edge of the signal CS_CLK_O and the rising edge of the first chip select sampling odd signal PCS_OD; that is, the pulse width of the target command signal CMD (2Tck-delay), which results in the target command signal CMD possibly being at high frequency.
  • 2Tck means 2 times the preset clock period.
  • the first chip select sampling even signal PCS_ED/the first chip select sampling odd signal PCS_OD is used to shield the clock odd signal PCLK_O/clock even signal PCLK_E, so that the chip select clock odd signal CS_CLK_O/chip select clock
  • the even signal CS_CLK_E will only retain one valid signal, and the pulse width is a preset clock cycle (such as the chip select clock odd signal CS_CLK_O in Figure 4).
  • the valid signal in the chip select clock odd signal CS_CLK_O/chip select clock even signal CS_CLK_E is sampled after the pending instruction odd signal CA[4:0]_1T_O/the pending instruction even signal CA[4:0]_1T_E passes through the combinational logic
  • a target command signal CMD without a falling edge will be generated, and then it needs to perform an AND logic operation with the valid signal in the first chip selection odd signal PCS_OD/the first chip selection even signal PCS_ED to generate the target command signal
  • the falling edge of CMD so the pulse width of the target command signal CMD is expected to be 2 times the preset clock cycle.
  • the pulse width of the final target command signal CMD will be (2Tck-delay ), causing the pulse to have an error such that the pulse width of the target command signal CMD is uncertain and fails under high frequency and PVT changes.
  • a signal sampling circuit which includes a signal input circuit, a clock receiving circuit, a sampling logic circuit and a decoding circuit; wherein the signal input circuit is used to determine the instruction signal to be processed and The chip select signal to be processed; the clock receiving circuit is used to receive the initial clock signal and perform frequency division processing on the initial clock signal to obtain the first clock signal; wherein the clock cycle of the initial clock signal is the preset clock cycle, and the first clock The clock cycle of the signal is twice the preset clock cycle; the sampling logic circuit is used to perform two-level sampling processing and logical operation processing on the chip select signal to be processed according to the first clock signal to obtain the chip select clock signal; wherein, the chip select clock The signal includes two pulses, and the width of each pulse is a preset clock cycle; the decoding circuit is used to decode and sample the instruction signal to be processed according to the chip select signal to be processed and the chip select clock signal to obtain the target command signal.
  • the chip select clock signal after processing by the signal sampling circuit, includes two pulses, and the width of each pulse is a preset clock cycle, so that the pulse width of the target command signal after decoding and sampling will not follow the process, Changes in voltage, temperature, etc. produce deviations, which improves the problem of uncertain pulse width of the target command signal, improves signal quality, and prevents data failure.
  • FIG. 5 shows a schematic structural diagram of a signal sampling circuit 40 provided by an embodiment of the present disclosure.
  • the signal sampling circuit 40 includes a signal input circuit 41, a clock receiving circuit 42, a sampling logic circuit 43 and a decoding circuit 44; wherein,
  • Signal input circuit 41 used to determine the instruction signal to be processed and the chip select signal to be processed
  • the clock receiving circuit 42 is used to receive the initial clock signal, and perform frequency division processing on the initial clock signal to obtain the first clock signal; wherein, the clock period of the initial clock signal is a preset clock period, and the clock period of the first clock signal is 2 times the preset clock period;
  • the sampling logic circuit 43 is used to perform two-level sampling processing and logical operation processing on the chip select signal to be processed according to the first clock signal to obtain a chip select clock signal; wherein the chip select clock signal includes two pulses, and the width of each pulse is a preset clock cycle;
  • the decoding circuit 44 is used to decode and sample the instruction signal to be processed according to the chip select signal to be processed and the chip select clock signal to obtain the target instruction signal.
  • the signal sampling circuit 40 of the embodiment of the present disclosure can be applied in a variety of circuit scenarios.
  • the following explanation and description will take the instruction decoding process of the command address signal in DRAM as an example, but this does not constitute a relevant limitation.
  • the command signal to be processed may be determined based on the command address signal in the DRAM.
  • the pending chip select signal is a signal indicating whether the memory chip is selected.
  • the pending command signal is valid only when the memory chip is selected. Therefore, the pending chip select signal is also a signal used to indicate whether the pending instruction signal is valid.
  • the target instruction signal is an instruction signal obtained by decoding the instruction signal to be processed.
  • the instruction signal to be processed needs to be decoded to obtain the target instruction signal.
  • the signal sampling circuit 40 can be applied to the command signal of two preset clock cycles (represented by 2T CMD).
  • 2T CMD the command signal of two preset clock cycles
  • the command address signal includes valid signals of two preset clock cycles.
  • the target command signal CMD Valid commands include two preset clock cycles. It should be understood that in each clock cycle, the command address signal is composed of multi-bit signals, that is, the command address signal is not an isolated signal, but composed of a group of signals.
  • the command address signal can be composed of CA[0 ], CA[1]...CA[13], these 14-bit signals are represented as CA[13:0].
  • the chip select signal CS_n is a signal used to indicate that the memory chip is selected, and the pulse width is a preset clock cycle.
  • the chip select signal CS_n is an active low-level pulse signal. This clock cycle and the next clock cycle
  • the command address signal CA[13:0] corresponding to the clock cycle is valid (Valid).
  • CA[13:0] of the first clock cycle and CA[13:0] of the second clock cycle need to be sampled as address signals, and CA[4:0] of the first clock cycle also needs to be is sampled and decoded into a command signal.
  • CA[4:0] refers to CA[0], CA[1], CA[2], CA[3] and CA[4].
  • the signal sampling circuit 40 can be used for the command address signal as a sampling and decoding process of the instruction signal. Specifically, through the signal input circuit 41, the command signal to be processed is determined based on the command address signal CA[13:0] of the first clock cycle, and the chip select signal to be processed is determined based on the chip select signal CS_n. Secondly, through the clock receiving circuit 42, the initial clock signal is divided by frequency to obtain the first clock signal. Then, through the sampling logic circuit 43, the first clock signal is used to perform two-stage sampling and logical operation processing on the chip select signal to be processed, and the chip select clock signal is obtained, so that the chip select clock signal includes two pulses, and the width of each pulse for a preset clock cycle. Finally, the chip select signal to be processed and the instruction signal to be processed are decoded together, and the chip select clock signal is used as a clock signal to sample and output the decoded signal to obtain the target instruction signal.
  • the target command signal includes a pulse, and the width of the pulse is two preset clock cycles; wherein, the rising edge of the first pulse in the chip select clock signal is used to generate the rising edge of the target command signal. , the rising edge of the second pulse in the chip select clock signal is used to generate the falling edge of the target command signal.
  • the rising edge means that the signal changes from a low-level state to a high-level state
  • the falling edge means that the signal changes from a high-level state to a low-level state
  • the rising edge of the first pulse of the chip select clock signal is used to generate the rising edge of the target command signal
  • the rising edge of the second pulse of the chip select clock signal is used to generate the falling edge of the target command signal, so that the target command signal
  • the pulse width is twice the preset clock cycle, which can avoid the problem of uncertain pulse width of the target command signal and prevent data failure in high-frequency environments or PVT changes.
  • the pulse width of the target command signal is 2 times the preset clock cycle” described in the embodiment of the present disclosure means that the deviation between the pulse width of the target command signal and 2 times the preset clock cycle is within the preset Within the accuracy range, other instructions related to signal pulse width can also be understood by reference.
  • the first clock signal includes an odd clock signal and an even clock signal; wherein the clock periods of the odd clock signal and the even clock signal are both twice the preset clock period, and the odd clock signal and the even clock signal are The phase difference between them is 180 degrees.
  • the signal input circuit 41 includes a first input circuit 411 and a second input circuit 412; wherein,
  • the first input circuit 411 is used for receiving the initial command signal and outputting the intermediate command signal; and using the odd clock signal to sample the intermediate command signal to obtain the odd command signal to be processed, and using the even clock signal to sample the intermediate command signal. Get the pending instruction signal;
  • the second input circuit 422 is used to receive the initial chip select signal and output the intermediate chip select signal; and use the odd clock signal to sample and invert the intermediate chip select signal to obtain the odd chip select signal to be processed, and use the even clock signal to The signal is sampled and inverted on the intermediate chip select signal to obtain the chip select even signal to be processed.
  • the instruction odd signal to be processed and the even signal to be processed constitute the instruction signal to be processed
  • the chip select odd signal to be processed and the chip select even signal to be processed constitute the chip select signal to be processed
  • the initial clock signal here is represented by CK_t/CK_c
  • the odd clock signal is represented by PCLK_O
  • the even clock signal is represented by PCLK_E
  • the initial instruction signal is represented by CA[13:0]
  • the instructions to be processed are The odd signal is represented by CA[4:0]_1T_O
  • the even signal of the instruction to be processed is represented by CA[4:0]_1T_E
  • the initial chip select signal CS_n the odd signal of the chip select to be processed
  • PCS_O the chip select to be processed is represented Even signals are represented by PCS_E.
  • the first input circuit 411 may include 14 identical structures, respectively used to receive and sample 14 signals such as CA[0], CA[1],..., CA[13], etc., as shown in Figure Only one structure is shown in as an illustration.
  • CA[4:0]_1T_E is not a signal, but represents a set of command address signals, namely CA[0]_1T_E ⁇ CA[4]_1T_E
  • CA[4:0]_1T_O is not a signal, but represents a set of command address signals, namely CA[0]_1T_O ⁇ CA[4]_1T_O.
  • the initial chip select signal CS_n can be received and sampled to obtain the odd chip select signal PCS_O to be processed and the even chip select signal PCS_E to be processed respectively.
  • the initial chip select signal CS_n is a pulse signal with low level. If the initial chip select signal CS_n is low level at the rising edge of an odd clock cycle, then the odd chip select signal PCS_O to be processed is valid, and the chip select to be processed is The even signal PCS_E is invalid; if the initial chip select signal CS_n is low level on the rising edge of an even clock cycle, then the even signal PCS_E to be processed is valid, and the odd signal PCS_O to be processed is invalid. That is to say, there is at most one valid signal among the chip select odd signal PCS_O to be processed and the even chip select signal PCS_E to be processed.
  • the even clock period or the odd clock period refers to the clock period of the initial clock signal CK_t/CK_c.
  • the odd clock signal PCLK_E and the even clock signal PCLK_O can be obtained; then the clock cycle where the rising edge of the even clock signal PCLK_E is located is regarded as the even clock cycle, and the odd clock signal PCLK_O is The clock cycle where the rising edge is located is regarded as the odd clock cycle.
  • the first input circuit 411 may include a first receiver 511 , a fifth flip-flop 514 and a sixth flip-flop 515 .
  • the input terminal of the first receiver 511 is used to receive the initial command signal CA[13:0] and the reference voltage signal VREFCA, and the output terminal of the first receiver 511 is used to output the intermediate command signal (represented by CA);
  • the fifth The input terminal of the flip-flop 514 is connected to the output terminal of the first receiver 511, the clock terminal of the fifth flip-flop 514 is connected to the clock signal PCLK_E, and the output terminal of the fifth flip-flop 514 is used to output the pending command signal CA[ 4:0]_1T_E.
  • the input terminal of the sixth flip-flop 515 is connected to the output terminal of the first receiver 511, the clock terminal of the sixth flip-flop 515 is connected to the odd clock signal PCLK_O, and the output terminal of the sixth flip-flop 515 is used to output the odd signal of the instruction to be processed.
  • the second input circuit 412 may include a second receiver 512 , a seventh flip-flop 516 , a first inverter 517 , an eighth flip-flop 518 and a second inverter 519 .
  • the input terminal of the second receiver 512 is used to receive the initial chip select signal CS_n and the reference voltage signal VREFCA, and the output terminal of the second receiver 512 is used to output the intermediate chip select signal (represented by PCS);
  • the seventh flip-flop 516 The input terminal of is connected to the output terminal of the second receiver 512, the clock terminal of the seventh flip-flop 516 is connected to the clock even signal PCLK_E, the output terminal of the seventh flip-flop 516 is connected to the first inverter 517, the first inverter
  • the output terminal of the processor 517 is used to output the chip select signal PCS_E to be processed.
  • the input terminal of the eighth flip-flop 518 is connected to the output terminal of the second receiver 512, the clock terminal of the eighth flip-flop 518 is connected to the odd clock signal PCLK_O, and the output terminal of the eighth flip-flop 518 is connected to the second inverter 519. , the output terminal of the second inverter 519 is used to output the chip select odd signal PCS_O to be processed.
  • the intermediate chip select signal PCS is an active low-level pulse signal
  • the first inverter 517 and the second inverter 519 need to be set correspondingly after the seventh flip-flop 516 and the eighth flip-flop 518, so as to The intermediate sampled even signal PCS_E or the intermediate sampled odd signal PCS_O becomes a high-level active pulse signal for subsequent logic operations.
  • the first inverter 517 and the second inverter 519 may not be provided after the seventh flip-flop 516 and the eighth flip-flop 518, then subsequent logical operations need to be adjusted accordingly to achieve the same effect.
  • the clock receiving circuit 42 may include a third receiver 513.
  • the input terminal of the third receiver 513 is used to receive the initial clock signal CK_t/CK_c
  • the output terminal of the third receiver 513 is used to receive the initial clock signal CK_t/CK_c.
  • CK_t/CK_c is a set of signals with the same clock cycle but a phase difference of 180 degrees.
  • PCLK_O/PCLK_E is also a set of signals with the same clock cycle but a phase difference of 180 degrees, and the clock cycle of CK_t/CK_c is pre Assume the clock cycle, the clock cycle of PCLK_O/PCLK_E is twice the preset clock cycle.
  • the sampling logic circuit 43 may include a first sampling circuit 431, a second sampling circuit 432, a first logic circuit 433 and a second logic circuit 434; wherein,
  • the first sampling circuit 431 is used to use the odd clock signal to perform first-level sampling processing on the chip select even signal to be processed to obtain the first chip select sampled odd signal; and use the clock odd signal to perform the second level sampling process on the first chip select sampled odd signal. stage sampling processing to obtain the second chip selection sampling odd signal;
  • the second sampling circuit 432 is used to use the clock even signal to perform first-level sampling processing on the chip select odd signal to be processed to obtain the first chip select sample even signal; and use the clock even signal to perform the second level sampling process on the first chip select sample even signal. stage sampling processing to obtain the second chip selected even signal;
  • the first logic circuit 433 is used to perform logical operations on the clock odd signal, the first chip select sample odd signal and the second chip select sample odd signal to obtain the chip select clock odd signal;
  • the second logic circuit 434 is used to perform logical operations on the clock even signal, the first chip select sampled even signal and the second chip select sampled even signal to obtain the chip select clock even signal.
  • the chip select clock even signal and the chip select clock odd signal constitute the chip select clock signal.
  • the first sampling circuit 431 and the first logic circuit 433 are used to determine the chip select clock odd signal; the second sampling circuit 432 and the second logic circuit 434 are used to determine the chip select clock even signal. Signal.
  • the first chip select sampled odd signal is represented by PCS_OD
  • the first chip select sampled even signal is represented by PCS_ED
  • the second chip select sampled odd signal is represented by PCS_ODD
  • the second chip select sampled even signal is represented by PCS_EDD
  • the odd signal of the chip select clock is represented by CS_CLK_O
  • the even signal of the chip select clock here is represented by CS_CLK_E.
  • the chip select odd signal PCS_O to be processed and the even chip select signal PCS_E to be processed is valid.
  • the chip select even signal PCS_E to be processed is valid, the first chip select sample odd signal PCS_OD, the second chip select signal PCS_OD, and the even chip select signal PCS_E are valid.
  • the odd sampling signal PCS_ODD and the odd chip selection clock signal CS_CLK_O are valid; when the odd chip selection signal PCS_O to be processed is valid, the first chip selection sampling even signal PCS_ED, the second chip selection sampling even signal PCS_EDD and the chip selection clock Even signal CS_CLK_E is valid.
  • the first-level sampling processing refers to rising edge sampling processing
  • the second-level sampling processing refers to falling edge sampling processing
  • the rising edge of the clock odd signal PCLK_O is used to sample the chip select even signal PCS_E to be processed, to obtain the first chip select sampling odd signal PCS_OD, and then the falling edge of the clock odd signal PCLK_O is used to sample the chip select even signal PCS_E.
  • One chip selects the odd signal PCS_OD for sampling, and obtains the second chip selects the odd signal PCS_ODD.
  • the first logic circuit 433 performs operations on the clock odd signal PCLK_O, the first chip select sampling odd signal PCS_OD, and the second chip select sampling odd signal PCS_ODD to obtain a signal that there are two pulses and each pulse is a preset clock cycle.
  • the rising edge of the clock even signal PCLK_E is used to sample the chip select odd signal PCS_O to be processed to obtain the first chip select even signal PCS_ED, and then the falling edge of the clock even signal PCLK_E is used to sample the first chip select odd signal PCS_ED.
  • the chip select sampling even signal PCS_ED is sampled to obtain the second chip select sampling even signal PCS_EDD.
  • the second logic circuit 434 performs operations on the clock even signal PCLK_E, the first chip select sample even signal PCS_ED and the second chip select sample even signal PCS_EDD, and obtains that there are two pulses and each pulse is a preset clock cycle.
  • Chip select clock even signal CS_CLK_E Chip select clock even signal CS_CLK_E.
  • a chip select clock signal (chip select clock odd signal or chip select clock signal) with two pulses and each pulse being a preset clock cycle can be obtained.
  • Clock even signal and subsequently ensure that the pulse width of the target command signal is twice the preset clock cycle, avoiding the problem of uncertain pulse width of the target command signal and preventing data errors in high-frequency environments or PVT changes.
  • the pulse width of the target command signal is 2 times the preset clock cycle
  • described in the embodiment of the present disclosure means that the deviation between the pulse width of the target command signal and 2 times the preset clock cycle is within the preset within the accuracy range.
  • first-level sampling and the second-level sampling are to ensure that the chip select clock signal obtained after subsequent logic processing includes two pulses, and the width of each pulse is one preset clock cycle. Therefore, using rising edge sampling as the first level sampling and falling edge sampling as the second level sampling is only a feasible method and does not constitute relevant restrictions.
  • the first sampling circuit 431 and the second sampling circuit 432 may adopt the following structure.
  • the first sampling circuit 431 may include a first flip-flop 501, a first NOT gate 502 and a second flip-flop 503; wherein,
  • the input terminal of the first flip-flop 501 is connected to the chip select even signal PCS_E to be processed, the clock terminal of the first flip-flop 501 is connected to the clock odd signal PCLK_O, and the output terminal of the first flip-flop 501 is used to output the first chip select sample odd signal.
  • signal PCS_OD the input terminal of the second flip-flop 503 is connected to the output terminal of the first flip-flop 501, the input terminal of the first NOT gate 502 is connected to the odd clock signal PCLK_O, and the output terminal of the first NOT gate 502 is connected to the second flip-flop 503
  • the clock terminal is connected, and the output terminal of the second flip-flop 503 is used to output the second chip select sampling odd signal PCS_ODD.
  • odd clock signal PCLK_O is inverted through the first NOT gate 502, and then the rising edge of the inverted odd clock signal PCLK_O is used to sample the first chip select sampling odd signal PCS_OD to achieve utilization.
  • the falling edge of the clock odd signal PCLK_O samples the first chip select sampling odd signal PCS_OD.
  • the second sampling circuit 432 may include a third flip-flop 504, a second NOT gate 505 and a fourth flip-flop 506; wherein,
  • the input terminal of the third flip-flop 504 is connected to the chip select odd signal PCS_O to be processed, the clock terminal of the third flip-flop 504 is connected to the clock even signal PCLK_E, and the output terminal of the third flip-flop 504 is used to output the first chip select sample even signal.
  • signal PCS_ED the input terminal of the fourth flip-flop 506 is connected to the output terminal of the third flip-flop 504, the input terminal of the second NOT gate 505 is connected to the clock even signal PCLK_E, and the output terminal of the second NOT gate 505 is connected to the fourth flip-flop.
  • the clock terminal of 506 is connected, and the output terminal of the fourth flip-flop 506 is used to output the second chip select sampling even signal PCS_EDD.
  • clock even signal PCLK_E is inverted through the second NOT gate 505, and then the rising edge of the inverted clock even signal PCLK_E is used to sample the first chip select even signal PCS_ED to achieve utilization
  • the falling edge of the clock even signal PCLK_E samples the first chip select sampling even signal PCS_ED.
  • first flip-flop 501 the aforementioned first flip-flop 501, second flip-flop 503, third flip-flop 504, fourth flip-flop 506, fifth flip-flop 514, sixth flip-flop 515, seventh flip-flop 516, eighth
  • the flip-flops 518 can all be D-type flip-flops.
  • the first logic circuit 433 may include a first OR gate 507 and a first AND gate 508; wherein,
  • the first OR gate 507 is used to perform an OR operation on the first chip selection sampling odd signal PCS_OD and the second chip selection sampling odd signal represented by PCS_ODD to obtain the intermediate odd signal;
  • the first AND gate 508 is used to perform an AND operation on the intermediate odd signal and the clock odd signal PCLK_O to obtain the chip select clock odd signal CS_CLK_O.
  • the OR operation of the first chip select sampling odd signal PCS_OD and the second chip select sampling odd signal PCS_ODD can broaden the scope Pulse width, the pulse width of the obtained intermediate odd signal is 3 times the preset clock period.
  • the intermediate odd signal is ANDed with the clock odd signal PCLK_O.
  • the obtained chip select clock odd signal CS_CLK_O has two pulses, and the pulse The width is one preset clock period. In this way, the odd signal of the chip select clock is used for subsequent sampling and decoding, so that the pulse width of the final output target instruction signal is twice the preset clock cycle.
  • the chip select clock odd signal CS_CLK_O is in an invalid state.
  • the second logic circuit 434 may include a second OR gate 509 and a second AND gate 510; wherein,
  • the second OR gate 509 is used to perform an OR operation on the first chip selection sampling even signal PCS_ED and the second chip selection sampling even signal PCS_EDD to obtain the intermediate even signal;
  • the second AND gate 510 is used to perform an AND operation on the intermediate even signal and the clock even signal PCLK_E to obtain the chip select clock even signal CS_CLK_E.
  • the pulse width of the obtained intermediate even signal is 3 times the preset clock period.
  • the intermediate even signal is ANDed with the clock even signal PCLK_E.
  • the obtained chip select clock even signal CS_CLK_E has two pulses, and the pulse The width is one preset clock period.
  • the chip select clock even signal CS_CLK_E is also in an invalid state.
  • the odd clock signal PCLK_O/the even clock signal PCLK_E are used to perform two-level sampling and logical operations on the odd chip select signal PCS_O to be processed/the even chip select signal PCS_E to be processed, and the chip select clock odd signal CS_CLK_O/chip is obtained.
  • the clock select even signal CS_CLK_E is followed by the instruction odd signal CA[4: 0]_1T_O/pending command even signal CA[4:0]_1T_E is decoded and sampled, so that the pulse width of the final output target command signal is twice the preset clock cycle.
  • the decoding circuit 44 may include a first instruction decoding circuit 441, a second instruction decoding circuit 442, and a third OR gate 443; wherein,
  • the first instruction decoding circuit 441 is used to decode and sample the instruction even signal CA[4:0]_1T_E to be processed according to the chip select even signal PCS_E and the chip select clock odd signal CS_CLK_O to obtain the instruction even signal CMD_E;
  • the second instruction decoding circuit 442 is used to decode and sample the instruction odd signal CA[4:0]_1T_O to be processed according to the chip select odd signal PCS_O and the chip select clock even signal CS_CLK_E to obtain the instruction odd signal CMD_O;
  • the third OR gate 443 is used to perform an OR operation on the even command signal CMD_E and the odd command signal CMD_O to obtain the target command signal CMD.
  • the to-be-processed chip select even signal PCS_E and the chip select clock odd signal CS_CLK_O is valid.
  • the command even signal CMD_E output by the first command decoding circuit 441 is valid, and the command odd signal CMD_O output by the second command decoding circuit 442 is invalid.
  • the command even signal is converted by the third OR gate 443 CMD_E is output as the target command signal CMD.
  • the second instruction decoding circuit 442 outputs The command odd signal CMD_O is valid, the command even signal CMD_E output by the first command decoding circuit 441 is invalid, and the command odd signal CMD_O is output as the target command signal CMD through the third OR gate 443 .
  • the initial chip select signal is a signal indicating that the target chip is selected, and the initial chip select signal is a low-level active pulse signal; among them, if the initial chip select signal rises in an even-numbered clock cycle If the edge sampling is low level, the chip select even signal to be processed is a high-level pulse signal; accordingly, the rising edge of the first pulse in the chip select clock odd signal is used to generate the rising edge of the target command signal, and the chip select The rising edge of the second pulse in the clock odd signal is used to generate the falling edge of the target command signal.
  • the odd chip select signal to be processed is a pulse signal with active high level; correspondingly, the even signal of the chip select clock
  • the rising edge of the first pulse is used to generate the rising edge of the target command signal
  • the rising edge of the second pulse in the chip select clock even signal is used to generate the falling edge of the target command signal.
  • the effective signal in the chip select clock signal includes two pulses, and the pulse width of each pulse is a preset clock cycle, and the first pulse
  • the rising edge of the second pulse is used to generate the rising edge of the target command signal CMD
  • the rising edge of the second pulse is used to generate the falling edge of the target command signal CMD, so that the pulse width of the final output target command signal CMD is twice the preset clock cycle. , that is, the deviation between the pulse width of the target command signal CMD and 2 times the preset clock cycle is within the preset accuracy range.
  • the specific design of the first instruction decoding circuit 441 and the second instruction decoding circuit 442 is determined based on the instruction decoding rules. For different products/different application scenarios/different instructions, the decoding rules may be different. , then the logic of the instruction decoding circuit can also be adjusted accordingly.
  • the first instruction decoding circuit 441 may include a first decoding circuit and a third sampling circuit; wherein,
  • the first decoding circuit is used to decode the instruction even signal CA[4:0]_1T_E to be processed and the chip select even signal PCS_E to be processed, to obtain the instruction decoding even signal;
  • the third sampling circuit is used to sample the instruction decoding even signal according to the chip select clock odd signal CS_CLK_O to obtain the instruction even signal CMD_E.
  • the instruction even signal CA[4:0]_1T_E to be processed may include CA[0]_1T_E, CA[1]_1T_E, CA[2]_1T_E, CA[3]_1T_E, CA[ 4]_1T_E and other command signals
  • the first decoding circuit may be composed of a three-input NAND gate, a three-input NAND gate and a two-input NOR gate.
  • PCS_E, CA[0]_1T_E and CA[1]_1T_E are input to the first three-input NAND gate
  • CA[2]_1T_E, CA[3]_1T_E and CA[4]_1T_E are input to the second three-input NAND gate
  • the output of the first three-input NAND gate is connected to one input of the two-input NOR gate
  • the output of the second three-input NAND gate is connected to the two-input NOR gate.
  • the other input end of the gate is connected, and the output end of the two-input NOR gate is used to output the instruction decoding even signal, thereby realizing the decoding of the chip select even signal PCS_E to be processed and the instruction even signal CA[4:0]_1T_E to be processed. code.
  • the specific design of the first instruction decoding circuit 441 is determined based on the instruction decoding rules. For different products/different application scenarios/different instructions, the decoding rules may be different, so the instruction decoding circuit Logic can also be adjusted accordingly.
  • the third sampling circuit is used to perform sampling output.
  • the third sampling circuit can be a D-type flip-flop.
  • the clock terminal of the D-type flip-flop is connected to the chip select clock odd signal CS_CLK_O.
  • the input terminal of the D-type flip-flop is connected to the output terminal of the two-input NOR gate.
  • the output terminal of the D-type flip-flop is used to output the command signal CMD_E.
  • the second instruction decoding circuit 442 includes a second decoding circuit and a fourth sampling circuit; wherein,
  • the second decoding circuit is used to decode the instruction odd signal CA[4:0]_1T_O to be processed and the chip select odd signal PCS_O to be processed, to obtain the instruction decoding odd signal;
  • the fourth sampling circuit is used to sample the instruction decoding odd signal according to the chip select clock even signal CS_CLK_E to obtain the instruction odd signal CMD_O.
  • the instruction odd signal CA[4:0]_1T_O to be processed may include CA[0]_1T_O, CA[1]_1T_O, CA[2]_1T_O, CA[3]_1T_O, CA[ 4]_1T_O and other command signals
  • the second decoding circuit may be composed of a three-input NAND gate, a three-input NAND gate and a two-input NOR gate.
  • PCS_O, CA[0]_1T_O and CA[1]_1T_O are input to the first three-input NAND gate, and CA[2]_1T_O, CA[3]_1T_O and CA[4]_1T_O are input to the second three-input NAND gate, then the output of the first three-input NAND gate is connected to one input of the two-input NOR gate, and the output of the second three-input NAND gate is connected to the two-input NOR gate.
  • the other input end of the gate is connected, and the output end of the two-input NOR gate is used to output the instruction decoding odd signal, thereby realizing the decoding of the chip select odd signal PCS_O to be processed and the instruction odd signal CA[4:0]_1T_O to be processed. code.
  • the specific design of the second instruction decoding circuit 442 is determined based on the instruction decoding rules. For different products/different application scenarios/different instructions, the decoding rules may be different, so the instruction decoding circuit Logic can also be adjusted accordingly.
  • the fourth sampling circuit is used to perform sampling output.
  • the fourth sampling circuit can be a D-type flip-flop, the clock terminal of the D-type flip-flop is connected to the chip select clock even signal CS_CLK_E, and the input terminal of the D-type flip-flop is connected to the output terminal of the two-input NOR gate.
  • the output terminal of the D-type flip-flop is used to output the command odd signal CMD_O.
  • the first clock signal is used to perform two-level sampling and logical operations on the chip select signal to be processed, and the chip select clock signal is obtained, so that the chip select clock signal includes two pulses, and each pulse
  • the width is a preset clock cycle, so that the rising edge of the first pulse of the chip select clock signal is used to generate the rising edge of the target command signal, and the rising edge of the second pulse of the chip select clock signal is used to generate the falling edge of the target command signal.
  • the pulse width of the final output target command signal is twice the preset clock cycle, avoiding the problem of uncertain pulse width of the target command signal, and preventing data errors in high-frequency environments or PVT changes.
  • Embodiments of the present disclosure provide a signal sampling circuit.
  • the signal sampling circuit includes a signal input circuit, a clock receiving circuit, a sampling logic circuit and a decoding circuit.
  • the signal input circuit is used to determine the instruction signal to be processed and the slice to be processed.
  • the clock receiving circuit is used to receive the initial clock signal and perform frequency division processing on the initial clock signal to obtain the first clock signal; wherein the clock cycle of the initial clock signal is the preset clock cycle, and the clock cycle of the first clock signal is The cycle is 2 times the preset clock cycle;
  • the sampling logic circuit is used to perform two-level sampling processing and logical operation processing on the chip select signal to be processed based on the first clock signal to obtain the chip select clock signal; wherein, the chip select clock signal includes two pulses, and the width of each pulse is a preset clock cycle;
  • the decoding circuit is used to decode and sample the instruction signal to be processed according to the chip select signal to be processed and the chip select clock signal to obtain the target instruction signal.
  • the chip select clock signal after processing by the signal sampling circuit, includes two pulses, and the width of each pulse is a preset clock cycle, so that the pulse width of the target command signal after decoding and sampling will not follow the process, Changes in voltage, temperature, etc. produce deviations, which improves the problem of uncertain pulse width of the target command signal, improves signal quality, and prevents data failure.
  • the signal sampling circuit 40 may include a first receiver 611, a second receiver 612, a third receiver 613, a fifth flip-flop 614, a sixth flip-flop 615, a seventh flip-flop 616, a first Inverter 617, eighth flip-flop 618, second inverter 619, first flip-flop 601, first NOT gate 602, second flip-flop 603, third flip-flop 604, second NOT gate 605, fourth Flip-flop 606, first OR gate 607, first AND gate 608, second OR gate 609, second AND gate 610, instruction decoder 620, third OR gate 621.
  • the first flip-flop 601, the second flip-flop 603, the third flip-flop 604, the fourth flip-flop 606, the fifth flip-flop 614, the sixth flip-flop 615, the seventh flip-flop 616, and the eighth flip-flop 618 can all be used. It is a D-type flip-flop.
  • the instruction decoder 620 may include a first instruction decoding circuit and a second instruction decoding circuit. The specific structure is shown in FIG. 8A and FIG. 8B .
  • the input signals of the first receiver 611 are the initial command signal (expressed by CA[13:0]) and the reference signal (expressed by VREFCA), and the output signal is the intermediate command signal (expressed by CA).
  • the initial command signal and the intermediate command signal are not one signal, but represent a group of signals, that is, CA[13:0] includes CA[13] ⁇ CA[0]; for each signal
  • CA[13:0] includes CA[13] ⁇ CA[0]; for each signal
  • Both require a first receiver 611 and a fifth flip-flop 614, so the embodiment of the present disclosure requires 14 first receivers 611 and 14 fifth flip-flops 614. Only one first receiver 611 and a fifth flip-flop 614 are shown in the figure. Five flip-flops 614 are shown as an illustration.
  • the input signals of the second receiver 612 are the initial chip select signal (represented by CS_n) and the reference signal (represented by VREFCA), and the output signal is the intermediate chip select signal (represented by PCS); the input signal of the third receiver 613 is the initial The clock signal (including CK_t signal and CK_c signal), after frequency division processing, the output signal is an even clock signal (represented by PCLK_E) and an odd clock signal (represented by PCLK_O).
  • the clock cycle of CK_t/CK_c is the preset clock cycle
  • the clock cycle of PCLK_E_/PCLK_O is twice the preset clock cycle.
  • the clock even signal PCLK_E is used to sample the intermediate instruction signal CA to obtain the instruction even signal to be processed (represented by CA[4:0]_1T_E); through the sixth flip-flop 615, the clock even signal PCLK_E is used to obtain the instruction even signal to be processed.
  • the odd signal PCLK_O samples the intermediate command signal CA to obtain the odd signal of the command to be processed (represented by CA[4:0]_1T_O); through the seventh flip-flop 616 and the first inverter 617, the clock even signal PCLK_E is used to The intermediate chip select signal PCS is sampled and inverted to obtain the chip select even signal to be processed (represented by PCS_E).
  • the odd clock signal PCLK_O is used to compare the intermediate chip select signal PCS Perform sampling and inversion processing to obtain the chip select odd signal to be processed (represented by PCS_O).
  • CA[4:0] includes CA[4] ⁇ CA[0], that is, the first 5 bits of the initial command signal CA[13:0] form the command to be processed after being received and sampled.
  • the rising edge of the clock odd signal PCLK_O is used to sample PCS_E to obtain the first chip select sampling odd signal (represented by PCS_OD).
  • the first chip select sampling odd signal PCS_OD is sampled using the falling edge of the clock odd signal PCLK_O to obtain the second chip select sampling odd signal (represented by PCS_ODD), and the first chip select sampling odd signal PCS_OD is obtained through the first OR gate 607 Perform an OR operation with the second chip select sample odd signal PCS_ODD to obtain the intermediate odd signal.
  • the second AND gate 610 performs an AND operation on the intermediate odd signal and the clock odd signal PCLK_O to obtain the chip select clock odd signal (represented by CS_CLK_O).
  • the rising edge of the clock even signal PCLK_E is used to sample the chip select odd signal PCS_O to be processed, to obtain the first chip select even signal (represented by PCS_ED), which is passed through the second NOT gate 605 and
  • the fourth flip-flop 606 uses the falling edge of the clock even signal PCLK_E to sample the first chip select sampling even signal PCS_ED to obtain the second chip select sampling even signal (represented by PCS_EDD).
  • the first chip selection sampling even signal PCS_ED is obtained through the second OR gate 609.
  • the chip select sample even signal PCS_ED and the second chip select sample even signal PCS_EDD perform an OR operation to obtain the intermediate even signal.
  • the second AND gate 610 performs an AND operation on the intermediate even signal and the clock even signal PCLK_E to obtain the chip select clock even signal ( Represented by CS_CLK_E).
  • CS_CLK_E chip select clock even signal
  • the even signal CS_CLK_E signal of the chip select clock/odd signal CS_CLK_O signal of the chip select clock is used to process the even signal CA[4:0]_1T_E signal/odd signal CA[4:0] of the instruction to be processed.
  • the chip select even signal PCS_E signal to be processed/the chip select odd signal PCS_O signal to be processed are decoded and sampled to obtain the instruction even signal (represented by CMD_E) and the instruction odd signal (represented by CMD_O), and then pass through the third
  • the OR gate 621 performs an OR logic operation on the command even signal CMD_E and the command odd signal CMD_O to obtain the target command signal (represented by CMD).
  • the pulse width of the obtained target command signal CMD is 2 times the preset clock cycle and will not proceed with the PVT. changes, thereby solving the problem of uncertainty and failure of the target command signal CMD pulse width under high frequency and PVT changes.
  • the pulse width of the target command signal is 2 times the preset clock cycle
  • the signal timing diagram of the signal sampling circuit 40 shown in FIG. 9 is as shown in FIG. 10 .
  • the intermediate command signal is represented by CA, and CA can include Cy, Cz, C0, C1, C2 and C3; the initial chip select signal is represented by CS_n, and the intermediate chip select signal is represented by PCS, which is active at low level.
  • the pulse signal, and the pulse width is the preset clock cycle, PCS is used to represent the signal that the target chip is selected; for the description of other signals, please refer to the above.
  • the even clock period or the odd clock period refers to the clock period of the initial clock signal CK_t/CK_c.
  • the odd clock signal PCLK_E and the even clock signal PCLK_O can be obtained; then the clock cycle where the rising edge of the even clock signal PCLK_E is located is regarded as the even clock cycle, and the odd clock signal PCLK_E is The clock cycle where the rising edge of PCLK_O is located is regarded as the odd clock cycle.
  • the instruction even signal to be processed CA[4:0]_1T_E is obtained, which includes C0 and C2.
  • the intermediate chip select signal PCS is generated.
  • the to-be-processed chip select even signal PCS_E is obtained.
  • the first chip select sampling odd signal PCS_OD is obtained, and then using the odd clock signal PCLK_O to perform the third level sampling of the first chip select sampling odd signal PCS_OD After sampling, the second chip select sampling odd signal PCS_ODD is obtained; similarly, after using the rising edge of the clock odd signal PCLK_O signal to perform first-level sampling and inversion processing on the intermediate chip select signal PCS, the chip select odd signal to be processed is obtained (represented by PCS_O), after using the clock even signal PCLK_E to perform the second level sampling of the chip select odd signal PCS_O to be processed, the first chip select sampling even signal PCS_ED is obtained, and then using the clock even signal PCLK_E to sample the first chip select even signal After PCS_ED performs the third level of sampling, the second chip select sampling even signal PCS_EDD is obtained.
  • the samples are numbered starting from the middle chip select signal PCS.
  • the samples are numbered starting from the odd chip select signal PCS_O to be processed/the even chip select signal PCS_E to be processed.
  • the second-level sampling in this embodiment is equivalent to the aforementioned first-level sampling
  • the third-level sampling is equivalent to the aforementioned second-level sampling.
  • the third level sampling is falling edge sampling, and other unspecified sampling can be selected as rising edge sampling.
  • the initial chip select signal CS_n is active low when sampled on the even clock edge, so the chip select even signal PCS_E to be processed, the first chip select sample odd signal PCS_OD, and the second chip select sample odd signal PCS_ODD are all high.
  • a pulse signal with a valid level, and the rising edges of the chip select even signal PCS_E to be processed, the first chip select sample odd signal PCS_OD, and the second chip select sample odd signal PCS_ODD are sequentially different from each other by one preset clock period.
  • the chip select clock odd signal CS_CLK_O is obtained.
  • the chip select clock odd signal CS_CLK_O includes two pulses, and the width of each pulse is a preset clock cycle.
  • the aforementioned instruction decoder 620 is used to decode the instruction even signal CA[4:0]_1T_E to be processed and the chip select even signal PCS_E to be processed, and use the chip select clock odd signal CS_CLK_O samples and outputs the clock signal to obtain the target command signal CMD.
  • the rising edge of the first pulse in the chip select clock odd signal CS_CLK_O is used to generate the rising edge of the target command signal CMD
  • the rising edge of the second pulse in the chip select clock odd signal CS_CLK_O is used to generate the target command.
  • the falling edge of signal CMD ensures that the pulse width of the target command signal CMD is twice the preset clock cycle.
  • the chip select odd signal PCS_O, the first chip select sample even signal PCS_ED, and the second chip select sample even signal PCS_EDD to be processed are:
  • the calculated chip select clock even signal CS_CLK_E is also an invalid signal, and the instruction decoder 620 will not use the chip select clock even signal CS_CLK_E to sample and output.
  • the initial chip select signal CS_n is active low when sampled at the odd clock edge.
  • the chip select even signal PCS_E, the first chip select sample odd signal PCS_OD, and the second chip select sample odd signal to be processed The signal PCS_ODD and the chip select clock odd signal CS_CLK_O will be in an invalid state; the to-be-processed chip select odd signal PCS_O, the first chip select sample even signal PCS_ED, the second chip select sample even signal PCS_EDD, and the chip select clock even signal CS_CLK_E will be in a valid state.
  • the chip select clock even signal CS_CLK_E includes two pulses, and the width of each pulse is a preset clock cycle.
  • the command decoder 620 will sample and output according to the chip select clock even signal CS_CLK_E to obtain the target command signal CMD signal.
  • the rising edge of the first pulse in the chip select clock even signal CS_CLK_E is used to generate the rising edge of the target command signal CMD.
  • the rising edge of the second pulse in the chip select clock even signal CS_CLK_E is used to generate the falling edge of the target command signal CMD, and also ensures that the pulse width of CMD is twice the preset clock period.
  • the intermediate command signal CA whose content is C0 and the low-level active intermediate chip select signal PCS are sampled by the clock even signal PCLK_E at the first level to generate the chip select even signal to be processed.
  • the effective pulses of the clock odd signal PCLK_O are selected after the OR logic of the first chip select odd signal PCS_OD and the second chip select odd signal PCS_ODD, resulting in two pulses of the odd chip select clock signal CS_CLK_O, and the width of each pulse for a preset clock cycle.
  • the first chip selection sampling odd signal PCS_OD and the second chip selection sampling odd signal PCS_ODD are ORed to widen the pulse width.
  • the pulse width of the obtained intermediate odd signal is 3 times the preset clock cycle.
  • the obtained chip select clock odd signal CS_CLK_O has two pulses, and the pulse width is one preset clock cycle.
  • the purpose of the first pulse is to sample and output the target command signal CMD
  • the purpose of the second pulse is to generate the falling edge of the target command signal CMD.
  • the pulse width of the target command signal CMD is twice the preset clock period, and the pulse width does not change with changes in PVT. This solves the problem of uncertainty and failure of the target command signal CMD pulse width under high frequency and PVT changes.
  • the embodiment of the present disclosure provides a signal sampling circuit.
  • the specific implementation of the foregoing embodiment is described in detail through this embodiment. It can be seen that the embodiment of the present disclosure is optimized based on the existing direct sampling decoding. , so that the chip select clock signal includes two pulses, and the width of each pulse is a preset clock cycle, so that the pulse width of the target command signal after decoding is twice the preset clock cycle, and the pulse width of the target command signal It will not cause deviations following changes in process, voltage, temperature, etc., improve the problem of uncertain pulse width of the target command signal, improve signal quality, and prevent data failure.
  • FIG. 11 shows a schematic structural diagram of a semiconductor memory 110 provided by an embodiment of the present disclosure.
  • the semiconductor memory 110 may include the signal sampling circuit 40 described in any of the previous embodiments.
  • the semiconductor memory 110 may be a DRAM chip.
  • the DRAM chip complies with DDR5 memory specifications.
  • the disclosed embodiments mainly involve circuits related to instruction decoding in integrated circuit design.
  • the disclosed embodiments are optimized for 2T CMD based on the existing direct sampling decoding, so that the chip select clock signal It includes two pulses, and the width of each pulse is a preset clock cycle, so that the pulse width of the target instruction signal after decoding is twice the preset clock cycle.
  • control circuits for command address signal sampling and decoding in DRAM chips can be applied to control circuits for command address signal sampling and decoding in DRAM chips, but are not limited to this scope.
  • Other related circuits for input signal sampling and command decoding can all adopt this method. design.
  • the pulse width of the target command signal will not deviate following changes in process, voltage, temperature, etc., thereby improving the pulse width of the target command signal. Uncertain issues, improve signal quality and prevent data failure.
  • Embodiments of the present disclosure provide a signal sampling circuit and a semiconductor memory.
  • the signal sampling circuit includes a signal input circuit, a clock receiving circuit, a sampling logic circuit and a decoding circuit; wherein the signal input circuit is used to determine the instruction signal to be processed and The chip select signal to be processed; the clock receiving circuit is used to receive the initial clock signal and perform frequency division processing on the initial clock signal to obtain the first clock signal; wherein the clock cycle of the initial clock signal is the preset clock cycle, and the first clock The clock cycle of the signal is twice the preset clock cycle; the sampling logic circuit is used to perform two-level sampling processing and logical operation processing on the chip select signal to be processed according to the first clock signal to obtain the chip select clock signal; wherein, the chip select clock The signal includes two pulses, and the width of each pulse is a preset clock cycle; the decoding circuit is used to decode and sample the instruction signal to be processed according to the chip select signal to be processed and the chip select clock signal to obtain the target command signal.
  • the chip select clock signal after processing by the signal sampling circuit, includes two pulses, and the width of each pulse is a preset clock cycle, so that the pulse width of the target command signal after decoding and sampling will not follow the process, Changes in voltage, temperature, etc. produce deviations, which improves the problem of uncertain pulse width of the target command signal and prevents data failure.

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Abstract

一种信号采样电路（40）以及半导体存储器，包括：信号输入电路（41），用于确定待处理指令信号和待处理片选信号；时钟接收电路（42），用于接收初始时钟信号，并对初始时钟信号进行分频处理，得到第一时钟信号；采样逻辑电路（43），用于根据第一时钟信号对待处理片选信号进行两级采样处理和逻辑运算处理，得到片选时钟信号；片选时钟信号包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期；译码电路（44），用于根据待处理片选信号和片选时钟信号对待处理指令信号进行译码处理和采样处理，得到目标指令信号。

Description

一种信号采样电路以及半导体存储器
相关申请的交叉引用
本公开基于申请号为202210295379.8、申请日为2022年03月23日、发明名称为“一种信号采样电路以及半导体存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种信号采样电路以及半导体存储器。
背景技术
随着半导体技术的不断发展，人们在制造和使用计算机等设备时，对数据的传输速度提出了越来越高的要求。为了获得更快的数据传输速度，应运而生了一系列数据可以双倍速率(Double Data Rate，DDR)传输的存储器等器件。
在动态随机存取存储器(Dynamic Random Access Memory，DRAM)中，输入的命令地址信号既可以作为地址进行采样又可以作为指令进行采样译码。在输入的命令地址信号作为指令时，需要采样译码得到译码信号。然而，译码信号的脉冲宽度存在不确定性，可能会导致数据失效，影响了半导体的性能。
发明内容
本公开提供了一种信号采样电路以及半导体存储器，能够改善信号脉冲宽度存在不确定性的问题，提高目标指令信号的质量。
第一方面，本公开实施例提供了一种信号采样电路，所述信号采样电路包括信号输入电路、时钟接收电路、采样逻辑电路和译码电路；其中，
所述信号输入电路，用于确定待处理指令信号和待处理片选信号；
所述时钟接收电路，用于接收初始时钟信号，并对所述初始时钟信号进行分频处理，得到第一时钟信号；其中，所述初始时钟信号的时钟周期为预设时钟周期，所述第一时钟信号的时钟周期为所述预设时钟周期的2倍；
所述采样逻辑电路，用于根据所述第一时钟信号对所述待处理片选信号进行两级采样处理和逻辑运算处理，得到片选时钟信号；其中，所述片选时钟信号包括两个脉冲，且每个脉冲的宽度为预设时钟周期；
所述译码电路，用于根据所述待处理片选信号和所述片选时钟信号对所述待处理指令信号进行译码处理和采样处理，得到目标指令信号。
在一些实施例中，所述目标指令信号包括一个脉冲，且所述脉冲的宽度为所述预设时钟周期的2倍；其中，所述片选时钟信号中第一个脉冲的上升沿用于产生所述目标指令信号的上升沿，所述片选时钟信号中第二个脉冲的上升沿用于产生所述目标指令信号的下降沿。
在一些实施例中，所述第一时钟信号包括时钟奇信号和时钟偶信号；其中，
所述时钟奇信号和所述时钟偶信号的时钟周期均是所述预设时钟周期的2倍，且所述时钟奇信号和所述时钟偶信号之间的相位差为180度。
在一些实施例中，所述信号输入电路包括第一输入电路和第二输入电路；其中，
所述第一输入电路，用于接收初始指令信号，输出中间指令信号；以及
利用所述时钟奇信号对所述中间指令信号进行采样处理，得到待处理指令奇信号，利用所述时钟偶信号对所述中间指令信号进行采样处理，得到待处理指令偶信号；
所述第二输入电路，用于接收初始片选信号，输出中间片选信号；以及
利用所述时钟奇信号对所述中间片选信号进行采样处理和反相处理，得到待处理片选奇信号，并利用所述时钟偶信号对所述中间片选信号进行采样处理和反相处理，得到待处理片选偶信号；
其中，所述待处理指令奇信号和所述待处理指令偶信号组成所述待处理指令信号，所述待处理片选奇信号和所述待处理片选偶信号组成所述待处理片选信号。
在一些实施例中，所述采样逻辑电路包括第一采样电路、第二采样电路、第一逻辑电路和第二逻辑电路；其中，
所述第一采样电路，用于利用所述时钟奇信号对所述待处理片选偶信号进行第一级采样处理，得到第一片选采样奇信号；并利用所述时钟奇信号对所述第一片选采样奇信号进行第二级采样处理，得到第二片选采样奇信号；
所述第二采样电路，用于利用所述时钟偶信号对所述待处理片选奇信号进行第一级采样处理，得到第一片选采样偶信号；并利用所述时钟偶信号对所述第一片选采样偶信号进行第二级采样处理，得到第二片选采样偶信号；
所述第一逻辑电路，用于对所述时钟奇信号、所述第一片选采样奇信号和所述第二片选采样奇信号进行逻辑运算，得到片选时钟奇信号；
所述第二逻辑电路，用于对所述时钟偶信号、所述第一片选采样偶信号和所述第二片选采样偶信号进行逻辑运算，得到片选时钟偶信号；
其中，所述片选时钟偶信号和所述片选时钟奇信号组成所述片选时钟信号。
在一些实施例中，所述第一级采样处理是指上升沿采样处理，所述第二级采样处理是指下降沿采样处理。
在一些实施例中，所述第一采样电路包括第一触发器、第一非门和第二触发器；其中，
所述第一触发器的输入端与所述待处理片选偶信号连接，所述第一触发器的时钟端与所述时钟奇信号连接，所述第二触发器的输入端与所述第一触发器的输出端连接，所述第一非门的输入端与所述时钟奇信号连接，所述第一非门的输出端与所述第二触发器的时钟端连接，所述第二触发器的输出端用于输出所述第二片选采样奇信号。
在一些实施例中，所述第二采样电路包括第三触发器、第二非门和第四触发器；其中，
所述第三触发器的输入端与所述待处理片选奇信号连接，所述第三触发器的时钟端与所述时钟偶信号连接，所述第四触发器的输入端与所述第三触发器的输出端连接，所述第二非门的输入端与所述时钟偶信号连接，所述第二非门的输出端与所述第四触发器的时钟端连接，所述第四触发器的输出端用于输出所述第二片选采样偶信号。
在一些实施例中，所述第一逻辑电路包括第一或门和第一与门；其中，
所述第一或门，用于对所述第一片选采样奇信号和所述第二片选采样奇信号进行或运算，得到中间奇信号；
所述第一与门，用于对所述中间奇信号和所述时钟奇信号进行与运算，得到所述片选时钟奇信号。
在一些实施例中，所述第二逻辑电路包括第二或门和第二与门；其中，
所述第二或门，用于对所述第一片选采样偶信号和所述第二片选采样偶信号进行或运算，得到中间偶信号；
所述第二与门，用于对所述中间偶信号和所述时钟偶信号进行与运算，得到所述片选时钟偶信号。
在一些实施例中，所述译码电路包括第一指令译码电路、第二指令译码电路以及第三或门；其中，
所述第一指令译码电路，用于根据所述待处理片选偶信号和所述片选时钟奇信号对所述待处理指令偶信号进行译码和采样处理，得到指令偶信号；
所述第二指令译码电路，用于根据所述待处理片选奇信号和所述片选时钟偶信号对所述待处理指令奇信号进行译码和采样处理，得到指令奇信号；
所述第三或门，用于对所述指令偶信号和所述指令奇信号进行或运算，得到所述目标指令信号。
在一些实施例中，所述第一指令译码电路包括第一译码电路和第三采样电路；其中，
所述第一译码电路，用于对所述待处理指令偶信号和所述待处理片选偶信号进行译码处理，得到指令译码偶信号；
所述第三采样电路，用于根据所述片选时钟奇信号对所述指令译码偶信号进行采样处理，得到 所述指令偶信号。
在一些实施例中，所述第二指令译码电路包括第二译码电路和第四采样电路；其中，
所述第二译码电路，用于对所述待处理指令奇信号和所述待处理片选奇信号进行译码处理，得到指令译码奇信号；
所述第四采样电路，用于根据所述片选时钟偶信号对所述指令译码奇信号进行采样处理，得到所述指令奇信号。
在一些实施例中，所述初始片选信号是表征目标芯片被选中的信号，且所述初始片选信号为低电平有效的脉冲信号；其中，
若所述初始片选信号在偶数时钟周期的上升沿采样为低电平，则所述待处理片选偶信号为高电平有效的脉冲信号；以及
所述片选时钟奇信号中第一个脉冲的上升沿用于产生所述目标指令信号的上升沿，所述片选时钟奇信号中第二个脉冲的上升沿用于产生所述目标指令信号的下降沿。
在一些实施例中，若所述初始片选信号在奇数时钟周期的上升沿采样为低电平，则所述待处理片选奇信号为高电平有效的脉冲信号；以及
所述片选时钟偶信号中第一个脉冲的上升沿用于产生所述目标指令信号的上升沿，所述片选时钟偶信号中第二个脉冲的上升沿用于产生所述目标指令信号的下降沿。
第二方面，本公开实施例提供了一种半导体存储器，包括如第一方面中任一项所述的信号采样电路。
在一些实施例中，该半导体存储器为动态随机存取存储器DRAM芯片。
本公开实施例提供了一种信号采样电路以及半导体存储器，该信号采样电路包括信号输入电路、时钟接收电路、采样逻辑电路和译码电路；其中，信号输入电路，用于确定待处理指令信号和待处理片选信号；时钟接收电路，用于接收初始时钟信号，并对初始时钟信号进行分频处理，得到第一时钟信号；其中，初始时钟信号的时钟周期为预设时钟周期，第一时钟信号的时钟周期为预设时钟周期的2倍；采样逻辑电路，用于根据第一时钟信号对待处理片选信号进行两级采样处理和逻辑运算处理，得到片选时钟信号；其中，片选时钟信号包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期；译码电路，用于根据待处理片选信号和片选时钟信号对待处理指令信号进行译码处理和采样处理，得到目标指令信号。这样，经过该信号采样电路的处理，片选时钟信号包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期，从而译码及采样之后的目标指令信号的脉冲宽度不会跟随工艺、电压、温度等变化产生偏差，改善目标指令信号的脉冲宽度不确定的问题，防止数据失效。
附图说明
图1为两个时钟周期命令的信号时序示意图；
图2为一种信号采样电路的组成结构示意图；
图3为一种指令译码器的组成结构示意图；
图4为一种信号采样电路的信号时序示意图；
图5为本公开实施例提供的一种信号采样电路的组成结构示意图；
图6为本公开实施例提供的另一种信号采样电路的组成结构示意图；
图7为本公开实施例提供的又一种信号采样电路的组成结构示意图
图8A为本公开实施例提供的第一指令译码电路的组成结构示意图；
图8B为本公开实施例提供的第二指令译码电路的组成结构示意图；
图9为本公开实施例提供的一种信号采样电路的详细结构示意图；
图10为本公开实施例提供的一种信号采样电路的信号时序示意图；
图11为本公开实施例提供的一种半导体存储器的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似地对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
以下为本公开实施例中涉及到的专业名词解释以及部分名词的对应关系：
动态随机存取存储器(Dynamic Random Access Memory，DRAM)
同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)
双倍速率(Double Data Rate，DDR)
第五代DDR(5th DDR，DDR5)
命令地址输入(Command/Address，CMD/ADD或简称为CA)
时钟输入(Clock Input，CLK)
片选输入(Chip Select Input，CS)
缓冲器(Buffer/Repeater，RPT)
指令译码器(Command Decoder，CMD DEC)
D型触发器(Data Flip-Flop或Delay Flip-Flop，DFF)
工艺、电压、温度(Process、Voltage、Temperature，PVT)
可以理解，以DDR5DRAM设计为例，CA输入既可以作为地址进行采样又可以作为指令进行采样译码。其中，这里的CA是DRAM各种命令地址信号的统称，可以包括行地址选通脉冲(Row Address Strobe，RAS)、列地址选通脉冲(Column Address Strobe，CAS)、写命令(Write，WE)、激活命令(ACT，Active)等命令信号，以及还可以包括有A13～A0的地址信号等。另外，在实际应用中，该命令地址信号包括几位地址信号，具体可以是根据DRAM的规格确定，本公开实施例不作任何限定。
对于DDR5DRAM中两个时钟周期的指令信号(用2T CMD表示)来说，参见图1，其示出了两个时钟周期命令的信号时序示意图。在图1中，CK_t、CK_c为一对互补的时钟信号，CA[13:0]就是CA输入，CMD为CA译码后得到的指令信号，CS_n为指示CA有效的片选信号。如图1所示，CA[13:0]为持续两个时钟周期的信号，第1个时钟周期的CA[13:0]和第2个时钟周期的CA[13:0]需要作为地址信号进行采样，在DDR5内，第1个时钟周期的CA[4:0]还需要作为指令信号进行采样和译码。另外，时钟周期是指CK_t/CK_c的时钟周期。
在本公开实施例中，主要涉及CA作为指令信号进行采样和译码的部分，对于CA作为地址信号进行采样和输出的部分进行省略，不作过多叙述。
示例性地，参见图2，其示出了一种信号采样电路的组成结构示意图。如图2所示，该信号采样译码电路包括第一接收器101、第二接收器102、第三接收器103、第一触发器104、第二触发器105、第三触发器106、第一反相器107、第四触发器108、第二反相器109、第五触发器110、第六触发器111、第一缓冲器112、第一与门113、第二缓冲器114、第二与门115、指令译码器116和或门117。其中，第一触发器104、第二触发器105、第三触发器106、第四触发器108、第五触发器110、第六触发器111均可以是由D型触发器组成；对于指令译码器116而言，其可以是由三输入与非门、二输入或非门和缓冲器等逻辑部件组成，详见图3所示。
在图2中，第一接收器101的输入信号为初始命令地址信号(用CA[13:0]表示)和参考信号(用VREFCA表示)，输出信号为中间命令地址信号(用CA表示)；第二接收器102的输入信号为初始片选信号(用CS_n表示)和参考信号(用VREFCA表示)，输出信号为中间片选信号(用PCS表示)；第三接收器103的输入信号为初始时钟信号(包括CK_t信号和CK_c信号)，经过分频处理后得到时钟偶信号(用PCLK_E表示)和时钟奇信号(用PCLK_O表示)。在这里，CK_t/CK_c是一对相位差为180°的互补信号，且CK_t/CK_c的时钟周期为预设时钟周期，PCLK_E/PCLK_O的时钟周期是预设时钟周期的2倍，且相位差为180°。需要注意的是，这里的CA[13:0]表示一组信号，是CA[0]、CA[1]、…、CA[13]的合并统称。相应地，第一接收器101中其实包括有14个接收电路，以及输出的线路，甚至包括后面的采样电路也是有14个，与CA[0]、CA[1]、…、CA[13]是一一对应的。
然后，在CA[13:0]中，CA[0]、CA[1]、CA[2]、CA[3]和CA[4]用于译码形成指令信号，表示为CA[4:0]。因此，通过第一触发器104，利用时钟奇信号PCLK_O对中间命令地址信号CA进行一级采样处理，得到待处理指令奇信号(用CA[4:0]_1T_O表示)；通过第二触发器105，利用时钟偶信号PCLK_E对中间命令地址信号CA进行一级采样处理，得到待处理指令偶信号(用CA[4:0]_1T_E)表示。在这里，中间命令地址信号CA其实还会作为地址信号进行采样输出，但是该部分电路与本公开实施例无关，已经进行了省略，在此不作相关叙述。
同时，通过第三触发器106和第一反相器107，利用时钟偶信号PCLK_E对中间片选信号PCS进行采样及反相处理，得到待处理片选偶信号(用PCS_E表示)，通过第五触发器110，利用时钟奇信号PCLK_O对待处理片选偶信号PCS_E进行采样处理，得到第一片选采样奇信号(用PCS_OD表示)；类似地，通过第四触发器108和第二反相器109，利用时钟奇信号PCLK_O对中间片选信号PCS进行采样及反相处理，得到待处理片选奇信号(用PCS_O表示)，用时钟偶信号PCLK_E对待处理片选奇信号PCS_O进行采样处理，得到第一片选采样偶信号(用PCS_ED表示)。
在这里，由于初始片选信号CS_n是低电平有效的脉冲信号，所以如果中间片选信号PCS在偶数时钟周期的上升沿处于低电平，则待处理片选偶信号PCS_E和第一片选采样奇信号PCS_OD有效；如果初始片选信号CS_n在奇数时钟周期的上升沿处于低电平，则待处理片选奇信号PCS_O和第一片选采样奇信号PCS_ED有效。在这里，偶数时钟周期或者奇数时钟周期是指初始时钟信号CK_t/CK_c的时钟周期。具体来说，经过第三接收器103的分频处理之后，可以得到时钟奇信号PCLK_E和时钟偶信号PCLK_O；然后将时钟偶信号PCLK_E的上升沿所在的时钟周期作为偶数时钟周期，将时钟奇信号PCLK_O的上升沿所在的时钟周期作为奇数时钟周期。
另外，时钟偶信号PCLK_E在经过第一缓冲器112后和第一片选采样偶信号PCS_ED输入到第一与门113，从而运算得到片选时钟偶信号(用CS_CLK_E表示)，时钟奇信号PCLK_O在经过第二缓冲器114后和第一片选采样奇信号PCS_OD输入到第二与门115，从而运算得到片选时钟奇信号(用CS_CLK_O表示)。特别地，由于第一片选采样偶信号PCS_ED和第一片选采样奇信号PCS_OD之中仅有一个信号有效，所以片选时钟奇信号CS_CLK_O和片选时钟偶信号CS_CLK_E同样仅有一个信号有效。
最后，通过指令译码器116，利用片选时钟奇信号CS_CLK_O/片选时钟偶信号CS_CLK_E对待处理指令偶信号CA[4:0]_1T_E/待处理指令奇信号CA[4:0]_1T_O，以及第一片选采样奇信号PCS_OD/第一片选采样偶信号PCS_ED进行译码和采样处理，得到指令偶信号(用CMD_E表示)和指令奇信号(用CMD_O表示)；最后，通过或门117对指令偶信号CMD_E和指令奇信号CMD_O进行或逻辑运算，得到目标指令信号(用CMD表示)，以便目标指令信号CMD进入到后续模块进行下一步应用。
基于图2和图3所示的信号采样电路，其对应的信号时序图如图4所示。在图4中，初始时钟信号用CK_t/CK_c表示，时钟偶信号用PCLK_E表示，时钟奇信号用PCLK_O表示，且CK_t/CK_c的时钟周期为预设时钟周期，PCLK_E/PCLK_O的时钟周期均为预设时钟周期的两倍；中间命令地址信号用CA表示，且CA可以包括Cy、Cz、C0、C1、C2和C3；初始片选信号用CS_n表示，中间片选信号用PCS表示，且PCS为低电平有效的脉冲信号，PCS用于表征目标芯片被选中的信号，其他信号的含义和出处请参见图2。
如图4所示，首先，内容为C0和C2的中间命令地址信号CA和低电平的中间片选信号PCS被时钟偶信号PCLK_E进行一级采样，产生待处理指令偶信号CA[4:0]_1T_E和有效的待处理片选偶信号PCS_E；然后，待处理片选偶信号PCS_E被时钟奇信号PCLK_O进行二级采样得到第一片选采样奇信号PCS_OD，且第一片选采样奇信号PCS_OD与时钟奇信号PCLK_O运算后得到有效的片选时钟奇信号CS_CLK_O。然后，利用有效的第一片选采样奇信号PCS_OD和有效的片选时钟奇信号CS_CLK_O对待处理指令偶信号CA[4:0]_1T_E进行译码和采样处理，得到目标指令信号。类似地，内容为C1和C3的中间命令地址信号CA和高电平的中间片选信号PCS被时钟奇信号PCLK_O进行一级采样，产生CA[4:0]_1T_O(未图示)和无效的中间片选奇信号PCS_O，且中间片选奇信号PCS_O被时钟偶信号PCLK_E进行二级采样，产生无效的第一片选采样偶信号PCS_ED，且第一片选采样偶信号PCS_ED与时钟偶信号PCLK_E运算后得到无效的片选时钟偶信号CS_CLK_E。然后，利用无效的第一片选采样偶信号PCS_ED和无效的片选时钟偶信号CS_CLK_E对待处理指令奇信号CA[4:0]_1T_O进行译码和采样处理，并不会得到有效信号。
这样，通过第一片选采样奇信号PCS_OD/第一片选采样偶信号PCS_ED来屏蔽时钟奇信号PCLK_O/时钟偶信号PCLK_E的方式，使得片选时钟奇信号CS_CLK_O/片选时钟偶信号CS_CLK_E 只会保留一个有效信号，且片选时钟奇信号CS_CLK_O/片选时钟偶信号CS_CLK_E中的有效信号包括一个脉冲，该脉冲的脉冲宽度为预设时钟周期。在这里，预设时钟周期是指初始时钟信号CK_t/CK_c的时钟周期。
也就是说，在本场景中，片选时钟奇信号CS_CLK_O包括一个脉冲，且脉冲宽度为一个预设时钟周期，第一片选采样奇信号PCS_OD包括一个脉冲，且脉冲宽度为预设时钟周期的2倍。片选时钟奇信号CS_CLK_O用于产生CMD的上升沿，第一片选采样奇信号PCS_OD用于产生CMD的下降沿。但是，如图2所示，片选时钟奇信号CS_CLK_O是由第一片选采样奇信号PCS_OD与时钟奇信号PCLK_O进行与运算后得到的，所以片选时钟奇信号CS_CLK_O的上升沿与第一片选采样奇信号PCS_OD的上升沿之间存在延时。如图3所示，虽然第一片选采样奇信号PCS_OD信号会持续两个预设时钟周期，但是由于片选时钟奇信号CS_CLK_O的上升沿与第一片选采样奇信号PCS_OD的上升沿之间存在延时，目标指令信号CMD的脉冲宽度并非是预设时钟周期的两倍，而是预设时钟周期的2倍与所述延时的差值，所述延时指的是片选时钟奇信号CS_CLK_O的上升沿与第一片选采样奇信号PCS_OD的上升沿之间的延时；即目标指令信号CMD的脉冲宽度＝(2Tck-延时)，这导致目标指令信号CMD可能会在高频状态下或者PVT变化时出现由于脉冲宽度较小而失效的错误。在这里，2Tck表示预设时钟周期的2倍。
简单来说，在上述场景中，利用第一片选采样偶信号PCS_ED/第一片选采样奇信号PCS_OD来屏蔽时钟奇信号PCLK_O/时钟偶信号PCLK_E，使得片选时钟奇信号CS_CLK_O/片选时钟偶信号CS_CLK_E只会保留一个有效信号，且脉冲宽度为一个预设时钟周期(如图4中片选时钟奇信号CS_CLK_O)。然而，片选时钟奇信号CS_CLK_O/片选时钟偶信号CS_CLK_E中的有效信号在采样待处理指令奇信号CA[4:0]_1T_O/待处理指令偶信号CA[4:0]_1T_E经过组合逻辑之后的指令时，会产生一个没有下降沿的目标指令信号CMD，然后需要和第一片选采样奇信号PCS_OD/第一片选采样偶信号PCS_ED中的有效信号进行与逻辑运算，来产生目标指令信号CMD的下降沿，从而期望目标指令信号CMD的脉冲宽度为预设时钟周期的2倍。但由于第一片选采样奇信号PCS_OD的上升沿和片选时钟奇信号CS_CLK_O的上升沿之间有逻辑电路的延时，最后产生的目标指令信号CMD的脉冲宽度就会是(2Tck-延时)，导致该脉冲在高频和PVT变化下出现目标指令信号CMD的脉冲宽度不确定进而失效的错误。
基于此，本公开实施例提供了一种信号采样电路，该信号采样电路包括信号输入电路、时钟接收电路、采样逻辑电路和译码电路；其中，信号输入电路，用于确定待处理指令信号和待处理片选信号；时钟接收电路，用于接收初始时钟信号，并对初始时钟信号进行分频处理，得到第一时钟信号；其中，初始时钟信号的时钟周期为预设时钟周期，第一时钟信号的时钟周期为预设时钟周期的2倍；采样逻辑电路，用于根据第一时钟信号对待处理片选信号进行两级采样处理和逻辑运算处理，得到片选时钟信号；其中，片选时钟信号包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期；译码电路，用于根据待处理片选信号和片选时钟信号对待处理指令信号进行译码处理和采样处理，得到目标指令信号。这样，经过该信号采样电路的处理，片选时钟信号包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期，从而译码及采样之后的目标指令信号的脉冲宽度不会跟随工艺、电压、温度等变化产生偏差，改善目标指令信号的脉冲宽度不确定的问题，提高信号质量，防止数据失效。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图5，其示出了本公开实施例提供的一种信号采样电路40的组成结构示意图。如图5所示，信号采样电路40包括信号输入电路41、时钟接收电路42、采样逻辑电路43和译码电路44；其中，
信号输入电路41，用于确定待处理指令信号和待处理片选信号；
时钟接收电路42，用于接收初始时钟信号，并对初始时钟信号进行分频处理，得到第一时钟信号；其中，初始时钟信号的时钟周期为预设时钟周期，第一时钟信号的时钟周期为预设时钟周期的2倍；
采样逻辑电路43，用于根据第一时钟信号对待处理片选信号进行两级采样处理和逻辑运算处理，得到片选时钟信号；其中，片选时钟信号包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期；
译码电路44，用于根据待处理片选信号和片选时钟信号对待处理指令信号进行译码处理和采样处理，得到目标指令信号。
需要说明的是，本公开实施例的信号采样电路40可以应用于多种电路场景中，后续以DRAM中命令地址信号的指令译码过程为例进行解释和说明，但这并不构成相关限定。
因此，待处理指令信号可以是根据DRAM中命令地址信号确定的。待处理片选信号用于指示存 储芯片是否被选中的信号。在存储芯片被选中的情况下，待处理指令信号才是有效的。所以，待处理片选信号也是用于指示待处理指令信号是否有效的信号。目标指令信号是待处理指令信号译码得到的指令信号。
也就是说，在待处理片选信号有效的情况下，需要对待处理指令信号进行译码，得到目标指令信号。
需要说明的是，本公开实施例提供的信号采样电路40可以应用于两个预设时钟周期的指令信号(用2T CMD表示)。以下对2T CMD的场景进行简要说明。如图1所示，在2T CMD模式下，存在命令地址信号CA[13:0]和片选信号CS_n，且命令地址信号包括两个预设时钟周期的有效信号，相应地，目标指令信号CMD包括两个预设时钟周期的有效命令。应理解，在每一个时钟周期中，命令地址信号均是由多位信号构成的，即命令地址信号并非孤立的一个信号，而是由一组信号组成的，例如命令地址信号可以由CA[0]、CA[1]……CA[13]这14位信号构成，表示为CA[13:0]。另外，片选信号CS_n是用来指示存储芯片被选中的信号，且脉冲宽度为一个预设时钟周期，片选信号CS_n为低电平有效的脉冲信号，该时钟周期和该时钟周期的下一时钟周期对应的命令地址信号CA[13:0]是有效(Valid)的。具体地，第一个时钟周期的CA[13:0]和第二个时钟周期的CA[13:0]需要被采样为地址信号，且第一个时钟周期的CA[4:0]还需要被采样和译码为指令信号。在这里，CA[4:0]是指CA[0]、CA[1]、CA[2]、CA[3]和CA[4]。
在上述场景中，信号采样电路40可以用于命令地址信号作为指令信号的采样和译码过程。具体地，通过信号输入电路41，根据第一个时钟周期的命令地址信号CA[13:0]确定待处理指令信号，根据片选信号CS_n确定待处理片选信号。其次，通过时钟接收电路42，初始时钟信号经过分频处理后得到第一时钟信号。然后，通过采样逻辑电路43，利用第一时钟信号对待处理片选信号进行两级采样和逻辑运算处理，得到片选时钟信号，以使得片选时钟信号包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期。最后，对待处理片选信号和待处理指令信号一起进行译码处理，并将片选时钟信号作为时钟信号对译码处理后的信号进行采样输出，得到目标指令信号。
具体地，在一些实施例中，目标指令信号包括一个脉冲，且脉冲的宽度为两个预设时钟周期；其中，片选时钟信号中第一个脉冲的上升沿用于产生目标指令信号的上升沿，片选时钟信号中第二个脉冲的上升沿用于产生目标指令信号的下降沿。
需要说明的是，上升沿是指信号由低电平状态变化成高电平状态，下降沿是指信号由高电平状态变化为低电平状态。
这样，由于片选时钟信号的第一个脉冲的上升沿用来产生目标指令信号的上升沿，片选时钟信号的第二个脉冲的上升沿用来产生目标指令信号的下降沿，从而目标指令信号的脉冲宽度为预设时钟周期的2倍，能够避免目标指令信号的脉冲宽度不确定的问题，防止在高频环境下或者PVT变化的情况下出现数据失效。特别地，本公开实施例所述的“目标指令信号的脉冲宽度为预设时钟周期的2倍”指的是目标指令信号的脉冲宽度和预设时钟周期的2倍之间的偏差在预设精度范围内，其他涉及到信号脉冲宽度的说明也可参照理解。
在一些实施例中，第一时钟信号包括时钟奇信号和时钟偶信号；其中，时钟奇信号和时钟偶信号的时钟周期均是预设时钟周期的2倍，且时钟奇信号和时钟偶信号之间的相位差为180度。
在一些实施例中，在图5所示信号采样电路40的基础上，如图6所示，信号输入电路41包括第一输入电路411和第二输入电路412；其中，
第一输入电路411，用于接收初始指令信号，输出中间指令信号；以及利用时钟奇信号对中间指令信号进行采样处理，得到待处理指令奇信号，利用时钟偶信号对中间指令信号进行采样处理，得到待处理指令偶信号；
第二输入电路422，用于接收初始片选信号，输出中间片选信号；以及利用时钟奇信号对中间片选信号进行采样处理和反相处理，得到待处理片选奇信号，并利用时钟偶信号对中间片选信号进行采样处理和反相处理，得到待处理片选偶信号。
在这里，待处理指令奇信号和待处理指令偶信号组成待处理指令信号，待处理片选奇信号和待处理片选偶信号组成待处理片选信号。
在图6中，这里的初始时钟信号用于CK_t/CK_c进行表示，时钟奇信号用PCLK_O进行表示，时钟偶信号用PCLK_E进行表示，初始指令信号用CA[13:0]进行表示，待处理指令奇信号用CA[4:0]_1T_O进行表示，待处理指令偶信号用CA[4:0]_1T_E进行表示，初始片选信号CS_n，待处理片选奇信号用PCS_O进行表示，待处理片选偶信号用PCS_E进行表示。
需要注意的是，无论是初始指令信号还是中间指令信号，其并非是一个信号，而是代表一组命 令地址信号，即CA[0]～CA[13]，表示为CA[13:0]；因此，对于第一输入电路411而言，这里可以包括有14个相同的结构，分别用于接收和采样CA[0]、CA[1]、…、CA[13]等14个信号的，图中仅示出一个结构作为示意。
CA[13:0]的前5位信号被采样作为CA[4:0]_1T。也就是说，CA[4:0]_1T_E也并非是一个信号，而是代表一组命令地址信号，即CA[0]_1T_E～CA[4]_1T_E；CA[4:0]_1T_O也并非是一个信号，而是代表一组命令地址信号，即CA[0]_1T_O～CA[4]_1T_O。
通过第二输入电路412，可以对初始片选信号CS_n进行接收和采样处理，分别获得待处理片选奇信号PCS_O和待处理片选偶信号PCS_E。其中，初始片选信号CS_n为低电平有效的脉冲信号，如果初始片选信号CS_n在奇数时钟周期的上升沿为低电平，那么待处理片选奇信号PCS_O是有效的，待处理片选偶信号PCS_E是无效的；如果初始片选信号CS_n在偶数时钟周期的上升沿为低电平，那么待处理片选偶信号PCS_E是有效的，待处理片选奇信号PCS_O是无效的。也就是说，待处理片选奇信号PCS_O和待处理片选偶信号PCS_E之中至多存在一个有效信号。
在这里，偶数时钟周期或者奇数时钟周期是指初始时钟信号CK_t/CK_c的时钟周期。具体来说，对初始时钟信号经过分频处理之后，可以得到时钟奇信号PCLK_E和时钟偶信号PCLK_O；然后将时钟偶信号PCLK_E的上升沿所在的时钟周期作为偶数时钟周期，将时钟奇信号PCLK_O的上升沿所在的时钟周期作为奇数时钟周期。
在一种具体的实施例中，在图6的基础上，参见图7，第一输入电路411可以包括第一接收器511、第五触发器514和第六触发器515。其中，第一接收器511的输入端用于接收初始指令信号CA[13:0]和参考电压信号VREFCA，第一接收器511的输出端用于输出中间指令信号(用CA表示)；第五触发器514的输入端与第一接收器511的输出端连接，第五触发器514的时钟端与时钟偶信号PCLK_E连接，第五触发器514的输出端用于输出待处理指令偶信号CA[4:0]_1T_E。第六触发器515的输入端与第一接收器511的输出端连接，第六触发器515的时钟端与时钟奇信号PCLK_O连接，第六触发器515的输出端用于输出待处理指令奇信号CA[4:0]_1T_O。
如图7所示，第二输入电路412可以包括第二接收器512、第七触发器516、第一反相器517、第八触发器518和第二反相器519。其中，第二接收器512的输入端用于接收初始片选信号CS_n和参考电压信号VREFCA，第二接收器512的输出端用于输出中间片选信号(用PCS表示)；第七触发器516的输入端与第二接收器512的输出端连接，第七触发器516的时钟端与时钟偶信号PCLK_E连接，第七触发器516的输出端与第一反相器517连接，第一反相器517的输出端用于输出待处理片选偶信号PCS_E。第八触发器518的输入端与第二接收器512的输出端连接，第八触发器518的时钟端与时钟奇信号PCLK_O连接，第八触发器518的输出端与第二反相器519连接，第二反相器519的输出端用于输出待处理片选奇信号PCS_O。
应理解，由于中间片选信号PCS为低电平有效的脉冲信号，因此需要在第七触发器516和第八触发器518之后对应设置第一反相器517和第二反相器519，以使得中间采样偶信号PCS_E或者中间采样奇信号PCS_O变成高电平有效的脉冲信号，以便后续的逻辑运算。另外，第七触发器516和第八触发器518之后也可以不设置第一反相器517和第二反相器519，那么后续的逻辑运算则需进行相应调整，从而达到相同效果。
还需要说明的是，如图7所示，时钟接收电路42可以包括第三接收器513，第三接收器513的输入端用于接收初始时钟信号CK_t/CK_c，第三接收器513的输出端用于输出时钟奇信号PCLK_O和时钟偶信号PCLK_E。在这里，CK_t/CK_c是一组时钟周期相同，但是相位差为180度的信号，PCLK_O/PCLK_E也是一组时钟周期相同，但是相位差为180度的信号，且CK_t/CK_c的时钟周期为预设时钟周期，PCLK_O/PCLK_E的时钟周期为预设时钟周期的2倍。
这样，通过信号输入电路41和时钟接收电路42，获得时钟奇信号PCLK_O、时钟偶信号PCLK_E、待处理片选奇信号PCS_O、待处理片选偶信号PCS_E、待处理指令奇信号CA[4:0]_1T_O和待处理指令偶信号CA[4:0]_1T_E，以便进行后续处理。
在一些实施例中，如图6所示，采样逻辑电路43可以包括第一采样电路431、第二采样电路432、第一逻辑电路433和第二逻辑电路434；其中，
第一采样电路431，用于利用时钟奇信号对待处理片选偶信号进行第一级采样处理，得到第一片选采样奇信号；并利用时钟奇信号对第一片选采样奇信号进行第二级采样处理，得到第二片选采样奇信号；
第二采样电路432，用于利用时钟偶信号对待处理片选奇信号进行第一级采样处理，得到第一片选采样偶信号；并利用时钟偶信号对第一片选采样偶信号进行第二级采样处理，得到第二片选采 样偶信号；
第一逻辑电路433，用于对时钟奇信号、第一片选采样奇信号和第二片选采样奇信号进行逻辑运算，得到片选时钟奇信号；
第二逻辑电路434，用于对时钟偶信号、第一片选采样偶信号和第二片选采样偶信号进行逻辑运算，得到片选时钟偶信号。
在这里，片选时钟偶信号和片选时钟奇信号组成片选时钟信号。
需要说明的是，在采样逻辑电路43中，第一采样电路431和第一逻辑电路433用于确定片选时钟奇信号；第二采样电路432和第二逻辑电路434用于确定片选时钟偶信号。
在图6中，这里的第一片选采样奇信号用PCS_OD表示，第一片选采样偶信号用PCS_ED表示，第二片选采样奇信号用PCS_ODD表示，第二片选采样偶信号用PCS_EDD表示，片选时钟奇信号用CS_CLK_O表示，这里的片选时钟偶信号用CS_CLK_E表示。
如前述，待处理片选奇信号PCS_O和待处理片选偶信号PCS_E之中至多只有一个有效，在待处理片选偶信号PCS_E有效的情况下，第一片选采样奇信号PCS_OD、第二片选采样奇信号PCS_ODD和片选时钟奇信号CS_CLK_O是有效的；在待处理片选奇信号PCS_O有效的情况下，第一片选采样偶信号PCS_ED、第二片选采样偶信号PCS_EDD和片选时钟偶信号CS_CLK_E是有效的。
在一些实施例中，第一级采样处理是指上升沿采样处理，第二级采样处理是指下降沿采样处理。
也就是说，通过第一采样电路431，利用时钟奇信号PCLK_O的上升沿对待处理片选偶信号PCS_E进行采样，得到第一片选采样奇信号PCS_OD，再利用时钟奇信号PCLK_O的下降沿对第一片选采样奇信号PCS_OD进行采样，得到第二片选采样奇信号PCS_ODD。这样，在待处理片选偶信号PCS_E有效的情况下，待处理片选偶信号PCS_E的上升沿、第一片选采样奇信号PCS_OD的上升沿和第二片选采样奇信号PCS_ODD的上升沿依次延迟了一个预设时钟周期。然后，通过第一逻辑电路433对时钟奇信号PCLK_O、第一片选采样奇信号PCS_OD和第二片选采样奇信号PCS_ODD进行运算，得到存在两个脉冲且每个脉冲为一个预设时钟周期的片选时钟奇信号CS_CLK_O。
类似地，通过第二采样电路432，利用时钟偶信号PCLK_E的上升沿对待处理片选奇信号PCS_O进行采样，得到第一片选采样偶信号PCS_ED，再利用时钟偶信号PCLK_E的下降沿对第一片选采样偶信号PCS_ED进行采样，得到第二片选采样偶信号PCS_EDD。这样，在待处理片选奇信号PCS_O有效的情况下，待处理片选奇信号PCS_O的上升沿、第一片选采样偶信号PCS_ED的上升沿和第二片选采样偶信号PCS_EDD的上升沿依次延迟了一个预设时钟周期。然后，通过第二逻辑电路434对时钟偶信号PCLK_E、第一片选采样偶信号PCS_ED和第二片选采样偶信号PCS_EDD进行运算，得到存在两个脉冲且每个脉冲为一个预设时钟周期的片选时钟偶信号CS_CLK_E。
需要说明的是，在本公开实施例中，其他未明确说明类型的采样处理均可选择采用上升沿采样。
这样，通过两级采样(上升沿采样和下降沿采样)和逻辑运算处理，能够得到存在两个脉冲且每个脉冲为一个预设时钟周期的片选时钟信号(片选时钟奇信号或者片选时钟偶信号)，后续保证目标指令信号的脉冲宽度为预设时钟周期的2倍，避免目标指令信号的脉冲宽度不确定的问题，防止在高频环境下或者PVT变化的情况下出现数据错误。特别地，本公开实施例所述的“目标指令信号的脉冲宽度为预设时钟周期的2倍”指的是目标指令信号的脉冲宽度和预设时钟周期的2倍之间的偏差在预设精度范围内。
应理解，第一级采样和第二级采样的目的是为了保证后续经过逻辑处理后得到的片选时钟信号包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期。因此，采用上升沿采样作为第一级采样，采用下降沿采样作为第二级采样只是一种可行的方式，并不构成相关限制。
在第一级采样为上升沿采样，第二级采样为下降沿采样的情况下，第一采样电路431和第二采样电路432可以采用以下结构。
在一种具体的实施例中，如图7所示，第一采样电路431可以包括第一触发器501、第一非门502和第二触发器503；其中，
第一触发器501的输入端与待处理片选偶信号PCS_E连接，第一触发器501的时钟端与时钟奇信号PCLK_O连接，第一触发器501的输出端用于输出第一片选采样奇信号PCS_OD，第二触发器503的输入端与第一触发器501输出端连接，第一非门502的输入端与时钟奇信号PCLK_O连接，第一非门502的输出端与第二触发器503的时钟端连接，第二触发器503的输出端用于输出第二片选采样奇信号PCS_ODD。
需要说明的是，通过第一非门502对时钟奇信号PCLK_O进行反相处理，然后利用反相处理后的时钟奇信号PCLK_O的上升沿对第一片选采样奇信号PCS_OD进行采样，以实现利用时钟奇信号PCLK_O的下降沿对第一片选采样奇信号PCS_OD进行采样。
在一种具体的实施例中，如图7所示，第二采样电路432可以包括第三触发器504、第二非门505和第四触发器506；其中，
第三触发器504的输入端与待处理片选奇信号PCS_O连接，第三触发器504的时钟端与时钟偶信号PCLK_E连接，第三触发器504的输出端用于输出第一片选采样偶信号PCS_ED，第四触发器506的输入端与第三触发器504的输出端连接，第二非门505的输入端与时钟偶信号PCLK_E连接，第二非门505的输出端与第四触发器506的时钟端连接，第四触发器506的输出端用于输出第二片选采样偶信号PCS_EDD。
需要说明的是，通过第二非门505对时钟偶信号PCLK_E进行反相处理，然后利用反相处理后的时钟偶信号PCLK_E的上升沿对第一片选采样偶信号PCS_ED进行采样，以实现利用时钟偶信号PCLK_E的下降沿对第一片选采样偶信号PCS_ED进行采样。
示例性地，前述的第一触发器501、第二触发器503、第三触发器504、第四触发器506、第五触发器514、第六触发器515、第七触发器516、第八触发器518均可以为D型触发器。
在一种具体的实施例中，如图6和图7所示，第一逻辑电路433可以包括第一或门507和第一与门508；其中，
第一或门507，用于对第一片选采样奇信号PCS_OD和第二片选采样奇信号用PCS_ODD表示进行或运算，得到中间奇信号；
第一与门508，用于对中间奇信号和时钟奇信号PCLK_O进行与运算，得到片选时钟奇信号CS_CLK_O。
需要说明的是，在第一片选采样奇信号PCS_OD和第二片选采样奇信号PCS_ODD有效的情况下，第一片选采样奇信号PCS_OD和第二片选采样奇信号PCS_ODD进行或运算能够拓宽脉冲宽度，所得到的中间奇信号的脉冲宽度是预设时钟周期的3倍，中间奇信号再与时钟奇信号PCLK_O做与逻辑，所得到的片选时钟奇信号CS_CLK_O具有两个脉冲，且脉冲宽度为一个预设时钟周期。这样，利用片选时钟奇信号进行后续的采样和译码，从而使得最终输出的目标指令信号的脉冲宽度为预设时钟周期的2倍。
另外，在第一片选采样奇信号PCS_OD和第二片选采样奇信号PCS_ODD无效的情况下，片选时钟奇信号CS_CLK_O为无效状态。
在一种具体的实施例中，第二逻辑电路434可以包括第二或门509和第二与门510；其中，
第二或门509，用于对第一片选采样偶信号PCS_ED和第二片选采样偶信号PCS_EDD进行或运算，得到中间偶信号；
第二与门510，用于对中间偶信号和时钟偶信号PCLK_E进行与运算，得到片选时钟偶信号CS_CLK_E。
需要说明的是，在第一片选采样偶信号PCS_ED和第二片选采样偶信号PCS_EDD有效的情况下，第一片选采样偶信号PCS_ED和第二片选采样偶信号PCS_EDD进行或运算能够拓宽脉冲宽度，所得到的中间偶信号的脉冲宽度是预设时钟周期的3倍，中间偶信号再与时钟偶信号PCLK_E做与逻辑，所得到的片选时钟偶信号CS_CLK_E具有两个脉冲，且脉冲宽度为一个预设时钟周期。
另外，在第一片选采样偶信号PCS_ED和第二片选采样偶信号PCS_EDD无效的情况下，片选时钟偶信号CS_CLK_E也为无效状态。
这样，通过采样逻辑电路43，利用时钟奇信号PCLK_O/时钟偶信号PCLK_E对待处理片选奇信号PCS_O/待处理片选偶信号PCS_E进行两级采样和逻辑运算，得到片选时钟奇信号CS_CLK_O/片选时钟偶信号CS_CLK_E，后续根据待处理片选奇信号PCS_O/待处理片选偶信号PCS_E、片选时钟奇信号CS_CLK_O/片选时钟偶信号CS_CLK_E这两对信号对待处理指令奇信号CA[4:0]_1T_O/待处理指令偶信号CA[4:0]_1T_E进行译码和采样处理，从而使得最终输出的目标指令信号的脉冲宽度为预设时钟周期的2倍。
在一些实施例中，如图6和图7所示，译码电路44可以包括第一指令译码电路441、第二指令译码电路442以及第三或门443；其中，
第一指令译码电路441，用于根据待处理片选偶信号PCS_E和片选时钟奇信号CS_CLK_O对待处理指令偶信号CA[4:0]_1T_E进行译码和采样处理，得到指令偶信号CMD_E；
第二指令译码电路442，用于根据待处理片选奇信号PCS_O和片选时钟偶信号CS_CLK_E对待 处理指令奇信号CA[4:0]_1T_O进行译码和采样处理，得到指令奇信号CMD_O；
第三或门443，用于对指令偶信号CMD_E和指令奇信号CMD_O进行或运算，得到目标指令信号CMD。
需要说明的是，根据前述的初始片选信号CS_n的功能，若初始片选信号CS_n在偶数时钟周期的上升沿采样为低电平，则待处理片选偶信号PCS_E和片选时钟奇信号CS_CLK_O是有效的，此时第一指令译码电路441输出的指令偶信号CMD_E是有效的，第二指令译码电路442输出的指令奇信号CMD_O是无效的，通过第三或门443将指令偶信号CMD_E作为目标指令信号CMD进行输出。反之，若初始片选信号CS_n在奇数时钟周期的上升沿采样为低电平，则待处理片选奇信号PCS_O和片选时钟偶信号CS_CLK_E是有效的，此时第二指令译码电路442输出的指令奇信号CMD_O是有效的，第一指令译码电路441输出的指令偶信号CMD_E是无效的，通过第三或门443将指令奇信号CMD_O作为目标指令信号CMD进行输出。
换句话说，在一种情况中，初始片选信号是表征目标芯片被选中的信号，且初始片选信号为低电平有效的脉冲信号；其中，若初始片选信号在偶数时钟周期的上升沿采样为低电平，则待处理片选偶信号为高电平有效的脉冲信号；相应地，片选时钟奇信号中第一个脉冲的上升沿用于产生目标指令信号的上升沿，片选时钟奇信号中第二个脉冲的上升沿用于产生目标指令信号的下降沿。
在另一种情况中，若初始片选信号在奇数时钟周期的上升沿采样为低电平，则待处理片选奇信号为高电平有效的脉冲信号；相应地，片选时钟偶信号中第一个脉冲的上升沿用于产生目标指令信号的上升沿，片选时钟偶信号中第二个脉冲的上升沿用于产生目标指令信号的下降沿。
这样，由于片选时钟信号中的有效信号(片选时钟奇信号CS_CLK_O或者片选时钟偶信号CS_CLK_E)包括两个脉冲，且每个脉冲的脉冲宽度是一个预设时钟周期，且第一个脉冲的上升沿用于产生目标指令信号CMD的上升沿，第二个脉冲的上升沿用于产生目标指令信号CMD的下降沿，从而使得最终输出的目标指令信号CMD的脉冲宽度为预设时钟周期的2倍，即目标指令信号CMD的脉冲宽度与预设时钟周期的2倍之间的偏差在预设精度范围内。
需要注意的是，第一指令译码电路441和第二指令译码电路442的具体设计是根据指令译码规则确定，对于不同的产品/不同的应用场景/不同的指令，译码规则可能不同，那么指令译码电路的逻辑也可以相应调整。
在一种具体的实施例中，如图8A所示，第一指令译码电路441可以包括第一译码电路和第三采样电路；其中，
第一译码电路，用于对待处理指令偶信号CA[4:0]_1T_E和待处理片选偶信号PCS_E进行译码处理，得到指令译码偶信号；
第三采样电路，用于根据片选时钟奇信号CS_CLK_O对指令译码偶信号进行采样处理，得到指令偶信号CMD_E。
需要说明的是，在图8A中，待处理指令偶信号CA[4:0]_1T_E可以包括CA[0]_1T_E、CA[1]_1T_E、CA[2]_1T_E、CA[3]_1T_E、CA[4]_1T_E等指令信号，而且第一译码电路可以是由三输入与非门、三输入与非门和二输入或非门组成。其中，如图8A所示，PCS_E、CA[0]_1T_E和CA[1]_1T_E输入到第一个三输入与非门，CA[2]_1T_E、CA[3]_1T_E和CA[4]_1T_E输入到第二个三输入与非门，然后第一个三输入与非门的输出端和二输入或非门的一个输入端连接，第二个三输入与非门的输出端和二输入或非门的另一个输入端连接，而二输入或非门的输出端用于输出指令译码偶信号，从而实现对待处理片选偶信号PCS_E和待处理指令偶信号CA[4:0]_1T_E的译码。
需要说明的是，第一指令译码电路441的具体设计是根据指令译码规则确定的，对于不同的产品/不同的应用场景/不同的指令，译码规则可能不同，那么指令译码电路的逻辑也可以相应调整。
在得到指令译码偶信号后，利用第三采样电路进行采样输出。具体地，第三采样电路可以为一个D型触发器，该D型触发器的时钟端与片选时钟奇信号CS_CLK_O连接，D型触发器的输入端与二输入或非门的输出端连接，D型触发器的输出端用于输出指令偶信号CMD_E。
类似地，在一种具体的实施例中，如图8B所示，第二指令译码电路442包括第二译码电路和第四采样电路；其中，
第二译码电路，用于对待处理指令奇信号CA[4:0]_1T_O和待处理片选奇信号PCS_O进行译码处理，得到指令译码奇信号；
第四采样电路，用于根据片选时钟偶信号CS_CLK_E对指令译码奇信号进行采样处理，得到指令奇信号CMD_O。
需要说明的是，在图8B中，待处理指令奇信号CA[4:0]_1T_O可以包括CA[0]_1T_O、 CA[1]_1T_O、CA[2]_1T_O、CA[3]_1T_O、CA[4]_1T_O等指令信号，而且第二译码电路可以是由三输入与非门、三输入与非门和二输入或非门组成。其中，如图8B所示，PCS_O、CA[0]_1T_O和CA[1]_1T_O输入到第一个三输入与非门，CA[2]_1T_O、CA[3]_1T_O和CA[4]_1T_O输入到第二个三输入与非门，然后第一个三输入与非门的输出端和二输入或非门的一个输入端连接，第二个三输入与非门的输出端和二输入或非门的另一个输入端连接，而二输入或非门的输出端用于输出指令译码奇信号，从而实现对待处理片选奇信号PCS_O和待处理指令奇信号CA[4:0]_1T_O的译码。
需要说明的是，第二指令译码电路442的具体设计是根据指令译码规则确定的，对于不同的产品/不同的应用场景/不同的指令，译码规则可能不同，那么指令译码电路的逻辑也可以相应调整。
在得到指令译码奇信号后，利用第四采样电路进行采样输出。具体地，第四采样电路可以为一个D型触发器，该D型触发器的时钟端与片选时钟偶信号CS_CLK_E连接，D型触发器的输入端与二输入或非门的输出端连接，D型触发器的输出端用于输出指令奇信号CMD_O。
从以上可以看出，通过信号采样电路，利用第一时钟信号对待处理片选信号进行两级采样和逻辑运算，得到片选时钟信号，使片选时钟信号包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期，从而片选时钟信号的第一个脉冲的上升沿用于产生目标指令信号的上升沿，片选时钟信号的第二个脉冲的上升沿用于产生目标指令信号的下降沿，从而使得最终输出的目标指令信号的脉冲宽度为预设时钟周期的2倍，避免目标指令信号的脉冲宽度不确定的问题，防止在高频环境下或者PVT变化的情况下出现数据错误。
本公开实施例提供了一种信号采样电路，该信号采样电路包括信号输入电路、时钟接收电路、采样逻辑电路和译码电路；其中，信号输入电路，用于确定待处理指令信号和待处理片选信号；时钟接收电路，用于接收初始时钟信号，并对初始时钟信号进行分频处理，得到第一时钟信号；其中，初始时钟信号的时钟周期为预设时钟周期，第一时钟信号的时钟周期为预设时钟周期的2倍；采样逻辑电路，用于根据第一时钟信号对待处理片选信号进行两级采样处理和逻辑运算处理，得到片选时钟信号；其中，片选时钟信号包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期；译码电路，用于根据待处理片选信号和片选时钟信号对待处理指令信号进行译码处理和采样处理，得到目标指令信号。这样，经过该信号采样电路的处理，片选时钟信号包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期，从而译码及采样之后的目标指令信号的脉冲宽度不会跟随工艺、电压、温度等变化产生偏差，改善目标指令信号的脉冲宽度不确定的问题，提高信号质量，防止数据失效。
在本公开的另一实施例中，基于前述实施例所述的信号采样电路40，参见图9，其示出了本公开实施例提供的一种信号采样电路的详细结构示意图。如图9所示，信号采样电路40可以包括第一接收器611、第二接收器612、第三接收器613、第五触发器614、第六触发器615、第七触发器616、第一反相器617、第八触发器618、第二反相器619、第一触发器601、第一非门602、第二触发器603、第三触发器604、第二非门605、第四触发器606、第一或门607、第一与门608、第二或门609、第二与门610、指令译码器620、第三或门621。其中，第一触发器601、第二触发603、第三触发器604、第四触发器606、第五触发器614、第六触发器615、第七触发器616、第八触发器618均可以为D型触发器。另外，指令译码器620可以包括第一指令译码电路和第二指令译码电路，具体结构详见图8A和图8B所示。
在图9中，首先，第一接收器611的输入信号为初始指令信号(用CA[13:0]表示)和参考信号(用VREFCA表示)，输出信号为中间指令信号(用CA表示)。需要注意的是，对于初始指令信号和中间指令信号，其并非是一个信号，而是代表一组信号，即CA[13:0]包括了CA[13]～CA[0]；针对每一个信号都需要一个第一接收器611和第五触发器614，故本公开实施例需要14个第一接收器611和14个第五触发器614，图中仅示出一个第一接收器611和第五触发器614作为示意。第二接收器612的输入信号为初始片选信号(用CS_n表示)和参考信号(用VREFCA表示)，输出信号为中间片选信号(用PCS表示)；第三接收器613的输入信号为初始时钟信号(包括CK_t信号和CK_c信号)，经过分频处理后输出信号为时钟偶信号(用PCLK_E表示)和时钟奇信号(用PCLK_O表示)。在这里，CK_t/CK_c的时钟周期为预设时钟周期，PCLK_E_/PCLK_O的时钟周期是预设时钟周期的2倍。
其次，通过第五触发器614，利用时钟偶信号PCLK_E对中间指令信号CA进行采样处理，得到待处理指令偶信号(用CA[4:0]_1T_E表示)；通过第六触发器615，利用时钟奇信号PCLK_O对中间指令信号CA进行采样处理，得到待处理指令奇信号(用CA[4:0]_1T_O表示)；通过第七触发器616和第一反相器617，利用时钟偶信号PCLK_E对中间片选信号PCS进行采样及反相处理，得到待处理片选偶信号(用PCS_E表示)，通过第八触发器618和第二反相器619，利用时钟奇信号 PCLK_O对中间片选信号PCS进行采样及反相处理，得到待处理片选奇信号(用PCS_O表示)。需要注意的是，CA[4:0]包括了CA[4]～CA[0]，即初始指令信号CA[13:0]中的前5位信号在经过接收和采样后形成待处理指令奇信号CA[4:0]_1T_O和待处理指令偶信号CA[4:0]_1T_E。
然后，通过第一触发器601，利用时钟奇信号PCLK_O的上升沿对PCS_E进行采样处理，得到第一片选采样奇信号(用PCS_OD表示)，通过第一非门602和第二触发器603，利用时钟奇信号PCLK_O的下降沿对第一片选采样奇信号PCS_OD进行采样处理，得到第二片选采样奇信号(用PCS_ODD表示)，通过第一或门607对第一片选采样奇信号PCS_OD和第二片选采样奇信号PCS_ODD进行或运算，得到中间奇信号，通过第二与门610对中间奇信号和时钟奇信号PCLK_O进行与运算，得到片选时钟奇信号(用CS_CLK_O表示)。类似地，通过第三触发器604，利用时钟偶信号PCLK_E的上升沿对待处理片选奇信号PCS_O进行采样处理，得到第一片选采样偶信号(用PCS_ED表示)，通过第二非门605和第四触发器606，利用时钟偶信号PCLK_E的下降沿对第一片选采样偶信号PCS_ED进行采样处理，得到第二片选采样偶信号(用PCS_EDD表示)，通过第二或门609对第一片选采样偶信号PCS_ED和第二片选采样偶信号PCS_EDD进行或运算，得到中间偶信号，通过第二与门610对中间偶信号和时钟偶信号PCLK_E进行与运算，得到片选时钟偶信号(用CS_CLK_E表示)。在这里，片选时钟偶信号CS_CLK_E和片选时钟奇信号CS_CLK_O之中至多存在一个有效信号。
最后，通过指令译码器620，利用片选时钟偶信号CS_CLK_E信号/片选时钟奇信号CS_CLK_O信号对待处理指令偶信号CA[4:0]_1T_E信号/待处理指令奇信号CA[4:0]_1T_O信号、待处理片选偶信号PCS_E信号/待处理片选奇信号PCS_O信号进行译码及采样处理，得到指令偶信号(用CMD_E表示)和指令奇信号(用CMD_O表示)，再通过第三或门621对指令偶信号CMD_E和指令奇信号CMD_O进行或逻辑运算，得到目标指令信号(用CMD表示)。
信号采样电路40的详细工作原理可参见前述实施例，在此不作赘述。
这样，通过以上处理，片选时钟偶信号CS_CLK_E/片选时钟奇信号CS_CLK_O之中的有效信号存在两个脉冲，且每个脉冲的宽度为一个预设时钟周期；利用片选时钟偶信号CS_CLK_E/片选时钟奇信号CS_CLK_O之中的有效信号的两个脉冲对译码后的指令信号进行采样后，得到的目标指令信号CMD的脉冲宽度为预设时钟周期的2倍，不会随着PVT进行变化，从而解决在高频和PVT变化下出现目标指令信号CMD脉冲宽度不确定而失效的错误。特别地，本公开实施例所述的“目标指令信号的脉冲宽度为预设时钟周期的2倍”指的是目标指令信号的脉冲宽度和预设时钟周期的2倍之间的偏差在预设精度范围内。
在一种具体的场景中，假设初始指令信号在偶数时钟沿采样呈现低电平有效，此时图9所示的信号采样电路40的信号时序图如图10所示。在图10中，中间指令信号用CA表示，且CA可以包括Cy、Cz、C0、C1、C2和C3；初始片选信号用CS_n表示，中间片选信号用PCS表示，PCS为低电平有效的脉冲信号，且脉冲宽度为预设时钟周期，PCS用于表征目标芯片被选中的信号；其他信号的说明请参见前述。在这里，偶数时钟周期或者奇数时钟周期是指初始时钟信号CK_t/CK_c的时钟周期。具体来说，经过第三接收器613的分频处理之后，可以得到时钟奇信号PCLK_E和时钟偶信号PCLK_O；然后将时钟偶信号PCLK_E的上升沿所在的时钟周期作为偶数时钟周期，将时钟奇信号PCLK_O的上升沿所在的时钟周期作为奇数时钟周期。
在利用时钟偶信号PCLK_E的上升沿对中间指令信号用CA进行采样处理后，得到待处理指令偶信号CA[4:0]_1T_E，其包括C0和C2。在初始片选信号CS_n被接收后产生中间片选信号PCS，在利用时钟偶信号PCLK_E的上升沿对中间片选信号PCS进行第1级采样及反相处理后，得到待处理片选偶信号PCS_E，在利用时钟奇信号PCLK_O对待处理片选偶信号PCS_E进行第2级采样后，得到第一片选采样奇信号PCS_OD，在利用时钟奇信号PCLK_O对第一片选采样奇信号PCS_OD进行第3级采样后，得到第二片选采样奇信号PCS_ODD；类似地，在利用时钟奇信号PCLK_O信号的上升沿对中间片选信号PCS进行第1级采样及反相处理后，得到待处理片选奇信号(用PCS_O表示)，在利用时钟偶信号PCLK_E对待处理片选奇信号PCS_O进行第2级采样后，得到第一片选采样偶信号PCS_ED，在利用时钟偶信号PCLK_E对第一片选采样偶信号PCS_ED进行第3级采样后，得到第二片选采样偶信号PCS_EDD。
需要注意的是，以中间片选信号PCS为起始点开始对采样进行编号，在前述实施例中，以待处理片选奇信号PCS_O/待处理片选偶信号PCS_E为起始点开始对采样进行编号，所以本实施例中的第2级采样相当于前述的第一级采样，第3级采样相当于前述的第二级采样。同样的，第3级采样为下降沿采样，其他未明确说明的采样可以选择为上升沿采样。
在本场景中，初始片选信号CS_n在偶数时钟沿采样呈现低电平有效，因此待处理片选偶信号PCS_E、第一片选采样奇信号PCS_OD和第二片选采样奇信号PCS_ODD均为高电平有效的脉冲信号，且待处理片选偶信号PCS_E、第一片选采样奇信号PCS_OD和第二片选采样奇信号PCS_ODD的上升沿依次相差一个预设时钟周期。通过对第一片选采样奇信号PCS_OD、第二片选采样奇信号PCS_ODD与时钟奇信号PCLK_O进行逻辑运算，得到片选时钟奇信号CS_CLK_O。如图10所示，片选时钟奇信号CS_CLK_O包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期。
在得到片选时钟奇信号CS_CLK_O后，利用前述的指令译码器620，对待处理指令偶信号CA[4:0]_1T_E和待处理片选偶信号PCS_E进行译码，并以片选时钟奇信号CS_CLK_O为时钟信号进行采样输出，得到目标指令信号CMD。如图10所示，片选时钟奇信号CS_CLK_O中的第一个脉冲的上升沿用来产生目标指令信号CMD的上升沿，片选时钟奇信号CS_CLK_O中的第二个脉冲的上升沿用来产生目标指令信号CMD的下降沿，保证目标指令信号CMD的脉冲宽度为预设时钟周期的2倍。
另外，在本场景中，由于初始时钟信号CS_n在偶数时钟沿采样呈现低电平有效，所以待处理片选奇信号PCS_O、第一片选采样偶信号PCS_ED和第二片选采样偶信号PCS_EDD为低电平的无效信号，计算到的片选时钟偶信号CS_CLK_E也为无效信号，从对指令译码器620并不会利用片选时钟偶信号CS_CLK_E进行采样输出。
当然，在另一场景中，假设初始片选信号CS_n在奇数时钟沿采样呈现低电平有效，此时待处理片选偶信号PCS_E、第一片选采样奇信号PCS_OD、第二片选采样奇信号PCS_ODD、片选时钟奇信号CS_CLK_O将处于无效状态；待处理片选奇信号PCS_O、第一片选采样偶信号PCS_ED、第二片选采样偶信号PCS_EDD、片选时钟偶信号CS_CLK_E将处于有效状态，且片选时钟偶信号CS_CLK_E包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期。这样，指令译码器620将根据片选时钟偶信号CS_CLK_E进行采样输出，得到目标指令信号CMD信号，片选时钟偶信号CS_CLK_E中的第一个脉冲的上升沿用来产生目标指令信号CMD的上升沿，片选时钟偶信号CS_CLK_E中的第二个脉冲的上升沿用来产生目标指令信号CMD的下降沿，同样保证CMD的脉冲宽度为预设时钟周期的2倍。
简单来说，如图9和图10所示，内容为C0的中间指令信号CA和低电平有效的中间片选信号PCS被时钟偶信号PCLK_E在第1级采样，产生待处理片选偶信号PCS_E和待处理指令偶信号CA[4:0]_1T_E；然后待处理片选偶信号PCS_E被时钟奇信号PCLK_O上升沿在第2级采样，产生第一片选采样奇信号PCS_OD，第一片选采样奇信号PCS_OD再被时钟奇信号PCLK_O的下降沿在第3级采样，产生第二片选采样奇信号PCS_ODD。由第一片选采样奇信号PCS_OD和第二片选采样奇信号PCS_ODD进行或逻辑之后选取时钟奇信号PCLK_O的有效脉冲，产生了两个脉冲的片选时钟奇信号CS_CLK_O，且每个脉冲的宽度为一个预设时钟周期。
在这里，第一片选采样奇信号PCS_OD和第二片选采样奇信号PCS_ODD进行或运算是为了拓宽脉冲宽度，所得到的中间奇信号的脉冲宽度是预设时钟周期的3倍，中间奇信号再与时钟奇信号PCLK_O做与逻辑，所得到的片选时钟奇信号CS_CLK_O具有两个脉冲，且脉冲宽度为一个预设时钟周期。其中，对于片选时钟奇信号CS_CLK_O，第一个脉冲的目的用于采样输出目标指令信号CMD，第二个脉冲的目的是产生目标指令信号CMD的下降沿。这样，目标指令信号CMD的脉冲宽度为预设时钟周期的2倍，该脉冲宽度不随PVT变化而变化。从而解决在高频和PVT变化下出现目标指令信号CMD脉冲宽度不确定而失效的错误。
本公开实施例提供了一种信号采样电路，通过本实施例对前述实施例的具体实现进行详细阐述，从中可以看出，本公开实施例是在已有的直接采样译码的基础上进行优化，使得片选时钟信号包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期，从而译码之后的目标指令信号的脉冲宽度为预设时钟周期的2倍，目标指令信号的脉冲宽度不会跟随工艺、电压、温度等变化产生偏差，改善目标指令信号的脉冲宽度不确定的问题，提高信号质量，防止数据失效。
在本公开的又一实施例中，参见图11，其示出了本公开实施例提供的一种半导体存储器110的组成结构示意图。如图11所示，半导体存储器110可以包括前述实施例任一项所述的信号采样电路40。
在本公开实施例中，半导体存储器110可以为DRAM芯片。
进一步地，在一些实施例中，DRAM芯片符合DDR5内存规格。
需要说明的是，本公开实施例主要涉及集成电路设计中指令译码的相关电路，本公开实施例是针对2T CMD，在已有的直接采样译码的基础上进行优化，使得片选时钟信号包括两个脉冲，且每 个脉冲的宽度为一个预设时钟周期，从而译码之后的目标指令信号的脉冲宽度为预设时钟周期的2倍。
还需要说明的是，本公开实施例可以应用于DRAM芯片中命令地址信号采样和译码的控制电路，但并不局限于此范围，其他输入信号采样及指令译码的相关电路均可采用此设计。
这样，在本公开实施例中，对于半导体存储器110而言，其包括有信号采样电路40，目标指令信号的脉冲宽度不会跟随工艺、电压、温度等变化产生偏差，改善目标指令信号的脉冲宽度不确定的问题，提高信号质量，防止数据失效。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种信号采样电路以及半导体存储器，该信号采样电路包括信号输入电路、时钟接收电路、采样逻辑电路和译码电路；其中，信号输入电路，用于确定待处理指令信号和待处理片选信号；时钟接收电路，用于接收初始时钟信号，并对初始时钟信号进行分频处理，得到第一时钟信号；其中，初始时钟信号的时钟周期为预设时钟周期，第一时钟信号的时钟周期为预设时钟周期的2倍；采样逻辑电路，用于根据第一时钟信号对待处理片选信号进行两级采样处理和逻辑运算处理，得到片选时钟信号；其中，片选时钟信号包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期；译码电路，用于根据待处理片选信号和片选时钟信号对待处理指令信号进行译码处理和采样处理，得到目标指令信号。这样，经过该信号采样电路的处理，片选时钟信号包括两个脉冲，且每个脉冲的宽度为一个预设时钟周期，从而译码及采样之后的目标指令信号的脉冲宽度不会跟随工艺、电压、温度等变化产生偏差，改善目标指令信号的脉冲宽度不确定的问题，防止数据失效。

Claims (17)

  1. 一种信号采样电路，所述信号采样电路包括信号输入电路、时钟接收电路、采样逻辑电路和译码电路；其中，
    所述信号输入电路，用于确定待处理指令信号和待处理片选信号；
    所述时钟接收电路，用于接收初始时钟信号，并对所述初始时钟信号进行分频处理，得到第一时钟信号；其中，所述初始时钟信号的时钟周期为预设时钟周期，所述第一时钟信号的时钟周期为所述预设时钟周期的2倍；
    所述采样逻辑电路，用于根据所述第一时钟信号对所述待处理片选信号进行两级采样处理和逻辑运算处理，得到片选时钟信号；其中，所述片选时钟信号包括两个脉冲，且每个脉冲的宽度为预设时钟周期；
    所述译码电路，用于根据所述待处理片选信号和所述片选时钟信号对所述待处理指令信号进行译码处理和采样处理，得到目标指令信号。
  2. 根据权利要求1所述的信号采样电路，其中，
    所述目标指令信号包括一个脉冲，且所述脉冲的宽度为所述预设时钟周期的2倍；其中，所述片选时钟信号中第一个脉冲的上升沿用于产生所述目标指令信号的上升沿，所述片选时钟信号中第二个脉冲的上升沿用于产生所述目标指令信号的下降沿。
  3. 根据权利要求1所述的信号采样电路，其中，所述第一时钟信号包括时钟奇信号和时钟偶信号；其中，
    所述时钟奇信号和所述时钟偶信号的时钟周期均是所述预设时钟周期的2倍，且所述时钟奇信号和所述时钟偶信号之间的相位差为180度。
  4. 根据权利要求3所述的信号采样电路，其中，所述信号输入电路包括第一输入电路和第二输入电路；其中，
    所述第一输入电路，用于接收初始指令信号，输出中间指令信号；以及
    利用所述时钟奇信号对所述中间指令信号进行采样处理，得到待处理指令奇信号，利用所述时钟偶信号对所述中间指令信号进行采样处理，得到待处理指令偶信号；
    所述第二输入电路，用于接收初始片选信号，输出中间片选信号；以及
    利用所述时钟奇信号对所述中间片选信号进行采样处理和反相处理，得到待处理片选奇信号，并利用所述时钟偶信号对所述中间片选信号进行采样处理和反相处理，得到待处理片选偶信号；
    其中，所述待处理指令奇信号和所述待处理指令偶信号组成所述待处理指令信号，所述待处理片选奇信号和所述待处理片选偶信号组成所述待处理片选信号。
  5. 根据权利要求4所述的信号采样电路，其中，所述采样逻辑电路包括第一采样电路、第二采样电路、第一逻辑电路和第二逻辑电路；其中，
    所述第一采样电路，用于利用所述时钟奇信号对所述待处理片选偶信号进行第一级采样处理，得到第一片选采样奇信号；并利用所述时钟奇信号对所述第一片选采样奇信号进行第二级采样处理，得到第二片选采样奇信号；
    所述第二采样电路，用于利用所述时钟偶信号对所述待处理片选奇信号进行第一级采样处理，得到第一片选采样偶信号；并利用所述时钟偶信号对所述第一片选采样偶信号进行第二级采样处理，得到第二片选采样偶信号；
    所述第一逻辑电路，用于对所述时钟奇信号、所述第一片选采样奇信号和所述第二片选采样奇信号进行逻辑运算，得到片选时钟奇信号；
    所述第二逻辑电路，用于对所述时钟偶信号、所述第一片选采样偶信号和所述第二片选采样偶信号进行逻辑运算，得到片选时钟偶信号；
    其中，所述片选时钟偶信号和所述片选时钟奇信号组成所述片选时钟信号。
  6. 根据权利要求5所述的信号采样电路，其中，所述第一级采样处理是指上升沿采样处理，所述第二级采样处理是指下降沿采样处理。
  7. 根据权利要求6所述的信号采样电路，其中，所述第一采样电路包括第一触发器、第一非门和第二触发器；其中，
    所述第一触发器的输入端与所述待处理片选偶信号连接，所述第一触发器的时钟端与所述时钟 奇信号连接，所述第二触发器的输入端与所述第一触发器的输出端连接，所述第一非门的输入端与所述时钟奇信号连接，所述第一非门的输出端与所述第二触发器的时钟端连接，所述第二触发器的输出端用于输出所述第二片选采样奇信号。
  8. 根据权利要求7所述的信号采样电路，其中，所述第二采样电路包括第三触发器、第二非门和第四触发器；其中，
    所述第三触发器的输入端与所述待处理片选奇信号连接，所述第三触发器的时钟端与所述时钟偶信号连接，所述第四触发器的输入端与所述第三触发器的输出端连接，所述第二非门的输入端与所述时钟偶信号连接，所述第二非门的输出端与所述第四触发器的时钟端连接，所述第四触发器的输出端用于输出所述第二片选采样偶信号。
  9. 根据权利要求7所述的信号采样电路，其中，所述第一逻辑电路包括第一或门和第一与门；其中，
    所述第一或门，用于对所述第一片选采样奇信号和所述第二片选采样奇信号进行或运算，得到中间奇信号；
    所述第一与门，用于对所述中间奇信号和所述时钟奇信号进行与运算，得到所述片选时钟奇信号。
  10. 根据权利要求7所述的信号采样电路，其中，所述第二逻辑电路包括第二或门和第二与门；其中，
    所述第二或门，用于对所述第一片选采样偶信号和所述第二片选采样偶信号进行或运算，得到中间偶信号；
    所述第二与门，用于对所述中间偶信号和所述时钟偶信号进行与运算，得到所述片选时钟偶信号。
  11. 根据权利要求7所述的信号采样电路，其中，所述译码电路包括第一指令译码电路、第二指令译码电路以及第三或门；其中，
    所述第一指令译码电路，用于根据所述待处理片选偶信号和所述片选时钟奇信号对所述待处理指令偶信号进行译码和采样处理，得到指令偶信号；
    所述第二指令译码电路，用于根据所述待处理片选奇信号和所述片选时钟偶信号对所述待处理指令奇信号进行译码和采样处理，得到指令奇信号；
    所述第三或门，用于对所述指令偶信号和所述指令奇信号进行或运算，得到所述目标指令信号。
  12. 根据权利要求11所述的信号采样电路，其中，所述第一指令译码电路包括第一译码电路和第三采样电路；其中，
    所述第一译码电路，用于对所述待处理指令偶信号和所述待处理片选偶信号进行译码处理，得到指令译码偶信号；
    所述第三采样电路，用于根据所述片选时钟奇信号对所述指令译码偶信号进行采样处理，得到所述指令偶信号。
  13. 根据权利要求11所述的信号采样电路，其中，所述第二指令译码电路包括第二译码电路和第四采样电路；其中，
    所述第二译码电路，用于对所述待处理指令奇信号和所述待处理片选奇信号进行译码处理，得到指令译码奇信号；
    所述第四采样电路，用于根据所述片选时钟偶信号对所述指令译码奇信号进行采样处理，得到所述指令奇信号。
  14. 根据权利要求5所述的信号采样电路，其中，所述初始片选信号是表征目标芯片被选中的信号，且所述初始片选信号为低电平有效的脉冲信号；其中，
    若所述初始片选信号在偶数时钟周期的上升沿采样为低电平，则所述待处理片选偶信号为高电平有效的脉冲信号；以及
    所述片选时钟奇信号中第一个脉冲的上升沿用于产生所述目标指令信号的上升沿，所述片选时钟奇信号中第二个脉冲的上升沿用于产生所述目标指令信号的下降沿。
  15. 根据权利要求14所述的信号采样电路，其中，
    若所述初始片选信号在奇数时钟周期的上升沿采样为低电平，则所述待处理片选奇信号为高电平有效的脉冲信号；以及
    所述片选时钟偶信号中第一个脉冲的上升沿用于产生所述目标指令信号的上升沿，所述片选时钟偶信号中第二个脉冲的上升沿用于产生所述目标指令信号的下降沿。
  16. 一种半导体存储器，包括如权利要求1至15任一项所述的信号采样电路。
  17. 根据权利要求16所述的半导体存储器，其中，所述半导体存储器为动态随机存取存储器DRAM芯片。
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