WO2024007399A1 - 一种存储器、控制装置、时钟处理方法和电子设备 - Google Patents

一种存储器、控制装置、时钟处理方法和电子设备 Download PDF

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Publication number
WO2024007399A1
WO2024007399A1 PCT/CN2022/109993 CN2022109993W WO2024007399A1 WO 2024007399 A1 WO2024007399 A1 WO 2024007399A1 CN 2022109993 W CN2022109993 W CN 2022109993W WO 2024007399 A1 WO2024007399 A1 WO 2024007399A1
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Prior art keywords
read
clock signal
data
signal
memory
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PCT/CN2022/109993
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English (en)
French (fr)
Inventor
程景伟
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长鑫存储技术有限公司
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Priority to KR1020227042133A priority Critical patent/KR20240007735A/ko
Priority to EP22838627.2A priority patent/EP4325503A1/en
Priority to US18/154,208 priority patent/US20240012444A1/en
Publication of WO2024007399A1 publication Critical patent/WO2024007399A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Definitions

  • the present disclosure relates to the field of semiconductor memory technology, and in particular, to a memory, a control device, a clock processing method and an electronic device.
  • the Central Processing Unit sends a read instruction to the memory, then receives the read clock signal and read data signal returned by the memory, and uses the read clock signal to latch the read data signal in order to obtain the desired required data.
  • the central processor needs to obtain the duty cycle parameters of the clock signal by reading the corresponding mode register in the memory.
  • the clock signal inside the memory may be The read clock signal returned by the memory to the central controller is also distorted, causing the central processor to obtain erroneous data and ultimately causing the duty cycle adjustment of the clock signal to fail.
  • the present disclosure provides a memory, a control device, a clock processing method and an electronic device.
  • a second read clock signal with a single level change edge can be selected as the target read clock. signal to avoid data latch failure.
  • an embodiment of the present disclosure provides a memory, the memory includes a clock processing circuit, and the clock processing circuit includes:
  • a duty cycle module configured to receive an externally generated data clock signal; perform duty cycle adjustment on the data clock signal and output an internal clock signal;
  • a first clock generation module configured to receive the internal clock signal and output a first read clock signal based on the internal clock signal; wherein the first read clock signal is a pulse signal;
  • a second clock generation module configured to generate and output a second read clock signal during the existence of the first read clock signal; wherein the second read clock signal has only one level state change edge;
  • the selection module is configured to receive the first read clock signal and the second read clock signal, and output one of the first read clock signal and the second read clock signal as a target read clock signal.
  • the clock processing circuit further includes a detection module and a mode register; wherein the detection module is configured to receive the internal clock signal, detect the duty cycle of the internal clock signal, and output a duty cycle ratio parameter; the mode register is configured to receive and store the duty cycle parameter.
  • the selection module is specifically configured to receive a selection indication signal, and when the selection indication signal is in a first state, output the first read clock signal as a target read clock signal; or, When the selection indication signal is in the second state, the second read clock signal is output as a target read clock signal.
  • the memory is configured to receive a data read instruction; based on the data read instruction, output a read data signal, and output the target read clock signal through the clock processing circuit; wherein the target read The clock signal is used to latch the read data signal, and the level state change edge of the second read clock signal indicates the end time of valid data in the read data signal.
  • the memory is further configured to set the selection indication signal to a first state when the data read instruction is a first read instruction; or, when the data read instruction is a first read instruction, In the case of a second read instruction, the selection indication signal is set to a second state; wherein the second read instruction instructs to obtain the duty cycle parameter of the mode register in the clock processing circuit, and the first read instruction is Refers to data read instructions other than the second read instruction.
  • the memory is further configured to set the selection indication signal to a first state when the data read instruction is a first read instruction; or, when the data read instruction is a first read instruction, When the second read instruction is issued and the duty cycle of the internal clock signal is within the preset range, the selection indication signal is set to the first state; or, when the data read instruction is the second read instruction and the internal When the duty cycle of the clock signal is not within the preset range, the selection indication signal is set to the second state.
  • the first read clock signal includes 8 clock cycles, and the level state change edge of the second read clock signal is consistent with the rising edge of the 5th clock cycle in the first read clock signal. Alignment; wherein, the level state change edge of the second read clock signal means that the second read clock signal changes from a low level state to a high level state.
  • the duty cycle module includes: a receiving module configured to receive and output the data clock signal from the outside; an adjustment module configured to perform duty cycle adjustment on the data clock signal and output the Internal clock signal.
  • the data clock signal is a write clock signal.
  • embodiments of the present disclosure provide a control device, which is connected to a memory; wherein,
  • the control device is configured to send a data read instruction to the memory; and, receive the read data signal and the target read clock signal returned by the memory, and use the target read clock signal to perform latch processing on the read data signal. ;
  • the target read clock signal is a first read clock signal or a second read clock signal
  • the first read clock signal is a pulse signal
  • the second read clock signal has only one level state change edge
  • control device is specifically configured to receive a first read clock signal returned by the memory when the data read instruction is a first read instruction, and use the first read clock signal to The read data signal is latched; or, when the data read instruction is a second read instruction, the second read clock signal returned by the memory is received, and the level of the second read clock signal is used.
  • the read data signal is latched along the state change edge; wherein the memory includes a clock processing circuit, the second read instruction indicates obtaining the duty cycle parameter of the mode register in the clock processing circuit, and the first The read command indicates a data read command other than the second read command.
  • control device is further configured to receive a first read clock signal returned by the memory when the data read instruction is a second read instruction, and use the first read clock signal to The read data signal is latched along the changing edge of the level state.
  • embodiments of the present disclosure provide a clock processing method applied to a memory.
  • the method includes:
  • a first read clock signal is determined; wherein the first read clock signal is a pulse signal;
  • a second read clock signal is generated; wherein the second read clock signal only has one level state change edge;
  • One of the first read clock signal and the second read clock signal is output as a target read clock signal.
  • the memory includes a mode register, and the method further includes:
  • Duty cycle detection is performed on the internal clock signal to obtain duty cycle parameters; and the duty cycle parameters are stored in the mode register.
  • the memory is connected to a control device, and outputting one of the first read clock signal and the second read clock signal as a target read clock signal includes:
  • the read data signal is determined based on the first read instruction, and the first read clock signal is determined as the target read clock signal; after receiving the first read instruction sent by the control device;
  • the read data signal is determined based on the second read instruction, and the second read clock signal is determined as the target read clock signal; wherein the target read clock signal is used for latch
  • the second read instruction indicates obtaining the duty cycle parameter of the mode register
  • the first read instruction indicates a data read instruction other than the second read instruction.
  • the memory is connected to a control device, and outputting one of the first read clock signal and the second read clock signal as a target read clock signal includes:
  • the read data signal is determined based on the second read command, and the second read clock The signal is determined to be the target read clock signal; wherein the target read clock signal is used to latch the read data signal, the second read instruction indicates obtaining the duty cycle parameter of the mode register, and the first read instruction Indicates a data read command other than the second read command.
  • embodiments of the present disclosure provide an electronic device, which at least includes the memory as described in the first aspect and the control device as described in the second aspect.
  • Embodiments of the present disclosure provide a memory, a control device, a clock processing method, and an electronic device.
  • the memory includes a clock processing circuit.
  • the clock processing circuit includes: a duty cycle module configured to receive an externally generated data clock signal; and to process the data clock signal.
  • the first clock generation module is configured to receive the internal clock signal and output a first read clock signal based on the internal clock signal; wherein the first read clock signal is a pulse signal; the second clock The generation module is configured to generate and output the second read clock signal during the existence of the first read clock signal; wherein the second read clock signal has only one level state change edge; the selection module is configured to receive the first read clock signal and the second read clock signal, and output one of the first read clock signal and the second read clock signal as the target read clock signal.
  • the second read clock signal with a single level change edge can be selected as the target read clock signal to avoid data latch failure.
  • Figure 1 is a schematic diagram of the operation timing of the MRR instruction
  • Figure 2 is a schematic structural diagram of a clock processing circuit
  • Figure 3 is a schematic waveform diagram of a read clock signal
  • Figure 4 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic diagram 1 of a partial structure of a clock processing circuit provided by an embodiment of the present disclosure
  • Figure 6 is a schematic diagram 2 of a partial structure of a clock processing circuit provided by an embodiment of the present disclosure
  • Figure 7 is a schematic diagram of a signal waveform of a data latch process provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram of the working process of a clock processing circuit provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic structural diagram of a control device provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic flowchart of a clock processing method provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first ⁇ second ⁇ third” Where permitted, the specific order or sequence may be interchanged so that the embodiments of the disclosure described herein can be practiced in an order other than that illustrated or described herein.
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • NMOS N-Metal-Oxide-Semiconductor: N-type channel field effect transistor
  • PMOS P-Metal-Oxide-Semiconductor
  • FIG. 1 a schematic diagram of the operation timing of the MRR instruction is shown.
  • T0, T1... are used to identify different clock cycles
  • CK_c and CK_t are a pair of differential clock signals
  • CS is the chip select signal
  • CA is the command address signal
  • COMMAND indicates the operation instruction
  • DQ[7:0 ] is the data signal of the 8-bit memory
  • DQ[15:0] is the data signal of the 16-bit memory
  • the data clock signal WCK is the external write clock signal sent to the memory by the host of the electronic device (Host), at different circuit locations It may appear as a single signal or a pair of differential clock signals WCK_c and WCK_t
  • the read clock signal RDQS is the clock signal output by the memory to the electronic device, and may appear as a single signal or a pair of differential clock signals RDQS_c and RDQS_t at different circuit locations.
  • the memory After the memory receives the MRR instruction sent by the CPU, it generates the data signal DQ (which may also be called a read data signal), and uses the data clock signal WCK received from the outside to generate the read clock signal RDQS.
  • the memory During the execution of the data read instruction, the memory returns the read data signal DQ and the read clock signal RDQS to the CPU, and then the CPU uses the read clock signal RDQS to latch the read data signal DQ to obtain the required data.
  • Figure 1 shows the standard timing sequence stipulated by the Joint Electronic Device Engineering Design Council (JEDEC) standard.
  • JEDEC Joint Electronic Device Engineering Design Council
  • a clock processing circuit is provided in the memory for adjusting the duty cycle of the data clock signal WCK0 (including a pair of complementary signals WCK_c/WCK_t) so that the duty cycle of the data clock signal WCK0 meets the requirements.
  • FIG 2 shows a schematic structural diagram of a clock processing circuit.
  • the receiving module is configured to receive the data clock signal WCK0 from the outside
  • the adjustment module adjusts the duty cycle of the data clock signal WCK to obtain the internal clock signal WCK1
  • the detection module is configured to detect the internal clock The duty cycle parameter of signal WCK1 and stores it in the mode register.
  • the CPU sends an MRR instruction to read the duty cycle parameters in the mode register to determine the next operation.
  • the duty cycle adjustment module will The duty cycle of the data clock signal WCK0 is increased by 7 units (the upper limit specified by JEDEC, and each unit is 5 picoseconds), which is an increase of 35 picoseconds, which is equivalent to increasing the duty cycle by 15% at a speed of 8533Mbps.
  • the duty cycle of the internal clock signal WCK1 in the memory will be as high as 72%, and the duty cycle of the read clock signal RDQS generated by it will also be as high as 72%.
  • FIG. 3 shows a schematic waveform diagram of a read clock signal.
  • the read clock signal RDQS with a duty cycle of up to 72% is attenuated by the channel during the transmission process, and will be severely distorted when it reaches the CPU receiving end, making it difficult to be correctly recognized by the CPU, that is, the MRR instruction may be incorrectly data, ultimately causing duty cycle adjustment to fail. This problem will be more serious if the memory speed is higher.
  • the clock processing circuit includes: a duty cycle module configured to receive an externally generated data clock signal; and perform duty cycle adjustment on the data clock signal, Output an internal clock signal; the first clock generation module is configured to receive the internal clock signal and output a first read clock signal based on the internal clock signal; wherein the first read clock signal is a pulse signal; the second clock generation module is configured to During the existence of the first read clock signal, a second read clock signal is generated and output; wherein, the second read clock signal has only one level state change edge; the selection module is configured to receive the first read clock signal and the second read clock signal, and output one of the first read clock signal and the second read clock signal as the target read clock signal.
  • the second read clock signal with a single level change edge can be selected as the target read clock signal to avoid data latch failure.
  • FIG. 4 shows a schematic structural diagram of a memory 10 provided by an embodiment of the present disclosure.
  • the memory 10 includes a clock processing circuit 20, and the clock processing circuit 20 includes:
  • the duty cycle module 21 is configured to receive an externally generated data clock signal; adjust the duty cycle of the data clock signal and output an internal clock signal;
  • the first clock generation module 22 is configured to receive an internal clock signal and output a first read clock signal based on the internal clock signal; wherein the first read clock signal is a pulse signal;
  • the second clock generation module 23 is configured to generate and output a second read clock signal during the existence of the first read clock signal; wherein the second read clock signal has only one level state change edge;
  • the selection module 24 is configured to receive the first read clock signal and the second read clock signal, and output one of the first read clock signal and the second read clock signal as the target read clock signal.
  • the memory 10 in the embodiment of the present disclosure may be various types of semiconductor memories, such as DRAM, SDRAM, double-rate DRAM, low-power double-rate DRAM, etc.
  • the memory 10 is provided with a first clock generation module 22 and a second clock generation module 23 at the same time.
  • the first clock generation module 22 can generate a first read clock signal with multiple pulses according to the data clock signal received from the outside.
  • the clock generation module 23 may generate a second read clock signal with only one level state change edge. In this way, under different working scenarios, the first read clock signal or the second read clock signal can be selected as the target read clock signal and sent to the CPU to implement data latch processing.
  • the second read clock signal is not affected by the duty cycle distortion of the internal clock signal, correct latching of data can still be ensured in scenarios where the duty cycle distortion of the internal clock signal is large.
  • the level change edge of the second read clock signal is synchronized with the end time of the valid data in the read data signal, or the level change edge of the second read clock signal is ahead of the end time of the valid data in the read data signal, thereby ensuring Correct latching of valid data.
  • the level change edge may be a rising edge (that is, the second read clock signal changes from low level to high level) or a falling edge (that is, the second read clock signal changes from high level to low level).
  • the duty cycle module 21 includes two parts: a receiving module 211 and an adjustment module 212.
  • the first clock generation module 22 can be composed of a logic device and a delay unit.
  • the second clock generation module 23 can be composed of a frequency divider composed of a D-type flip-flop and an inverter, and the selection module 24 can be implemented by a two-to-one data selector.
  • the data clock signal is a write clock signal received from the outside, and is subsequently represented as WCK0; the internal clock signal is a write clock signal with a duty cycle adjusted inside the memory, and is subsequently represented as WCK1; the target read clock signal is read
  • the operating data strobe signal is subsequently expressed as RDQS; the read data signal can be expressed as DQ.
  • the clock processing circuit 20 also includes a detection module 25 and a mode register 26; wherein the detection module 25 is configured to receive the internal clock signal WCK1 and perform duty cycle detection on the internal clock signal WCK1. , output the duty cycle parameter; the mode register 26 is configured to receive and store the duty cycle parameter.
  • the detection module 25 may be composed of a logic gate, a transmission gate, a capacitor and a signal comparator.
  • the selection module 24 is specifically configured to receive the selection indication signal, and when the selection indication signal is in the first state, output the first read clock signal as the target read clock signal RDQS; Alternatively, when the selection instruction signal is in the second state, the second read clock signal is output as the target read clock signal RDQS.
  • the selection module 24 may be a two-select data selector, thereby outputting a first read clock signal or a second read clock signal according to the state of the selection indication signal.
  • the memory 10 is configured to receive a data read instruction; based on the data read instruction, output the read data signal DQ, and output the target read clock signal RDQS through the clock processing circuit 20; wherein the target read clock signal RDQS is used to lock The read data signal DQ is stored, and the level state change edge of the second read clock signal indicates the end time of the valid data in the read data signal DQ.
  • the CPU of the electronic device issues operation instructions to the memory 10 to implement data writing or data reading.
  • the CPU sends a data read instruction to the memory 10.
  • the memory 10 generates a read data signal DQ (carrying the parameters that the CPU needs to read) according to the data read instruction, and generates a target read clock through the clock processing circuit 20.
  • Signal RDQS In this way, both the read data signal DQ and the target read clock signal RDQS are sent to the CPU, so that the CPU uses the target read clock signal RDQS to latch the read data signal, and subsequently decodes it to obtain the required parameters.
  • data read instructions are divided into two types, namely first read instructions and second read instructions.
  • the second read instruction indicates obtaining the duty cycle parameter of the mode register 26 in the clock processing circuit 20, and the first read instruction refers to a data read instruction other than the second read instruction.
  • the memory 10 is further configured to set the selection indication signal to the first state when the data read instruction is the first read instruction; or, when the data read instruction is the second read instruction, In this case, the selection indication signal is set to the second state.
  • the memory 10 may be in the process of duty cycle adjustment, and in some cases the internal clock signal WCK1 has been distorted, for example The duty cycle of the internal clock signal WCK1 may be as high as 72%. At this time, the first read clock signal will also be distorted, and the CPU may obtain erroneous results by using the first read clock signal to latch the read data signal DQ.
  • the second read clock signal is output as the target read clock signal RDQS, because the second read clock signal only There is a level change edge that will not be affected by the duty cycle distortion of the internal clock signal WCK1. Therefore, the CPU can use the level change edge in the second read clock signal to latch the data signal to obtain the correct duty cycle. Empty ratio parameter.
  • the second clock generation module 23 may be disabled, that is, the second clock generation module 23 does not work, thereby reducing current and power consumption. the goal of.
  • the memory 10 is further configured to set the selection indication signal to the first state when the data read instruction is the first read instruction; or, when the data read instruction is the second read instruction And when the duty cycle of the internal clock signal WCK1 is within the preset range, the selection indication signal is set to the first state; or, when the data read instruction is the second read instruction and the duty cycle of the internal clock signal WCK1 is not in the preset range.
  • the selection indication signal is set to the second state.
  • the data read instruction when used to read the duty cycle parameter in the mode register 26, if the duty cycle of the internal clock signal WCK1 meets the requirements, the first read clock signal will not be distorted at this time. , at this time, the CPU can still use the first read clock signal to latch the read data signal.
  • the following uses a DRAM with a burst length of 16 and 16 DQ terminals as an example to illustrate the specific waveform of the second read clock signal and the latching process of the read data signal.
  • the first 8 bits of the read data signal DQ carry valid data, expressed as DQ ⁇ 7:0>.
  • the parameter value of the mode register (MR Content) is transmitted in the first 8 beats (the first 4 clock cycles) of the target read clock signal RDQS, and the data of no concern (MR Content) is transmitted in the last 8 beats (the last 4 clock cycles).
  • the first read clock signal includes 8 clock cycles, and the level state change edge of the second read clock signal is aligned with the rising edge of the 5th clock cycle in the first read clock signal; wherein, the second read clock signal
  • the level state change edge refers to the change of the second read clock signal from a low level state to a high level state.
  • the CPU will use the signal edge of the target read clock signal RDQS to read the data signal DQ ⁇ 7:0> Latching is performed, the data latched in the first 4 clock cycles is MR Content, and the data Valid latched in the next 4 clock cycles is not used; as shown in (2) in Figure 7, if the second read clock signal is used as the target Read clock signal RDQS, the CPU will use the rising edge of the second read clock signal to latch the read data signal DQ ⁇ 7:0> to obtain MR Content.
  • the duty cycle module 21 includes: a receiving module 211 configured to receive and output the data clock signal WCK0 from the outside; and an adjustment module 212 configured to adjust the data clock signal WCK0 Duty cycle adjustment, output internal clock signal WCK1.
  • the adjustment module 212 is configured for duty cycle adjustment.
  • the default settings of the adjustment module 212 will cause the duty cycle of the data clock signal WCK0 to increase by a certain value.
  • the upper limit of the duty cycle increase is 7 units (Step), that is, 35 picoseconds. Second.
  • the receiving module 211 can be implemented by a signal receiver composed of NMOS and PMOS devices, and the adjustment module 212 can be composed of cascaded delay units. Each delay unit is composed of NMOS and PMOS, thereby realizing the rising edge of the data clock signal WCK0. Forward/backward adjustment, and/or, forward/backward adjustment of the falling edge of the data clock signal WCK0, and ultimately adjustment of the duty cycle of the data clock signal WCK0.
  • the duty cycle of the externally generated data clock signal WCK0 is 57%.
  • the duty cycle of the data clock signal WCK0 is increased by 7 units by default ( 35 picoseconds), if the memory speed is 8633Mbps, the duty cycle of the internal clock signal WCK1 will continue to increase by 15% based on the data clock signal WCK0, that is, the duty cycle of the internal clock signal WCK1 will be as high as 72%.
  • the duty cycle of the internal clock signal WCK1 will be as high as 72%.
  • the CPU sends a second read instruction to the memory, the selection indication signal will be set to the second state, and the memory 10 uses the second read clock signal with a single signal edge as the target read clock.
  • signal RDQS so that the CPU can use the second read clock signal to latch the read data signal DQ ⁇ 7:0> to obtain the correct duty cycle parameters and ensure the success of the duty cycle adjustment operation.
  • the clock processing circuit includes: a duty cycle module configured to receive an externally generated data clock signal; and perform duty cycle calculation on the data clock signal. Adjust and output the internal clock signal; the first clock generation module is configured to receive the internal clock signal and output the first read clock signal based on the internal clock signal; wherein the first read clock signal is a pulse signal; the second clock generation module is configured To generate and output a second read clock signal during the existence of the first read clock signal; wherein the second read clock signal has only one level state change edge; the selection module is configured to receive the first read clock signal and the second The read clock signal outputs one of the first read clock signal and the second read clock signal as the target read clock signal. In this way, when the internal clock signal has duty cycle distortion, the second read clock signal with a single level change edge can be selected as the target read clock signal to avoid data latch failure.
  • FIG. 9 shows a schematic structural diagram of a control device 30 provided by an embodiment of the present disclosure. As shown in Figure 9, the control device 30 is connected to the memory 10; wherein,
  • the control device 30 is configured to send a data read instruction to the memory 10; and, receive the read data signal DQ and the target read clock signal RDQS returned by the memory 10, and use the target read clock signal RDQS to perform latch processing on the read data signal DQ; wherein,
  • the target read clock signal RDQS is a first read clock signal or a second read clock signal.
  • the first read clock signal is a pulse signal, and the second read clock signal has only one level state change edge.
  • control device 30 may be a CPU. Specifically, the control device 30 sends an instruction through the memory controller (Controller) of the memory 10 to read the data of the mode register/storage array in the memory 10 . Specifically, when reading data from the memory 10, the CPU sends a data read instruction to the memory through the command bus and the data bus. The memory 10 parses the data read instruction and performs a corresponding read operation to obtain a read data signal. In addition, the memory will also generate a target read clock signal, so that the control device 30 uses the target read clock signal RDQS to latch the read data signal DQ to obtain the required data.
  • the memory controller Controller
  • the target read clock signal RDQS received by the control device 30 from the memory 10 may have multiple pulses or only one level state change edge. That is to say, when the duty cycle of the first read clock signal is distorted, the memory 10 sends the second read clock signal with only one level state change edge as the target read clock signal RDQS to the control device 30 to read data. Signal DQ is latched correctly.
  • control device 30 is specifically configured to receive the first read clock signal returned by the memory 10 when the data read command is a first read command, and use the first read clock signal to read the data signal.
  • DQ performs latch processing; or, when the data read instruction is a second read instruction, receive the second read clock signal returned by the memory 10, and use the level state change edge of the second read clock signal to perform the latch processing on the read data signal DQ. latch processing.
  • the memory 10 includes a clock processing circuit 20
  • the second read instruction indicates obtaining the duty cycle parameter of the mode register in the clock processing circuit 20
  • the first read instruction indicates a data reading instruction other than the second read instruction.
  • the memory 10 may be in the process of duty cycle adjustment, and the internal clock signal WCK1 in the memory 10 may be distorted, that is, the first read clock signal is distorted.
  • the second read clock signal is used as the target read clock signal RDQS, so that the control device 30 can obtain the correct duty cycle parameter.
  • the data read instruction is the first read instruction
  • the internal clock signal WCK1 and the first read clock signal in the memory are both normal. Therefore, the first read clock signal can be used as the target read clock signal RDQS to control Device 30 can obtain correct results.
  • control device 30 is further configured to receive the first read clock signal returned by the memory 10 when the data read command is a second read command, and use the level of the first read clock signal to The read data signal DQ is latched along the state change edge.
  • the internal clock signal WCK1 and the first read clock signal in the memory 10 may still be normal, so the memory 10 may still use the first read clock signal as the target read clock.
  • Signal RDQS the internal clock signal WCK1 and the first read clock signal in the memory 10 may still be normal, so the memory 10 may still use the first read clock signal as the target read clock.
  • Embodiments of the present disclosure provide a control device, which is connected to a memory; the control device is configured to send a data read instruction to the memory; and, receives a read data signal and a target read clock signal returned by the memory, and uses the target read clock signal Perform latch processing on the read data signal; wherein, the target read clock signal is the first read clock signal or the second read clock signal, the first read clock signal is a pulse signal, and the second read clock signal has only one level state change edge. . In this way, when the internal clock signal has duty cycle distortion, the second read clock signal with a single level change edge can be used to latch the read data signal to avoid data latch failure.
  • FIG. 10 shows a schematic flowchart of a clock processing method provided by an embodiment of the present disclosure. As shown in Figure 10, the method includes:
  • S401 Receive the externally generated data clock signal; adjust the duty cycle of the data clock signal to determine the internal clock signal.
  • S402 Determine the first read clock signal based on the internal clock signal; wherein the first read clock signal is a pulse signal.
  • S404 Output one of the first read clock signal and the second read clock signal as the target read clock signal.
  • this method is applied to the aforementioned memory 10 .
  • the memory 10 can generate the first read clock signal and the second read clock signal at the same time.
  • the first read clock signal or the second read clock signal can be selected as the target read clock signal RDQS and sent to the CPU, so that Implement latch processing of data signals.
  • the second read clock signal is not affected by the duty cycle distortion of the internal clock signal WCK1, correct latching of the data signal can still be ensured in a scenario where the duty cycle distortion of the internal clock signal WCK1 is large.
  • the memory 10 includes the mode register 26, and the method further includes:
  • the memory 10 is connected to the control device 30, and outputting one of the first read clock signal and the second read clock signal as the target read clock signal includes:
  • the read data signal is determined based on the first read command, and the first read clock signal is determined as the target read clock signal; after receiving the second read command sent by the control device In the case of , the read data signal is determined based on the second read command, and the second read clock signal is determined as the target read clock signal.
  • the target read clock signal is used to latch the read data signal
  • the second read instruction indicates acquisition of the duty cycle parameter of the mode register
  • the first read instruction indicates a data read instruction other than the second read instruction.
  • outputting one of the first read clock signal and the second read clock signal as the target read clock signal includes:
  • the read data signal is determined based on the first read command, and the first read clock signal is determined as the target read clock signal; after receiving the second read command sent by the control device And when the duty cycle parameter is within the preset range, the read data signal is determined based on the second read command, and the first read clock signal is determined as the target read clock signal; after receiving the second read command sent by the control device and occupying When the duty ratio parameter is not within the preset range, the read data signal is determined based on the second read command, and the second read clock signal is determined as the target read clock signal.
  • Embodiments of the present disclosure provide a clock processing method, which method includes: receiving an externally generated data clock signal; performing duty cycle adjustment on the data clock signal to determine an internal clock signal; and determining a first read clock signal based on the internal clock signal. ; Wherein, the first read clock signal is a pulse signal; during the existence of the first read clock signal, a second read clock signal is generated; wherein, the second read clock signal only has one level state change edge; the first read clock signal is One of the signal and the second read clock signal is output as the target read clock signal. In this way, when the internal clock signal has duty cycle distortion, the second read clock signal with a single level change edge can be selected as the target read clock signal to avoid data latch failure.
  • FIG. 11 shows a schematic structural diagram of an electronic device 50 provided by an embodiment of the present disclosure.
  • the electronic device 50 at least includes the aforementioned memory 10 and the aforementioned control device 30 .
  • the memory 10 is capable of outputting a first read clock signal with multiple pulses or a second read clock signal with a single level change edge, in the case where the duty cycle distortion occurs in the internal clock signal in the memory 10 , it is possible to choose to have a single read clock signal.
  • the second read clock signal with a level change edge is used as the target read clock signal.
  • the control device 30 uses the level change edge of the second read clock signal to perform data latching to avoid obtaining erroneous data.
  • Embodiments of the present disclosure provide a memory, a control device, a clock processing method, and an electronic device.
  • the memory includes a clock processing circuit.
  • the clock processing circuit includes: a duty cycle module configured to receive an externally generated data clock signal; and to process the data clock signal.
  • the first clock generation module is configured to receive the internal clock signal and output a first read clock signal based on the internal clock signal; wherein the first read clock signal is a pulse signal; the second clock The generation module is configured to generate and output the second read clock signal during the existence of the first read clock signal; wherein the second read clock signal has only one level state change edge; the selection module is configured to receive the first read clock signal and the second read clock signal, and output one of the first read clock signal and the second read clock signal as the target read clock signal.
  • the second read clock signal with a single level change edge can be selected as the target read clock signal to avoid data latch failure.

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Abstract

一种存储器（10）、控制装置、时钟处理方法和电子设备，存储器（10）中的时钟处理电路（20）包括：占空比模块（21），配置为对数据时钟信号进行占空比调节，输出内部时钟信号；第一时钟产生模块（22），配置为接收内部时钟信号，基于内部时钟信号，输出第一读时钟信号；第一读时钟信号为脉冲信号；第二时钟产生模块（23），配置为产生并输出第二读时钟信号；第二读时钟信号仅存在一个电平状态变化沿；选择模块（24），配置为接收第一读时钟信号和第二读时钟信号，将第一读时钟信号和第二读时钟信号的两者之一输出为目标读时钟信号。

Description

一种存储器、控制装置、时钟处理方法和电子设备
相关申请的交叉引用
本公开基于申请号为202210806176.0、申请日为2022年07月08日、发明名称为“一种存储器、控制装置、时钟处理方法和电子设备”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体存储器技术领域，尤其涉及一种存储器、控制装置、时钟处理方法和电子设备。
背景技术
在电子设备中，中央处理器(Central Processing Unit，CPU)向存储器发送读指令，然后接收存储器返回的读时钟信号和读数据信号，利用读时钟信号对读数据信号进行锁存处理，以便得到所需的数据。然而，在存储器对时钟信号进行占空比调整的过程中，中央处理器需要通过读取存储器中相应的模式寄存器获得时钟信号的占空比参数，然而这一过程中存储器内部的时钟信号可能是畸变的，进而存储器返回给中央控制器的读时钟信号也是畸变的，导致中央处理器获得错误的数据，最终导致时钟信号的占空比调整失败。
发明内容
本公开提供了一种存储器、控制装置、时钟处理方法和电子设备，在存储器的内部时钟信号占空比畸变的情况下，可以选择具有单个电平变化沿的第二读时钟信号作为目标读时钟信号，避免数据锁存失败。
本公开的技术方案是这样实现的：
第一方面，本公开实施例提供了一种存储器，所述存储器包括时钟处理电路，所述时钟处理电路包括：
占空比模块，配置为接收外部产生的数据时钟信号；对所述数据时钟信号进行占空比调节，输出内部时钟信号；
第一时钟产生模块，配置为接收所述内部时钟信号，基于所述内部时钟信号，输出第一读时钟信号；其中，所述第一读时钟信号为脉冲信号；
第二时钟产生模块，配置为在所述第一读时钟信号的存在期间，产生并输出第二读时钟信号；其中，所述第二读时钟信号仅存在一个电平状态变化沿；
选择模块，配置为接收所述第一读时钟信号和所述第二读时钟信号，将所述第一读时钟信号和所述第二读时钟信号的两者之一输出为目标读时钟信号。
在一些实施例中，所述时钟处理电路还包括检测模块和模式寄存器；其中，所述检测模块，配置为接收所述内部时钟信号，对所述内部时钟信号进行占空比检测，输出占空比参数；所述模式寄存器，配置为接收并存储所述占空比参数。
在一些实施例中，所述选择模块，具体配置为接收选择指示信号，在所述选择指示信号处于第一状态的情况下，将所述第一读时钟信号输出为目标读时钟信号；或者，在所述选择指示信号处于第二状态的情况下，将所述第二读时钟信号输出为目标读时钟信号。
在一些实施例中，所述存储器，配置为接收数据读指令；基于所述数据读指令，输出读数据信号，并通过所述时钟处理电路输出所述目标读时钟信号；其中，所述目标读时钟信号用于锁存所述读数据信号，且所述第二读时钟信号的电平状态变化沿指示所述读数据信号中有效数据的结束时刻。
在一些实施例中，所述存储器，还配置为在所述数据读指令为第一读指令的情况下，将所述选择指示信号置为第一状态；或者，在所述数据读指令为第二读指令的情况下，将所述选择指示信号置为第二状态；其中，所述第二读指令指示获取所述时钟处理电路中模式寄存器的占空比参数，所述第一读指令是指除所述第二读指令之外的数据读取指令。
在一些实施例中，所述存储器，还配置为在所述数据读指令为第一读指令的情况下，将所述选择指示信号置为第一状态；或者，在所述数据读 指令为第二读指令且所述内部时钟信号的占空比处于预设范围的情况下，将所述选择指示信号置为第一状态；或者，在所述数据读指令为第二读指令且所述内部时钟信号的占空比并非处于预设范围的情况下，将所述选择指示信号置为第二状态。
在一些实施例中，所述第一读时钟信号包括8个时钟周期，所述第二读时钟信号的电平状态变化沿与所述第一读时钟信号中的第5个时钟周期的上升沿对齐；其中，所述第二读时钟信号的电平状态变化沿是指所述第二读时钟信号由低电平状态变化为高电平状态。
在一些实施例中，所述占空比模块包括：接收模块，配置为从外部接收并输出所述数据时钟信号；调节模块，配置为对所述数据时钟信号进行占空比调节，输出所述内部时钟信号。
在一些实施例中，所述数据时钟信号为写时钟信号。
第二方面，本公开实施例提供了一种控制装置，所述控制装置与存储器连接；其中，
所述控制装置，配置为向所述存储器发送数据读指令；以及，接收所述存储器返回的读数据信号和目标读时钟信号，利用所述目标读时钟信号对所述读数据信号进行锁存处理；
其中，所述目标读时钟信号为第一读时钟信号或者第二读时钟信号，所述第一读时钟信号为脉冲信号，所述第二读时钟信号仅存在一个电平状态变化沿。
在一些实施例中，所述控制装置，具体配置为在所述数据读指令为第一读指令的情况下，接收所述存储器返回的第一读时钟信号，利用所述第一读时钟信号对所述读数据信号进行锁存处理；或者，在所述数据读指令为第二读指令的情况下，接收所述存储器返回的第二读时钟信号，利用所述第二读时钟信号的电平状态变化沿对所述读数据信号进行锁存处理；其中，所述存储器包括时钟处理电路，所述第二读指令指示获取所述时钟处理电路中模式寄存器的占空比参数，所述第一读指令指示除所述第二读指令之外的数据读取指令。
在一些实施例中，所述控制装置，还配置为在所述数据读指令为第二读指令的情况下，接收所述存储器返回的第一读时钟信号，利用所述第一 读时钟信号的电平状态变化沿对所述读数据信号进行锁存处理。
第三方面，本公开实施例提供了一种时钟处理方法，应用于存储器，所述方法包括：
接收外部产生的数据时钟信号；对所述数据时钟信号进行占空比调节，确定内部时钟信号；
基于所述内部时钟信号，确定第一读时钟信号；其中，所述第一读时钟信号为脉冲信号；
在所述第一读时钟信号的存在期间，产生第二读时钟信号；其中，所述第二读时钟信号仅存在一个电平状态变化沿；
将所述第一读时钟信号和所述第二读时钟信号的两者之一输出为目标读时钟信号。
在一些实施例中，所述存储器包括模式寄存器，所述方法还包括：
对所述内部时钟信号进行占空比检测，得到占空比参数；将所述占空比参数存储至所述模式寄存器。
在一些实施例中，所述存储器与控制装置连接，所述将所述第一读时钟信号和所述第二读时钟信号的两者之一输出为目标读时钟信号，包括：
在接收到控制装置发送的第一读指令的情况下，基于所述第一读指令确定读数据信号，并将所述第一读时钟信号确定为目标读时钟信号；在接收到控制装置发送的第二读指令的情况下，基于所述第二读指令确定所述读数据信号，并将所述第二读时钟信号确定为目标读时钟信号；其中，所述目标读时钟信号用于锁存所述读数据信号，所述第二读指令指示获取所述模式寄存器的占空比参数，所述第一读指令指示除所述第二读指令之外的数据读取指令。
在一些实施例中，所述存储器与控制装置连接，所述将所述第一读时钟信号和所述第二读时钟信号的两者之一输出为目标读时钟信号，包括：
在接收到所述控制装置发送的第一读指令的情况下，基于所述第一读指令确定读数据信号，并将所述第一读时钟信号确定为目标读时钟信号；在接收到所述控制装置发送的第二读指令且所述占空比参数处于预设范围的情况下，基于所述第二读指令确定读数据信号，并将所述第一读时钟信号确定为目标读时钟信号；在接收到控制装置发送的第二读指令且所述占 空比参数并非处于预设范围的情况下，基于所述第二读指令确定所述读数据信号，并将所述第二读时钟信号确定为目标读时钟信号；其中，所述目标读时钟信号用于锁存所述读数据信号，所述第二读指令指示获取所述模式寄存器的占空比参数，所述第一读指令指示除所述第二读指令之外的数据读取指令。
第四方面，本公开实施例提供了一种电子设备，所述电子设备至少包括如第一方面所述的存储器和如第二方面所述的控制装置。
本公开实施例提供了一种存储器、控制装置、时钟处理方法和电子设备，存储器包括时钟处理电路，时钟处理电路包括：占空比模块，配置为接收外部产生的数据时钟信号；对数据时钟信号进行占空比调节，输出内部时钟信号；第一时钟产生模块，配置为接收内部时钟信号，基于内部时钟信号，输出第一读时钟信号；其中，第一读时钟信号为脉冲信号；第二时钟产生模块，配置为在第一读时钟信号的存在期间，产生并输出第二读时钟信号；其中，第二读时钟信号仅存在一个电平状态变化沿；选择模块，配置为接收第一读时钟信号和第二读时钟信号，将第一读时钟信号和第二读时钟信号的两者之一输出为目标读时钟信号。这样，在存储器的内部时钟信号发生占空比畸变的情况下，可以选择具有单个电平变化沿的第二读时钟信号作为目标读时钟信号，避免数据锁存失败。
附图说明
图1为MRR指令的操作时序示意图；
图2为一种时钟处理电路的结构示意图；
图3为一种读时钟信号的波形示意图；
图4为本公开实施例提供的一种存储器的结构示意图；
图5为本公开实施例提供的一种时钟处理电路的局部结构示意图一；
图6为本公开实施例提供的一种时钟处理电路的局部结构示意图二；
图7为本公开实施例提供的一种数据锁存处理的信号波形示意图；
图8为本公开实施例提供的一种时钟处理电路的工作过程示意图；
图9为本公开实施例提供的一种控制装置的结构示意图；
图10为本公开实施例提供的一种时钟处理方法的流程示意图；
图11为本公开实施例提供的一种电子设备的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
DRAM(Dynamic Random Access Memory)：动态随机存取存储器
SDRAM(Synchronous Dynamic Random Access Memory)：同步动态随机存储器
MRR(Mode Register Read)：模式寄存器读指令
Mbps(Million bits per second)：兆比特每秒
NMOS(N-Metal-Oxide-Semiconductor)：N型沟道场效应晶体管
PMOS(P-Metal-Oxide-Semiconductor)：N型沟道场效应晶体管
在存储器(例如DRAM)中，MRR指令和正常读指令采用完全一样的操作时序。参见图1，其示出了MRR指令的操作时序示意图。在图1中，T0、T1……用于标识不同的时钟周期，CK_c和CK_t是一对差分时钟信号，CS为片选信号，CA为命令地址信号，COMMAND指示操作指令，DQ[7:0]为8位存储器的数据信号，DQ[15:0]为16位存储器的数据信号，数据时钟信号WCK是电子设备的主机端(Host)发送给存储器的外部写时钟信号， 在不同的电路位置可能表现为单个信号或者一对差分时钟信号WCK_c和WCK_t；读时钟信号RDQS是存储器向电子设备输出的时钟信号，在不同的电路位置可能表现为单个信号或者一对差分时钟信号RDQS_c和RDQS_t。具体来说，在存储器接收到CPU发送的MRR指令后，生成数据信号DQ(也可以称为读数据信号)，以及利用从外部接收的数据时钟信号WCK产生读时钟信号RDQS。在数据读指令的执行过程中，存储器将读数据信号DQ和读时钟信号RDQS共同返回给CPU，然后CPU利用读时钟信号RDQS锁存读数据信号DQ，从而获得需要的数据。另外，图1为电子装置工程设计联合协会(JEDEC)标准规定的标准时序，其中各信号的含义、相关变化的原理以及未经提及的部分名词缩写均可参照行业标准文件JEDEC进行理解，且与本公开实施例的技术方案无关，不会影响技术人员对本公开实施例的理解，因此不作解释。
存储器中设置有时钟处理电路，用于对数据时钟信号WCK0(包括一对互补的信号WCK_c/WCK_t)的占空比进行调整，以使得数据时钟信号WCK0的占空比符合要求。参见图2，其示出了一种时钟处理电路的结构示意图。如图2所示，在时钟处理电路中，接收模块配置为从外部接收数据时钟信号WCK0，调节模块对数据时钟信号WCK进行占空比调整以得到内部时钟信号WCK1，检测模块配置为检测内部时钟信号WCK1的占空比参数并将其存储在模式寄存器中。同时，在存储器进行占空比调整的过程中，CPU发送MRR指令读取模式寄存器中的占空比参数，从而决定下一步的操作。在一种示例的情况中，如图2所示，假设外部输入的数据时钟信号WCK0的占空比为JEDEC规定的上限57％，在占空比调整的初始步骤中，占空比调节模块将数据时钟信号WCK0的占空比增加7个单位(JEDEC规定的上限，且每个单位为5皮秒)，即增加了35皮秒，相当于在8533Mbps的速度下将占空比增加15％，此时存储器中的内部时钟信号WCK1的占空比将高达72％，利用其产生的读时钟信号RDQS的占空比也将高达72％。此时，参见图3，其示出了一种读时钟信号的波形示意图。如图3所示，占空比高达72％的读时钟信号RDQS在传输过程中经过通道衰减，在到达CPU接收端时会严重畸变，导致很难被CPU正确识别，即MRR指令可能得到错误的数据，最终导致占空比调整失败。如果存储器的速度 更高，这一问题将更加严重。
基于此，本公开实施例提供了一种存储器，该存储器包括时钟处理电路，时钟处理电路包括：占空比模块，配置为接收外部产生的数据时钟信号；对数据时钟信号进行占空比调节，输出内部时钟信号；第一时钟产生模块，配置为接收内部时钟信号，基于内部时钟信号，输出第一读时钟信号；其中，第一读时钟信号为脉冲信号；第二时钟产生模块，配置为在第一读时钟信号的存在期间，产生并输出第二读时钟信号；其中，第二读时钟信号仅存在一个电平状态变化沿；选择模块，配置为接收第一读时钟信号和第二读时钟信号，将第一读时钟信号和第二读时钟信号的两者之一输出为目标读时钟信号。这样，在存储器的内部时钟信号发生占空比畸变的情况下，可以选择具有单个电平变化沿的第二读时钟信号作为目标读时钟信号，避免数据锁存失败。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图4，其示出了本公开实施例提供的一种存储器10的结构示意图。如图4所示，存储器10包括时钟处理电路20，时钟处理电路20包括：
占空比模块21，配置为接收外部产生的数据时钟信号；对数据时钟信号进行占空比调节，输出内部时钟信号；
第一时钟产生模块22，配置为接收内部时钟信号，基于内部时钟信号，输出第一读时钟信号；其中，第一读时钟信号为脉冲信号；
第二时钟产生模块23，配置为在第一读时钟信号的存在期间，产生并输出第二读时钟信号；其中，第二读时钟信号仅存在一个电平状态变化沿；
选择模块24，配置为接收第一读时钟信号和第二读时钟信号，将第一读时钟信号和第二读时钟信号的两者之一输出为目标读时钟信号。
需要说明的是，本公开实施例中存储器10可以为多种类型的半导体存储器，例如DRAM、SDRAM、双倍速率DRAM、低功率双倍速率DRAM等。
在存储器10中同时设置有第一时钟产生模块22和第二时钟产生模块23，第一时钟产生模块22可以根据从外部接收的数据时钟信号产生存在多个脉冲的第一读时钟信号，第二时钟产生模块23可以在产生仅存在一个电 平状态变化沿的第二读时钟信号。这样，在不同的工作场景下，可以选择第一读时钟信号或者第二读时钟信号作为目标读时钟信号发送到CPU，以便实现数据锁存处理。特别地，由于第二读时钟信号并不会受到内部时钟信号发生占空比畸变的影响，在内部时钟信号的占空比畸变较大的场景中依然可以保证数据的正确锁存。
在这里，第二读时钟信号的具体波形和产生过程具有多种可能，本公开实施例后续仅作为示例而不构成具体限定。特别地，第二读时钟信号的电平变化沿与读数据信号中有效数据的结束时刻同步，或者第二读时钟信号的电平变化沿提前于读数据信号中有效数据的结束时刻，从而保证有效数据的正确锁存。另外，电平变化沿可以是上升沿(即第二读时钟信号由低电平变化为高电平)或下降沿(即第二读时钟信号由高电平变化为低电平)。
需要说明的是，如图5所示，占空比模块21包括接收模块211和调节模块212两个部分，具体实现可以参见后续描述；第一时钟产生模块22可以由逻辑器件和延迟单元构成，以实现延迟匹配且符合JEDEC标准规定的标准时序；第二时钟产生模块23可以由D型触发器和反相器组成的分频器构成，选择模块24可以通过二选一数据选择器实现。
在一些实施例中，数据时钟信号为从外部接收的写时钟信号，后续表示为WCK0；内部时钟信号为存储器内部经过占空比调整的写时钟信号，后续表示为WCK1；目标读时钟信号为读操作数据选通信号，后续表示为RDQS；读数据信号可以表示为DQ。
在一些实施例中，如图5所示，时钟处理电路20还包括检测模块25和模式寄存器26；其中，检测模块25，配置为接收内部时钟信号WCK1，对内部时钟信号WCK1进行占空比检测，输出占空比参数；模式寄存器26，配置为接收并存储占空比参数。
需要说明的是，检测模块25可以由逻辑门、传输门、电容以及信号比较器构成。
在一些实施例中，如图6所示，选择模块24，具体配置为接收选择指示信号，在选择指示信号处于第一状态的情况下，将第一读时钟信号输出为目标读时钟信号RDQS；或者，在选择指示信号处于第二状态的情况下， 将第二读时钟信号输出为目标读时钟信号RDQS。
在这里，选择模块24可以为二选一数据选择器，从而根据选择指示信号的状态输出第一读时钟信号或者输出第二读时钟信号。
在一些实施例中，存储器10，配置为接收数据读指令；基于数据读指令，输出读数据信号DQ，并通过时钟处理电路20输出目标读时钟信号RDQS；其中，目标读时钟信号RDQS用于锁存读数据信号DQ，且第二读时钟信号的电平状态变化沿指示读数据信号DQ中有效数据的结束时刻。
也就是说，在包含存储器10的电子设备中，电子设备的CPU向存储器10下发操作指令，以便实现数据写入或者数据读出。在数据读出的过程中，CPU向存储器10发送数据读指令，存储器10根据数据读指令生成读数据信号DQ(携带有CPU所需要读取的参数)，并通过时钟处理电路20产生目标读时钟信号RDQS。这样，读数据信号DQ和目标读时钟信号RDQS均被发送至CPU，以便CPU利用目标读时钟信号RDQS对读数据信号进行锁存，后续译码得到需要的参数。
在本公开实施例中，将数据读指令划分为两种类型，即第一读指令和第二读指令。第二读指令指示获取时钟处理电路20中模式寄存器26的占空比参数，第一读指令是指除第二读指令之外的数据读取指令。
在一种具体的实施例中，存储器10，还配置为在数据读指令为第一读指令的情况下，将选择指示信号置为第一状态；或者，在数据读指令为第二读指令的情况下，将选择指示信号置为第二状态。
如前述，在数据读指令用于读取模式寄存器26中的占空比参数的情况下，存储器10可能处于占空比调整的过程中，在某些情况下内部时钟信号WCK1已经发生畸变，例如内部时钟信号WCK1的占空比可能高达72％，此时第一读时钟信号也将发生畸变，CPU利用第一读时钟信号对读数据信号DQ进行锁存可能会得到错误结果。对于本公开实施例来说，在数据读指令用于读取模式寄存器26中的占空比参数的情况下，将第二读时钟信号输出为目标读时钟信号RDQS，由于第二读时钟信号仅有一个电平变化沿，并不会受到内部时钟信号WCK1的占空比畸变的影响，因此CPU可以利用第二读时钟信号中的电平变化沿对数据信号进行锁存，从而获得正确的占空比参数。
另外，为了节约功耗，在数据读指令为第一读指令的情况下，第二时钟产生模块23可以是不使能的，即第二时钟产生模块23不工作，从而达到减少电流和功耗的目的。
在另一种具体的实施例中，存储器10，还配置为在数据读指令为第一读指令的情况下，将选择指示信号置为第一状态；或者，在数据读指令为第二读指令且内部时钟信号WCK1的占空比处于预设范围的情况下，将选择指示信号置为第一状态；或者，在数据读指令为第二读指令且内部时钟信号WCK1的占空比并非处于预设范围的情况下，将选择指示信号置为第二状态。
也就是说，在数据读指令用于读取模式寄存器26中的占空比参数的情况下，如果内部时钟信号WCK1的占空比是符合要求的，此时第一读时钟信号并不会畸变，此时CPU仍然可以利用第一读时钟信号对读数据信号进行锁存。
以下以DRAM的突发长度为16，且具有16个DQ端作为示例，说明第二读时钟信号的具体波形和读数据信号的锁存过程。
针对第二读指令，读数据信号DQ的前8位携带有效数据，表示为DQ<7:0>。根据JEDEC标准的规定，在目标读时钟信号RDQS的前8拍(前4个时钟周期)传输模式寄存器的参数值(MR Content)，后8拍(后4个时钟周期)传输不关心的数据(Valid)。此时，第一读时钟信号包括8个时钟周期，第二读时钟信号的电平状态变化沿与第一读时钟信号中的第5个时钟周期的上升沿对齐；其中，第二读时钟信号的电平状态变化沿是指第二读时钟信号由低电平状态变化为高电平状态。
也就是说，如图7中的(1)所示，如果利用第一读时钟信号作为目标读时钟信号RDQS，CPU将利用目标读时钟信号RDQS的信号沿对读数据信号DQ<7:0>进行锁存，前4个时钟周期锁存的数据为MR Content，后4个时钟周期锁存的数据Valid不作使用；如图7中的(2)所示，如果利用第二读时钟信号作为目标读时钟信号RDQS，CPU将利用第二读时钟信号中的上升沿对读数据信号DQ<7:0>进行锁存，得到MR Content。
在一些实施例中，如图5或者图6所示，占空比模块21包括：接收模块211，配置为从外部接收并输出数据时钟信号WCK0；调节模块212，配 置为对数据时钟信号WCK0进行占空比调节，输出内部时钟信号WCK1。
需要说明的是，调节模块212配置为占空比调节。在占空比调节开始时，调节模块212的默认设置会导致数据时钟信号WCK0的占空比增加一定值，根据JEDEC的规定，占空比增加的上限为7个单位(Step)，即35皮秒。
接收模块211可以通过由NMOS和PMOS等器件构成的信号接收器实现，调节模块212可以通过级联的延迟单元组成，每个延迟单元由NMOS和PMOS构成，从而实现数据时钟信号WCK0中上升沿的向前/向后调整，和/或，实现数据时钟信号WCK0中下降沿的向前/向后调整，最终调整数据时钟信号WCK0的占空比。
以下提供一种可能出现的工作场景，对本公开实施例的技术效果进行说明。如图8中的(a)所示，外部产生的数据时钟信号WCK0的占空比为57％，在占空比调节过程开始时，默认将数据时钟信号WCK0的占空比增加7个单位(35皮秒)，如果存储器的速度为8633Mbps，此时内部时钟信号WCK1的占空比将在数据时钟信号WCK0的基础上继续增加15％，即内部时钟信号WCK1的占空比将高达72％。如图8中的(b)所示，此时CPU向存储器发送第二读指令，选择指示信号将被置为第二状态，存储器10将具有单个信号沿的第二读时钟信号作为目标读时钟信号RDQS，从而CPU可以利用第二读时钟信号对读数据信号DQ<7:0>进行锁存，获得正确的占空比参数，保证占空比调整操作的成功。
综上所述，本公开实施例提供了一种存储器，该存储器包括时钟处理电路，时钟处理电路包括：占空比模块，配置为接收外部产生的数据时钟信号；对数据时钟信号进行占空比调节，输出内部时钟信号；第一时钟产生模块，配置为接收内部时钟信号，基于内部时钟信号，输出第一读时钟信号；其中，第一读时钟信号为脉冲信号；第二时钟产生模块，配置为在第一读时钟信号的存在期间，产生并输出第二读时钟信号；其中，第二读时钟信号仅存在一个电平状态变化沿；选择模块，配置为接收第一读时钟信号和第二读时钟信号，将第一读时钟信号和第二读时钟信号的两者之一输出为目标读时钟信号。这样，在内部时钟信号发生占空比畸变的情况下，可以选择具有单个电平变化沿的第二读时钟信号作为目标读时钟信号，避 免数据锁存失败。
在本公开的另一实施例中，参见图9，其示出了本公开实施例提供的一种控制装置30的结构示意图。如图9所示，控制装置30与存储器10连接；其中，
控制装置30，配置为向存储器10发送数据读指令；以及，接收存储器10返回的读数据信号DQ和目标读时钟信号RDQS，利用目标读时钟信号RDQS对读数据信号DQ进行锁存处理；其中，目标读时钟信号RDQS为第一读时钟信号或者第二读时钟信号，第一读时钟信号为脉冲信号，第二读时钟信号仅存在一个电平状态变化沿。
需要说明的是，控制装置30可以为CPU。具体来说，控制装置30通过存储器10的内存控制器(Controller)发送指令，以读取存储器10中的模式寄存器/存储阵列的数据。具体来说，在读取存储器10的数据时，CPU通过命令总线和数据总线将数据读指令发送给存储器，存储器10对数据读指令进行解析并执行相应的读操作，以便得到读数据信号。除此之外，存储器还会产生目标读时钟信号，以便控制装置30利用目标读时钟信号RDQS对读数据信号DQ进行锁存处理，获得所需要的数据。
请结合图4～图6，在本公开实施例中，控制装置30从存储器10处接收到的目标读时钟信号RDQS可能具有多个脉冲或者仅存在一个电平状态变化沿。也就是说，在第一读时钟信号的占空比畸变时，存储器10将仅有一个电平状态变化沿的第二读时钟信号作为目标读时钟信号RDQS发送给控制装置30，以将读数据信号DQ进行正确锁存。
在一种具体的实施例中，控制装置30，具体配置为在数据读指令为第一读指令的情况下，接收存储器10返回的第一读时钟信号，利用第一读时钟信号对读数据信号DQ进行锁存处理；或者，在数据读指令为第二读指令的情况下，接收存储器10返回的第二读时钟信号，利用第二读时钟信号的电平状态变化沿对读数据信号DQ进行锁存处理。
需要说明的是，存储器10包括时钟处理电路20，第二读指令指示获取时钟处理电路20中模式寄存器的占空比参数，第一读指令指示除第二读指令之外的数据读取指令。
这样，在数据读指令为第二读指令的情况下，存储器10可能处于占空 比调整的过程，存储器10中的内部时钟信号WCK1可能是畸变的，即第一读时钟信号是畸变的，可以采用第二读时钟信号作为目标读时钟信号RDQS，以便控制装置30能够获取正确的占空比参数。反之，在数据读指令为第一读指令的情况下，存储器中的内部时钟信号WCK1和第一读时钟信号均是正常的，因此，可以采用第一读时钟信号作为目标读时钟信号RDQS，控制装置30可以获得正确的结果。
在另一种具体的实施例中，控制装置30，还配置为在数据读指令为第二读指令的情况下，接收存储器10返回的第一读时钟信号，利用第一读时钟信号的电平状态变化沿对读数据信号DQ进行锁存处理。
这样，在数据读指令为第二读指令的情况下，存储器10中的内部时钟信号WCK1和第一读时钟信号仍然可能是正常的，所以存储器10仍然可以采用第一读时钟信号作为目标读时钟信号RDQS。
本公开实施例提供了一种控制装置，该控制装置与存储器连接；控制装置，配置为向存储器发送数据读指令；以及，接收存储器返回的读数据信号和目标读时钟信号，利用目标读时钟信号对读数据信号进行锁存处理；其中，目标读时钟信号为第一读时钟信号或者第二读时钟信号，第一读时钟信号为脉冲信号，第二读时钟信号仅存在一个电平状态变化沿。这样，在内部时钟信号发生占空比畸变的情况下，可以利用具有单个电平变化沿的第二读时钟信号对读数据信号进行锁存，避免数据锁存失败。
在本公开的又一实施例中，参见图10，其示出了本公开实施例提供的一种时钟处理方法的流程示意图。如图10所示，该方法包括：
S401：接收外部产生的数据时钟信号；对数据时钟信号进行占空比调节，确定内部时钟信号。
S402：基于内部时钟信号，确定第一读时钟信号；其中，第一读时钟信号为脉冲信号。
S403：在第一读时钟信号的存在期间，产生第二读时钟信号；其中，第二读时钟信号仅存在一个电平状态变化沿。
S404：将第一读时钟信号和第二读时钟信号的两者之一输出为目标读时钟信号。
需要说明的是，该方法应用于前述的存储器10。这样，存储器10可以 同时产生第一读时钟信号和第二读时钟信号，在不同的工作场景下，可以选择第一读时钟信号或者第二读时钟信号作为目标读时钟信号RDQS发送到CPU，以便实现数据信号的锁存处理。特别地，由于第二读时钟信号并不会受到内部时钟信号WCK1的占空比畸变的影响，在内部时钟信号WCK1的占空比畸变较大的场景中依然可以保证数据信号的正确锁存。
在一些实施例中，如前述，存储器10包括模式寄存器26，该方法还包括：
对内部时钟信号进行占空比检测，得到占空比参数；将占空比参数存储至模式寄存器。
在一种具体的实施例中，如前述，存储器10与控制装置30连接，所述将第一读时钟信号和第二读时钟信号的两者之一输出为目标读时钟信号，包括：
在接收到控制装置发送的第一读指令的情况下，基于第一读指令确定读数据信号，并将第一读时钟信号确定为目标读时钟信号；在接收到控制装置发送的第二读指令的情况下，基于第二读指令确定读数据信号，并将第二读时钟信号确定为目标读时钟信号。
在这里，目标读时钟信号用于锁存读数据信号，第二读指令指示获取模式寄存器的占空比参数，第一读指令指示除第二读指令之外的数据读取指令。
在另一种具体的实施例中，所述将第一读时钟信号和第二读时钟信号的两者之一输出为目标读时钟信号，包括：
在接收到控制装置发送的第一读指令的情况下，基于第一读指令确定读数据信号，并将第一读时钟信号确定为目标读时钟信号；在接收到控制装置发送的第二读指令且占空比参数处于预设范围的情况下，基于第二读指令确定读数据信号，并将第一读时钟信号确定为目标读时钟信号；在接收到控制装置发送的第二读指令且占空比参数并非处于预设范围的情况下，基于第二读指令确定读数据信号，并将第二读时钟信号确定为目标读时钟信号。
本公开实施例提供了一种时钟处理方法，该方法包括：接收外部产生的数据时钟信号；对数据时钟信号进行占空比调节，确定内部时钟信号； 基于内部时钟信号，确定第一读时钟信号；其中，第一读时钟信号为脉冲信号；在第一读时钟信号的存在期间，产生第二读时钟信号；其中，第二读时钟信号仅存在一个电平状态变化沿；将第一读时钟信号和第二读时钟信号的两者之一输出为目标读时钟信号。这样，在内部时钟信号发生占空比畸变的情况下，可以选择具有单个电平变化沿的第二读时钟信号作为目标读时钟信号，避免数据锁存失败。
在本公开的又一实施例中，参见图11，其示出了本公开实施例提供的一种电子设备50组成结构示意图。如图11所示，电子设备50至少包括前述的存储器10和前述的控制装置30。
由于存储器10能够输出具有多个脉冲的第一读时钟信号或者具有单个电平变化沿的第二读时钟信号，在存储器10中的内部时钟信号发生占空比畸变的情况下，可以选择具有单个电平变化沿的第二读时钟信号作为目标读时钟信号，控制装置30利用第二读时钟信号中的电平变化沿进行数据锁存，避免获得错误的数据。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种存储器、控制装置、时钟处理方法和电子设备，存储器包括时钟处理电路，时钟处理电路包括：占空比模块，配置为接收外部产生的数据时钟信号；对数据时钟信号进行占空比调节，输出内部时钟信号；第一时钟产生模块，配置为接收内部时钟信号，基于内部时钟信号，输出第一读时钟信号；其中，第一读时钟信号为脉冲信号；第二时钟产生模块，配置为在第一读时钟信号的存在期间，产生并输出第二读时钟信号；其中，第二读时钟信号仅存在一个电平状态变化沿；选择模块，配置为接收第一读时钟信号和第二读时钟信号，将第一读时钟信号和第二读时钟信号的两者之一输出为目标读时钟信号。这样，在存储器的内部时钟信号发生占空比畸变的情况下，可以选择具有单个电平变化沿的第二读时钟信号作为目标读时钟信号，避免数据锁存失败。

Claims (17)

  1. 一种存储器，所述存储器包括时钟处理电路，所述时钟处理电路包括：
    占空比模块，配置为接收外部产生的数据时钟信号；对所述数据时钟信号进行占空比调节，输出内部时钟信号；
    第一时钟产生模块，配置为接收所述内部时钟信号，基于所述内部时钟信号，输出第一读时钟信号；其中，所述第一读时钟信号为脉冲信号；
    第二时钟产生模块，配置为在所述第一读时钟信号的存在期间，产生并输出第二读时钟信号；其中，所述第二读时钟信号仅存在一个电平状态变化沿；
    选择模块，配置为接收所述第一读时钟信号和所述第二读时钟信号，将所述第一读时钟信号和所述第二读时钟信号的两者之一输出为目标读时钟信号。
  2. 根据权利要求1所述的存储器，其中，所述时钟处理电路还包括检测模块和模式寄存器；其中，
    所述检测模块，配置为接收所述内部时钟信号，对所述内部时钟信号进行占空比检测，输出占空比参数；
    所述模式寄存器，配置为接收并存储所述占空比参数。
  3. 根据权利要求2所述的存储器，其中，
    所述选择模块，具体配置为接收选择指示信号，在所述选择指示信号处于第一状态的情况下，将所述第一读时钟信号输出为目标读时钟信号；或者，在所述选择指示信号处于第二状态的情况下，将所述第二读时钟信号输出为目标读时钟信号。
  4. 根据权利要求3所述的存储器，其中，
    所述存储器，配置为接收数据读指令；基于所述数据读指令，输出读数据信号，并通过所述时钟处理电路输出所述目标读时钟信号；
    其中，所述目标读时钟信号用于锁存所述读数据信号，且所述第二读时钟信号的电平状态变化沿指示所述读数据信号中有效数据的结束时刻。
  5. 根据权利要求4所述的存储器，其中，
    所述存储器，还配置为在所述数据读指令为第一读指令的情况下，将 所述选择指示信号置为第一状态；或者，在所述数据读指令为第二读指令的情况下，将所述选择指示信号置为第二状态；
    其中，所述第二读指令指示获取所述时钟处理电路中模式寄存器的占空比参数，所述第一读指令是指除所述第二读指令之外的数据读取指令。
  6. 根据权利要求5所述的存储器，其中，
    所述存储器，还配置为在所述数据读指令为第一读指令的情况下，将所述选择指示信号置为第一状态；或者，
    在所述数据读指令为第二读指令且所述内部时钟信号的占空比处于预设范围的情况下，将所述选择指示信号置为第一状态；或者，
    在所述数据读指令为第二读指令且所述内部时钟信号的占空比并非处于预设范围的情况下，将所述选择指示信号置为第二状态。
  7. 根据权利要求1-6任一项所述的存储器，其中，所述第一读时钟信号包括8个时钟周期，所述第二读时钟信号的电平状态变化沿与所述第一读时钟信号中的第5个时钟周期的上升沿对齐；
    其中，所述第二读时钟信号的电平状态变化沿是指所述第二读时钟信号由低电平状态变化为高电平状态。
  8. 根据权利要求7所述的存储器，其中，所述占空比模块包括：
    接收模块，配置为从外部接收并输出所述数据时钟信号；
    调节模块，配置为对所述数据时钟信号进行占空比调节，输出所述内部时钟信号。
  9. 根据权利要求8所述的存储器，其中，所述数据时钟信号为写时钟信号。
  10. 一种控制装置，所述控制装置与存储器连接；其中，
    所述控制装置，配置为向所述存储器发送数据读指令；以及，接收所述存储器返回的读数据信号和目标读时钟信号，利用所述目标读时钟信号对所述读数据信号进行锁存处理；
    其中，所述目标读时钟信号为第一读时钟信号或者第二读时钟信号，所述第一读时钟信号为脉冲信号，所述第二读时钟信号仅存在一个电平状态变化沿。
  11. 根据权利要求10所述的控制装置，其中，
    所述控制装置，具体配置为在所述数据读指令为第一读指令的情况下，接收所述存储器返回的第一读时钟信号，利用所述第一读时钟信号对所述读数据信号进行锁存处理；或者，
    在所述数据读指令为第二读指令的情况下，接收所述存储器返回的第二读时钟信号，利用所述第二读时钟信号的电平状态变化沿对所述读数据信号进行锁存处理；
    其中，所述存储器包括时钟处理电路，所述第二读指令指示获取所述时钟处理电路中模式寄存器的占空比参数，所述第一读指令指示除所述第二读指令之外的数据读取指令。
  12. 根据权利要求10所述的控制装置，其中，
    所述控制装置，还配置为在所述数据读指令为第二读指令的情况下，接收所述存储器返回的第一读时钟信号，利用所述第一读时钟信号的电平状态变化沿对所述读数据信号进行锁存处理。
  13. 一种时钟处理方法，应用于存储器，所述方法包括：
    接收外部产生的数据时钟信号；对所述数据时钟信号进行占空比调节，确定内部时钟信号；
    基于所述内部时钟信号，确定第一读时钟信号；其中，所述第一读时钟信号为脉冲信号；
    在所述第一读时钟信号的存在期间，产生第二读时钟信号；其中，所述第二读时钟信号仅存在一个电平状态变化沿；
    将所述第一读时钟信号和所述第二读时钟信号的两者之一输出为目标读时钟信号。
  14. 根据权利要求13所述的时钟处理方法，其中，所述存储器包括模式寄存器，所述方法还包括：
    对所述内部时钟信号进行占空比检测，得到占空比参数；
    将所述占空比参数存储至所述模式寄存器。
  15. 根据权利要求14所述的时钟处理方法，其中，所述存储器与控制装置连接，所述将所述第一读时钟信号和所述第二读时钟信号的两者之一输出为目标读时钟信号，包括：
    在接收到所述控制装置发送的第一读指令的情况下，基于所述第一读 指令确定读数据信号，并将所述第一读时钟信号确定为目标读时钟信号；
    在接收到所述控制装置发送的第二读指令的情况下，基于所述第二读指令确定所述读数据信号，并将所述第二读时钟信号确定为目标读时钟信号；
    其中，所述目标读时钟信号用于锁存所述读数据信号，所述第二读指令指示获取所述模式寄存器的占空比参数，所述第一读指令指示除所述第二读指令之外的数据读取指令。
  16. 根据权利要求14所述的时钟处理方法，其中，所述存储器与控制装置连接，所述将所述第一读时钟信号和所述第二读时钟信号的两者之一输出为目标读时钟信号，包括：
    在接收到所述控制装置发送的第一读指令的情况下，基于所述第一读指令确定读数据信号，并将所述第一读时钟信号确定为目标读时钟信号；
    在接收到所述控制装置发送的第二读指令且所述占空比参数处于预设范围的情况下，基于所述第二读指令确定读数据信号，并将所述第一读时钟信号确定为目标读时钟信号；
    在接收到控制装置发送的第二读指令且所述占空比参数并非处于预设范围的情况下，基于所述第二读指令确定所述读数据信号，并将所述第二读时钟信号确定为目标读时钟信号；
    其中，所述目标读时钟信号用于锁存所述读数据信号，所述第二读指令指示获取所述模式寄存器的占空比参数，所述第一读指令指示除所述第二读指令之外的数据读取指令。
  17. 一种电子设备，所述电子设备包括如权利要求1-9任一项所述的存储器和如权利要求10-12任一项所述的控制装置。
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