WO2024007398A1 - 一种控制装置、存储器、信号处理方法和电子设备 - Google Patents

一种控制装置、存储器、信号处理方法和电子设备 Download PDF

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Publication number
WO2024007398A1
WO2024007398A1 PCT/CN2022/109916 CN2022109916W WO2024007398A1 WO 2024007398 A1 WO2024007398 A1 WO 2024007398A1 CN 2022109916 W CN2022109916 W CN 2022109916W WO 2024007398 A1 WO2024007398 A1 WO 2024007398A1
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Prior art keywords
read
clock signal
signal
memory
data
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PCT/CN2022/109916
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English (en)
French (fr)
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程景伟
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长鑫存储技术有限公司
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Priority to KR1020227042780A priority Critical patent/KR20240007736A/ko
Priority to EP22838629.8A priority patent/EP4325492A4/en
Priority to JP2022566194A priority patent/JP7539487B2/ja
Priority to US18/154,815 priority patent/US20240013825A1/en
Publication of WO2024007398A1 publication Critical patent/WO2024007398A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Definitions

  • the present disclosure relates to the field of semiconductor memory technology, and in particular, to a control device, a memory, a signal processing method and an electronic device.
  • the Central Processing Unit sends a read instruction to the memory, then receives the read clock signal and read data signal returned by the memory, and uses the read clock signal to latch the read data signal in order to obtain the desired required data.
  • the central processor needs to obtain the duty cycle parameters of the clock signal by reading the corresponding mode register in the memory.
  • the clock signal inside the memory may be The read clock signal returned by the memory to the central controller is also distorted, causing the central processor to obtain erroneous data and ultimately causing the duty cycle adjustment of the clock signal to fail.
  • the present disclosure provides a control device, a memory, a signal processing method and an electronic device, which can not only improve the accuracy of data latching, but also save power consumption.
  • an embodiment of the present disclosure provides a control device, the control device is connected to a memory, and the control device includes:
  • a receiving module configured to receive a read clock signal from the memory and output the read clock signal
  • a clock module configured to generate a first internal clock signal
  • a selection module configured to receive the read clock signal and the first internal clock signal, and output one of the read clock signal and the first internal clock signal as a target read clock signal;
  • the latch module is configured to receive the target read clock signal and the read data signal sent by the memory, and use the target read clock signal to perform latch processing on the read data signal.
  • the selection module is specifically configured to receive a selection indication signal, and when the selection indication signal is in the first state, output the read clock signal as the target read clock signal; or, When the selection indication signal is in the second state, the first internal clock signal is output as the target read clock signal.
  • control device is further configured to send a data read instruction to the memory, so that the memory generates the read clock signal and the read data signal.
  • control device is further configured to set the selection indication signal to the first state when the data read instruction is a first read instruction; or, when the data read instruction is a first read instruction In the case of a second read instruction, the selection indication signal is set to the second state; wherein the second read instruction instructs to obtain the duty cycle parameter stored in the mode register in the memory, and the first read instruction is Refers to data read instructions other than the second read instruction.
  • an embodiment of the present disclosure provides a memory, the memory includes a clock processing circuit, and the memory is connected to a control device; wherein,
  • the memory is configured to, upon receiving a first read instruction, determine a read data signal based on the first read instruction, determine a read clock signal through the clock processing circuit, and combine the read data signal with the The read clock signals are collectively sent to the control device; or,
  • the read data signal is determined based on the second read command, and the read data signal is sent to the control device.
  • the memory is further configured to control the read clock signal to be in a floating state when receiving a second read instruction.
  • the clock processing circuit includes: a duty cycle module configured to receive an externally generated data clock signal; perform duty cycle adjustment on the data clock signal and output a second internal clock signal; a clock generation module , configured to receive the second internal clock signal, and output the read clock signal based on the second internal clock signal; wherein the read clock signal is a pulse signal.
  • the clock processing circuit further includes: a detection module configured to receive the second internal clock signal, perform duty cycle detection on the second internal clock signal, and output a duty cycle parameter; a mode register , configured to receive and store the duty cycle parameter; wherein, the second read instruction indicates obtaining the duty cycle parameter stored in the mode register, and the first read instruction refers to the second read instruction in addition to the second read instruction. external data read instructions.
  • the duty cycle module includes: a receiver configured to receive and output the data clock signal from the outside; an adjustment module configured to perform duty cycle adjustment on the data clock signal and output the Second internal clock signal.
  • the data clock signal is a write clock signal.
  • embodiments of the present disclosure provide a signal processing method applied to a control device, and the control device is connected to a memory.
  • the method includes:
  • the read data signal is latched using the target read clock signal.
  • the method before receiving the read clock signal and the read data signal sent by the memory, the method further includes:
  • a data read instruction is sent to the memory, so that the memory generates the read clock signal and the read data signal.
  • the method further includes:
  • the read clock signal is determined as the target read clock signal; or, when the data read instruction is a second read instruction, the read clock signal is determined as the target read clock signal.
  • the first internal clock signal is determined as the target read clock signal; wherein the second read instruction indicates obtaining the duty cycle parameter stored in the mode register in the memory, and the first read instruction refers to removing the second Data read instructions other than read instructions.
  • embodiments of the present disclosure provide a signal processing method applied to a memory, and the memory is connected to a control device.
  • the method includes:
  • a read data signal is determined based on the first read instruction, a read clock signal is generated through a clock processing circuit in the memory, and the read data signal and the read clock signal are jointly sent to the control device; or, when a second read instruction is received, the read data signal is determined based on the second read instruction, and the read data signal is sent to the control device.
  • the method further includes: when receiving the first read instruction, controlling the read clock signal to be in a floating state.
  • generating a read clock signal through a clock processing circuit in the memory includes:
  • the method further includes: performing duty cycle detection on the second internal clock signal to obtain a duty cycle parameter; storing the duty cycle parameter into a mode register; wherein, the first The second read instruction indicates obtaining the duty cycle parameter stored in the mode register, and the first read instruction refers to a data read instruction other than the second read instruction.
  • an embodiment of the present disclosure provides an electronic device, which at least includes the control device as described in the first aspect and the memory as described in the second aspect.
  • Embodiments of the present disclosure provide a control device, a memory, a signal processing method and an electronic device.
  • the control device is connected to the memory.
  • the control device includes: a receiving module configured to receive a read clock signal from the memory and output the read clock signal; a clock module , configured to generate a first internal clock signal; the selection module is configured to receive a read clock signal and a first internal clock signal, and output one of the read clock signal and the first internal clock signal as a target read clock signal; latch The module is configured to receive a target read clock signal and a read data signal sent by the memory, and use the target read clock signal to latch the read data signal. In this way, when the clock signal in the memory has duty cycle distortion, the control device can still latch the read data signal through the first internal clock signal, which not only improves the accuracy of data latching, but also saves power consumption.
  • Figure 1 is a schematic diagram of the operation timing of the MRR instruction
  • Figure 2 is a schematic structural diagram of a clock processing circuit
  • Figure 3 is a schematic waveform diagram of a read clock signal
  • Figure 4 is a schematic structural diagram of a control device provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another control device provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic diagram of a signal waveform of a data latch process provided by an embodiment of the present disclosure
  • Figure 7 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram 1 of a partial structure of a clock processing circuit provided by an embodiment of the present disclosure
  • Figure 9 is a schematic diagram 2 of a partial structure of a clock processing circuit provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic diagram of the working process of a clock processing circuit provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic flow chart of a signal processing method provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic flow chart of another signal processing method provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first ⁇ second ⁇ third” Where permitted, the specific order or sequence may be interchanged so that the embodiments of the disclosure described herein can be practiced in an order other than that illustrated or described herein.
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • NMOS N-Metal-Oxide-Semiconductor: N-type channel field effect transistor
  • PMOS P-Metal-Oxide-Semiconductor
  • FIG. 1 a schematic diagram of the operation timing of the MRR instruction is shown.
  • T0, T1... are used to identify different clock cycles
  • CK_c and CK_t are a pair of differential clock signals
  • CS is the chip select signal
  • CA is the command address signal
  • COMMAND indicates the operation instruction
  • DQ[7:0 ] is the data signal of the 8-bit memory
  • DQ[15:0] is the data signal of the 16-bit memory
  • the data clock signal WCK is the external write clock signal sent to the memory by the host of the electronic device (Host), at different circuit locations It may appear as a single signal or a pair of differential clock signals WCK_c and WCK_t
  • the read clock signal RDQS is the clock signal output by the memory to the electronic device, and may appear as a single signal or a pair of differential clock signals RDQS_c and RDQS_t at different circuit locations.
  • the memory After the memory receives the MRR instruction sent by the CPU, it generates the data signal DQ (which may also be called a read data signal), and generates a read clock signal using the data clock signal received from the outside. During the execution of the data read instruction, the memory returns the read data signal DQ and the read clock signal RDQS to the CPU, and then the CPU uses the read clock signal RDQS to latch the read data signal DQ to obtain the required data.
  • Figure 1 shows the standard timing sequence stipulated by the Joint Electronic Device Engineering Design Council (JEDEC) standard.
  • JEDEC Joint Electronic Device Engineering Design Council
  • a clock processing circuit is provided in the memory for adjusting the duty cycle of the data clock signal WCK0 (including a pair of complementary signals WCK_c/WCK_t) so that the duty cycle of the data clock signal WCK0 meets the requirements.
  • FIG 2 shows a schematic structural diagram of a clock processing circuit.
  • the receiver is used to receive the data clock signal WCK0 from the outside, the adjustment module adjusts the duty cycle of the data clock signal WCK to obtain the second internal clock signal WCK1, and the detection module is used to detect the third internal clock signal WCK1. 2.
  • the duty cycle parameter of the internal clock signal WCK1 and stores it in the mode register.
  • the CPU sends the MRR instruction to read the duty cycle parameters in the mode register to determine the next operation.
  • the duty cycle of the externally input data clock signal WCK0 is 57%, the upper limit specified by JEDEC.
  • the duty cycle adjustment module adjusts the data
  • the duty cycle of the clock signal WCK0 is increased by 7 units (the upper limit specified by JEDEC, and each unit is 5 picoseconds), which is an increase of 35 picoseconds, which is equivalent to increasing the duty cycle by 15% at a speed of 8533Mbps.
  • the duty cycle of the second internal clock signal WCK1 in the memory will be as high as 72%, and the duty cycle of the read clock signal RDQS generated by it will also be as high as 72%.
  • FIG. 3 shows a schematic waveform diagram of a read clock signal.
  • the read clock signal RDQS with a duty cycle of up to 72% is attenuated by the channel during transmission through the circuit module, and will be severely distorted when it reaches the CPU receiving end, making it difficult to be correctly recognized by the CPU, that is, the MRR instruction Wrong data may be obtained, ultimately causing duty cycle adjustment to fail. This problem will be more serious if the memory speed is higher.
  • an embodiment of the present disclosure provides a control device, which is connected to a memory.
  • the control device includes: a receiving module configured to receive a read clock signal from the memory and output the read clock signal; a clock module , configured to generate a first internal clock signal; a selection module configured to receive the read clock signal and the first internal clock signal, and output one of the read clock signal and the first internal clock signal A target read clock signal; a latch module configured to receive the target read clock signal and the read data signal sent by the memory, and use the target read clock signal to perform latch processing on the read data signal.
  • the control device can still latch the read data signal through the first internal clock signal, which not only improves the accuracy of data latch but also saves power consumption.
  • FIG. 4 shows a schematic structural diagram of a control device 10 provided by an embodiment of the present disclosure.
  • the control device 10 is connected to the memory, and the control device 10 includes:
  • the receiving module 11 is configured to receive a read clock signal from the memory and output the read clock signal;
  • the clock module 12 is configured to generate a first internal clock signal
  • the selection module 13 is configured to receive the read clock signal and the first internal clock signal, and output one of the read clock signal and the first internal clock signal as the target read clock signal;
  • the latch module 14 is configured to receive a target read clock signal and a read data signal sent by the memory, and use the target read clock signal to perform latch processing on the read data signal.
  • control device 10 may be a CPU of an electronic device; the memory may be various types of semiconductor memories, such as DRAM, SDRAM, double-rate DRAM, low-power double-rate DRAM, etc.
  • the control device 10 can use the read clock signal obtained from the memory as the target read clock signal, or use the first internal clock signal generated internally as the target read clock signal, thereby completing the latch of the read data signal. deal with. In this way, when the clock signal in the memory has duty cycle distortion, the control device 10 can still latch the read data signal through the first internal clock signal to ensure correct latching of data.
  • the receiving module 11 can be implemented by a signal receiver composed of NMOS and PMOS devices
  • the clock module 12 can be implemented by a clock generator and a transmission gate
  • the selection module 13 can be implemented by a two-to-one data selector.
  • the memory module 14 can be implemented by a D-type flip-flop.
  • the read clock signal can be represented as RDQS
  • the first internal clock signal can be represented as Internal CLK
  • the target read clock signal can be represented as Sample CLK
  • the read data signal can be represented as DQ.
  • the selection module 13 is specifically configured to receive the selection indication signal, and when the selection indication signal is in the first state, output the read clock signal RDQS as the target read clock signal Sample CLK; Alternatively, when the selection indication signal is in the second state, the first internal clock signal Internal CLK is output as the target read clock signal Sample CLK.
  • the selection module 13 can be a two-select data selector, thereby outputting the read clock signal RDQS or the first internal clock signal Internal CLK according to the state of the selection indication signal.
  • the clock terminal of the latch module 14 is connected to the output terminal of the selection module 13, the input terminal of the latch module 14 receives the read data signal DQ, and the output terminal of the latch module 14 outputs the sampled data signal, so as to It is sent to the subsequent circuit of the control device 10 for processing.
  • control device 10 is also configured to send a data read instruction to the memory, so that the memory generates a read clock signal RDQS and a read data signal DQ.
  • control device 10 is further configured to set the selection indication signal to the first state when the data read instruction is the first read instruction; or, when the data read instruction is the second read instruction , sets the selection indication signal to the second state.
  • data read instructions are divided into two types: first read instructions and second read instructions.
  • the second read instruction indicates obtaining the duty cycle parameter stored in the mode register in the memory
  • the first read instruction refers to a data read instruction other than the second read instruction.
  • the memory when the data read instruction is used to read the duty cycle parameter, the memory may be in the process of duty cycle adjustment.
  • the clock signal in the memory ie, the second internal clock signal WCK1
  • the duty cycle of the second internal clock signal WCK1 in Figure 2 may be as high as 72%.
  • the read clock signal RDQS output by the memory will also be distorted.
  • the control device 10 uses the read clock signal RDQS to read the read data signal DQ. Latching may give incorrect results.
  • the first internal clock signal Internal CLK generated by the control device 10 itself is used as the target read clock signal. Since the first internal clock signal Internal CLK will not be affected by the duty cycle distortion of the second internal clock signal WCK1, so the CPU can use the level changing edge of the first internal clock signal Internal CLK to latch the read data signal to obtain the correct duty cycle. ratio parameter.
  • the read clock signal RDQS of the memory has no actual effect. Therefore, the memory can control the read clock signal RDQS to be in a floating state, and the memory does not need to send any signal to the controller. Device 10 sends the read clock signal RDQS to save current.
  • the following uses the burst length of DRAM as 16 and 16 DQ terminals as an example to illustrate the latching process of the read data signal.
  • the first 8 bits of the read data signal DQ carry valid data, expressed as DQ ⁇ 7:0>.
  • the parameter value (MR Content) of the mode register is transmitted in the first 8 beats (the first 4 clock cycles) of the target read clock signal RDQS, and the data that does not matter (MR Content) is transmitted in the last 8 beats (the last 4 clock cycles). Valid).
  • the read data signal DQ ⁇ 7:0> is latched using the signal edge of the read clock signal RDQS sent by the memory.
  • the first 4 clocks The data latched in cycles is MR Content, and the data Valid latched in the next four clock cycles are not used;
  • the read clock signal RDQS is in a floating Floating state, and the control
  • the first internal clock signal Internal CLK of the device 10 itself serves as the second read clock signal as the target read clock signal RDQS. Since the retention time of the read data signal is long enough, the control device 10 can use the first internal clock signal Internal CLK to read data.
  • Signal DQ ⁇ 7:0> is latched to obtain MR Content.
  • control device which is connected to a memory.
  • the control device includes: a receiving module configured to receive a read clock signal from the memory and output a read clock signal; and a clock module configured to generate a first internal clock signal; a selection module configured to receive a read clock signal and a first internal clock signal, and output one of the read clock signal and the first internal clock signal as a target read clock signal; a latch module configured to Receive the target read clock signal and the read data signal sent by the memory, and use the target read clock signal to latch the read data signal.
  • the control device can still latch the read data signal through the first internal clock signal, which not only improves the accuracy of data latch but also saves power consumption.
  • FIG. 7 shows a schematic structural diagram of a memory 20 provided by an embodiment of the present disclosure.
  • the memory 20 includes a clock processing circuit 21, and the memory 20 is connected to the control device 10; wherein,
  • the memory 20 is configured to determine the read data signal DQ based on the first read instruction when receiving the first read instruction, and determine the read clock signal RDQS through the clock processing circuit 21, and combine the read data signal DQ and the read clock signal RDQS. is sent to the control device 10; or, in the case of receiving the second read command, the read data signal DQ is determined based on the second read command, and the read data signal DQ is sent to the control device 10.
  • the first read instruction and the second read instruction are collectively referred to as data read instructions.
  • the read clock signal RDQS output by the memory 20 may be distorted, resulting in data latch failure.
  • the read clock signal RDQS is normal, the memory 20 provides the read data signal DQ and the normal read clock signal RDQS, and the control device 10 uses the read clock signal RDQS to process the read data signal DQ. Latch; for the second read command, the read clock signal RDQS may be distorted, and the memory 20 may only provide the read data signal DQ, so that the control device 10 uses the first internal clock signal Internal CLK generated by itself to lock the read data signal DQ. storage, thereby avoiding data latch failure and also saving current and power consumption.
  • the memory 20 is further configured to control the read clock signal RDQS to be in a floating state when receiving the first read instruction.
  • the memory 20 may disable the relevant control module of the read clock signal, that is, the read clock signal is in a floating state, and the memory 20 does not need to send the read clock signal RDQS to the control device 10, thereby saving current and power consumption.
  • clock processing circuit 21 includes:
  • the duty cycle module 211 is configured to receive an externally generated data clock signal; perform duty cycle adjustment on the data clock signal and output a second internal clock signal;
  • the clock generation module 212 is configured to receive a second internal clock signal and output a read clock signal RDQS based on the second internal clock signal; wherein the read clock signal RDQS is a pulse signal.
  • the read clock signal RDQS and the read data signal DQ are transmitted to the control device 10 via the hardware circuit, so that the control device 10 obtains the required parameters.
  • the duty cycle module 211 includes two parts.
  • the clock generation module 212 can be composed of a logic device and a delay unit to achieve delay matching and comply with the standard timing specified by the JEDEC standard.
  • the data clock signal WCK0 is an externally received write clock signal (denoted as WCK0 )
  • the second internal clock signal WCK1 is a duty cycle-adjusted write clock signal (denoted as WCK1 ) inside the memory 20 .
  • the clock processing circuit 21 further includes:
  • the detection module 213 is configured to receive the second internal clock signal WCK1, perform duty cycle detection on the second internal clock signal WCK1, and output the duty cycle parameter;
  • Mode register 214 configured to receive and store the duty cycle parameter
  • the second read instruction instructs to obtain the duty cycle parameter stored in the mode register, and the first read instruction refers to a data read instruction other than the second read instruction.
  • the detection module 213 may be composed of a logic gate, a transmission gate, a capacitor and a signal comparator.
  • duty cycle module 211 includes:
  • a receiver configured to receive and output the data clock signal WCK0 externally
  • the adjustment module is configured to adjust the duty cycle of the data clock signal WCK0 and output the second internal clock signal.
  • the adjustment module is used for duty cycle adjustment.
  • the default settings of the adjustment module will cause the duty cycle of the data clock signal WCK0 to increase by a certain value.
  • the upper limit of the duty cycle increase is 7 units (Step), which is 35 picoseconds. .
  • the adjustment module can be composed of cascaded delay units.
  • Each delay unit is composed of NMOS and PMOS, thereby realizing forward/backward adjustment of the rising edge of the data clock signal WCK0, and/or realizing the data clock.
  • the forward/backward adjustment of the falling edge in signal WCK0 ultimately adjusts the duty cycle of the data clock signal WCK0.
  • the duty cycle of the externally generated data clock signal WCK0 is 57%.
  • the duty cycle of the data clock signal WCK0 is increased by 7 units (35 picoseconds) by default. If The speed of the memory is 8633Mbps.
  • the duty cycle of the second internal clock signal WCK1 will continue to increase by 15% based on the data clock signal WCK0, that is, the duty cycle of the second internal clock signal WCK1 will be as high as 72%.
  • the control device 10 sends the second read command to the memory.
  • the memory 20 only needs to send the read data signal DQ to the control device 10.
  • the single memory 20 does not need to use the clock processing circuit 21 to generate the read clock signal RDQS.
  • Control The device 10 uses the first internal clock signal Internal CLK generated by itself to latch the read data signal DQ to obtain the correct duty cycle parameters and ensure the success of the duty cycle adjustment operation.
  • Embodiments of the present disclosure provide a memory, the memory includes a clock processing circuit, and the memory is connected to a control device; wherein the memory is configured to determine a read data signal based on the first read instruction when receiving a first read instruction, And determine the read clock signal through the clock processing circuit, and send the read data signal and the read clock signal to the control device; or, when receiving the second read instruction, determine the read data signal based on the second read instruction, and send the read data signal to the control device. Data signals are sent to the control device. In this way, for the second read instruction, the memory does not need to perform additional control on the read clock signal, and does not need to send the read clock signal to the control device. This not only avoids the adverse effects caused by the duty cycle distortion of the read clock signal, but also saves current and power consumption.
  • FIG. 11 shows a schematic flowchart of a signal processing method provided by an embodiment of the present disclosure. As shown in Figure 11, the method includes:
  • S301 Receive the read clock signal and read data signal sent by the memory, and determine the first internal clock signal generated by the control device.
  • S302 Determine one of the read clock signal and the first internal clock signal as the target read clock signal.
  • control device 10 can use the read clock signal RDQS obtained from the memory as the target read clock signal Sample CLK, or use the first internal clock signal Internal generated internally. CLK serves as the target read clock signal Sample CLK, thereby completing the latch processing of the read data signal DQ. In this way, when the clock signal in the memory has duty cycle distortion, the control device 10 can still latch the read data signal DQ through the first internal clock signal Internal CLK to ensure correct latching of data.
  • step S301 when the first internal clock signal is determined as the target read clock signal, the memory 20 may not send the read clock signal to the control device 10 to save energy. This solution is also Within the protection scope of the embodiments of the present disclosure.
  • the method before receiving the read clock signal and the read data signal sent by the memory, the method further includes:
  • the method further includes:
  • the read clock signal is determined as the target read clock signal; or, when the data read instruction is the second read instruction, the first internal clock signal is determined as the target read clock signal; wherein, the second read instruction indicates obtaining the duty cycle parameter stored in the mode register in the memory, and the first read instruction refers to a data read instruction other than the second read instruction.
  • the control device 10 when the data read command is the first read command, the control device 10 receives the read clock signal and the read data signal sent by the memory, and uses the read clock signal to perform latch processing on the read data signal; during the data read When the command is a second read command, the control device 10 receives the read clock signal sent by the memory, and the control device 10 determines the first internal clock signal generated by itself, and uses the first internal clock signal to latch the read data signal. deal with.
  • An embodiment of the present disclosure provides a signal processing method, which method includes: receiving a read clock signal sent by the memory, and determining the first internal clock signal generated by the control device; combining the read clock signal and the third One of the two internal clock signals is determined as the target read clock signal; the read data signal sent by the memory is received, and the read data signal is latched using the target read clock signal.
  • the control device can latch the read data signal through the first internal clock signal, which can not only improve the accuracy of data latching, but also save power consumption.
  • FIG. 12 shows a schematic flowchart of another signal processing method provided by an embodiment of the present disclosure. As shown in Figure 12, the method includes:
  • the first read command and the second read command are collectively referred to as data read commands.
  • the read clock signal RDQS is normal, and the memory 20 provides the read data signal DQ and the read clock signal RDQS, so that the control device 10 uses the read clock signal RDQS to read data.
  • the signal DQ is latched; in the scenario where the second read command is received, the read clock signal RDQS may be distorted, and the memory 20 only provides the read data signal DQ so that the control device 10 uses the first internal clock signal Internal CLK generated by itself.
  • the read data signal DQ is latched to avoid data latch failure.
  • the method further includes: when receiving the first read instruction, controlling the read clock signal to be in a floating state.
  • generating a read clock signal through a clock processing circuit in the memory includes:
  • the method further includes: performing duty cycle detection on the second internal clock signal to obtain a duty cycle parameter; storing the duty cycle parameter into a mode register; wherein the second read instruction indicates obtaining the mode register
  • the stored duty cycle parameter, the first read command refers to the data read command except the second read command.
  • An embodiment of the present disclosure provides a signal processing method, which method includes: when receiving a first read instruction, determining a read data signal based on the first read instruction, and generating it through a clock processing circuit in the memory. Read a clock signal, and send the read data signal and the read clock signal to the control device; or, in the case of receiving a second read instruction, determine the read data signal based on the second read instruction. , and sends the read data signal to the control device.
  • the memory does not need to generate a read clock signal, which not only avoids the adverse effects caused by duty cycle distortion of the read clock signal, but also saves current and power consumption.
  • FIG. 13 shows a schematic structural diagram of an electronic device 50 provided by an embodiment of the present disclosure.
  • the electronic device 50 at least includes the aforementioned control device 10 and the aforementioned memory 20 .
  • control device 10 may use the read clock signal obtained from the memory 20 as the target read clock signal, or use the first internal clock signal generated internally as the target read clock signal, thereby completing the reading of the data signal DQ. latch processing. In this way, when the clock signal in the memory has duty cycle distortion, the control device 10 can still latch the read data signal through the first internal clock signal, which not only improves the accuracy of data latching, but also saves power consumption.
  • Embodiments of the present disclosure provide a control device, a memory, a signal processing method and an electronic device.
  • the control device is connected to the memory.
  • the control device includes: a receiving module configured to receive a read clock signal from the memory and output the read clock signal; a clock module , configured to generate a first internal clock signal; the selection module is configured to receive a read clock signal and a first internal clock signal, and output one of the read clock signal and the first internal clock signal as a target read clock signal; latch The module is configured to receive a target read clock signal and a read data signal sent by the memory, and use the target read clock signal to latch the read data signal. In this way, when the clock signal in the memory has duty cycle distortion, the control device can still latch the read data signal through the first internal clock signal, which not only improves the accuracy of data latching, but also saves power consumption.

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Abstract

一种控制装置(10)、存储器(20)、信号处理方法和电子设备(50)，该控制装置(10)包括：接收模块(11)，配置为从存储器接收读时钟信号，输出读时钟信号；时钟模块(12)，配置为产生第一内部时钟信号；选择模块(13)，配置为接收读时钟信号和第一内部时钟信号，将读时钟信号和第一内部时钟信号的两者之一输出为目标读时钟信号；锁存模块(14)，配置为接收目标读时钟信号和存储器发送的读数据信号，利用目标读时钟信号对读数据信号进行锁存处理。

Description

一种控制装置、存储器、信号处理方法和电子设备
相关申请的交叉引用
本公开基于申请号为202210815505.8、申请日为2022年07月08日、发明名称为“一种控制装置、存储器、信号处理方法和电子设备”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体存储器技术领域，尤其涉及一种控制装置、存储器、信号处理方法和电子设备。
背景技术
在电子设备中，中央处理器(Central Processing Unit，CPU)向存储器发送读指令，然后接收存储器返回的读时钟信号和读数据信号，利用读时钟信号对读数据信号进行锁存处理，以便得到所需的数据。然而，在存储器对时钟信号进行占空比调整的过程中，中央处理器需要通过读取存储器中相应的模式寄存器获得时钟信号的占空比参数，然而这一过程中存储器内部的时钟信号可能是畸变的，进而存储器返回给中央控制器的读时钟信号也是畸变的，导致中央处理器获得错误的数据，最终导致时钟信号的占空比调整失败。
发明内容
本公开提供了一种控制装置、存储器、信号处理方法和电子设备，不仅能够提高数据锁存的正确性，还可以节省功耗。
本公开的技术方案是这样实现的：
第一方面，本公开实施例提供了一种控制装置，所述控制装置与存储器连接，所述控制装置包括：
接收模块，配置为从所述存储器接收读时钟信号，输出所述读时钟信 号；
时钟模块，配置为产生第一内部时钟信号；
选择模块，配置为接收所述读时钟信号和所述第一内部时钟信号，将所述读时钟信号和所述第一内部时钟信号的两者之一输出为目标读时钟信号；
锁存模块，配置为接收所述目标读时钟信号和所述存储器发送的读数据信号，利用所述目标读时钟信号对所述读数据信号进行锁存处理。
在一些实施例中，所述选择模块，具体配置为接收选择指示信号，在所述选择指示信号处于第一状态的情况下，将所述读时钟信号输出为所述目标读时钟信号；或者，在所述选择指示信号处于第二状态的情况下，将所述第一内部时钟信号输出为所述目标读时钟信号。
在一些实施例中，所述控制装置，还配置为向所述存储器发送数据读指令，以使得所述存储器产生所述读时钟信号和所述读数据信号。
在一些实施例中，所述控制装置，还配置为在所述数据读指令为第一读指令的情况下，将所述选择指示信号置为第一状态；或者，在所述数据读指令为第二读指令的情况下，将所述选择指示信号置为第二状态；其中，所述第二读指令指示获取所述存储器中模式寄存器存储的占空比参数，所述第一读指令是指除所述第二读指令之外的数据读取指令。
第二方面，本公开实施例提供了一种存储器，存储器包括时钟处理电路，且所述存储器与控制装置连接；其中，
所述存储器，配置为在接收到第一读指令的情况下，基于所述第一读指令确定读数据信号，并通过所述时钟处理电路确定读时钟信号，将所述读数据信号和所述读时钟信号共同发送至所述控制装置；或者，
在接收到第二读指令的情况下，基于所述第二读指令确定所述读数据信号，并将所述读数据信号发送至所述控制装置。
在一些实施例中，所述存储器，还配置为在接收到第二读指令的情况下，控制所述读时钟信号处于悬空状态。
在一些实施例中，所述时钟处理电路包括：占空比模块，配置为接收外部产生的数据时钟信号；对所述数据时钟信号进行占空比调节，输出第二内部时钟信号；时钟产生模块，配置为接收所述第二内部时钟信号，基 于所述第二内部时钟信号，输出所述读时钟信号；其中，所述读时钟信号为脉冲信号。
在一些实施例中，所述时钟处理电路还包括：检测模块，配置为接收所述第二内部时钟信号，对所述第二内部时钟信号进行占空比检测，输出占空比参数；模式寄存器，配置为接收并存储所述占空比参数；其中，所述第二读指令指示获取所述模式寄存器存储的占空比参数，所述第一读指令是指除所述第二读指令之外的数据读取指令。
在一些实施例中，所述占空比模块包括：接收器，配置为从外部接收并输出所述数据时钟信号；调节模块，配置为对所述数据时钟信号进行占空比调节，输出所述第二内部时钟信号。
在一些实施例中，所述数据时钟信号为写时钟信号。
第三方面，本公开实施例提供了一种信号处理方法，应用于控制装置，且所述控制装置与存储器连接，所述方法包括：
接收所述存储器发送的读时钟信号和读数据信号，确定所述控制装置产生的第一内部时钟信号；
将所述读时钟信号和所述第一内部时钟信号的两者之一确定为目标读时钟信号；
利用所述目标读时钟信号对所述读数据信号进行锁存处理。
在一些实施例中，在所述接收所述存储器发送的读时钟信号和读数据信号之前，所述方法还包括：
向所述存储器发送数据读指令，以使得所述存储器产生所述读时钟信号和所述读数据信号。
在一些实施例中，所述方法还包括：
在所述数据读指令为第一读指令的情况下，将所述读时钟信号确定为所述目标读时钟信号；或者，在所述数据读指令为第二读指令的情况下，将所述第一内部时钟信号确定为所述目标读时钟信号；其中，所述第二读指令指示获取所述存储器中模式寄存器存储的占空比参数，所述第一读指令是指除所述第二读指令之外的数据读取指令。
第四方面，本公开实施例提供了一种信号处理方法，应用于存储器，且所述存储器与控制装置连接，所述方法包括：
在接收到第一读指令的情况下，基于所述第一读指令确定读数据信号，并通过所述存储器中的时钟处理电路产生读时钟信号，将所述读数据信号和所述读时钟信号共同发送至所述控制装置；或者，在接收到第二读指令的情况下，基于所述第二读指令确定所述读数据信号，并将所述读数据信号发送至所述控制装置。
在一些实施例中，所述方法还包括：在接收到第一读指令的情况下，控制所述读时钟信号处于悬空状态。
在一些实施例中，所述通过所述存储器中的时钟处理电路产生读时钟信号，包括：
接收外部产生的数据时钟信号；对所述数据时钟信号进行占空比调节，输出第二内部时钟信号；基于所述第二内部时钟信号，产生所述读时钟信号；其中，所述读时钟信号为脉冲信号。
在一些实施例中，所述方法还包括：对所述第二内部时钟信号进行占空比检测，得到占空比参数；将所述占空比参数存储至模式寄存器中；其中，所述第二读指令指示获取所述模式寄存器存储的占空比参数，所述第一读指令是指除所述第二读指令之外的数据读取指令。
第五方面，本公开实施例提供了一种电子设备，所述电子设备至少包括如第一方面所述的控制装置和如第二方面所述的存储器。
本公开实施例提供了一种控制装置、存储器、信号处理方法和电子设备，该控制装置与存储器连接，控制装置包括：接收模块，配置为从存储器接收读时钟信号，输出读时钟信号；时钟模块，配置为产生第一内部时钟信号；选择模块，配置为接收读时钟信号和第一内部时钟信号，将读时钟信号和第一内部时钟信号的两者之一输出为目标读时钟信号；锁存模块，配置为接收目标读时钟信号和存储器发送的读数据信号，利用目标读时钟信号对读数据信号进行锁存处理。这样，在存储器中的时钟信号发生占空比畸变的情况下，控制装置仍然可以通过第一内部时钟信号锁存读数据信号，不仅能够提高数据锁存的正确性，还可以节省功耗。
附图说明
图1为MRR指令的操作时序示意图；
图2为一种时钟处理电路的结构示意图；
图3为一种读时钟信号的波形示意图；
图4为本公开实施例提供的一种控制装置的结构示意图；
图5为本公开实施例提供的另一种控制装置的结构示意图；
图6为本公开实施例提供的一种数据锁存处理的信号波形示意图；
图7为本公开实施例提供的一种存储器的结构示意图；
图8为本公开实施例提供的一种时钟处理电路的局部结构示意图一；
图9为本公开实施例提供的一种时钟处理电路的局部结构示意图二；
图10为本公开实施例提供的一种时钟处理电路的工作过程示意图；
图11为本公开实施例提供的一种信号处理方法的流程示意图；
图12为本公开实施例提供的另一种信号处理方法的流程示意图；
图13为本公开实施例提供的一种电子设备的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
DRAM(Dynamic Random Access Memory)：动态随机存取存储器
SDRAM(Synchronous Dynamic Random Access Memory)：同步动态 随机存储器
MRR(Mode Register Read)：模式寄存器读指令
Mbps(Million bits per second)：兆比特每秒
NMOS(N-Metal-Oxide-Semiconductor)：N型沟道场效应晶体管
PMOS(P-Metal-Oxide-Semiconductor)：N型沟道场效应晶体管
在存储器(例如DRAM)中，MRR指令和正常读指令采用完全一样的操作时序。参见图1，其示出了MRR指令的操作时序示意图。在图1中，T0、T1……用于标识不同的时钟周期，CK_c和CK_t是一对差分时钟信号，CS为片选信号，CA为命令地址信号，COMMAND指示操作指令，DQ[7:0]为8位存储器的数据信号，DQ[15:0]为16位存储器的数据信号，数据时钟信号WCK是电子设备的主机端(Host)发送给存储器的外部写时钟信号，在不同的电路位置可能表现为单个信号或者一对差分时钟信号WCK_c和WCK_t；读时钟信号RDQS是存储器向电子设备输出的时钟信号，在不同的电路位置可能表现为单个信号或者一对差分时钟信号RDQS_c和RDQS_t。具体来说，在存储器接收到CPU发送的MRR指令后，生成数据信号DQ(也可以称为读数据信号)，以及利用从外部接收的数据时钟信号产生读时钟信号。在数据读指令的执行过程中，存储器将读数据信号DQ和读时钟信号RDQS共同返回给CPU，然后CPU利用读时钟信号RDQS锁存读数据信号DQ，从而获得需要的数据。另外，图1为电子装置工程设计联合协会(JEDEC)标准规定的标准时序，其中各信号的含义、相关变化的原理以及未经提及的部分名词缩写均可参照行业标准文件JEDEC进行理解，且与本公开实施例的技术方案无关，不会影响技术人员对本公开实施例的理解，因此不作解释。
存储器中设置有时钟处理电路，用于对数据时钟信号WCK0(包括一对互补的信号WCK_c/WCK_t)的占空比进行调整，以使得数据时钟信号WCK0的占空比符合要求。参见图2，其示出了一种时钟处理电路的结构示意图。如图2所示，在时钟处理电路中，接收器用于从外部接收数据时钟信号WCK0，调节模块对数据时钟信号WCK进行占空比调整以得到第二内部时钟信号WCK1，检测模块用于检测第二内部时钟信号WCK1的占空比参数并将其存储在模式寄存器中。同时，在存储器进行占空比调整的过 程中，CPU发送MRR指令读取模式寄存器中的占空比参数，从而决定下一步的操作。在一种示例的情况中，如图2所示，外部输入的数据时钟信号WCK0的占空比为JEDEC规定的上限57％，在占空比调整的初始步骤中，占空比调节模块将数据时钟信号WCK0的占空比增加7个单位(JEDEC规定的上限，且每个单位为5皮秒)，即增加了35皮秒，相当于在8533Mbps的速度下将占空比增加15％，此时存储器中的第二内部时钟信号WCK1的占空比将高达72％，利用其产生的读时钟信号RDQS的占空比也将高达72％。此时，参见图3，其示出了一种读时钟信号的波形示意图。如图3所示，占空比高达72％的读时钟信号RDQS在经由电路模块进行传输过程中经过通道衰减，在到达CPU接收端时会严重畸变，导致很难被CPU正确识别，即MRR指令可能得到错误的数据，最终导致占空比调整失败。如果存储器的速度更高，这一问题将更加严重。
基于此，本公开实施例提供了一种控制装置，该控制装置与存储器连接，所述控制装置包括：接收模块，配置为从所述存储器接收读时钟信号，输出所述读时钟信号；时钟模块，配置为产生第一内部时钟信号；选择模块，配置为接收所述读时钟信号和所述第一内部时钟信号，将所述读时钟信号和所述第一内部时钟信号的两者之一输出为目标读时钟信号；锁存模块，配置为接收所述目标读时钟信号和所述存储器发送的读数据信号，利用所述目标读时钟信号对所述读数据信号进行锁存处理。这样，即使存储器中的时钟信号发生占空比畸变，控制装置仍然可以通过第一内部时钟信号锁存读数据信号，不仅能够提高数据锁存的正确性，还可以节省功耗。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图4，其示出了本公开实施例提供的一种控制装置10的结构示意图。如图4所示，控制装置10与存储器连接，控制装置10包括：
接收模块11，配置为从存储器接收读时钟信号，输出读时钟信号；
时钟模块12，配置为产生第一内部时钟信号；
选择模块13，配置为接收读时钟信号和第一内部时钟信号，将读时钟信号和第一内部时钟信号的两者之一输出为目标读时钟信号；
锁存模块14，配置为接收目标读时钟信号和存储器发送的读数据信号， 利用目标读时钟信号对读数据信号进行锁存处理。
需要说明的是，本公开实施例中，控制装置10可以是电子设备的CPU；存储器可以为多种类型的半导体存储器，例如DRAM、SDRAM、双倍速率DRAM、低功率双倍速率DRAM等。
在不同的工作场景下，控制装置10可以将从存储器获取的读时钟信号作为目标读时钟信号，或者将自身内部产生的第一内部时钟信号作为目标读时钟信号，从而完成读数据信号的锁存处理。这样，在存储器中的时钟信号发生占空比畸变的情况下，控制装置10仍然可以通过第一内部时钟信号锁存读数据信号，保证数据的正确锁存。
需要说明的是，接收模块11可以通过由NMOS和PMOS等器件构成的信号接收器实现，时钟模块12可以通过时钟发生器及传输门实现，选择模块13可以通过二选一数据选择器实现，锁存模块14可以通过D型触发器实现。
参见图5，其示出了本公开实施例提供的另一种控制装置10的结构示意图。在图5中，读时钟信号可以表示为RDQS，第一内部时钟信号可以表示为Internal CLK，目标读时钟信号可以表示为Sample CLK，读数据信号可以表示为DQ。
在一些实施例中，如图5所示，选择模块13，具体配置为接收选择指示信号，在选择指示信号处于第一状态的情况下，将读时钟信号RDQS输出为目标读时钟信号Sample CLK；或者，在选择指示信号处于第二状态的情况下，将第一内部时钟信号Internal CLK输出为目标读时钟信号Sample CLK。
在这里，选择模块13可以为二选一数据选择器，从而根据选择指示信号的状态输出读时钟信号RDQS或者第一内部时钟信号Internal CLK。
在一些实施例中，锁存模块14的时钟端与选择模块13的输出端连接，锁存模块14的输入端接收读数据信号DQ，锁存模块14的输出端输出采样后的数据信号，以送入控制装置10的后续电路进行处理。
在一些实施例中，控制装置10，还配置为向存储器发送数据读指令，以使得存储器产生读时钟信号RDQS和读数据信号DQ。
在一些实施例中，控制装置10，还配置为在数据读指令为第一读指令 的情况下，将选择指示信号置为第一状态；或者，在数据读指令为第二读指令的情况下，将选择指示信号置为第二状态。
需要说明的是，将数据读指令划分为两种类型：第一读指令和第二读指令。其中，第二读指令指示获取存储器中模式寄存器存储的占空比参数，第一读指令是指除第二读指令之外的数据读取指令。
如前述，在数据读指令用于读取占空比参数的情况下，存储器可能处于占空比调整的过程中，在某些情况下存储器中的时钟信号(即第二内部时钟信号WCK1)已经发生畸变，例如图2中的第二内部时钟信号WCK1的占空比可能高达72％，此时存储器输出的读时钟信号RDQS也将发生畸变，控制装置10利用读时钟信号RDQS对读数据信号DQ进行锁存可能会得到错误结果。对于本公开实施例来说，在数据读指令用于读取占空比参数的情况下，将控制装置10自身产生的第一内部时钟信号Internal CLK作为目标读时钟信号，由于第一内部时钟信号Internal CLK并不会受到第二内部时钟信号WCK1的占空比畸变的影响，因此CPU可以利用第一内部时钟信号Internal CLK的电平变化沿对读数据信号进行锁存，从而获得正确的占空比参数。
另外，为了节约功耗，在数据读指令为第一读指令的情况下，存储器的读时钟信号RDQS并不具有实际作用，因此存储器可以控制读时钟信号RDQS处于悬空Floating状态，且存储器无需向控制装置10发送读时钟信号RDQS，以节省电流。
以下以DRAM的突发长度为16，且具有16个DQ端作为示例，说明读数据信号的锁存过程。
针对第二读指令，读数据信号DQ的前8位携带有效数据，表示为DQ<7:0>。根据行业协议的规定，在目标读时钟信号RDQS的前8拍(前4个时钟周期)传输模式寄存器的参数值(MR Content)，后8拍(后4个时钟周期)传输不关心的数据(Valid)。
也就是说，如图6中的(1)所示，针对第一读指令，利用存储器发送的读时钟信号RDQS的信号沿对读数据信号DQ<7:0>进行锁存，前4个时钟周期锁存的数据为MR Content，后4个时钟周期锁存的数据Valid不作使用；如图6中的(2)所示，针对第二读指令，读时钟信号RDQS为悬空 Floating状态，利用控制装置10自身的第一内部时钟信号Internal CLK作为第二读时钟信号作为目标读时钟信号RDQS，由于读数据信号的保持时间足够长，所以控制装置10可以利用第一内部时钟信号Internal CLK对读数据信号DQ<7:0>进行锁存，得到MR Content。
综上所述，本公开实施例提供了一种控制装置，该控制装置与存储器连接，控制装置包括：接收模块，配置为从存储器接收读时钟信号，输出读时钟信号；时钟模块，配置为产生第一内部时钟信号；选择模块，配置为接收读时钟信号和第一内部时钟信号，将读时钟信号和第一内部时钟信号的两者之一输出为目标读时钟信号；锁存模块，配置为接收目标读时钟信号和存储器发送的读数据信号，利用目标读时钟信号对读数据信号进行锁存处理。这样，即使存储器中的时钟信号发生占空比畸变，控制装置仍然可以通过第一内部时钟信号锁存读数据信号，不仅能够提高数据锁存的正确性，还可以节省功耗。
在另一实施例中，参见图7，其示出了本公开实施例提供的一种存储器20的结构示意图。如图7所示，存储器20包括时钟处理电路21，且存储器20与控制装置10连接；其中，
存储器20，配置为在接收到第一读指令的情况下，基于第一读指令确定读数据信号DQ，并通过时钟处理电路21确定读时钟信号RDQS，将读数据信号DQ和读时钟信号RDQS共同发送至控制装置10；或者，在接收到第二读指令的情况下，基于第二读指令确定读数据信号DQ，并将读数据信号DQ发送至控制装置10。
应理解，在图7中，第一读指令和第二读指令统称为数据读指令。
需要说明的是，在存储器20对时钟信号进行占空比调节的过程中，其输出的读时钟信号RDQS可能是畸变的，从而导致数据锁存失败。在本公开实施例中，针对第一读指令，读时钟信号RDQS是正常的，存储器20提供读数据信号DQ和正常的读时钟信号RDQS，控制装置10利用读时钟信号RDQS对读数据信号DQ进行锁存；针对第二读指令，读时钟信号RDQS可能是畸变的，存储器20可以仅提供读数据信号DQ，以便控制装置10利用自身产生的第一内部时钟信号Internal CLK对读数据信号DQ进行锁存，从而避免数据锁存失败，而且还节省了电流和功耗。
在一些实施例中，存储器20，还配置为在接收到第一读指令的情况下，控制读时钟信号RDQS处于悬空状态。
这样，针对第二读指令，存储器20可以不使能读时钟信号的相关控制模块，即读时钟信号处于悬空Floating状态，而且存储器20无需将读时钟信号RDQS发送给控制装置10，从而节省电流和功耗。
在一些实施例中，如图8所示，时钟处理电路21包括：
占空比模块211，配置为接收外部产生的数据时钟信号；对数据时钟信号进行占空比调节，输出第二内部时钟信号；
时钟产生模块212，配置为接收第二内部时钟信号，基于第二内部时钟信号，输出读时钟信号RDQS；其中，读时钟信号RDQS为脉冲信号。
这样，针对第一读指令，读时钟信号RDQS和读数据信号DQ经由硬件电路传输到控制装置10，以便控制装置10获取需要的参数。
需要说明的是，占空比模块211包括两个部分，具体实现可以参见后续描述；时钟产生模块212可以由逻辑器件和延迟单元构成，以实现延迟匹配且符合JEDEC标准规定的标准时序。
在一些实施例中，数据时钟信号WCK0为从外部接收的写时钟信号(表示为WCK0)，第二内部时钟信号WCK1为存储器20内部经过占空比调整的写时钟信号(表示为WCK1)。
在一些实施例中，如图9所示，时钟处理电路21还包括：
检测模块213，配置为接收第二内部时钟信号WCK1，对第二内部时钟信号WCK1进行占空比检测，输出占空比参数；
模式寄存器214，配置为接收并存储占空比参数；
其中，第二读指令指示获取模式寄存器存储的占空比参数，第一读指令是指除第二读指令之外的数据读取指令。
需要说明的是，检测模块213可以由逻辑门、传输门、电容以及信号比较器构成。
在一些实施例中，占空比模块211包括：
接收器，配置为从外部接收并输出数据时钟信号WCK0；
调节模块，配置为对数据时钟信号WCK0进行占空比调节，输出第二内部时钟信号。
需要说明的是，调节模块用于占空比调节。在占空比调节开始时，调节模块的默认设置会导致数据时钟信号WCK0的占空比增加一定值，根据JEDEC的规定，占空比增加的上限为7个单位(Step)，即35皮秒。
需要说明的是，调节模块可以通过级联的延迟单元组成，每个延迟单元由NMOS和PMOS构成，从而实现数据时钟信号WCK0中上升沿的向前/向后调整，和/或，实现数据时钟信号WCK0中下降沿的向前/向后调整，最终调整数据时钟信号WCK0的占空比。
以下提供一种可能出现的工作场景，对本公开实施例的技术效果进行说明。请参见图10，外部产生的数据时钟信号WCK0的占空比为57％，在占空比调节过程开始时，默认将数据时钟信号WCK0的占空比增加7个单位(35皮秒)，如果存储器的速度为8633Mbps，此时第二内部时钟信号WCK1的占空比将在数据时钟信号WCK0的基础上继续增加15％，即第二内部时钟信号WCK1的占空比将高达72％。在这种情况下，控制装置10向存储器发送第二读指令，存储器20仅需要将读数据信号DQ发送给控制装置10，单存储器20并不需要利用时钟处理电路21产生读时钟信号RDQS，控制装置10利用自身产生的第一内部时钟信号Internal CLK对将读数据信号DQ进行锁存，获得正确的占空比参数，保证占空比调整操作的成功。
本公开实施例提供了一种存储器，存储器包括时钟处理电路，且存储器与控制装置连接；其中，存储器，配置为在接收到第一读指令的情况下，基于第一读指令确定读数据信号，并通过时钟处理电路确定读时钟信号，将读数据信号和读时钟信号共同发送至控制装置；或者，在接收到第二读指令的情况下，基于第二读指令确定读数据信号，并将读数据信号发送至控制装置。这样，对于第二读指令，存储器无需对读时钟信号进行额外控制，而且无需将读时钟信号发送给控制装置，不仅可以避免读时钟信号的占空比畸变带来的不利影响，而且节省电流和功耗。
在本公开的又一实施例中，参见图11，其示出了本公开实施例提供的一种信号处理方法的流程示意图。如图11所示，该方法包括：
S301：接收存储器发送的读时钟信号和读数据信号，确定控制装置产生的第一内部时钟信号。
S302：将读时钟信号和第一内部时钟信号的两者之一确定为目标读时 钟信号。
S303：利用目标读时钟信号对读数据信号进行锁存处理。
需要说明的是，该方法应用于前述的控制装置10，且控制装置10与存储器20连接。结合图4和图5可以看出，在不同的工作场景下，控制装置10可以将从存储器获取的读时钟信号RDQS作为目标读时钟信号Sample CLK，或者将自身内部产生的第一内部时钟信号Internal CLK作为目标读时钟信号Sample CLK，从而完成读数据信号DQ的锁存处理。这样，在存储器中的时钟信号发生占空比畸变的情况下，控制装置10仍然可以通过第一内部时钟信号Internal CLK锁存读数据信号DQ，保证数据的正确锁存。
需要说明说明的是，在步骤S301中，在将第一内部时钟信号确定为目标读时钟信号的情况下，存储器20也可以不向控制装置10发送读时钟信号，以节省能源，该方案也在本公开实施例的保护范围之内。
在一些实施例中，在接收存储器发送的读时钟信号和读数据信号之前，该方法还包括：
向存储器发送数据读指令，以使得存储器产生读时钟信号和读数据信号。
在一些实施例中，该方法还包括：
在数据读指令为第一读指令的情况下，将读时钟信号确定为目标读时钟信号；或者，在数据读指令为第二读指令的情况下，将第一内部时钟信号确定为目标读时钟信号；其中，第二读指令指示获取存储器中模式寄存器存储的占空比参数，第一读指令是指除第二读指令之外的数据读取指令。
也就是说，在数据读指令为第一读指令的情况下，控制装置10接收存储器发送的读时钟信号和读数据信号，利用所述读时钟信号对读数据信号进行锁存处理；在数据读指令为第二读指令的情况下，控制装置10接收存储器发送的读时钟信号，且控制装置10确定自身产生的第一内部时钟信号，利用所述第一内部时钟信号对读数据信号进行锁存处理。
本公开实施例提供了一种信号处理方法，该方法包括：接收所述存储器发送的读时钟信号，并确定所述控制装置产生的第一内部时钟信号；将所述读时钟信号和所述第一内部时钟信号的两者之一确定为目标读时钟信号；接收所述存储器发送的读数据信号，利用所述目标读时钟信号对所述 读数据信号进行锁存处理。这样，在存储器中的时钟信号发生占空比畸变的情况下，控制装置可以通过第一内部时钟信号锁存读数据信号，不仅能够提高数据锁存的正确性，还可以节省功耗。
在本公开的再一实施例中，参见图12，其示出了本公开实施例提供的另一种信号处理方法的流程示意图。如图12所示，该方法包括：
S401：在接收到第一读指令的情况下，基于第一读指令确定读数据信号，并通过存储器中的时钟处理电路产生读时钟信号，将读数据信号和读时钟信号共同发送至控制装置。
S402：在接收到第二读指令的情况下，基于第二读指令确定读数据信号，并将读数据信号发送至控制装置。
需要说明的是，该方法应用于前述的存储器20，且存储器20与控制装置10连接。在图12中，第一读指令和第二读指令统称为数据读指令。对于存储器20来说，在接收到第一读指令的场景下，读时钟信号RDQS是正常的，存储器20提供读数据信号DQ和读时钟信号RDQS，以便控制装置10利用读时钟信号RDQS对读数据信号DQ进行锁存；在接收到第二读指令的场景下，读时钟信号RDQS可能是畸变的，存储器20仅提供读数据信号DQ，以便控制装置10利用自身产生的第一内部时钟信号Internal CLK对读数据信号DQ进行锁存，从而避免数据锁存失败。
在一些实施例中，该方法还包括：在接收到第一读指令的情况下，控制读时钟信号处于悬空Floating状态。
在一些实施例中，所述通过存储器中的时钟处理电路产生读时钟信号，包括：
接收外部产生的数据时钟信号；对数据时钟信号进行占空比调节，输出第二内部时钟信号；基于第二内部时钟信号，产生读时钟信号；其中，读时钟信号为脉冲信号。
在一些实施例中，该方法还包括：对第二内部时钟信号进行占空比检测，得到占空比参数；将占空比参数存储至模式寄存器中；其中，第二读指令指示获取模式寄存器存储的占空比参数，第一读指令是指除第二读指令之外的数据读取指令。
本公开实施例提供了一种信号处理方法，该方法包括：在接收到第一 读指令的情况下，基于所述第一读指令确定读数据信号，并通过所述存储器中的时钟处理电路产生读时钟信号，将所述读数据信号和所述读时钟信号共同发送至所述控制装置；或者，在接收到第二读指令的情况下，基于所述第二读指令确定所述读数据信号，并将所述读数据信号发送至所述控制装置。这样，对于第二读指令，存储器无需产生读时钟信号，不仅可以避免读时钟信号的占空比畸变带来的不利影响，而且节省电流和功耗。
在本公开的又一实施例中，参见图13，其示出了本公开实施例提供的一种电子设备50组成结构示意图。如图13所示，电子设备50至少包括前述的控制装置10和前述的存储器20。
在不同的工作场景下，控制装置10可以将从存储器20获取的读时钟信号作为目标读时钟信号，或者将自身内部产生的第一内部时钟信号作为目标读时钟信号，从而完成读数据信号DQ的锁存处理。这样，在存储器中的时钟信号发生占空比畸变的情况下，控制装置10仍然可以通过第一内部时钟信号锁存读数据信号，不仅能够提高数据锁存的正确性，还可以节省功耗。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围 之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种控制装置、存储器、信号处理方法和电子设备，该控制装置与存储器连接，控制装置包括：接收模块，配置为从存储器接收读时钟信号，输出读时钟信号；时钟模块，配置为产生第一内部时钟信号；选择模块，配置为接收读时钟信号和第一内部时钟信号，将读时钟信号和第一内部时钟信号的两者之一输出为目标读时钟信号；锁存模块，配置为接收目标读时钟信号和存储器发送的读数据信号，利用目标读时钟信号对读数据信号进行锁存处理。这样，在存储器中的时钟信号发生占空比畸变的情况下，控制装置仍然可以通过第一内部时钟信号锁存读数据信号，不仅能够提高数据锁存的正确性，还可以节省功耗。

Claims (18)

  1. 一种控制装置，所述控制装置与存储器连接，所述控制装置包括：
    接收模块，配置为从所述存储器接收读时钟信号，输出所述读时钟信号；
    时钟模块，配置为产生第一内部时钟信号；
    选择模块，配置为接收所述读时钟信号和所述第一内部时钟信号，将所述读时钟信号和所述第一内部时钟信号的两者之一输出为目标读时钟信号；
    锁存模块，配置为接收所述目标读时钟信号和所述存储器发送的读数据信号，利用所述目标读时钟信号对所述读数据信号进行锁存处理。
  2. 根据权利要求1所述的控制装置，其中，
    所述选择模块，具体配置为接收选择指示信号，在所述选择指示信号处于第一状态的情况下，将所述读时钟信号输出为所述目标读时钟信号；或者，在所述选择指示信号处于第二状态的情况下，将所述第一内部时钟信号输出为所述目标读时钟信号。
  3. 根据权利要求2所述的控制装置，其中，
    所述控制装置，还配置为向所述存储器发送数据读指令，以使得所述存储器产生所述读时钟信号和所述读数据信号。
  4. 根据权利要求3所述的控制装置，其中，
    所述控制装置，还配置为在所述数据读指令为第一读指令的情况下，将所述选择指示信号置为第一状态；或者，在所述数据读指令为第二读指令的情况下，将所述选择指示信号置为第二状态；
    其中，所述第二读指令指示获取所述存储器中模式寄存器存储的占空比参数，所述第一读指令是指除所述第二读指令之外的数据读取指令。
  5. 一种存储器，所述存储器包括时钟处理电路，且所述存储器与控制装置连接；其中，
    所述存储器，配置为在接收到第一读指令的情况下，基于所述第一读指令确定读数据信号，并通过所述时钟处理电路确定读时钟信号，将所述读数据信号和所述读时钟信号共同发送至所述控制装置；或者，
    在接收到第二读指令的情况下，基于所述第二读指令确定所述读数据信号，并将所述读数据信号发送至所述控制装置。
  6. 根据权利要求5所述的存储器，其中，
    所述存储器，还配置为在接收到第二读指令的情况下，控制所述读时钟信号处于悬空状态。
  7. 根据权利要求5所述的存储器，其中，所述时钟处理电路包括：
    占空比模块，配置为接收外部产生的数据时钟信号；对所述数据时钟信号进行占空比调节，输出第二内部时钟信号；
    时钟产生模块，配置为接收所述第二内部时钟信号，基于所述第二内部时钟信号，输出所述读时钟信号；其中，所述读时钟信号为脉冲信号。
  8. 根据权利要求7所述的存储器，其中，所述时钟处理电路还包括：
    检测模块，配置为接收所述第二内部时钟信号，对所述第二内部时钟信号进行占空比检测，输出占空比参数；
    模式寄存器，配置为接收并存储所述占空比参数；
    其中，所述第二读指令指示获取所述模式寄存器存储的占空比参数，所述第一读指令是指除所述第二读指令之外的数据读取指令。
  9. 根据权利要求7所述的存储器，其中，所述占空比模块包括：
    接收器，配置为从外部接收并输出所述数据时钟信号；
    调节模块，配置为对所述数据时钟信号进行占空比调节，输出所述第二内部时钟信号。
  10. 根据权利要求5-9任一项所述的存储器，其中，所述数据时钟信号为写时钟信号。
  11. 一种信号处理方法，应用于控制装置，且所述控制装置与存储器连接，所述方法包括：
    接收所述存储器发送的读时钟信号和读数据信号，确定所述控制装置产生的第一内部时钟信号；
    将所述读时钟信号和所述第一内部时钟信号的两者之一确定为目标读时钟信号；
    利用所述目标读时钟信号对所述读数据信号进行锁存处理。
  12. 根据权利要求11所述的信号处理方法，其中，在所述接收所述存储 器发送的读时钟信号和读数据信号之前，所述方法还包括：
    向所述存储器发送数据读指令，以使得所述存储器产生所述读时钟信号和所述读数据信号。
  13. 根据权利要求12所述的信号处理方法，其中，所述方法还包括：
    在所述数据读指令为第一读指令的情况下，将所述读时钟信号确定为所述目标读时钟信号；或者，在所述数据读指令为第二读指令的情况下，将所述第一内部时钟信号确定为所述目标读时钟信号；
    其中，所述第二读指令指示获取所述存储器中模式寄存器存储的占空比参数，所述第一读指令是指除所述第二读指令之外的数据读取指令。
  14. 一种信号处理方法，应用于存储器，且所述存储器与控制装置连接，所述方法包括：
    在接收到第一读指令的情况下，基于所述第一读指令确定读数据信号，并通过所述存储器中的时钟处理电路产生读时钟信号，将所述读数据信号和所述读时钟信号共同发送至所述控制装置；或者，
    在接收到第二读指令的情况下，基于所述第二读指令确定所述读数据信号，并将所述读数据信号发送至所述控制装置。
  15. 根据权利要求14所述的信号处理方法，其中，所述方法还包括：
    在接收到第一读指令的情况下，控制所述读时钟信号处于悬空状态。
  16. 根据权利要求14所述的信号处理方法，其中，所述通过所述存储器中的时钟处理电路产生读时钟信号，包括：
    接收外部产生的数据时钟信号；
    对所述数据时钟信号进行占空比调节，输出第二内部时钟信号；
    基于所述第二内部时钟信号，产生所述读时钟信号；其中，所述读时钟信号为脉冲信号。
  17. 根据权利要求16所述的信号处理方法，其中，所述方法还包括：
    对所述第二内部时钟信号进行占空比检测，得到占空比参数；
    将所述占空比参数存储至模式寄存器中；
    其中，所述第二读指令指示获取所述模式寄存器存储的占空比参数，所述第一读指令是指除所述第二读指令之外的数据读取指令。
  18. 一种电子设备，所述电子设备包括如权利要求1-4任一项所述的控 制装置和如权利要求5-10任一项所述的存储器。
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