WO2024073909A1 - 一种延时控制电路、方法和半导体存储器 - Google Patents

一种延时控制电路、方法和半导体存储器 Download PDF

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WO2024073909A1
WO2024073909A1 PCT/CN2022/127103 CN2022127103W WO2024073909A1 WO 2024073909 A1 WO2024073909 A1 WO 2024073909A1 CN 2022127103 W CN2022127103 W CN 2022127103W WO 2024073909 A1 WO2024073909 A1 WO 2024073909A1
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signal
delay
module
target
decoding
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PCT/CN2022/127103
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English (en)
French (fr)
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黄泽群
孙凯
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长鑫存储技术有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a delay control circuit, method and semiconductor memory.
  • DDR double data rate
  • DRAM Dynamic Random Access Memory
  • ECS Error Check and Scrub
  • DRAM requires different commands to implement different functions, and there are timing requirements between different commands generated internally. However, in actual applications, the timing between different commands may not meet the timing conditions, affecting the performance of the memory.
  • Embodiments of the present disclosure provide a delay control circuit, method and semiconductor memory.
  • an embodiment of the present disclosure provides a delay control circuit, including a decoding module and a delay module, wherein:
  • the decoding module is configured to receive a mode register signal, perform decoding processing on the mode register signal, and generate at least one decoding signal;
  • the delay module includes at least one delay sub-module, which is configured to determine a selected target delay module from the at least one delay sub-module according to the at least one decoding signal, and to perform delay processing on the received initial command signal according to the target delay module and an external clock signal to obtain a target command signal; wherein the time interval between the target command signal and the initial command signal satisfies a preset timing condition.
  • the decoding module is specifically configured to decode the mode register signal to determine a delay time interval; and generate at least one decoding signal based on the delay time interval; wherein there is a corresponding relationship between the delay time interval and the clock frequency of the external clock signal.
  • the number of the at least one delay submodule is N, where N is an integer greater than 0, wherein:
  • the first input terminal of each delay submodule is connected to the initial command signal
  • the second input end of the delay submodule is connected to the ground signal, and the output end of the delay submodule is used to output the target command signal;
  • the second input end of the 1st delay submodule is connected to the ground signal
  • the second input end of the i-th delay submodule is connected to the output end of the i-1th delay submodule
  • the output end of the N-th delay submodule is used to output the target command signal, where i is an integer greater than 1 and less than or equal to N.
  • the decoding module is further configured to, in the process of generating the at least one decoding signal, if the j-th decoding signal is a first value, determine that all other decoding signals except the j-th decoding signal are second values; wherein the first value is different from the second value, and j is an integer greater than 0 and less than or equal to N.
  • the delay module is configured to, when the value of the j-th decoding signal is the first value, determine the j-th delay sub-module to the N-th delay sub-module as the target delay module; and to delay the initial command signal through the j-th delay sub-module to obtain the target command signal.
  • the j-th delay submodule includes a j-th selection module and a j-th shift register module, and the first input end of the j-th selection module is used to receive the initial command signal, the second input end of the j-th selection module is used to receive the first input signal, and the output end of the j-th selection module is connected to the input end of the j-th shift register module, wherein:
  • the j-th selection module is configured to receive the j-th decoding signal, and select a j-th target input signal from the initial command signal and the first input signal according to the j-th decoding signal;
  • the j-th shift register module is configured to receive the external clock signal and the j-th target input signal, and perform delay processing on the j-th target input signal according to the external clock signal to obtain a j-th target output signal;
  • the first input signal when j is equal to 1, the first input signal is the ground signal; when j is greater than 1 and less than or equal to N, the first input signal is the j-1th target output signal output by the j-1th shift register module; and, when j is equal to N, the Nth target output signal is the target command signal.
  • the j-th shift register module includes M shift registers, a clock terminal of each shift register is connected to the external clock signal, and M is an integer greater than 0, wherein:
  • the input end of the first shift register is connected to the output end of the j-th selection module, and the output end of the first shift register is used to output the j-th target output signal;
  • the input end of the first shift register is connected to the output end of the j-th selection module, the input end of the y-th shift register is connected to the output end of the y-1-th shift register, and the output end of the M-th shift register is used to output the j-th target output signal; wherein y is an integer greater than 1 and less than or equal to M.
  • the shift register is used to delay the signal received at the input end of the shift register by a first clock cycle for output.
  • the shift register includes L flip-flops, and the L flip-flops are connected in series, where L is an integer greater than 0, wherein:
  • the clock terminals of the L flip-flops are all connected to the external clock signal, and the output terminal of the flip-flop is connected to the input terminal of the next flip-flop.
  • the initial command signal includes an activation signal and the target command signal includes a read signal; or, the initial command signal includes a read signal and the target command signal includes a write signal; or, the initial command signal includes a write signal and the target command signal includes a pre-charge signal.
  • the delay control circuit further includes a buffer module, wherein:
  • the buffer module is configured to receive an error check and clear (ECS) signal and generate the initial command signal according to the ECS signal.
  • ECS error check and clear
  • the ECS signal supports the following two operation modes: a manual ECS operation mode based on an MPC command and an automatic ECS operation mode based on a self-refresh command.
  • an embodiment of the present disclosure provides a delay control method, which is applied to the delay control circuit described in the first aspect, and the method includes:
  • the time interval between the target command signal and the initial command signal meets a preset timing condition.
  • an embodiment of the present disclosure provides a semiconductor memory, comprising the delay control circuit as described in the first aspect.
  • the semiconductor memory includes a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the embodiments of the present disclosure provide a delay control circuit, method and semiconductor memory, wherein the delay control circuit includes a decoding module and a delay module, wherein: the decoding module is configured to receive a mode register signal, decode the mode register signal, and generate at least one decoding signal; the delay module includes at least one delay sub-module, configured to determine a selected target delay module from at least one delay sub-module according to at least one decoding signal, delay the received initial command signal according to the target delay module and an external clock signal, and obtain a target command signal; wherein the time interval between the target command signal and the initial command signal meets a preset timing condition.
  • At least one decoding signal can be generated based on the mode register signal, and then the target delay module is determined based on the at least one decoding signal. Then, based on the target delay module, the initial command signal is delayed by the external clock signal to obtain the target command signal. At this time, the time interval between the target command signal and the initial command signal meets the preset timing conditions. In this way, the delay control circuit can meet the timing control requirements between the self-generated commands inside the memory.
  • the target delay module corresponding to the clock frequency of the external clock signal can also be selected, so that under different clock frequencies, the time intervals between the command signals meet the preset timing conditions, thereby improving the performance of the memory.
  • FIG1 is a schematic diagram of a timing relationship between command signals
  • FIG2 is a schematic diagram of the structure of a delay control circuit provided in an embodiment of the present disclosure.
  • FIG3 is a schematic diagram of the composition structure of another delay control circuit provided in an embodiment of the present disclosure.
  • FIG4 is a schematic diagram of a specific structure of a delay control circuit provided by an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of the specific structure of another delay control circuit provided by an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of a specific structure of a shift register provided by an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of a specific structure of a delay module provided in an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of a signal timing sequence provided by an embodiment of the present disclosure.
  • FIG9 is another signal timing diagram provided by an embodiment of the present disclosure.
  • FIG10 is a schematic flow chart of a delay control method provided in an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that “first ⁇ second ⁇ third” can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.
  • FIG. 1 is a schematic diagram of the timing relationship between some command signals specified by the Joint Electron Device Engineering Council (JEDEC).
  • JEDEC Joint Electron Device Engineering Council
  • the order of self-generated command signals in DRAM is activation signal (Active, ACT), read operation signal or simply read signal (Read, RD), write operation signal or simply write signal (Write, WR) and precharge signal (Precharge, PRE), tRCD represents the time interval between ACT and RD (or “delay time”, “delay time”), WL represents the time interval between RD and WR, and tWR represents the time interval between WR and PRE. Since all command signals are internally self-generated commands, DRAM needs to internally control the timing from ACT to RD and other command signals. For example, in some memories, tRCD needs to meet 15 nanoseconds (ns). However, since the registers inside the DRAM do not record the values of tRCD, etc., it is impossible to directly implement the timing control from ACT to RD and other commands through clock shifting.
  • an embodiment of the present disclosure provides a delay control circuit, including: a decoding module and a delay module, wherein: the decoding module is configured to receive a mode register signal, decode the mode register signal, and generate at least one decoding signal; the delay module includes at least one delay sub-module, configured to determine a selected target delay module from at least one delay sub-module according to at least one decoding signal, and delay the received initial command signal according to the target delay module and an external clock signal to obtain a target command signal; wherein the time interval between the target command signal and the initial command signal meets a preset timing condition.
  • the decoding module is configured to receive a mode register signal, decode the mode register signal, and generate at least one decoding signal
  • the delay module includes at least one delay sub-module, configured to determine a selected target delay module from at least one delay sub-module according to at least one decoding signal, and delay the received initial command signal according to the target delay module and an external clock signal to obtain a target command signal; wherein the time interval between the
  • the initial command signal is delayed by the external clock signal to obtain the target command signal.
  • the time interval between the target command signal and the initial command signal meets the preset timing conditions.
  • the delay control circuit can meet the timing control requirements between the self-generated commands inside the memory.
  • the target delay module corresponding to the clock frequency of the external clock signal can also be selected, so that under different clock frequencies, the time intervals between the command signals meet the preset timing conditions, thereby improving the performance of the memory.
  • the delay control circuit 10 may include a decoding module 11 and a delay module 12, wherein:
  • the decoding module 11 is configured to receive the mode register signal, decode the mode register signal, and generate at least one decoding signal;
  • the delay module 12 includes at least one delay sub-module, and the delay module 12 is configured to determine a selected target delay module from at least one delay sub-module according to at least one decoding signal, and perform delay processing on the received initial command signal according to the target delay module and the external clock signal to obtain a target command signal; wherein the time interval between the target command signal and the initial command signal meets a preset timing condition.
  • the embodiments of the present disclosure relate to timing-related circuits between command signals generated internally in the integrated circuit design of semiconductors, and particularly to DRAM chips.
  • DRAMs require different command signals to implement different functions, and there are timing requirements between different command signals generated internally.
  • the delay control circuit 10 is used to meet the timing requirements of command signals generated internally at different frequencies. It can be applied to the timing control circuit between the activation signal and the read signal when the DRAM chip performs manual ECS operation or automatic ECS operation, but it is not limited to this scope. Other timing-related circuits between different commands generated internally can be implemented using the delay control circuit 10.
  • the decoding module 11 receives the mode register signal, and decodes the mode register signal to generate at least one decoding signal, and the number of the at least one decoding signal may be N, such as decoding signal 1, decoding signal 2 ... decoding signal N in FIG2 , where N is an integer greater than 0.
  • the delay module 12 includes at least one delay submodule, and the number of the at least one delay submodule is also N, such as delay submodule 1, delay submodule 2 ... delay submodule N shown in FIG2 .
  • the delay module 12 is connected to the decoding module 11.
  • the delay module 12 receives at least one decoding signal and determines a plurality of delay sub-modules from at least one delay sub-module as target delay modules according to the at least one decoding signal.
  • the target delay module performs delay processing on the initial command signal to obtain a target command signal.
  • the embodiments of the present disclosure can be applied to the timing control between command signals in a memory such as a DRAM.
  • the initial command signal is used to perform a first operation
  • the target command signal is used to perform a second operation.
  • the specific operation is related to the type of the command signal.
  • the embodiments of the present disclosure can be applied to the timing control between ACT and RD, or between RD and WR, or between WR and PRE, which are generated internally when a DRAM chip performs a manual ECS operation or an automatic ECS operation.
  • the initial command signal may include an activation signal
  • the target command signal may include a read signal
  • the initial command signal may include a read signal
  • the target command signal may include a write signal
  • the initial command signal may include a precharge signal.
  • the activation signal is used to perform an activation operation
  • the read signal is used to perform a read operation
  • the write signal is used to perform a write operation
  • the precharge signal is used to perform a precharge operation.
  • the embodiments of the present disclosure can be applied not only to the timing control between internal self-generated commands under ECS operation, but also to the timing control between command signals generated inside any memory, such as the time interval between activation/row addressing (Row Address Strobe, RAS) and read/write/column addressing (Column Address Strobe, CAS).
  • RAS Low Address Strobe
  • CAS Read/write/column addressing
  • the following is a detailed description of the implementation of the embodiments of the present disclosure, taking the timing control between command signals in the ECS process as an example.
  • ACT and RD are self-generated commands inside DRAM
  • DRAM needs to internally control the timing from ACT to RT to meet the time interval (tRCD).
  • tRCD time interval
  • this time interval can be 15ns.
  • the time interval from ACT to RD needs to be greater than or equal to tRCD.
  • the disclosed embodiment is mainly applicable to the manual ECS operation generated by the Multiple Purpose Command (MPC) and the automatic ECS operation generated by the refresh command (REFab), because in these two ECS modes, there is an external clock signal. That is to say, the disclosed embodiment uses the external clock signal as the clock to delay the initial command signal and obtain the target command signal, and the external clock signal is required as the clock to shift the initial command signal.
  • MPC Multiple Purpose Command
  • REFab refresh command
  • the time interval between the initial command signal and the target command signal needs to meet the preset timing conditions. However, if a completely consistent delay circuit is always used to delay the initial command signal, the delay circuit will always delay the initial command signal by the same number of clock cycles. When the DRAM operates at different frequencies, the time interval between the target command signal and the initial command signal will be different, which will not meet the preset timing conditions.
  • the delay circuit can delay the signal by A clock cycles.
  • the length of A clock cycles is exactly the required time interval, which meets the preset timing conditions. If the operating frequency of the DRAM is switched to the second frequency, the corresponding clock cycle corresponds to the second frequency at this time, and the length of A clock cycles is not equal to the required time interval, which does not meet the preset timing conditions.
  • the embodiment of the present disclosure sets at least one delay submodule in the delay module 12, and the decoding module 11 decodes the mode register signal, and selects which delay submodules as the target delay module according to the decoding result to delay the initial command signal.
  • the external clock signal is used as the clock of the delayed initial command signal, and the decoding result obtained by the decoding module 11 decoding the mode register signal can represent the clock frequency of the external clock signal.
  • the decoding module 11 decodes the mode register signal to obtain the clock frequency of the external clock signal, and then obtains at least one decoding signal, so that the target delay module matching the clock frequency of the external clock signal can be selected to achieve accurate delay of the initial command signal, so that the time interval between the target command signal and the initial command signal meets the preset timing conditions.
  • the decoding module 11 is specifically configured to decode the mode register signal to determine the delay time interval; generate at least one decoding signal according to the delay time interval; wherein there is a corresponding relationship between the delay time interval and the clock frequency of the external clock signal.
  • the mode register signal may specifically be a signal generated by mode register 13 (MR13) in the DRAM: MR OP ⁇ 3:0>.
  • Table 1 shows the correspondence between the mode register signal, delay time interval, and clock frequency in the DDR5 DRAM specified by JEDEC.
  • OP[3:0] represents the mode register signal (MR OP ⁇ 3:0>)
  • tCCD_L, tCCD_L_WR and tDLLK are several time setting values specified by JEDEC.
  • tCCD_L (CAS-to-CAS Delay (Long)) represents the time interval for the memory controller to continuously send two access instructions for the same row address with the same storage group (bank group) address.
  • These time setting values can all be used as the delay time interval in the embodiments of the present disclosure (in addition, the delay time interval is not limited to these time setting values.
  • the JEDEC standard also includes other values that can represent frequency, which can all be used as the delay time interval).
  • tCCD_L For example, taking the delay time interval tCCD_L as an example, if OP[3:0] is 0000, the decoded tCCD_L is 8, and the corresponding data rate (Data Rate, abbreviated as DR) is 3200 Megabits per second (Mbps). For the double data rate (Double Data Rate, DDR) memory, the corresponding clock cycle is 0.625ns.
  • the mode register signal MR13OP ⁇ 3:0> records the encoded data of the current setting tCCD_L.
  • the value of tCCD_L can be obtained.
  • the standard (SPEC) stores a correspondence table between frequency and tCCD_L (for example, Table 1).
  • a value of tCCD_L can represent the current frequency range, thereby deriving the specific frequency range of the external clock signal (represented by CK_t).
  • the specific size of tCCD_L is known through decoding the mode register MR13OP ⁇ 3:0>, and the specific frequency of the corresponding external clock signal can be parsed, thereby generating at least one decoding signal, and selecting a target delay module from at least one delay sub-module according to the at least one decoding signal, performing delay processing on the initial command signal, and obtaining a target command signal, and the time interval between the target command signal and the initial command signal meets the preset timing conditions.
  • Fig. 3 shows a schematic diagram of the composition structure of another delay control circuit 10 provided in an embodiment of the present disclosure.
  • the number of at least one delay submodule is N, N is an integer greater than 0, and the first input terminal of each delay submodule is connected to the initial command signal.
  • each delay sub-module includes a first input terminal and a second input terminal, and the first input terminal of each delay sub-module is connected to the initial command signal.
  • each delay sub-module is also connected to an external clock signal to delay the signal of the input delay sub-module according to the external clock signal and then output it.
  • the output end of the delay submodule is used to output the target command signal.
  • the delay module 12 includes only one delay submodule, and there is only one corresponding decoding signal, and the delay submodule is the target delay module.
  • the first input end of the delay submodule is connected to the initial command signal, and the second input end is connected to the ground signal (i.e., ground connection), and the delay submodule is also connected to the external clock signal.
  • the delay submodule receives a unique decoding signal, and delays the initial command signal according to the external clock signal to obtain the target command signal.
  • N is usually greater than 1, that is, the delay control circuit is applied in a variety of different frequency scenarios, and selects different numbers of delay submodules as target delay modules according to the operating frequency (i.e., the clock frequency of the external clock signal), which is suitable for a variety of frequency scenarios of DRAM, can be flexibly switched, and has stronger adaptability.
  • the operating frequency i.e., the clock frequency of the external clock signal
  • the second input end of the 1st delay submodule is connected to the ground signal
  • the second input end of the i-th delay submodule is connected to the output end of the i-1th delay submodule
  • the output end of the N-th delay submodule is used to output the target command signal, where i is an integer greater than 1 and less than or equal to N.
  • each delay submodule receives the corresponding decoding signal; the second input terminal of the first delay submodule (i.e., delay submodule 1) is connected to the ground signal, i.e., ground connection; the output terminals of the 2nd to N-1th delay submodules are all connected to the second input terminal of the next delay submodule, so that each delay submodule sends the delayed signal to the second input terminal of the next delay submodule; the output terminal of the last (Nth) delay submodule (delay submodule N) outputs the target command signal.
  • the decoding module 11 is also configured to, in the process of generating at least one decoding signal, if the j-th decoding signal is a first value, determine that all other decoding signals except the j-th decoding signal are a second value; wherein the first value is different from the second value, and j is an integer greater than 0 and less than or equal to N.
  • the first value can be specifically a high-level "logic 1”
  • the second value can be specifically a low-level “logic 0" that is, among the N decoding signals, only one decoding signal will have a value of "logic 1”, and the values of the remaining decoding signals are all logic "0".
  • the decoding signal is the first value
  • the first input end of the corresponding delay submodule is turned on and the second input end is turned off, so that the input signal of the decoding module is the signal received by the first input end, that is, the initial command signal
  • the decoding signal is the second value
  • the first input end of the corresponding delay submodule is turned off and the second input end is turned on, then the input signal of the delay submodule is the signal received by the second input end, that is, the signal output by the previous delay submodule, and for the first delay submodule, the second input end receives the ground signal.
  • the first value may specifically be a low level “logic 0”
  • the second value may specifically be a high level “logic 0”, which is not specifically limited here.
  • the j-th delay sub-module only one delay sub-module (denoted as the j-th delay sub-module) among the N delay sub-modules successfully receives the initial command signal at its first input end. Since the second input end of the first delay sub-module is connected to the ground signal, the delay sub-modules before the j-th delay sub-module are all grounded. The j-th delay sub-module and all subsequent delay sub-modules are selected as target delay modules. In this way, when determining the target delay module according to the decoding signal, the selected delay sub-module can be accurately determined to avoid errors.
  • the delay module 12 is configured to determine the jth delay sub-module to the Nth delay sub-module as the target delay module when the value of the jth decoding signal is the first value; and to delay the initial command signal through the jth delay sub-module to the Nth delay sub-module to obtain the target command signal.
  • delay submodule 1 corresponds to receiving decoding signal 1
  • delay submodule 2 corresponds to receiving decoding signal 2
  • delay submodule N corresponds to receiving decoding signal N.
  • the delay submodule j and the delay submodule after the delay submodule j are determined as the target delay module.
  • the selected target delay module performs delay processing on the initial command signal to obtain the target command signal.
  • the delay sub-module 1 to the delay sub-module N are selected as the target delay modules; if the value of the decoding signal 2 received by the delay sub-module 2 is the first value, and the values of the remaining decoding signals are all the second value, then the delay sub-module 2 to the delay sub-module N are selected as the target delay modules;...; if the value of the decoding signal N received by the delay sub-module N is the first value, and the values of the remaining decoding signals are all the second value, then the delay sub-module N is selected as the target delay module.
  • N delay submodules are cascaded together to ensure that the delay submodule corresponding to the first value and the subsequent delay submodules are selected as the target delay module, and the delay processing of the initial command signal by the selected target delay module can also save circuit structure, make full use of various components in the circuit, and avoid component waste.
  • the jth delay submodule includes a jth selection module and a jth shift register module, and the first input end of the jth selection module is used to receive the initial command signal, the second input end of the jth selection module is used to receive the first input signal, and the output end of the jth selection module is connected to the input end of the jth shift register module, wherein:
  • a j-th selection module configured to receive the j-th decoding signal and select the j-th target input signal from the initial command signal and the first input signal according to the j-th decoding signal;
  • a j-th shift register module configured to receive an external clock signal and a j-th target input signal, and perform delay processing on the j-th target input signal according to the external clock signal to obtain a j-th target output signal;
  • the first input signal when j is equal to 1, the first input signal is a ground signal; when j is greater than 1 and less than or equal to N, the first input signal is the j-1th target output signal output by the j-1th shift register module; and, when j is equal to N, the Nth target output signal is a target command signal.
  • each delay sub-module is composed of a selection module and a shift register module, that is, delay sub-module 1 (the first delay sub-module) is composed of selection module 1 (the first selection module) and shift register module 1 (the first shift register module), delay sub-module 2 (the second delay sub-module) is composed of selection module 2 (the second selection module) and shift register module 2 (the second shift register module), ..., delay sub-module N (the Nth delay sub-module) is composed of selection module N (the Nth selection module) and shift register module N (the Nth shift register module).
  • the selection module is configured to receive the corresponding decoding signal, that is: selection module 1 receives decoding signal 1 (the first decoding signal), selection module 2 receives decoding signal 2 (the second decoding signal), ..., selection module N receives decoding signal N (the Nth decoding signal).
  • Each selection module includes a first input terminal, a second input terminal, a control terminal and an output terminal.
  • the first input terminal of the jth selection module is the first input terminal of the jth delay submodule
  • the second input terminal of the jth selection module is the second input terminal of the jth delay submodule
  • the control terminal of the jth selection module is the control terminal of the jth delay submodule.
  • the first input end is used to receive the initial command signal
  • the control end is used to receive the corresponding decoding signal
  • the second input end is used to receive the first input signal.
  • the second input end of the selection module 1 is grounded and connected to receive the ground signal;
  • the second input end is connected to the output end of the shift register module in the previous delay submodule, and is used to receive the target output signal output by the shift register module in the previous delay submodule; each selection module selects one of the initial command signal and the first input signal as the target input signal according to the received decoding signal.
  • the output end of the selection module is connected to the input end of the shift register module, and the clock end of the shift register module is used to receive an external clock signal.
  • the shift register module delays the target input signal selected by the selection module according to the external clock signal to obtain a target output signal, which is output to the second input end of the next selection module.
  • the output of the shift register module N is the target command signal.
  • the selection module selects the initial command signal or the first input signal as the input signal of the delay submodule according to the decoded signal, thereby selecting the target delay module according to the decoded signal, and further realizing the delay processing of the initial command signal.
  • the j-th shift register module includes M shift registers, and the clock end of each shift register is connected to the external clock signal, and M is an integer greater than 0, wherein:
  • the input end of the first shift register is connected to the output end of the j-th selection module, and the output end of the first shift register is used to output the j-th target output signal.
  • the first shift register is the only shift register in the shift register module, and the shift register receives the target input signal selected by the selection module in the delay submodule to which it belongs, and performs delay processing on the target input signal according to the external clock signal to obtain the target output signal.
  • the target output signal will be transmitted to the selection module in the next delay submodule.
  • the output end of the shift register outputs the target command signal.
  • the input end of the first shift register is connected to the output end of the jth selection module, the input end of the yth shift register is connected to the output end of the y-1th shift register, and the output end of the Mth shift register is used to output the jth target output signal; wherein y is an integer greater than 1 and less than or equal to M.
  • M is greater than 1, that is, when the shift register module includes multiple shift registers, M shift registers are cascaded, and the input end of the first shift register is connected to the output end of the selection module in the delay sub-module to which it belongs, for receiving the target input signal selected by the selection module, delaying the target input signal and transmitting it to the next shift register, and then delaying the target input signal in turn to obtain the target output signal, which is passed to the selection module in the next delay sub-module, and finally the target command signal is obtained at the output end of the last shift register of the Nth delay sub-module.
  • the number M of shift registers included in each delay submodule can be the same, different, or partially the same, and needs to be determined in combination with specific frequency requirements.
  • N decoding signals correspond to the number of N types of shift registers, and these numbers are set in accordance with the corresponding frequency (i.e., the operating frequency of the memory application, that is, the clock frequency of the external clock signal) when designing the delay control circuit. Then, when using it, the number of shift registers of the corresponding number can be selected according to the specific frequency to achieve delay processing of the initial command signal.
  • the delay module 12 includes four delay submodules, the first delay submodule includes 3 shift registers, the second delay submodule includes 5 shift registers, and the third delay submodule includes 4 shift registers.
  • the clock frequency of the external clock signal is the first frequency, and 4 shift registers are required, then the third decoding signal is the first value, and the remaining decoding signals are the second value, and the third delay submodule is determined as the target delay module; in the second working mode, the clock frequency of the external clock signal is the second frequency, and 9 shift registers are required, then the second decoding signal is the first value, and the remaining decoding signals are the second value, and the second delay submodule and the third delay submodule are determined as the target delay module; in the third working mode, the clock frequency of the external clock signal is the third frequency, and 12 shift registers are required, then the first decoding signal is the first value, and the remaining decoding signals are the second value, and the first delay submodule, the second delay submodule and the third delay submodule.
  • the number of shift registers corresponding to each operating frequency is pre-set according to the frequency.
  • the selection module can be a two-to-one selector (2-1MUX), wherein "1" represents the first input terminal and "0" represents the second input terminal.
  • 2-1MUX two-to-one selector
  • At least one decoding signal can be combined and written as OPDEC ⁇ n:0>, which indicates the signal obtained after decoding the mode register signal
  • OPDEC ⁇ n:0> includes OPDEC ⁇ 0>, OPDEC ⁇ 1>, OPDEC ⁇ 2>, ..., OPDEC ⁇ n>, a total of n+1 signals.
  • OPDEC ⁇ 0> indicates decoding signal 1
  • OPDEC ⁇ 1> indicates decoding signal 2
  • OPDEC ⁇ 2> indicates decoding signal 3
  • OPDEC ⁇ n> indicates decoding signal N.
  • each shift register is used to delay the signal received at the input end of the shift register by the first clock cycle for output.
  • the time length for a shift register to delay a signal is the first clock cycle. If the target delay module includes Z shift registers in total, the product of the first clock cycle and Z is the time interval required by the preset timing condition.
  • the specific value of the first clock cycle is related to the frequency of the external clock signal and the structure of the shift register.
  • the shift register includes L flip-flops, and the L flip-flops are connected in series, L is an integer greater than 0, wherein: the clock terminals of the L flip-flops are all connected to the external clock signal, and the output terminal of the flip-flop is connected to the input terminal of the next flip-flop.
  • a trigger is used to delay the signal received at the input end of the trigger by a second clock cycle for output; wherein the first clock cycle is equal to the product of the second clock cycle and L, and the second clock cycle is equal to the clock cycle of the external clock signal.
  • the shift register is composed of L flip-flops connected in series, and for each shift register, the L value is the same (the L values of different shift registers may also be different, but it requires more complicated design and calculation.
  • the disclosed embodiment takes the same number of flip-flops included in each shift register as an example).
  • the flip-flop can be a D flip-flop (D Flip-Flop, DFF), and a flip-flop can delay the signal by the second clock cycle, where the second clock cycle is the same as the clock cycle of the current external clock signal.
  • DFF D Flip-Flop
  • the flip-flop can delay the signal by the duration corresponding to the clock cycle of the external signal, and the specific duration is related to the external clock signal itself.
  • FIG6 shows a specific structural diagram of a shift register provided by an embodiment of the present disclosure.
  • the shift register includes a first trigger DFF1, a second trigger DFF2, a third trigger DFF3 and a fourth trigger DFF4, wherein:
  • the clock terminals of the first flip-flop DFF1, the second flip-flop DFF2, the third flip-flop DFF3 and the fourth flip-flop DFF4 are all connected to the external clock signal CK_t;
  • An input terminal of the first flip-flop DFF1 is connected to an output terminal of the corresponding selection module, and an output terminal of the first flip-flop DFF1 is connected to an input terminal of the second flip-flop DFF2;
  • An output terminal of the second flip-flop DFF2 is connected to an input terminal of the third flip-flop DFF3;
  • An output terminal of the third flip-flop DFF3 is connected to an input terminal of the fourth flip-flop DFF4;
  • the output terminal of the fourth flip-flop DFF4 is used to output the output signal of the shift register.
  • each shift register its structure can be as shown in FIG6, except that the input and output of the shift registers at different positions are different.
  • the signal input into the shift register can be delayed by 4 second clock cycles (i.e., 4 clock cycles of the external clock signal CK_t).
  • the delay control circuit 10 may further include a buffer module 13 , wherein the buffer module 13 is configured to receive an ECS command signal and generate an initial command signal according to the ECS command signal.
  • the initial command signal when the DRAM is in ECS mode and the initial command signal is an activation signal, the initial command signal can be generated based on the ECS signal. Therefore, the initial command signal can also be obtained according to the ECS command signal through the buffer module 13, and the initial command signal can be further processed as described above to finally obtain the target command signal.
  • the ECS signal supports the following two operation modes: a manual ECS operation mode based on an MPC command and an automatic ECS operation mode based on a self-refresh command.
  • the ECS signal is used to instruct the memory to perform an ECS operation.
  • the memory will internally generate command signals such as ACT, RD, WR, etc.
  • the disclosed embodiments are mainly applied to manual ECS operations generated by MPC commands and automatic ECS operations generated by refresh (Refresh, which can be abbreviated as REFab) commands.
  • the buffer module can also be called a "transmission gate”, which not only has a delay function, but also has the function of enhancing the signal driving ability. Specifically, for the ECS command signal and the initial command signal, the initial command signal not only has a time delay compared to the ECS command signal, but also has a stronger driving ability.
  • FIG7 shows a specific structural diagram of a delay module 12 provided by an embodiment of the present disclosure.
  • at least one decoding signal includes a first decoding signal OPDEC ⁇ 0> and a second decoding signal OPDEC ⁇ 1>
  • at least one delay submodule includes a first delay submodule 121 and a second delay submodule 122
  • the first delay submodule 121 includes a first selection module 1211 and a first shift register module 1212
  • the second delay submodule 122 includes a second selection module 1221 and a second shift register module 1222, wherein,
  • the second decoding signal OPDEC ⁇ 1> is the first value
  • the first decoding signal OPDEC ⁇ 0> is the second value
  • the second delay submodule 122 is determined to be the target delay module
  • the initial command signal ECT_ACT is input to the second shift register module 1222 through the second selection module 1221, and the initial command signal is delayed by the second shift register module 1222 to obtain the target command signal;
  • the first decoding signal OPDEC ⁇ 0> is the first value
  • the second decoding signal OPDEC ⁇ 1> is the second value
  • the first delay sub-module 121 and the second delay sub-module 122 are determined to be target delay modules
  • the initial command signal ECT_ACT is input to the first shift register module 1212 through the first selection module 1211
  • the initial command signal ECT_ACT is subjected to a first delay processing through the first shift register module 1212 to obtain an intermediate command signal RD ⁇ 2>
  • the intermediate command signal RD ⁇ 2> is input to the second shift register module 1222 through the second selection module 1221
  • the intermediate command signal RD ⁇ 2> is subjected to a second delay processing through the second shift register module 1222 to obtain a target command signal ECT_RD.
  • the specific implementation of the embodiment of the present disclosure is exemplarily described by taking the delay module 12 including the first delay submodule 121 and the second delay submodule 122 as an example, which does not constitute a limitation of the present disclosure.
  • the first input end of the first selection module 1211 is connected to the initial command signal ECT_ACT (the initial command signal here is an activation signal ECS_ACT generated when the memory performs an ECS operation as an example), the second input end of the first selection module 1211 is connected to the ground signal VSS, and the output end of the first selection module 1211 is connected to the input end of the first shift register module 1212.
  • ECT_ACT the initial command signal here is an activation signal ECS_ACT generated when the memory performs an ECS operation as an example
  • the second input end of the first selection module 1211 is connected to the ground signal VSS
  • the output end of the first selection module 1211 is connected to the input end of the first shift register module 1212.
  • the first shift register module 1212 includes three shift registers (shift register 0, shift register 1, and shift register 2), the three shift registers are cascaded, the clock end of each shift register is connected to the external clock signal, the input end of shift register 0 is used as the input end of the first shift register module 1212, the output end of shift register 0 is connected to the input end of shift register 1, the output end of shift register 1 is connected to the input end of shift register 2, and the output end of shift register 2 is connected to the second input end of the second selection module 1221 as the output end of the first shift register module 1212.
  • the first input end of the second selection module 1221 is connected to the initial command signal ECT_ACT, and the output end of the second selection module 1221 is connected to the input end of the second shift register module 1222.
  • the second shift register module 1222 includes six shift registers (shift register 3, shift register 4, shift register 5, shift register 6, shift register 7 and shift register 8), the six shift registers are cascaded, the clock end of each shift register is connected to the external clock signal, the input end of the shift register 3 is used as the input end of the second delay submodule 122, and the output end of the shift register 8 is used as the output end of the second delay submodule 122.
  • the second delay submodule 122 includes six shift registers, that is, in this case, the second delay submodule 122 needs to be determined as the target delay module.
  • the decoding result of the decoding module 11 it is determined that the value of the second decoding signal OPDEC ⁇ 1> is the first value, and the value of the first decoding signal OPDEC ⁇ 0> is the second value, wherein the first value can be "logic 1" and the second value can be "logic 0".
  • the first selection module 1211 determines the signal at selection 0 (the second input terminal) according to the first decoding signal OPDEC ⁇ 0>, that is, the ground signal is selected to input the first delay submodule 121, and the first delay submodule 121 is connected to the ground; the second selection module 1221 determines the signal at selection 1 (the first input terminal) according to the second decoding signal OPDEC ⁇ 1>, that is, the initial command signal RCS_ACT is selected as the signal input to the second delay submodule 122.
  • the second delay submodule 122 is used as the target delay module to delay the initial command signal RCS_ACT, and the signals output by the shift register 0 to the shift register 7 are respectively recorded as RD ⁇ 0>, RD ⁇ 1>, RD ⁇ 2>...RD ⁇ 7>, and the signal output by the shift register 8 is the target command signal, recorded as ECS_RD.
  • FIG8 is a timing diagram of each signal when the clock frequency is 3200Mbps. As shown in FIG8, the clock period tCK_t of the external clock signal is 0.625ns, and the input signal of the first delay submodule 121 is a ground signal, so RD ⁇ 0>, RD ⁇ 1> and RD ⁇ 2> all maintain a low level state.
  • the input signal of the second delay submodule 122 is the target command signal, and is delayed through shift registers 3 to 8 in sequence. Each shift register delays 4 clock cycles, and the output signal of each shift register is delayed by 4 clock cycles relative to the output signal of the previous shift register. After 6 shift registers, the final target command signal ECS_RD is delayed by 24 clock cycles relative to the initial command signal ECS_ACT, i.e., 15ns.
  • the corresponding clock cycle is 0.416ns, and the delay is 15ns, that is, 36 clock cycles, and 9 shift registers are required.
  • the first delay submodule 121 and the second delay submodule 122 include 9 shift registers in total, that is, in this case, the first delay submodule 121 and the second delay submodule 122 need to be determined as the target delay module. Therefore, according to the decoding result of the decoding module 11, it is determined that the value of the first decoding signal OPDEC ⁇ 0> is the first value, and the value of the second decoding signal OPDEC ⁇ 1> is the second value.
  • FIG9 is a timing diagram of each signal when the clock frequency is 4800Mbps.
  • the clock cycle tCK_t of the external clock signal is 0.416ns
  • the input signal of the first delay submodule 121 is the initial command signal ECS_ACT
  • the input signal of the second delay submodule 122 is the signal output by the first delay submodule 121. Therefore, the initial command signal ECS_ACT is sequentially delayed by shift register 0 to shift register 8, and each shift register is delayed by 4 clock cycles.
  • the output signal of each shift register is delayed by 4 clock cycles relative to the output signal of the previous shift register.
  • the target command signal ECS_RD obtained is delayed by 36 clock cycles relative to the initial command signal ECS_ACT, that is, 15ns.
  • the embodiments of the present disclosure all achieve a time interval of 15 ns between the initial command signal and the target command signal.
  • the delay control circuit designed in the embodiment of the present disclosure meets the delay requirement of tRCD by using the external clock signal CK_t to move the clock cycle of the command signal different times at different operating frequencies, while ensuring that the delay of tRCD at different frequencies is basically the same.
  • the number of nRCD (nRCD is the number of cycles set at the current frequency, and generally the product of nRCD and the cycle needs to be greater than or equal to tRCD) is different at different frequencies, so a mode register signal is needed to determine the current frequency.
  • the cycle value of CK_t with a large frequency is small, so more shift registers are required to delay the same time. Therefore, to achieve the timing requirements of tRCD, it is necessary to know the value or value range of the specific frequency, so that the corresponding number of shift registers can be selected through the selection circuit to meet the timing of tRCD.
  • the embodiment of the present disclosure can use the value of tCCD_L to determine the current frequency and determine the number of shifts required for tRCD at the corresponding frequency (i.e., the number of clock cycles to shift). Therefore, the timing requirements of fixed tRCD can be achieved by a corresponding number of timing shifts at different frequencies. Since the embodiment of the present disclosure uses CK_t as a shift clock to delay the initial command signal, the embodiment of the present disclosure is mainly applicable to manual ECS operations generated by MPC commands and automatic ECS operations generated by refresh commands.
  • the specific size of tCCD_L is known by decoding the mode register signal MR13OP ⁇ 3:0>, so that the specific frequency of the corresponding external clock signal CK_t can be parsed, and then at least one decoding signal is obtained, and the number of shift registers is selected by the selector according to the decoding signal to achieve delays at different frequencies.
  • the disclosed embodiment uses a plurality of shift registers in cascade form, the external clock signal CK_t is used as the clock signal of the shift register, and at least one decoding signal OPDEC ⁇ n:0> after the mode register signal MR12OP ⁇ 3:0> is decoded is used as a selection signal to control which selector the initial command signal ECS_ACT passes through as the input of the shift register, thereby controlling the number of shifts (i.e., the number of clock cycles) from the initial command signal ECS_ACT to the target command signal ECS_RD.
  • a shift register composed of 4 DFFs as an example (refer to Figure 6).
  • a shift register can delay the signal by 4 clock cycles (tCK).
  • tCK clock cycles
  • the clock cycle corresponding to 3200Mbps is 0.625ns, and a delay of 15ns requires 6 registers, that is, 24 DFFs.
  • the clock cycle corresponding to 4800Mbps is 0.416ns, and a delay of 15ns requires 9 registers, that is, 36 DFFs.
  • the decoding signals corresponding to the shift register signals MR13OP ⁇ 3:0> of the frequencies 4800Mbps and 3200Mbps are OPDEC ⁇ 0> and OPDEC ⁇ 1> respectively.
  • OPDEC ⁇ 0> is the first value
  • the first input terminal of the first selection module 1211 is turned on
  • the second input terminal is turned off
  • OPDEC ⁇ 1> is the second value
  • the first input terminal of the second selection module 1221 is turned off
  • the second input terminal is turned on
  • the initial command signal ECS_ACT enters from the first input terminal of the first selection module 1211
  • the target command signal ECS_RD finally outputted satisfies tRCD of 15ns.
  • OPDEC ⁇ 0> is the second value, the first input terminal of the first selection module 1211 is closed, and the second input terminal is opened; OPDEC ⁇ 1> is the first value, the first input terminal of the second selection module 1221 is opened, and the second input terminal is closed, and the inputs of shift register 0 to shift register 2 are VSS, so the outputs RD ⁇ 0> to RD ⁇ 2> are all 0, and the initial command signal ECS_ACT enters from the first input terminal of the second selection module 1221, and after the delay processing of 6 shift registers, the target command signal ECS_RD finally output satisfies tRCD of 15ns. It can be seen from the timing diagrams of Figures 8 and 9 that although the periods of the external clock signal CK_t are different, the target command signal ECS_RD is delayed by 15ns from the initial command signal ECS_ACT.
  • the embodiment of the present disclosure provides a delay control circuit, including: a decoding module and a delay module, wherein: the decoding module is configured to receive a mode register signal, decode the mode register signal, and generate at least one decoding signal; the delay module includes at least one delay submodule, configured to determine the selected target delay module from at least one delay submodule according to at least one decoding signal, and delay the received initial command signal according to the target delay module and an external clock signal to obtain a target command signal; wherein the time interval between the target command signal and the initial command signal meets a preset timing condition.
  • At least one decoding signal is obtained based on the mode register signal, and then the target delay module is determined from at least one delay submodule according to at least one decoding signal, and the target delay module delays the initial command signal according to the external clock signal to obtain the target command signal, so that the time interval between the target command signal and the initial command signal meets the preset timing condition.
  • the delay control circuit the timing control requirements between any command signals generated by the memory can also be met, thereby improving the memory performance.
  • decoding the module register can obtain the clock frequency of the external clock signal, so that at least one selection signal is determined based on the clock frequency of the external clock signal, so that the target delay module finally selected corresponds to the clock frequency of the current external clock signal. Furthermore, when the initial command signal is delayed, since the target delay module is adapted to the external clock signal, it is ensured that under different clock frequencies, the time interval between the target command signal and the initial command signal can meet the preset timing conditions.
  • FIG10 a schematic flow chart of a delay control method provided by an embodiment of the present disclosure is shown. As shown in FIG10 , the method may include:
  • S1001 receiving a mode register signal through a decoding module, decoding the mode register signal, and generating at least one decoding signal.
  • S1002 Receive at least one decoding signal, an initial command signal and an external clock signal through a delay module, determine a selected target delay module from at least one delay sub-module included in the delay module according to the at least one decoding signal, and delay the initial command signal according to the target delay module and the external clock signal to obtain a target command signal.
  • the time interval between the target command signal and the initial command signal satisfies a preset timing condition.
  • decoding the mode register signal to generate at least one decoding signal may include: decoding the mode register signal to determine a delay time interval; generating at least one decoding signal based on the delay time interval; and there is a corresponding relationship between the delay time interval and the clock frequency of the external clock signal.
  • the method may further include: in the process of generating at least one decoding signal, if the jth decoding signal is a first value, determining that all other decoding signals except the jth decoding signal are a second value; wherein the first value is different from the second value, and j is an integer greater than 0 and less than or equal to N.
  • determining the selected target delay module from at least one delay sub-module included in the delay module according to at least one decoding signal may include: when the value of the jth decoding signal is the first value, determining the jth delay sub-module to the Nth delay sub-module as the target delay module; and delaying the initial command signal through the jth delay sub-module to the Nth delay sub-module to obtain the target command signal.
  • delay processing is performed on the initial command signal through the jth delay submodule to the Nth delay submodule to obtain the target command signal, which may include:
  • An external clock signal and a j-th target input signal are received through the j-th shift register module, and the j-th target input signal is delayed according to the external clock signal to obtain a j-th target output signal;
  • the first input signal when j is equal to 1, the first input signal is a ground signal; when j is greater than 1 and less than or equal to N, the first input signal is the j-1th target output signal output by the j-1th shift register module; and, when j is equal to N, the Nth target output signal is a target command signal.
  • the initial command signal includes an activation signal and the target command signal includes a read signal, or; the initial command signal includes a read signal and the target command signal includes a write signal, or; the initial command signal includes a write signal and the target command signal includes a precharge signal.
  • the method may further include: receiving an ECS signal through a buffer module, and performing delay and drive enhancement processing on the ECS signal to obtain an initial command signal.
  • the ECS signal is used to indicate the execution of an ECS operation, and the ECS signal is generated according to a multi-purpose control MPC command signal or a refresh signal.
  • the delay control method provided in the embodiment of the present disclosure may be applied to the aforementioned delay control circuit 10.
  • the aforementioned embodiment for understanding.
  • An embodiment of the present disclosure provides a delay control method, based on which an initial command signal is processed to obtain a target command signal, so that the time interval between the target command signal and the initial command signal meets a preset timing condition, thereby being able to meet the timing control requirements between self-generated commands inside a memory, thereby improving memory performance.
  • Figure 11 shows a schematic diagram of the composition structure of a semiconductor memory 20 provided by the embodiment of the present disclosure.
  • the semiconductor memory 20 at least includes the delay control circuit 10 described in any of the above embodiments.
  • the semiconductor memory 20 includes DRAM.
  • DRAM may not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, and DDR5, but may also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, and LPDDR5, without any limitation.
  • the semiconductor memory 20 includes the delay control circuit described in the above embodiment, which can meet the timing control requirements between self-generated commands inside the memory and improve the memory performance.
  • the disclosed embodiment can generate at least one decoding signal based on the mode register signal, and then determine the target delay module according to the at least one decoding signal, and then based on the target delay module, the initial command signal is delayed by the external clock signal to obtain the target command signal, and the time interval between the target command signal and the initial command signal at this time meets the preset timing conditions; in this way, the delay control circuit can meet the timing control requirements between the self-generated commands inside the memory, and at the same time, because the at least one decoding signal is related to the clock frequency of the external clock signal, the target delay module corresponding to the clock frequency of the external clock signal can also be selected, so that under different clock frequencies, the time intervals between the command signals meet the preset timing conditions, thereby improving the performance of the memory.

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Abstract

本公开实施例提供了一种延时控制电路、方法和半导体存储器，该延时控制电路包括译码模块和延时模块，其中：译码模块，配置为接收模式寄存器信号，对模式寄存器信号进行译码处理，生成至少一个译码信号；延时模块包括至少一个延时子模块，配置为根据至少一个译码信号从至少一个延时子模块中确定被选择的目标延时模块，根据目标延时模块和外部时钟信号对接收到的初始命令信号进行延时处理，得到目标命令信号；其中，目标命令信号与初始命令信号之间的时间间隔满足预设时序条件。

Description

一种延时控制电路、方法和半导体存储器
相关申请的交叉引用
本公开基于申请号为202211222709.7、申请日为2022年10月08日、发明名称为“一种延时控制电路、方法和半导体存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种延时控制电路、方法和半导体存储器。
背景技术
随着半导体技术的不断发展，人们在制造和使用计算机等设备时，对数据的传输速度提出了越来越高的要求。为了获得更快的数据传输速度，应运而生了一系列数据可以双倍速率(Double Data Rate，DDR)传输的存储器等器件。
以动态随机存取存储器(Dynamic Random Access Memory，DRAM)为例，错误检查与清除(Error Check and Scrub，ECS)操作允许DRAM内部读取、修改检测到的错误码字，并将修正后的数据写回存储阵列。在执行ECS操作的过程中，DRAM需要不同命令来实现不同的功能，内部产生不同命令之间存在时序的要求。然而，在实际应用中，不同命令之间的时序可能不满足时序条件，影响了存储器的性能。
发明内容
本公开实施例提供了一种延时控制电路、方法和半导体存储器。
第一方面，本公开实施例提供了一种延时控制电路，包括译码模块和延时模块，其中：
所述译码模块，配置为接收模式寄存器信号，对所述模式寄存器信号进行译码处理，生成至少一个译码信号；
所述延时模块包括至少一个延时子模块，配置为根据所述至少一个译码信号从所述至少一个延时子模块中确定被选择的目标延时模块，根据所述目标延时模块和外部时钟信号对接收到的初始命令信号进行延时处理，得到目标命令信号；其中，所述目标命令信号与所述初始命令信号之间的时间间隔满足预设时序条件。
在一些实施例中，所述译码模块，具体配置为对所述模式寄存器信号进行译码处理，确定延时时间间隔；根据所述延时时间间隔，生成所述至少一个译码信号；其中，所述延时时间间隔与所述外部时钟信号的时钟频率之间具有对应关系。
在一些实施例中，所述至少一个延时子模块的数量为N个，N为大于0的整数，其中：
在所述至少一个延时子模块中，每一个所述延时子模块的第一输入端均与所述初始命令信号连接；
当N等于1时，所述延时子模块的第二输入端与地信号连接，所述延时子模块的输出端用于输出所述目标命令信号；
当N大于1时，第1个延时子模块的第二输入端与地信号连接，第i个延时子模块的第二输入端与第i-1个延时子模块的输出端连接，第N个延时子模块的输出端用于输出所述目标命令信号，i为大于1且小于或等于N的整数。
在一些实施例中，所述译码模块，还配置为在生成所述至少一个译码信号的过程中，若第j个译码信号为第一值，则确定除所述第j个译码信号之外的其他译码信号均为第二值；其中，所述第一值与所述第二值不同，且j为大于0且小于或等于N的整数。
在一些实施例中，第j个延时子模块与第j个译码信号之间具有对应关系，其中：
所述延时模块，配置为在所述第j个译码信号的取值为第一值的情况下，将所述第j个延时子模块至第N个延时子模块确定为所述目标延时模块；以及通过所述第j个延时子模块至第N个延时子模块对所述初始命令信号进行延时处理，得到所述目标命令信号。
在一些实施例中，所述第j个延时子模块包括第j个选择模块和第j个移位寄存模块，且所述第j个选择模块的第一输入端用于接收所述初始命令信号，所述第j个选择模块的第二输入端用于接收第一输入信号，所述第j个选择模块的输出端与所述第j个移位寄存模块的输入端连接，其中：
所述第j个选择模块，配置为接收所述第j个译码信号，根据所述第j个译码信号在所述初始命令信号和所述第一输入信号中选择第j个目标输入信号；
所述第j个移位寄存模块，配置为接收所述外部时钟信号和所述第j个目标输入信号，根据所述外部时钟信号对所述第j个目标输入信号进行延时处理，得到第j个目标输出信号；
其中，当j等于1时，所述第一输入信号为所述地信号；当j大于1且小于或者等于N时，所述第一输入信号为第j-1个移位寄存模块输出的第j-1个目标输出信号；以及，当j等于N时，第N个目标输出信号为所述目标命令信号。
在一些实施例中，所述第j个移位寄存模块包括M个移位寄存器，每一个所述移位寄存器的时钟端均与所述外部时钟信号连接，M为大于0的整数，其中：
当M等于1时，第一个所述移位寄存器的输入端与第j个选择模块的输出端连接，第一个所述移位寄存器的输出端用于输出所述第j个目标输出信号；
当M大于1时，第一个所述移位寄存器的输入端与第j个选择模块的输出端连接，第y个所述移位寄存器的输入端与第y-1个所述移位寄存器的输出端连接，第M个所述移位寄存器的输出端用于输出所述第j个目标输出信号；其中，y为大于1且小于或者等于M的整数。
在一些实施例中，所述移位寄存器，用于将所述移位寄存器的输入端接收到的信号延迟第一时钟周期进行输出。
在一些实施例中，所述移位寄存器包括L个触发器，且所述L个触发器串接在一起，L为大于0的整数，其中：
所述L个触发器的时钟端均与所述外部时钟信号连接，所述触发器的输出端与下一个所述触发器的输入端连接。
在一些实施例中，所述初始命令信号包括激活信号，所述目标命令信号包括读信号；或者，所述初始命令信号包括读信号，所述目标命令信号包括写信号；或者，所述初始命令信号包括写信号，所述目标命令信号包括预充电信号。
在一些实施例中，所述延时控制电路还包括缓冲模块，其中，
所述缓冲模块，配置为接收错误检查与清除ECS信号，并根据所述ECS信号生成所述初始命令信号。
在一些实施例中，所述ECS信号支持下述两种操作模式：基于MPC命令的手动ECS操作模式和基于自刷新命令的自动ECS操作模式。
第二方面，本公开实施例提供了一种延时控制方法，应用于第一方面所述的延时控制电路，所述方法包括：
通过译码模块接收模式寄存器信号，对所述模式寄存器信号进行译码处理，生成至少一个译码信号；
通过延时模块接收所述至少一个译码信号、初始命令信号和外部时钟信号，根据所述至少一个译码信号从所述延时模块包括的至少一个延时子模块中确定被选择的目标延时模块，以及根据所述目标延时模块和所述外部时钟信号对所述初始命令信号进行延时处理，得到目标命令信号；
其中，所述目标命令信号与所述初始命令信号之间的时间间隔满足预设时序条件。
第三方面，本公开实施例提供了一种半导体存储器，包括如第一方面所述的延时控制电路。
在一些实施例中，所述半导体存储器包括动态随机存取存储器DRAM。
本公开实施例提供了一种延时控制电路、方法和半导体存储器，延时控制电路包括译码模块和延时模块，其中：译码模块，配置为接收模式寄存器信号，对模式寄存器信号进行译码处理，生成至少一个译码信号；延时模块包括至少一个延时子模块，配置为根据至少一个译码信号从至少一个延时子模块中确定被选择的目标延时模块，根据目标延时模块和外部时钟信号对接收到的初始命令信号进行延时处理，得到目标命令信号；其中，目标命令信号与初始命令信号之间的时间间隔满足预设时序条件。这样，基于模式寄存器信号可以生成至少一个译码信号，进而根据这至少一个译码信号来确定目标延时模块，然后基于目标延时模块，由外部时钟信号对初始命令信号进行延时处理，得到目标命令信号，此时的目标命令信号和初始命令信号之间的时间间隔满足预设时序条件；如此，该延时控制电路能够满足存储器内部自产生命令之间的时序控制要求，同时由于这至少一个译码信号与外部时钟信号的时钟频率相关，从而还能够选择出与外部时钟信号的时钟频率相对应的目标延时模块，使得在不同的时钟频率下，命令信号之间的时间间隔均满足预设时序条件，进而提升存储器的性能。
附图说明
图1为一种命令信号之间的时序关系示意图；
图2为本公开实施例提供的一种延时控制电路的组成结构示意图；
图3为本公开实施例提供的另一种延时控制电路的组成结构示意图；
图4为本公开实施例提供的一种延时控制电路的具体结构示意图；
图5为本公开实施例提供的另一种延时控制电路的具体结构示意图；
图6为本公开实施例提供的一种移位寄存器的具体结构示意图；
图7为本公开实施例提供的一种延时模块的具体结构示意图；
图8为本公开实施例提供的一种信号时序示意图；
图9为本公开实施例提供的另一种信号时序示意图；
图10为本公开实施例提供的一种延时控制方法的流程示意图；
图11为本公开实施例提供的一种半导体存储器的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅用于解释相关公开，而非对该公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关公开相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅仅是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
在DRAM等半导体存储器中，通常存在命令信号之间的时序要求，以执行ECS操作为例，在执行ECS操作的过程中，DRAM需要不同命令来实现不同的功能，内部产生不同命令之间存在时序的要求。图1为电子器件工程联合委员会(Joint Electron Device Engineering Council，JEDEC)规定的部分命令信号之间的时序关系示意图，如图1所示，在执行一次ECS操作时，DRAM内部自产生命令信号的顺序为激活信号(Active，ACT)、读操作信号或简称读信号(Read，RD)、写操作信号或简称写信号(Write，WR)和预充电信号(Precharge，PRE)，tRCD表示ACT到RD之间的时间间隔(或称“延时时间”、“延迟时间”)，WL表示RD到WR之间的时间间隔，tWR表示WR到PRE之间的时间间隔。由于所有命令信号均为内部自产生命令，DRAM需要内部控制从ACT到RD以及其它命令信号之间的时序。例如，在部分存储器中，tRCD需要满足15纳秒(nanosecond，ns)。但是，由于DRAM内部的寄存器并没有记录tRCD等的数值，导致无法直接通过时钟移位来实现ACT到RD，以及其它命令之间的时序控制。
基于此，本公开实施例提供了一种延时控制电路，包括：译码模块和延时模 块，其中：译码模块，配置为接收模式寄存器信号，对模式寄存器信号进行译码处理，生成至少一个译码信号；延时模块包括至少一个延时子模块，配置为根据至少一个译码信号从至少一个延时子模块中确定被选择的目标延时模块，根据目标延时模块和外部时钟信号对接收到的初始命令信号进行延时处理，得到目标命令信号；其中，目标命令信号与初始命令信号之间的时间间隔满足预设时序条件。这样，基于模式寄存器信号可以生成至少一个译码信号，进而根据这至少一个译码信号来确定目标延时模块，然后基于目标延时模块，由外部时钟信号对初始命令信号进行延时处理，得到目标命令信号，此时的目标命令信号和初始命令信号之间的时间间隔满足预设时序条件；如此，该延时控制电路能够满足存储器内部自产生命令之间的时序控制要求，同时由于这至少一个译码信号与外部时钟信号的时钟频率相关，从而还能够选择出与外部时钟信号的时钟频率相对应的目标延时模块，使得在不同的时钟频率下，命令信号之间的时间间隔均满足预设时序条件，进而提升存储器的性能。
下面将结合附图对本公开各实施例进行详细说明。
本公开的一实施例中，参见图2，其示出了本公开实施例提供的一种延时控制电路10的组成结构示意图，如图2所示，该延时控制电路10可以包括译码模块11和延时模块12，其中：
译码模块11，配置为接收模式寄存器信号，对模式寄存器信号进行译码处理，生成至少一个译码信号；
延时模块12包括至少一个延时子模块，延时模块12配置为根据至少一个译码信号从至少一个延时子模块中确定被选择的目标延时模块，根据目标延时模块和外部时钟信号对接收到的初始命令信号进行延时处理，得到目标命令信号；其中，目标命令信号与初始命令信号之间的时间间隔满足预设时序条件。
需要说明的是，本公开实施例涉及半导体的集成电路设计中，内部产生命令信号之间的时序相关电路，特别涉及DRAM芯片中，DRAM需要不同命令信号来实现不同的功能，内部产生不同命令信号之间存在时序要求。该延时控制电路10是用来满足不同频率下内部产生命令信号的时序要求。可以应用于DRAM芯片在执行手动ECS操作或者自动ECS操作时，激活信号到读信号之间的时序控制电路，但不局限于此范围，其他内部产生不同命令之间的时序相关电路均可利用延时控制电路10实现。
还需要说明的是，如图2所示，译码模块11接收模式寄存器信号，对模式寄存器信号进行译码处理生成至少一个译码信号，至少一个译码信号的数量可以为N个，如图2中的译码信号1、译码信号2…译码信号N，N为大于0的整数。延时模块12包括至少一个延时子模块，至少一个延时子模块的数量也为N个，如图2所示的延时子模块1、延时子模块2…延时子模块N。
延时模块12与译码模块11连接，延时模块12接收至少一个译码信号，并根据这至少一个译码信号从至少一个延时子模块中确定出若干个延时子模块作为目标延时模块，目标延时模块对初始命令信号进行延时处理，得到目标命令信号。
还需要说明的是，本公开实施例可以应用于DRAM等存储器中各命令信号之间的时序控制。其中，初始命令信号用于执行第一操作，目标命令信号用于执 行第二操作，具体的操作与命令信号的类型有关。例如，本公开实施例可以应用于DRAM芯片在执行手动ECS操作或者自动ECS操作时，内部自产生的ACT到RD之间的时序控制，或者RD到WR之间的时序控制，或者WR到PRE之间的时序控制。
也就是说，在本公开实施例中，初始命令信号可以包括激活信号，目标命令信号可以包括读信号；或者，初始命令信号可以包括读信号，目标命令信号可以包括写信号；或者，初始命令信号可以包括写信号，目标命令信号可以包括预充电信号。其中，激活信号用于执行激活操作，读信号用于执行读操作，写信号用于执行写操作，预充电信号用于执行预充电操作。
另外，本公开实施例不仅可以应用于ECS操作下内部自产生命令之间的时序控制，也可以应用于任意存储器内部产生的命令信号之间的时序控制，例如激活/行寻址(Row Address Strobe，RAS)与读/写/列寻址(Column Address Strobe，CAS)之间的时间间隔等。下面仅以ECS过程中命令信号之间的时序控制为例对本公开实施例的实现进行详细描述。
以ACT和RD为例，由于ACT和RD均为DRAM内部自产生命令，DRAM需要内部控制从ACT到RT的时序满足时间间隔(tRCD)，例如，这个时间间隔可以为15ns，通常ACT到RD的时间间隔需要大于或者等于tRCD。
对于DRAM的ECS操作，本公开实施例主要适用于由多用途命令(Multiple Purpose Conmand，MPC)产生的手动ECS操作和刷新命令(Refresh，REFab)产生的自动ECS操作，因为在这两种ECS模式下，存在有外部时钟信号。也就是说，本公开实施例以外部时钟信号作为时钟对初始命令信号进行延时处理，得到目标命令信号，需要外部时钟信号作为将初始命令信号进行移位的时钟。
还需要说明的是，初始命令信号和目标命令信号之间的时间间隔需要满足预设时序条件，然而，如果始终采用完全一致的延时电路对初始命令信号进行延时，延时电路会将初始命令信号始终延迟相同数量的时钟周期，当DRAM工作在不同频率下时，会导致目标命令信号和初始命令信号之间的时间间隔不同，不满足预设时序条件。
例如：延时电路能够将信号延时A个时钟周期，当DRAM的工作频率为第一频率时，A个时钟周期的时长恰好为所需的时间间隔，满足预设时序条件，如果DRAM的工作频率切换到第二频率，这时候对应的时钟周期与第二频率对应，A个时钟周期的时长就不等于所需的时间间隔，不满足预设时序条件。
因此，本公开实施例在延时模块12中设置至少一个延时子模块，译码模块11对模式寄存器信号进行译码，根据译码的结果来选择哪些延时子模块作为目标延时模块，以对初始命令信号进行延时处理。其中，外部时钟信号作为延时初始命令信号的时钟，译码模块11对模式寄存器信号进行译码得到的译码结果可以表征外部时钟信号的时钟频率。也就是说，在存在外部时钟信号但是不清楚外部时钟信号的时钟频率的具体值的情况下，译码模块11对模式寄存器信号进行译码得到外部时钟信号的时钟频率，进而得到至少一个译码信号，从而能够选择出与外部时钟信号的时钟频率相匹配的目标延时模块，实现对初始命令信号的精准延时，使得目标命令信号和初始命令信号之间的时间间隔满足预设时序条件。
在一些实施例中，译码模块11，具体配置为对模式寄存器信号进行译码处理， 确定延时时间间隔；根据延时时间间隔，生成至少一个译码信号；其中，延时时间间隔与外部时钟信号的时钟频率之间具有对应关系。
需要说明的是，模式寄存器信号具体可以为DRAM中的模式寄存器13(MR13)产生的信号：MR OP<3:0>。示例性地，表1为JEDEC所规定的DDR5DRAM中模式寄存器信号、延时时间间隔、以及时钟频率之间的对应关系。
表1
Figure PCTCN2022127103-appb-000001
需要说明的是，在表1中，OP[3:0]表示模式寄存器信号(MR OP<3:0>)，tCCD_L、tCCD_L_WR和tDLLK是JEDEC所规定的几个时间设置值，例如，tCCD_L(CAS-to-CAS Delay(Long))表示内存控制器连续发送具有相同存储组(bank group)地址的两个针对同一行地址的访问指令的时间间隔，这几个时间设置值均可以作为本公开实施例中的延时时间间隔(另外，延时时间间隔不限于这几个时间设置值，在JEDEC标准中，还包括其它可以表示频率的值，均可以作为延时时间间隔使用)。
示例性地，以延时时间间隔为tCCD_L为例，如果OP[3:0]为0000，则译码得到的tCCD_L为8，对应的数据速率(Data Rate，简写为DR)为3200兆比特每秒(Megabits per second，Mbps)，对于双倍数据速率(Double Data Rate，DDR)的存储器而言，对应的时钟周期即为0.625ns。
也就是说，对于译码模块11而言，模式寄存器信号MR13OP<3:0>记录的是当前设置tCCD_L的编码数据，对模式寄存器信号进行译码处理之后就能得到tCCD_L的数值，标准(SPEC)中保存有频率和tCCD_L的对应表(例如表1)，一个tCCD_L的数值可以表征当前的频率范围，从而得出外部时钟信号(用CK_t表示)的具体频率范围。
这样，通过模式寄存器MR13OP<3:0>译码知道具体tCCD_L的大小，可以解析出对应的外部时钟信号的具体频率，进而生成至少一个译码信号，根据至少一个译码信号从至少一个延时子模块中选择出目标延时模块，对初始命令信号进 行延时处理，得到目标命令信号，且目标命令信号和初始命令信号之间的时间间隔满足预设时序条件。
对于延时模块12而言，参见图3，其示出了本公开实施例提供的另一种延时控制电路10的组成结构示意图。如图3所示，在至少一个延时子模块中，至少一个延时子模块的数量为N个，N为大于0的整数，每一个延时子模块的第一输入端均与初始命令信号连接。
需要说明的是，每个延时子模块均包括第一输入端和第二输入端，且每个延时子模块的第一输入端均与初始命令信号连接，同时，每个延时子模块还与外部时钟信号连接，以根据外部时钟信号对输入延时子模块的信号进行延时处理后输出。
当N等于1时，延时子模块的输出端用于输出目标命令信号。
需要说明的是，在N等于1的情况下，延时模块12只包括一个延时子模块，相应的译码信号也只有一个，该延时子模块即目标延时模块。这时候，该延时子模块的第一输入端与初始命令信号连接，第二输入端与地信号连接(即接地连接)，同时该延时子模块还与外部时钟信号连接。该延时子模块接收唯一的译码信号，并根据外部时钟信号对初始命令信号进行延时处理，得到目标命令信号。
还需要说明的是，当N等于1时，只有一个唯一的延时子模块作为目标延时模块，无法满足多种不同的工作频率的要求。因此，在本公开实施例中，N通常大于1，也就是说，该延时控制电路应用多种不同的频率场景下，根据工作频率(即外部时钟信号的时钟频率)选择不同数量的延时子模块作为目标延时模块，适用于DRAM的多种频率场景，可以灵活切换，适配性更强。
当N大于1时，第1个延时子模块的第二输入端与地信号连接，第i个延时子模块的第二输入端与第i-1个延时子模块的输出端连接，第N个延时子模块的输出端用于输出目标命令信号，i为大于1且小于或等于N的整数。
需要说明的是，如图3所示，在N大于1时，每一个延时子模块的第一输入端与初始命令信号连接，每一个延时子模块的时钟端与外部时钟信号连接。每一个延时子模块接收对应的译码信号；第一个延时子模块(即延时子模块1)的第二输入端与地信号连接，即接地连接；第2个至第N-1个延时子模块的输出端均与下一个延时子模块的第二输入端连接，从而每个延时子模块将延迟处理后的信号发送到下一个延时子模块第二输入端；最后一个(第N个)延时子模块(延时子模块N)的输出端输出目标命令信号。
进一步地，在一些实施例中，译码模块11，还配置为在生成至少一个译码信号的过程中，若第j个译码信号为第一值，则确定除第j个译码信号之外的其他译码信号均为第二值；其中，第一值与第二值不同，且j为大于0且小于或等于N的整数。
需要说明的是，第一值具体可以为高电平的“逻辑1”，第二值具体可以为低电平的“逻辑0”，即N个译码信号中只会存在一个译码信号的取值为“逻辑1”，其余的译码信号的取值均为逻辑“0”。如果译码信号为第一值，则对应的延时子模块的第一输入端开启且第二输入端关闭，从而该译码模块的输入信号为第一输入端接收到的信号，即初始命令信号；如果译码信号为第二值，则对应的延时子模块的第一输入端关闭且第二输入端开启，则该延时子模块的输入信号为 第二输入端接收到的信号，即前一延时子模块输出的信号，对于第一个延时子模块，第二收入端接收的是地信号。
另外，第一值具体也可以为低电平的“逻辑0”，第二值具体也可以为高电平的“逻辑0”，这里不作具体限定。
这样，N个延时子模块中只有一个延时子模块(记为第j个延时子模块)的第一输入端成功接收初始命令信号，由于第一个延时子模块的第二输入端连接地信号，从而第j个延时子模块之前的延时子模块均接地，第j个延时子模块以及之后的所有延时子模块被选择作为目标延时模块，这样，在根据译码信号确定目标延时模块时，能够精准确定出被选择的延时子模块，避免出现错误。
也就是说，在本公开实施例中，第j个延时子模块与第j个译码信号之间具有对应关系，其中：
延时模块12，配置为在第j个译码信号的取值为第一值的情况下，将第j个延时子模块至第N个延时子模块确定为目标延时模块；以及通过第j个延时子模块至第N个延时子模块对初始命令信号进行延时处理，得到目标命令信号。
需要说明的是，如图3所示，一个译码信号与一个延时子模块之间具有对应关系，延时子模块1对应接收译码信号1，延时子模块2对应接收译码信号2，…，延时子模块N对应接收译码信号N。当延时子模块j接收到的译码信号j的取值为第一值时，延时子模块j以及延时子模块j之后的延时子模块就被确定为目标延时模块。由选中的目标延时模块对初始命令信号进行延时处理，得到目标命令信号。
例如，如果延时子模块1接收到的译码信号1的取值为第一值，其余的译码信号的取值均为第二值，则延时子模块1至延时子模块N就被选中作为目标延时模块；如果延时子模块2接收到的译码信号2的取值为第一值，其余的译码信号的取值均为第二值，则延时子模块2至延时子模块N就被选中作为目标延时模块；…；如果延时子模块N接收到的译码信号N的取值为第一值，其余的译码信号的取值均为第二值，则延时子模块N就被选中作为目标延时模块。
这样，通过这种方式选择目标延时模块，能够保证准确选择出目标延时模块，避免出现错误。另外，N个延时子模块级联在一起，保证第一值对应的延时子模块及之后的延时子模块都被选中作为目标延时模块，利用选择出的目标延时模块对初始命令信号的延时处理，还能够节省电路结构，充分利用电路中的各器件，避免器件浪费。
进一步地，参见图4，其示出了本公开实施例提供的一种延时控制电路10的具体结构示意图。如图4所示，在一些实施例中，第j个延时子模块包括第j个选择模块和第j个移位寄存模块，且第j个选择模块的第一输入端用于接收初始命令信号，第j个选择模块的第二输入端用于接收第一输入信号，第j个选择模块的输出端与第j个移位寄存模块的输入端连接，其中：
第j个选择模块，配置为接收第j个译码信号，根据第j个译码信号在初始命令信号和第一输入信号中选择第j个目标输入信号；
第j个移位寄存模块，配置为接收外部时钟信号和第j个目标输入信号，根据外部时钟信号对第j个目标输入信号进行延时处理，得到第j个目标输出信号；
其中，当j等于1时，第一输入信号为地信号；当j大于1且小于或者等于 N时，第一输入信号为第j-1个移位寄存模块输出的第j-1个目标输出信号；以及，当j等于N时，第N个目标输出信号为目标命令信号。
需要说明的是，如图4所示，每一个延时子模块由一个选择模块和一个移位寄存模块组成，即：延时子模块1(第1个延时子模块)由选择模块1(第1个选择模块)和移位寄存模块1(第1个移位寄存模块组成)，延时子模块2(第2个延时子模块)由选择模块2(第2个选择模块)和移位寄存模块2(第2个移位寄存模块组成)，…，延时子模块N(第N个延时子模块)由选择模块N(第N个选择模块)和移位寄存模块N(第N个移位寄存模块组成)。
在每一个延时子模块中，选择模块配置为接收对应的译码信号，即：选择模块1接收译码信号1(第1个译码信号)，选择模块2接收译码信号2(第2个译码信号)，…，选择模块N接收译码信号N(第N个译码信号)。
每一个选择模块均包括第一输入端、第二输入端、控制端和输出端。其中，第j个选择模块的第一输入端即第j个延时子模块的第一输入端，第j个选择模块的第二输入端即第j个延时子模块的第二输入端，第j个选择模块的控制端即第j个延时子模块的控制端。
其中，对于每一个选择模块而言，第一输入端用于接收初始命令信号，控制端用于接收对应的译码信号，第二输入端用于接收第一输入信号。如图4所示，对于第一个延时子模块中的选择模块，选择模块1的第二输入端为接地连接，用于接收地信号；对于第二个至第N个延时子模块中的选择模块，第二输入端与前一延时子模块中的移位寄存模块的输出端连接，用于接收前一延时子模块中的移位寄存模块输出的目标输出信号；每一个选择模块根据接收到的译码信号从初始命令信号和第一输入信号选择一者作为目标输入信号。
对于第一个至第N-1个延时子模块中的任一个，其中的选择模块的输出端与移位寄存模块的输入端连接，移位寄存模块的时钟端用于接收外部时钟信号，移位寄存模块根据外部时钟信号将选择模块选择的目标输入信号进行延时处理后，得到目标输出信号，输出至下一个选择模块的第二输入端。在延时子模块N中，移位寄存模块N输出的就是目标命令信号。
这样，由选择模块根据译码信号选择初始命令信号或者第一输入信号作为延时子模块的输入信号，从而实现根据译码信号选择目标延时模块，进而实现对初始命令信号的延时处理。
参见图5，其示出了本公开实施例提供的另一种延时控制电路10的具体结构示意图。如图5所示，对于移位寄存模块而言，在一些实施例中，第j个移位寄存模块包括M个移位寄存器，每一个移位寄存器的时钟端均与外部时钟信号连接，M为大于0的整数，其中：
当M等于1时，第一个移位寄存器的输入端与第j个选择模块的输出端连接，第一个移位寄存器的输出端用于输出第j个目标输出信号。
需要说明的是，在移位寄存模块只包括一个移位寄存器的情况下，第一个移位寄存器为该移位寄存模块中唯一的移位寄存器，该移位寄存器接收其所属的延时子模块中的选择模块选择的目标输入信号，并根据外部时钟信号对目标输入信号进行延时处理得到目标输出信号。对于第一个至第N-1个移位寄存模块，目标输出信号会传输给下一个延时子模块中的选择模块。对于第N个移位寄存模块， 移位寄存器的输出端输出的就是目标命令信号。
当M大于1时，第一个移位寄存器的输入端与第j个选择模块的输出端连接，第y个移位寄存器的输入端与第y-1个移位寄存器的输出端连接，第M个移位寄存器的输出端用于输出第j个目标输出信号；其中，y为大于1且小于或者等于M的整数。
需要说明的是，在M大于1时，即移位寄存模块包括多个移位寄存器的情况下，M个移位寄存器级联，其中的第一个移位寄存器的输入端与其所属的延时子模块中的选择模块的输出端连接，用于接收选择模块选择的目标输入信号，对目标输入信号进行延时处理后传输至下一个移位寄存器，并依次进行延迟处理后得到目标输出信号传递给下一个延时子模块中的选择模块，最终在第N个延时子模块的最后一个移位寄存器的输出端得到目标命令信号。
还需要说明的是，每个延时子模块所包括的移位寄存器的数量M可以相同，也可以不同，或者是部分相同，需要结合具体的频率需求进行确定。例如，N个译码信号对应N种移位寄存器的数量，这些数量在设计延时控制电路时就是对照相对应的频率(即存储器应用的工作频率，也就是外部时钟信号的时钟频率)设置的，然后在使用时，就可以根据具体的频率，选择对应数量的移位寄存器的数量，实现对初始命令信号的延时处理。
例如，延时模块12包括四个延时子模块，第一个延时子模块包括3个移位寄存器，第二个延时子模块包括5个移位寄存器，第三个延时子模块包括4个移位寄存器。在第一种工作模式下，外部时钟信号的时钟频率为第一频率，需要4个移位寄存器，则第三个译码信号为第一值，其余的译码信号为第二值，第三延时子模块被确定为目标延时模块；在第二种工作模式下，外部时钟信号的时钟频率为第二频率，需要9个移位寄存器，则第二个译码信号为第一值，其余的译码信号为第二值，第二延时子模块和第三延时子模块被确定为目标延时模块；在第三种工作模式下，外部时钟信号的时钟频率为第三频率，对应需要12个移位寄存器，则第一个译码信号为第一值，其余的译码信号为第二值，第一延时子模块、第二延时子模块和第三延时子模块被确定为目标延时模块。
这样，根据频率预先设定对应每种工作频率的移位寄存器的数量，在对初始命令信号进行延时时，只需要知晓用于延时的外部时钟信号的频率，就可以选择对应的延时子模块作为目标延时模块，实现对外部时钟信号的精确延时，得到目标时钟信号。
还需要说明的是，如图5所示，选择模块可以为二选一选择器(2-1MUX)，其中，“1”表示第一输入端，“0”表示第二输入端，当对应的译码信号为第一值时，表示选择1，第一输入端开启，选中初始命令信号传输；当对应的译码信号为第二值时，表示选择0，第二输入端开启，选中第一输入信号传输。
另外，如图5所示，在本公开实施例中，至少一个译码信号可以合并写作OPDEC<n:0>，表示对模式寄存器信号进行译码处理之后得到的信号，OPDEC<n:0>包括OPDEC<0>、OPDEC<1>、OPDEC<2>、…、OPDEC<n>共n+1个信号。与N个译码信号对应，OPDEC<0>表示译码信号1，OPDEC<1>表示译码信号2、OPDEC<2>表示译码信号3、…、OPDEC<n>表示译码信号N。
在本公开实施例，每一个移位寄存器用于将移位寄存器的输入端接收到的信 号延迟第一时钟周期进行输出。
需要说明的是，一个移位寄存器将信号延时的时长为第一时钟周期，如果目标延时模块总共包括Z个移位寄存器，则第一时钟周期和Z的乘积为预设时序条件要求的时间间隔。
进一步地，第一时钟周期的具体值和外部时钟信号的频率以及移位寄存器的结构有关。在一些实施例中，移位寄存器包括L个触发器，且L个触发器串接在一起，L为大于0的整数，其中：L个触发器的时钟端均与外部时钟信号连接，触发器的输出端与下一个触发器的输入端连接。
触发器，用于将触发器的输入端接收到的信号延迟第二时钟周期进行输出；其中，第一时钟周期等于第二时钟周期与L的乘积，第二时钟周期等于外部时钟信号的时钟周期。
需要说明的是，移位寄存器由L个串接的触发器组成，对于每一个移位寄存器，L值均相同(不同移位寄存器的L值也可以不同，但是需要较复杂的设计和计算，本公开实施例以每个移位寄存器所包括的触发器数量均相同为例)。触发器可以为D触发器(D Flip-Flop，DFF)，一个触发器可以将信号延迟第二时钟周期，这里的第二时钟周期与当前的外部时钟信号的时钟周期相同。也就是说，触发器能够实现将信号延时外部信号的时钟周期对应的时长，具体的时长与外部时钟信号自身相关。
具体地，当L等于4时，参见图6，其示出了本公开实施例提供的一种移位寄存器的具体结构示意图。如图6所示，移位寄存器包括第一触发器DFF1、第二触发器DFF2、第三触发器DFF3和第四触发器DFF4，其中：
第一触发器DFF1、第二触发器DFF2、第三触发器DFF3和第四触发器DFF4的时钟端均与外部时钟信号CK_t连接；
第一触发器DFF1的输入端与对应的选择模块的输出端连接，第一触发器DFF1的输出端与第二触发器DFF2的输入端连接；
第二触发器DFF2的输出端与第三触发器DFF3的输入端连接；
第三触发器DFF3的输出端与第四触发器DFF4的输入端连接；
第四触发器DFF4的输出端用于输出移位寄存器的输出信号。
需要说明的是，对于每个移位寄存器，其结构均可以如图6所示，只是对于不同位置的移位寄存器，其输入和输出不同。这样，经过4个DFF的延时，能够将输入该移位寄存器中的信号延时4个第二时钟周期(即4个外部时钟信号CK_t的时钟周期)。
进一步地，如图5所示，在一些实施例中，延时控制电路10还可以包括缓冲模块13，其中，缓冲模块13，配置为接收ECS命令信号，并根据ECS命令信号生成初始命令信号。
需要说明的是，当DRAM处于ECS模式时，初始命令信号为激活信号时，初始命令信号可以是基于ECS信号产生的，因此还可以通过缓冲模块13根据ECS命令信号来得到初始命令信号，并进一步对初始命令信号进行如前述的处理，最终得到目标命令信号。
其中，ECS信号支持下述两种操作模式：基于MPC命令的手动ECS操作模式和基于自刷新命令的自动ECS操作模式。
需要说明的是，ECS信号用于指示存储器执行ECS操作，在执行ECS操作期间，存储器会内部自产生命令信号，如ACT、RD、WR等等。本公开实施例主要应用于MPC命令产生的手动ECS操作和刷新(Refresh，可以简写为REFab)命令产生的自动ECS操作。
另外，在这里，缓冲模块(Buffer)也可以称为“传输门”，不仅具有延时功能，而且还可以具有增强信号驱动能力的作用。具体地，对于ECS命令信号与初始命令信号而言，初始命令信号相比ECS命令信号不仅存在时延，而且初始命令信号的驱动能力更强。
为了进一步描述延时控制电路10的具体实现，参见图7，其示出了本公开实施例提供的一种延时模块12的具体结构示意图。如图7所示，在一种具体的示例中，至少一个译码信号包括第一译码信号OPDEC<0>和第二译码信号OPDEC<1>，至少一个延时子模块包括第一延时子模块121和第二延时子模块122，第一延时子模块121包括第一选择模块1211和第一移位寄存模块1212，第二延时子模块122包括第二选择模块1221和第二移位寄存模块1222，其中，
在外部时钟信号CK_t的时钟频率为第一工作频率的情况下，第二译码信号OPDEC<1>为第一值，第一译码信号OPDEC<0>为第二值，确定第二延时子模块122为目标延时模块，以及通过第二选择模块1221将初始命令信号ECT_ACT输入到第二移位寄存模块1222，通过第二移位寄存模块1222对初始命令信号进行延时处理，得到目标命令信号；
在外部时钟信号CK_t的时钟频率为第二工作频率的情况下，第一译码信号OPDEC<0>为第一值，第二译码信号OPDEC<1>为第二值，确定第一延时子模块121和第二延时子模块122为目标延时模块，以及通过第一选择模块1211将初始命令信号ECT_ACT输入到第一移位寄存模块1212，通过第一移位寄存模块1212对初始命令信号ECT_ACT进行第一延时处理，得到中间命令信号RD<2>，通过第二选择模块1221将中间命令信号RD<2>输入到第二移位寄存模块1222，通过第二移位寄存模块1222对中间命令信号RD<2>进行第二延时处理，得到目标命令信号ECT_RD。
需要说明的是，在图7中，以延时模块12包括第一延时子模块121和第二延时子模块122为例对本公开实施例的具体实现进行示例性说明，这并不构成对本公开的限定。
如图7所示，在第一延时子模块121中，第一选择模块1211的第一输入端与初始命令信号ECT_ACT信号连接(这里的初始命令信号以存储器执行ECS操作时生成的激活信号ECS_ACT为例)，第一选择模块1211的第二输入端与地信号VSS连接，第一选择模块1211的输出端与第一移位寄存模块1212的输入端连接。在图7中，第一移位寄存模块1212包括三个移位寄存器(移位寄存器0、移位寄存器1和移位寄存器2)，三个移位寄存器级联，每个移位寄存器的时钟端均与外部时钟信号连接，移位寄存器0的输入端作为第一移位寄存模块1212的输入端，移位寄存器0的输出端与移位寄存器1的输入端连接，移位寄存器1的输出端与移位寄存器2的输入端连接，移位寄存器2的输出端与第二选择模块1221的第二输入端连接，作为第一移位寄存模块1212的输出端。
在第二延时子模块122中，第二选择模块1221的第一输入端与初始命令信 号ECT_ACT连接，第二选择模块1221的输出端与第二移位寄存模块1222的输入端连接。如图7所示，第二移位寄存模块1222包括六个移位寄存器(移位寄存器3、移位寄存器4、移位寄存器5、移位寄存器6、移位寄存器7和移位寄存器8)，六个移位寄存器级联，每个移位寄存器的时钟端均与外部时钟信号连接，移位寄存器3的输入端作为第二延时子模块122的输入端，移位寄存器8的输出端作为第二延时子模块122的输出端。
以预设时序条件要求的时间间隔为15ns为例，如果外部时钟信号的工作频率为第一工作频率(3200Mbps)，相应的时钟周期为0.625ns，延迟15ns即24个时钟周期，一个移位寄存器包括4个触发器，能够实现延迟4个时钟周期，则需要6个移位寄存器。第二延时子模块122包括六个移位寄存器，即在这种情况下，需要将第二延时子模块122确定为目标延时模块。因此，根据译码模块11的译码结果，确定第二译码信号OPDEC<1>的取值为第一值，第一译码信号OPDEC<0>的取值为第二值，其中，第一值可以为“逻辑1”，第二值可以为“逻辑0”。
如图7所示，第一选择模块1211根据第一译码信号OPDEC<0>确定选择0(第二输入端)处的信号，即选择地信号输入第一延时子模块121，则第一延时子模块121被连接到地；第二选择模块1221根据第二译码信号OPDEC<1>确定选择1(第一输入端)处的信号，即选择初始命令信号RCS_ACT作为输入第二延时子模块122的信号。
这时候，由第二延时子模块122作为目标延时模块对初始命令信号RCS_ACT进行延时处理，将移位寄存器0至移位寄存器7输出的信号分别记作RD<0>、RD<1>、RD<2>…RD<7>，移位寄存器8输出的信号为目标命令信号，记作ECS_RD。图8为在时钟频率为3200Mbps时，各信号的时序示意图。如图8所示，外部时钟信号的时钟周期t CK_t＝0.625ns，第一延时子模块121的输入信号为地信号，因此，RD<0>、RD<1>和RD<2>均维持低电平状态。第二延时子模块122的输入信号为目标命令信号，并依次经过移位寄存器3至移位寄存器8进行延时处理，每个移位寄存器延时4个时钟周期，则每个移位寄存器的输出信号相对于上一个移位寄存器的输出信号延迟4个时钟周期，经过6个移位寄存器，最终得到的目标命令信号ECS_RD相对初始命令信号ECS_ACT延时24个时钟周期，即15ns。
如果外部时钟信号的工作频率为第二工作频率(4800Mbps)，相应的时钟周期为0.416ns，延迟15ns即36个时钟周期，需要9个移位寄存器。第一延时子模块121和第二延时子模块122共包括9个移位寄存器，即在这种情况下，需要将第一延时子模块121和第二延时子模块122确定为目标延时模块。因此，根据译码模块11的译码结果，确定第一译码信号OPDEC<0>的取值为第一值，第二译码信号OPDEC<1>的取值为第二值。
这时候，由第一延时子模块121和第二延时子模块122作为目标延时模块对初始命令信号RCS_ACT进行延时处理。图9为在时钟频率为4800Mbps时，各信号的时序示意图。如图9所示，外部时钟信号的时钟周期t CK_t＝0.416ns，第一延时子模块121的输入信号为初始命令信号ECS_ACT，第二延时子模块122的输入信号为第一延时子模块121输出的信号。因此，初始命令信号ECS_ACT依次经过移位寄存器0至移位寄存器8进行延时处理，每个移位寄存器延时4个时 钟周期，则每个移位寄存器的输出信号相对于上一个移位寄存器的输出信号延迟4个时钟周期，经过9个移位寄存器，最终得到的目标命令信号ECS_RD相对初始命令信号ECS_ACT延时36个时钟周期，即15ns。
结合图8和图9所示，对于不同时钟频率的外部时钟信号，本公开实施例均实现了初始命令信号和目标命令信号之间的时间间隔为15ns。
简言之，本公开实施例设计的延时控制电路通过在不同的工作频率下，利用外部时钟信号CK_t来移动命令信号不同次数的的时钟周期，来满足tRCD的延时要求，同时保证不同频率下tRCD的延时基本相同。根据DDR5的tRCD时序要求，在不同频率下nRCD数目(nRCD是当前频率下设置的周期数目，一般情况下nRCD与周期的乘积需要大于或者等于tRCD)不同，因此，需要一个判断当前频率的模式寄存器信号。因为不同频率的外部时钟信号的时钟周期不同，频率大的CK_t的周期值小，所以延迟相同的时间所需要的移位寄存器要多，因此要实现tRCD的时序要求需要知道具体频率的数值或者数值范围，才能通过选择电路选择相应数量的移位寄存器来满足tRCD的时序。
由于不同频率下，模式寄存器的tCCD_L值是不同的，所以本公开实施例可以利用tCCD_L的值来判断当前频率，并且确定相应频率下，tRCD所需的移位数目(即移位几个时钟周期)。由此可以在不同频率下，通过相应数目的时序移位，来实现固定tRCD的时序要求。由于本公开实施例利用了CK_t作为将初始命令信号进行延时的移位时钟，所以本公开实施例主要适用于MPC命令产生的手动ECS操作和刷新命令产生的自动ECS操作。
在具体实现过程中，通过对模式寄存器信号MR13OP<3:0>进行译码处理知道具体tCCD_L的大小，从而可以解析出对应外部时钟信号CK_t具体频率，进而得到至少一个译码信号，通过选择器根据译码信号选择移位寄存器的数量来实现不同频率下的延迟。本公开实施例通过多个移位寄存器级联的形式，外部时钟信号CK_t作为移位寄存器的时钟信号，模式寄存器信号MR12OP<3:0>译码之后的至少一个译码信号OPDEC<n:0>作为选择信号，控制初始命令信号ECS_ACT通过哪个选择器作为移位寄存器的输入，从而控制初始命令信号ECS_ACT到目标命令信号ECS_RD的移位数目(即移位几个时钟周期)。
以一个移位寄存器由4个DFF组成为例(参照图6)，一个移位寄存器可以将信号延迟4个时钟周期(tCK)。对于时钟频率为m的外部时钟信号，延迟15ns需要n个移位寄存器。以频率分别为3200Mbps和4800Mbps为例(参照图7)，3200Mbps对应的时钟周期为0.625ns，延迟15ns需要6个寄存器，也就是24个DFF，4800Mbps对应的时钟周期为0.416ns，延迟15ns需要9个寄存器，也就是36个DFF。
频率4800Mbps和3200Mbps的移位寄存器信号MR13OP<3:0>对应的译码信号分别为OPDEC<0>和OPDEC<1>。在频率为4800Mbps时，OPDEC<0>为第一值，第一选择模块1211的第一输入端开启，第二输入端关闭；OPDEC<1>为第二值，第二选择模块1221的第一输入端关闭，第二输入端开启，初始命令信号ECS_ACT从第一选择模块1211的第一输入端进入，经过9个移位寄存器的延时处理，最终输出的目标命令信号ECS_RD满足tRCD为15ns。在频率为3200Mbps时，OPDEC<0>为第二值，第一选择模块1211的第一输入端关闭，第二输入端 开启；OPDEC<1>为第一值，第二选择模块1221的第一输入端开启，第二输入端关闭，移位寄存器0至移位寄存器2的输入为VSS，因此输出RD<0>至RD<2>均为0，初始命令信号ECS_ACT从第二选择模块1221的第一输入端进入，经过6个移位寄存器的延时处理，最终输出的目标命令信号ECS_RD满足tRCD为15ns。从图8和图9的时序示意图可以看出，虽然外部时钟信号CK_t的周期不同，但目标命令信号ECS_RD都距初始命令信号ECS_ACT延迟15ns。
本公开实施例提供了一种延时控制电路，包括：译码模块和延时模块，其中：译码模块，配置为接收模式寄存器信号，对模式寄存器信号进行译码处理，生成至少一个译码信号；延时模块包括至少一个延时子模块，配置为根据至少一个译码信号从至少一个延时子模块中确定被选择的目标延时模块，根据目标延时模块和外部时钟信号对接收到的初始命令信号进行延时处理，得到目标命令信号；其中，目标命令信号与初始命令信号之间的时间间隔满足预设时序条件。这样，基于模式寄存器信号得到至少一个译码信号，进而根据至少一个译码信号从至少一个延时子模块中确定目标延时模块，由目标延时模块根据外部时钟信号对初始命令信号进行延时处理，得到目标命令信号，使得目标命令信号和初始命令信号之间的时间间隔满足预设时序条件。通过该延时控制电路，还能够满足存储器内部自产生任意命令信号之间的时序控制要求，提升存储器性能。另外，对模块寄存器进行译码处理能够得到外部时钟信号的时钟频率，从而至少一个选择信号是根据外部时钟信号的时钟频率确定的，使得最终选择的目标延时模块是与当前的外部时钟信号的时钟频率相对应的，进而在对初始命令信号进行延时处理时，由于目标延时模块是与外部时钟信号相适配的，保证在不同的时钟频率下，都能够使得目标命令信号和初始命令信号之间的时间间隔满足预设时序条件。
本公开的另一实施例中，参见图10，其示出了本公开实施例提供的一种延时控制方法的流程示意图。如图10所示，该方法可以包括：
S1001：通过译码模块接收模式寄存器信号，对模式寄存器信号进行译码处理，生成至少一个译码信号。
S1002：通过延时模块接收至少一个译码信号、初始命令信号和外部时钟信号，根据至少一个译码信号从延时模块包括的至少一个延时子模块中确定被选择的目标延时模块，以及根据目标延时模块和外部时钟信号对初始命令信号进行延时处理，得到目标命令信号。
其中，目标命令信号与初始命令信号之间的时间间隔满足预设时序条件。
需要说明的是，本方法应用于前述实施例提供的延时控制电路。
在一些实施例中，对模式寄存器信号进行译码处理，生成至少一个译码信号，可以包括：对模式寄存器信号进行译码处理，确定延时时间间隔；根据延时时间间隔，生成至少一个译码信号；延时时间间隔与外部时钟信号的时钟频率之间具有对应关系。
在一些实施例中，该方法还可以包括：在生成至少一个译码信号的过程中，若第j个译码信号为第一值，则确定除第j个译码信号之外的其他译码信号均为第二值；其中，第一值与第二值不同，且j为大于0且小于或等于N的整数。
在一些实施例中，第j个延时子模块与第j个译码信号之间具有对应关系，根据至少一个译码信号从延时模块包括的至少一个延时子模块中确定被选择的 目标延时模块，可以包括：在第j个译码信号的取值为第一值的情况下，将第j个延时子模块至第N个延时子模块确定为目标延时模块；以及通过第j个延时子模块至第N个延时子模块对初始命令信号进行延时处理，得到目标命令信号。
在一些实施例中，通过第j个延时子模块至第N个延时子模块对初始命令信号进行延时处理，得到目标命令信号，可以包括：
通过第j个选择模块接收第j个译码信号，根据第j个译码信号在初始命令信号和第一输入信号中选择第j个目标输入信号；
通过第j个移位寄存模块接收外部时钟信号和第j个目标输入信号，根据外部时钟信号对第j个目标输入信号进行延时处理，得到第j个目标输出信号；
其中，当j等于1时，第一输入信号为地信号；当j大于1且小于或者等于N时，第一输入信号为第j-1个移位寄存模块输出的第j-1个目标输出信号；以及，当j等于N时，第N个目标输出信号为目标命令信号。
在一些实施例中，初始命令信号包括激活信号，目标命令信号包括读信号，或者；初始命令信号包括读信号，目标命令信号包括写信号，或者；初始命令信号包括写信号，目标命令信号包括预充电信号。
在一些实施例中，该方法还可以包括：通过缓冲模块接收ECS信号，并对ECS信号进行延时与驱动增强处理，得到初始命令信号。
在一些实施例中，ECS信号用于指示执行ECS操作，且ECS信号是根据多用途控制MPC命令信号或者刷新信号生成的。
本公开实施例提供的延时控制方法可以应用于前述的延时控制电路10，对于本公开实施例未披露的细节，请参照前述实施例的描述而理解。
本公开实施例提供了一种延时控制方法，基于该方法对初始命令信号进行处理得到目标命令信号，使得目标命令信号和初始命令信号之间的时间间隔满足预设时序条件，进而能够满足存储器内部自产生命令之间的时序控制要求，提升存储器性能。
本公开的再一实施例中，参见图11，其示出了本公开实施例提供的一种半导体存储器20的组成结构示意图。如图11所示，该半导体存储器20至少包括前述实施例任一项所述的延时控制电路10。
在一些实施例中，该半导体存储器20包括DRAM。
在本公开实施例中，对于DRAM来说，不仅可以符合DDR、DDR2、DDR3、DDR4、DDR5等内存规格，还可以符合LPDDR、LPDDR2、LPDDR3、LPDDR4、LPDDR5等内存规格，这里不作任何限定。
在本公开实施例中，对于该半导体存储器20而言，由于其包括前述实施例所述的延时控制电路，能够满足存储器内部自产生命令之间的时序控制要求，提升存储器性能。
以上所述，仅为本公开的较佳实施例，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置 中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或电路实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或电路实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例基于模式寄存器信号可以生成至少一个译码信号，进而根据这至少一个译码信号来确定目标延时模块，然后基于目标延时模块，由外部时钟信号对初始命令信号进行延时处理，得到目标命令信号，此时的目标命令信号和初始命令信号之间的时间间隔满足预设时序条件；如此，该延时控制电路能够满足存储器内部自产生命令之间的时序控制要求，同时由于这至少一个译码信号与外部时钟信号的时钟频率相关，从而还能够选择出与外部时钟信号的时钟频率相对应的目标延时模块，使得在不同的时钟频率下，命令信号之间的时间间隔均满足预设时序条件，进而提升存储器的性能。

Claims (15)

  1. 一种延时控制电路，包括译码模块和延时模块，其中：
    所述译码模块，配置为接收模式寄存器信号，对所述模式寄存器信号进行译码处理，生成至少一个译码信号；
    所述延时模块包括至少一个延时子模块，配置为根据所述至少一个译码信号从所述至少一个延时子模块中确定被选择的目标延时模块，根据所述目标延时模块和外部时钟信号对接收到的初始命令信号进行延时处理，得到目标命令信号；其中，所述目标命令信号与所述初始命令信号之间的时间间隔满足预设时序条件。
  2. 根据权利要求1所述的延时控制电路，其中，所述译码模块，具体配置为对所述模式寄存器信号进行译码处理，确定延时时间间隔；根据所述延时时间间隔，生成所述至少一个译码信号；其中，所述延时时间间隔与所述外部时钟信号的时钟频率之间具有对应关系。
  3. 根据权利要求1所述的延时控制电路，其中，所述至少一个延时子模块的数量为N个，N为大于0的整数，其中：
    在所述至少一个延时子模块中，每一个所述延时子模块的第一输入端均与所述初始命令信号连接；
    当N等于1时，所述延时子模块的第二输入端与地信号连接，所述延时子模块的输出端用于输出所述目标命令信号；
    当N大于1时，第1个延时子模块的第二输入端与地信号连接，第i个延时子模块的第二输入端与第i-1个延时子模块的输出端连接，第N个延时子模块的输出端用于输出所述目标命令信号，i为大于1且小于或等于N的整数。
  4. 根据权利要求3所述的延时控制电路，其中，所述译码模块，还配置为在生成所述至少一个译码信号的过程中，若第j个译码信号为第一值，则确定除所述第j个译码信号之外的其他译码信号均为第二值；其中，所述第一值与所述第二值不同，且j为大于0且小于或等于N的整数。
  5. 根据权利要求4所述的延时控制电路，其中，第j个延时子模块与第j个译码信号之间具有对应关系，其中：
    所述延时模块，配置为在所述第j个译码信号的取值为第一值的情况下，将所述第j个延时子模块至第N个延时子模块确定为所述目标延时模块；以及通过所述第j个延时子模块至第N个延时子模块对所述初始命令信号进行延时处理，得到所述目标命令信号。
  6. 根据权利要求5所述的延时控制电路，其中，所述第j个延时子模块包括第j个选择模块和第j个移位寄存模块，且所述第j个选择模块的第一输入端用于接收所述初始命令信号，所述第j个选择模块的第二输入端用于接收第一输入信号，所述第j个选择模块的输出端与所述第j个移位寄存模块的输入端连接，其中：
    所述第j个选择模块，配置为接收所述第j个译码信号，根据所述第j个译码信号在所述初始命令信号和所述第一输入信号中选择第j个目标输入信号；
    所述第j个移位寄存模块，配置为接收所述外部时钟信号和所述第j个目标 输入信号，根据所述外部时钟信号对所述第j个目标输入信号进行延时处理，得到第j个目标输出信号；
    其中，当j等于1时，所述第一输入信号为所述地信号；当j大于1且小于或者等于N时，所述第一输入信号为第j-1个移位寄存模块输出的第j-1个目标输出信号；以及，当j等于N时，第N个目标输出信号为所述目标命令信号。
  7. 根据权利要求6所述的延时控制电路，其中，所述第j个移位寄存模块包括M个移位寄存器，每一个所述移位寄存器的时钟端均与所述外部时钟信号连接，M为大于0的整数，其中：
    当M等于1时，第一个所述移位寄存器的输入端与第j个选择模块的输出端连接，第一个所述移位寄存器的输出端用于输出所述第j个目标输出信号；
    当M大于1时，第一个所述移位寄存器的输入端与第j个选择模块的输出端连接，第y个所述移位寄存器的输入端与第y-1个所述移位寄存器的输出端连接，第M个所述移位寄存器的输出端用于输出所述第j个目标输出信号；其中，y为大于1且小于或者等于M的整数。
  8. 根据权利要求7所述的延时控制电路，其中，所述移位寄存器，用于将所述移位寄存器的输入端接收到的信号延迟第一时钟周期进行输出。
  9. 根据权利要求8所述的延时控制电路，其中，所述移位寄存器包括L个触发器，且所述L个触发器串接在一起，L为大于0的整数，其中：
    所述L个触发器的时钟端均与所述外部时钟信号连接，所述触发器的输出端与下一个所述触发器的输入端连接。
  10. 根据权利要求1至9任一项所述的延时控制电路，其中，所述初始命令信号包括激活信号，所述目标命令信号包括读信号；或者，所述初始命令信号包括读信号，所述目标命令信号包括写信号；或者，所述初始命令信号包括写信号，所述目标命令信号包括预充电信号。
  11. 根据权利要求1至9任一项所述的延时控制电路，其中，所述延时控制电路还包括缓冲模块，其中：
    所述缓冲模块，配置为接收错误检查与清除ECS信号，并根据所述ECS信号生成所述初始命令信号。
  12. 根据权利要求11所述的延时控制电路，其中，所述ECS信号支持下述两种操作模式：基于MPC命令的手动ECS操作模式和基于自刷新命令的自动ECS操作模式。
  13. 一种延时控制方法，应用于延时控制电路，所述方法包括：
    通过译码模块接收模式寄存器信号，对所述模式寄存器信号进行译码处理，生成至少一个译码信号；
    通过延时模块接收所述至少一个译码信号、初始命令信号和外部时钟信号，根据所述至少一个译码信号从所述延时模块包括的至少一个延时子模块中确定被选择的目标延时模块，以及根据所述目标延时模块和所述外部时钟信号对所述初始命令信号进行延时处理，得到目标命令信号；
    其中，所述目标命令信号与所述初始命令信号之间的时间间隔满足预设时序条件。
  14. 一种半导体存储器，所述半导体存储器包括如权利要求1至12任一项所 述的延时控制电路。
  15. 根据权利要求14所述的半导体存储器，其中，所述半导体存储器包括动态随机存取存储器DRAM。
PCT/CN2022/127103 2022-10-08 2022-10-24 一种延时控制电路、方法和半导体存储器 WO2024073909A1 (zh)

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