WO2024073910A1 - 一种延时控制电路、方法和半导体存储器 - Google Patents

一种延时控制电路、方法和半导体存储器 Download PDF

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Publication number
WO2024073910A1
WO2024073910A1 PCT/CN2022/127123 CN2022127123W WO2024073910A1 WO 2024073910 A1 WO2024073910 A1 WO 2024073910A1 CN 2022127123 W CN2022127123 W CN 2022127123W WO 2024073910 A1 WO2024073910 A1 WO 2024073910A1
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signal
clock
module
value
clock signal
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PCT/CN2022/127123
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English (en)
French (fr)
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黄泽群
孙凯
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长鑫存储技术有限公司
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Priority to US18/446,508 priority Critical patent/US20240127881A1/en
Publication of WO2024073910A1 publication Critical patent/WO2024073910A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G06F1/206—Cooling means comprising thermal management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H03K2005/00241—Layout of the delay element using circuits having two logic levels using shift registers

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a delay control circuit, method and semiconductor memory.
  • DDR double data rate
  • DRAM Dynamic Random Access Memory
  • ECS Error Check and Scrub
  • Embodiments of the present disclosure provide a delay control circuit, method and semiconductor memory.
  • an embodiment of the present disclosure provides a delay control circuit, including a clock module and a delay module, wherein:
  • the clock module is configured to receive a temperature adjustment signal, generate a first clock signal according to the temperature adjustment signal, and a clock period of the first clock signal is a preset value;
  • the delay module is configured to receive the first clock signal and the initial command signal, and perform delay processing on the initial command signal according to the first clock signal to obtain a target command signal; wherein the time interval between the target command signal and the initial command signal meets a preset timing condition.
  • the clock module includes a temperature detection module and an oscillator module, wherein:
  • the temperature detection module is configured to monitor the temperature change of the clock module and generate the temperature adjustment signal according to the temperature change
  • the oscillator module is configured to receive the temperature adjustment signal, adjust the internal module structure according to the temperature adjustment signal, and generate the first clock signal.
  • the oscillator module includes a plurality of inverters, wherein:
  • the oscillator module is configured to control the number of inverters required to generate a clock signal internally according to the temperature adjustment signal, so as to adjust the internal module structure so that the clock period of the first clock signal is a preset value.
  • the oscillator module is configured to reduce the number of inverters required to generate the clock signal internally if the temperature adjustment signal indicates that the temperature change is on an upward trend, or;
  • the oscillator module is configured to increase the number of inverters required to generate a clock signal internally if the temperature adjustment signal indicates that the temperature change is in a downward trend.
  • the clock module further includes a fuse module, wherein:
  • the fuse module is configured to provide a fuse signal to the oscillator module; wherein the target mode value indicated by the fuse signal is determined in a test mode;
  • the oscillator module is further configured to generate the first clock signal according to the fuse signal and the temperature adjustment signal.
  • the clock module further includes a selection module, wherein:
  • the fuse module is further configured to set the value of the second test mode signal to the first candidate mode value in the test mode, and send the second test mode signal to the oscillator module;
  • the oscillator module is further configured to generate a test clock signal according to the second test mode signal
  • the selection module is configured to receive a first test mode signal and select the test clock signal for output according to the first test mode signal.
  • the fuse module is further configured to use the first candidate mode value as the target mode value and burn it into a preset fuse if the clock period of the test clock signal is equal to the preset value, so that the target mode value indicated by the fuse signal is the same as the value of the second test mode signal.
  • the fuse module is further configured to set the value of the second test mode signal to a second candidate mode value if the clock period of the test clock signal is not equal to the preset value, continue to execute the step of sending the second test mode signal to the oscillator module until the clock period of the test clock signal is equal to the preset value, and use the current candidate mode value of the second test mode signal as the target mode value and burn it into the preset fuse, so that the target mode value indicated by the fuse signal is the same as the value of the second test mode signal.
  • the first input terminal of the selection module is connected to the output terminal of the oscillator module for receiving the test clock signal
  • the second input terminal of the selection module is connected to the data signal
  • the control terminal of the selection module is connected to the first test mode signal
  • the selection module is configured to receive the first test mode signal, and select one of the test clock signal and the data signal for output according to the value of the first test mode signal;
  • the test clock signal is selected for output; if the value of the first test mode signal is a second value, the data signal is selected for output.
  • the delay module includes M shift registers, where M is an integer greater than 0, wherein:
  • the input end of the first shift register is connected to the initial command signal, the input end of the yth shift register is connected to the output end of the y-1th shift register, and the output end of the Mth shift register is used to output the target command signal;
  • each shift register is connected to the clock module, wherein y is an integer greater than 1 and less than or equal to M.
  • the shift register is used to delay the signal received at the input end by a first clock cycle for output; wherein the product of the first clock cycle and M is equal to the time interval.
  • the shift register includes L flip-flops, and the L flip-flops are connected in series, where L is an integer greater than 0, wherein:
  • the clock ends of the L triggers are all connected to the clock module for receiving the first clock signal, and the output end of the trigger is connected to the input end of the next trigger.
  • the initial command signal includes an activation signal and the target command signal includes a read signal, or; the initial command signal includes a read signal and the target command signal includes a write signal, or; the initial command signal includes a write signal and the target command signal includes a pre-charge signal.
  • the delay control circuit further includes a buffer module, wherein:
  • the buffer module is configured to receive an ECS command signal and generate the initial command signal according to the ECS command signal.
  • an embodiment of the present disclosure provides a delay control method, which is applied to a delay control circuit.
  • the method includes:
  • the first clock signal and the initial command signal are received through a delay module, and the initial command signal is delayed according to the first clock signal to obtain a target command signal; wherein the time interval between the target command signal and the initial command signal meets a preset timing condition.
  • an embodiment of the present disclosure provides a semiconductor memory, comprising a delay control circuit as described in any one of the first aspects.
  • the semiconductor memory includes a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the embodiment of the present disclosure provides a delay control circuit, method and semiconductor memory, wherein the delay control circuit includes a clock module and a delay module, wherein: the clock module is configured to receive a temperature adjustment signal, generate a first clock signal according to the temperature adjustment signal, and the clock period of the first clock signal is a preset value; the delay module is configured to receive the first clock signal and the initial command signal, and delay the initial command signal according to the first clock signal to obtain a target command signal; wherein the time interval between the target command signal and the initial command signal meets the preset timing condition.
  • the clock module generates the first clock signal based on the temperature adjustment signal, so that the clock period of the first clock signal is not affected by the temperature, and then delays the initial command signal according to the first clock signal, so that the time interval between the delayed target command signal and the initial clock signal meets the preset timing condition; thereby not only improving the influence of temperature on the first clock signal, but also making the delay time between the target command signal and the initial command signal under the first clock signal meet the timing condition, thereby ensuring the accuracy of the delay time and improving the performance of the memory.
  • FIG1 is a schematic diagram of a timing relationship between command signals
  • FIG2 is a schematic diagram of the structure of a delay control circuit provided in an embodiment of the present disclosure.
  • FIG3 is a schematic diagram of the composition structure of another delay control circuit provided in an embodiment of the present disclosure.
  • FIG4A is a schematic diagram of a specific structure of an oscillator module provided by an embodiment of the present disclosure.
  • FIG4B is a schematic diagram of an oscillation waveform of an oscillator module provided in an embodiment of the present disclosure.
  • FIG4C is a schematic diagram of a specific structure of another oscillator module provided in an embodiment of the present disclosure.
  • FIG5A is a schematic diagram of a specific structure of another oscillator module provided by an embodiment of the present disclosure.
  • FIG5B is a schematic diagram of an oscillation waveform of another oscillator module provided in an embodiment of the present disclosure.
  • FIG5C is a schematic diagram of a specific structure of another oscillator module provided in an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of the composition structure of another delay control circuit provided in an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of the structure of a clock module provided in an embodiment of the present disclosure.
  • FIG8 is a schematic diagram of the structure of another delay control circuit provided in an embodiment of the present disclosure.
  • FIG9 is a schematic diagram of the composition structure of a delay module provided in an embodiment of the present disclosure.
  • FIG10 is a schematic diagram of the structure of a shift register provided in an embodiment of the present disclosure.
  • FIG11 is a schematic diagram of a signal timing sequence of a shift register provided by an embodiment of the present disclosure.
  • FIG12 is a schematic flow chart of a delay control method provided in an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that “first ⁇ second ⁇ third” can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.
  • FIG. 1 is a schematic diagram of the timing relationship between some command signals specified by the Joint Electron Device Engineering Council (JEDEC).
  • JEDEC Joint Electron Device Engineering Council
  • the order of self-generated command signals in DRAM is activation signal (Active, ACT), read operation signal or simply read signal (Read, RD), write operation signal or simply write signal (Write, WR) and precharge signal (Precharge, PRE), tRCD represents the time interval between ACT and RD (or “delay time”, “delay time”), WL represents the time interval between RD and WR, and tWR represents the time interval between WR and PRE. Since all command signals are internally self-generated commands, DRAM needs to internally control the timing from ACT to RD and other command signals, for example, tRCD needs to meet 15 nanoseconds (ns). However, since the registers inside the DRAM do not record the values of tRCD, etc., it is impossible to directly implement the timing control between ACT to RD and other command signals through clock shifting.
  • the embodiment of the present disclosure provides a delay control circuit, including a clock module and a delay module, wherein: the clock module is configured to receive a temperature adjustment signal, generate a first clock signal according to the temperature adjustment signal, and the clock period of the first clock signal is a preset value; the delay module is configured to receive the first clock signal and the initial command signal, and delay the initial command signal according to the first clock signal to obtain a target command signal; wherein the time interval between the target command signal and the initial command signal meets the preset timing condition.
  • the clock module generates the first clock signal based on the temperature adjustment signal, so that the clock period of the first clock signal is not affected by the temperature, and then delays the initial command signal according to the first clock signal, so that the time interval between the delayed target command signal and the initial clock signal meets the preset timing condition; thereby not only improving the influence of temperature on the first clock signal, but also making the delay time between the target command signal and the initial command signal under the first clock signal meet the timing condition, thereby ensuring the accuracy of the delay time and improving the performance of the memory.
  • the delay control circuit 10 may include a clock module 11 and a delay module 12, wherein:
  • the clock module 11 is configured to receive a temperature adjustment signal, generate a first clock signal according to the temperature adjustment signal, and the clock period of the first clock signal is a preset value;
  • the delay module 12 is configured to receive a first clock signal and an initial command signal, and perform delay processing on the initial command signal according to the first clock signal to obtain a target command signal; wherein the time interval between the target command signal and the initial command signal meets a preset timing condition.
  • the embodiments of the present disclosure can be applied to the timing control between command signals in a memory such as DRAM.
  • the delay module 12 is configured to perform delay processing on the initial command signal to obtain a target command signal, and the time interval between the target command signal and the initial command signal meets the preset timing conditions.
  • the initial command signal is used to perform a first operation
  • the target command signal is used to perform a second operation.
  • the specific operation is related to the type of command signal.
  • the embodiments of the present disclosure can be applied to the timing control between ACT and RD generated internally by DRAM when performing manual or automatic ECS operations, or the timing control between RD and WR, or the timing control between WR and PRE.
  • the initial command signal may include an activation signal
  • the target command signal may include a read signal, or; the initial command signal may include a read signal, and the target command signal may include a write signal, or; the initial command signal may include a write signal, and the target command signal may include a precharge signal.
  • the activation signal is used to perform an activation operation
  • the read signal is used to perform a read operation
  • the write signal is used to perform a write operation
  • the precharge signal is used to perform a precharge operation.
  • the embodiments of the present disclosure can be applied not only to the timing control between internal self-generated commands under automatic ECS operation, but also to the timing control between command signals generated inside any memory, such as the time interval between activation/row addressing (Row Address Strobe, RAS) and read/write/column addressing (Column Address Strobe, CAS).
  • RAS Low Address Strobe
  • CAS Read/write/column addressing
  • the following is a detailed description of the implementation of the embodiments of the present disclosure, taking the timing control between command signals in the ECS process as an example.
  • tRCD preset timing condition
  • the delay module 12 When delaying the initial command signal, the delay module 12 needs a clock signal as a clock to delay the initial command signal.
  • the shift register can use the external clock signal as a clock to delay the initial command signal. Since the clock cycle corresponding to the external clock signal at different frequencies is different, the number of registers required is also different, and the specific frequency of the external clock signal cannot be known. At this time, it is necessary to decode with the help of the mode register signal MRS OP ⁇ 3:0> to know the clock cycle of the external clock signal, and then select a specific number of shift registers.
  • the embodiment of the present disclosure uses the clock module 11 to generate a first clock signal as the clock signal of the shift register, and provides a clock signal to the shift register in the absence of an external clock signal, so that the shift register can delay the signal.
  • a clock module 11 can also be added to the circuit, and the first clock signal generated by the clock module 11 can be used as a clock to implement delay processing of the initial command signal.
  • the delay control circuit provided in the embodiment of the present disclosure can still be used to self-generate the first clock signal to implement timing control between command signals.
  • timing control between command signals in ECS operation but also the timing control between any two command signals or other signals in the memory can be achieved by the delay control circuit provided in the embodiment of the present disclosure.
  • the clock module 11 is a module that can generate a clock signal internally, but in actual use, temperature changes (including changes in the temperature of the memory caused by changes in the temperature of the external environment, or temperature changes caused by the internal operation of the memory, etc.) will affect the performance of the internal circuit of the clock module 11, thereby causing changes in the clock cycle of the clock signal generated by the clock module 11. If the delay module 12 delays the initial command signal according to the changed clock signal, the time interval between the final target command signal and the initial command signal will not meet the preset timing conditions.
  • the embodiment of the present disclosure controls and adjusts the clock module 11 through the temperature adjustment signal, so that the clock module 11 generates a first clock signal with a clock period that is stable at a preset value.
  • the clock period of the first clock signal generated by the clock module 11 can always be unaffected by the temperature, so that when the delay module 12 performs delay processing on the initial command signal according to the first clock signal, it is ensured that the time interval between the obtained target command signal and the initial command signal meets the preset timing condition.
  • the clock module 11 may include a temperature detection module 111 and an oscillator module 112, wherein:
  • the temperature detection module 111 is configured to monitor the temperature change of the clock module 11 and generate a temperature adjustment signal according to the temperature change;
  • the oscillator module 112 is configured to receive a temperature adjustment signal, adjust an internal module structure according to the temperature adjustment signal, and generate a first clock signal.
  • the clock module 11 may include a temperature detection module 111 for generating a temperature adjustment signal and an oscillator module 112 for generating a first clock signal.
  • the temperature detection module 111 may monitor the temperature change of the clock module 11 in real time or at intervals, and generate a temperature adjustment signal according to the temperature change and send it to the oscillator module 112.
  • the temperature adjustment module 111 may be a temperature sensor (Temperature Sensor); after receiving the temperature adjustment signal, the oscillator module 112 adjusts its internal module structure according to the temperature adjustment signal, so that the clock period of the first clock signal generated by the oscillator module 112 is stable at a preset value and will not change with temperature, thereby ensuring the reliability of the first clock signal as a clock.
  • a temperature sensor Temporal Sensor
  • the oscillator module 112 may include an input terminal 1121, a plurality of inverters 1122, and an output terminal 1123; wherein, the number of the plurality of inverters 1122 is an odd number, and the plurality of inverters 1122 are connected in series, the output terminal of the last inverter 1122 is connected to the input terminal of the first inverter 1122, an input signal is given to the oscillator module 112 at the input terminal 1121, so that the oscillator module 112 oscillates, and a clock signal with a certain frequency is generated at the output terminal 1123, and the frequency of the clock signal is related to the delay value of each inverter 1122, that is, the clock period of the clock signal is related to the delay value of each inverter 1122.
  • the oscillator module 112 can be a ring oscillator (Ring oscillator, Ring OSC), which can also be simply referred to as an oscillator.
  • Ring oscillator Ring OSC
  • a high-level signal (indicated by 1) is input to the oscillator module 112 at the input terminal 1121, then after passing through an odd number of inverters 1122, the last inverter 1122 outputs a low-level signal (indicated by 0) and outputs it at the output terminal 1123.
  • the 0 output by the last inverter 1122 is also transmitted to the first inverter 1122 and output as 1 after passing through an odd number of inverters. In this way, a clock signal that meets a certain frequency can be obtained at the output terminal 1123.
  • FIG4B is a schematic diagram of the oscillation waveform of the oscillator module.
  • CLK1 represents the waveform of the signal output by the first inverter
  • CLK2 represents the waveform of the signal output by the second inverter
  • CLK represents the waveform of the signal output by the third inverter, that is, the first clock signal finally obtained.
  • a low level signal i.e., logic 0
  • a high level signal i.e., logic 1
  • logic 0 is obtained after passing through the second inverter
  • logic 1 is obtained after passing through the third inverter
  • logic 1 is output as the first clock signal
  • logic 1 is returned to the first inverter
  • logic 0 is obtained after passing through three inverters
  • logic 0 is output as the first clock signal, and returned to the first inverter, and considering the delay effect of the inverter, the first clock signal finally obtained is shown in FIG4B.
  • the oscillator module 112 is configured to control the number of inverters required to generate the internal clock signal according to the temperature adjustment signal, so as to adjust the internal module structure so that the clock period of the first clock signal is a preset value.
  • the embodiment of the present disclosure adjusts the number of inverters required to generate the clock signal inside the oscillator module 112 according to the temperature adjustment signal, and increases or decreases the number of inverters used to generate the clock signal according to the temperature adjustment signal to improve the influence of temperature on the clock period of the first clock signal, thereby obtaining a first clock signal with a stable clock period.
  • the oscillator module is configured to reduce the number of inverters required to generate the clock signal internally if the temperature adjustment signal indicates that the temperature change is on an upward trend; or,
  • the oscillator module is configured to increase the number of inverters required to internally generate a clock signal if the temperature adjustment signal indicates that the temperature change is in a decreasing trend.
  • the delay of a single inverter becomes larger. At this time, the number of inverters incorporated into the ring oscillator can be reduced according to the temperature adjustment signal to make the clock period of the first clock signal stable. Under low temperature conditions, the delay of a single inverter decreases. At this time, the number of inverters incorporated into the ring oscillator can be increased according to the temperature adjustment signal to make the clock period of the first clock signal stable.
  • FIG. 4C a specific structural diagram of another oscillator module 112 provided by an embodiment of the present disclosure is shown.
  • the oscillator module 112 includes A inverters 1122 and B switch modules 1124.
  • a inverters are connected in series, and the output end of the Ath inverter 1122 is connected to the input end of the first inverter 1122; the bth switch module 1124 is connected between the output end of the ath inverter 1122 and the input end of the first inverter 1122;
  • a and B are both integers greater than 0, a is an integer greater than 0 and less than or equal to A, and b is an integer greater than 0 and less than or equal to B, wherein:
  • the number of inverters inside the oscillator module 112 for generating the clock signal is A;
  • the number of inverters 1122 for generating clock signals inside the oscillator module 112 is a.
  • the number of inverters included in the ring oscillator is usually an odd number (if it is an even number, the output will always remain unchanged, and a clock signal with a high level and a low level cannot be obtained). Based on this, when adjusting the number of inverters included in the ring oscillator, it is necessary to ensure that the number of inverters used to generate the clock signal after adjustment is an odd number.
  • the number B of the switch modules 1124 is usually less than the number A of the inverters 1122, and the bth switch module 1124 is connected between the output end of the ath inverter 1122 and the input end of the first inverter 1122, where a usually refers to an odd number greater than 0 and less than A.
  • a here is usually not 1.
  • the switch module 1124 is not connected between the output end of the last inverter 1122 and the output end of the first inverter 1122. In other examples, the switch module 1124 may be connected between the two. As shown in FIG4C , when all the switch modules 1124 are disconnected, all A inverters 1122 are connected to the circuit to generate the first clock signal; if the first switch module 1124 is turned on and the remaining switch modules 1124 are disconnected, the first to third inverters 1122 are connected to the circuit to generate the first clock signal; if the second switch module 1124 is turned on and the remaining switch modules 1124 are disconnected, the first to fifth inverters 1122 are connected to the circuit to generate the first clock signal.
  • the switch module 1124 between the output end of the inverter 1122 and the input end of the first inverter 1122 is turned on, and the remaining switch modules 1124 remain disconnected; if all inverters 1122 need to be connected to the circuit, all switch modules 1124 will be disconnected.
  • a switch module can also be added between the last inverter 1122 and the first inverter 1122. When all inverters 1122 need to be incorporated into the circuit, the switch module between the last inverter 1122 and the first inverter 1122 is turned on.
  • the embodiment of the present disclosure can control the conduction and disconnection of the switch module according to the temperature adjustment signal, and then control the number of inverters inside the oscillator module for generating the clock signal, thereby ensuring that when the temperature changes, the oscillator module outputs a first clock signal with a stable clock period.
  • inventions of the present disclosure can also change the number of inverters connected to the circuit by adding a selector in the circuit, etc.
  • Figure 4C is only an exemplary implementation method. As long as the number of inverters can be increased or decreased according to temperature changes, the requirement of stabilizing the clock period of the first clock signal can be met.
  • the temperature adjustment signal may be a temperature adjustment code, and the value of the temperature adjustment code corresponds to the increased or decreased number of inverters.
  • the temperature adjustment signal can specifically be a temperature adjustment code, and different values of the temperature adjustment code indicate different numbers of inverters to be increased or decreased.
  • a temperature adjustment code value of 0 indicates that the number of inverters does not need to be changed
  • a positive temperature adjustment code value indicates that the number of inverters needs to be reduced, and the larger the positive value, the more the number needs to be reduced
  • a negative temperature adjustment code value indicates that the number of inverters needs to be increased, and the larger the absolute value of the negative value, the more the number needs to be increased.
  • a positive temperature adjustment code value indicates that the number of inverters needs to be increased
  • a negative temperature adjustment code value indicates that the number of inverters needs to be reduced, and the like, without specific limitation.
  • the temperature adjustment signal may also correspond to the temperature value of the clock module. Therefore, in some embodiments, the value of the temperature adjustment signal corresponds to the number of inverters required to generate the clock signal inside the oscillator module. In this way, the value of the temperature adjustment signal corresponds to a specific temperature value, and the number of inverters corresponds to the temperature value, or the number of inverters corresponds to the temperature range to which the temperature value belongs, so that the number of inverters can be adjusted directly according to the value of the temperature adjustment signal.
  • the embodiments of the present disclosure can adjust the number of inverters used to generate clock signals inside the oscillator module in different ways, so that when the temperature changes, the clock period of the first clock signal is not affected by the temperature and is stable at a preset value.
  • the oscillator module can also be implemented by a NAND gate and a buffer.
  • FIG. 5A it shows a specific structural schematic diagram of another oscillator module 112 provided by an embodiment of the present disclosure.
  • the oscillator module 112 can include a NAND gate 1125 and a plurality of buffers 1126, wherein:
  • the oscillator module 112 is configured to control the number of buffers required for generating the clock signal internally according to the temperature adjustment signal, so as to adjust the internal module structure so that the clock period of the first clock signal is a preset value.
  • FIG5A a NAND gate 1125 and a plurality of buffers 1126 form an oscillator module (ring oscillator), and the output and input ends of the plurality of buffers 1126 are connected end to end to form a ring.
  • FIG5B is a schematic diagram of the oscillation waveform of the oscillator module. As shown in FIG5B , after obtaining the Reset signal, the oscillator module starts to oscillate, and the oscillation frequency is related to the delay value of each level of buffer.
  • the oscillation waveform is shown in FIG5B , taking the number of buffers as four as an example, wherein CLK0 represents the waveform of the signal output by the NAND gate 1125, CLK1 represents the waveform of the signal output by the first buffer 1126, CLK2 represents the waveform of the signal output by the second buffer 1126, CLK3 represents the waveform of the signal output by the third buffer 1126, and CLK represents the waveform of the signal output by the fourth buffer 1126 (i.e., the first clock signal). It can be seen from the waveform diagram that the falling edge or rising edge of the signal output by the previous stage buffer is transmitted backward in sequence, and starts again in the reverse direction after reaching the last stage, and finally a periodic first clock signal is obtained.
  • the oscillator module 112 is configured to reduce the number of buffers required to generate the clock signal internally if the temperature adjustment signal indicates that the temperature change is on an increasing trend, or;
  • the oscillator module 112 is configured to increase the number of buffers required to generate the clock signal internally if the temperature adjustment signal indicates that the temperature change is on a downward trend.
  • the number of buffers required to generate a clock signal inside the oscillator module 112 can be changed by a temperature adjustment signal to stabilize the clock period, and the clock period is related to the delay value of the buffer.
  • Its adjustment method is similar to the adjustment method of the oscillator module 112 provided in FIG. 4A above, and will not be described in detail here, and will only be briefly described with the specific structural schematic diagram shown in FIG. 5C.
  • the oscillator module 112 may also include a plurality of switch modules 1124, and the switch module 1124 is connected between the output end of the buffer 1126 and the input end of the NAND gate 1125.
  • the oscillator module may include a number of oscillator devices (inverters or buffers) connected in series, and the oscillator module is configured to control the number of oscillator devices required to generate an internal clock signal according to a temperature adjustment signal, so as to adjust the internal module structure so that the clock period of the first clock signal is a preset value.
  • the oscillator module 112 is configured to reduce the number of oscillating components required to generate the clock signal internally if the temperature adjustment signal indicates that the temperature change is on an upward trend, or;
  • the oscillator module 112 is configured to increase the number of oscillating components required to generate the clock signal internally if the temperature adjustment signal indicates that the temperature change is on a downward trend.
  • the embodiment of the present disclosure changes the number of oscillating components required for generating a clock signal in the oscillator module through a temperature adjustment signal, so that when the temperature changes, a first clock signal with a stable clock period can still be generated.
  • the embodiment of the present disclosure uses the first clock signal generated by the oscillator as the clock signal of the shift register.
  • factors such as process and voltage will also affect the performance of the device during the manufacture and use of the device, that is, the oscillator will be affected by process, voltage and temperature (Process Voltage Temperature, PVT).
  • PVT Process Voltage Temperature
  • the embodiment of the present disclosure also considers the influence of process and voltage. Referring to Figure 6, it shows a schematic diagram of the composition structure of another delay control circuit 10 provided in the embodiment of the present disclosure.
  • the clock module 11 may also include a fuse module 113, wherein:
  • the fuse module 113 is configured to provide a fuse signal to the oscillator module 112; wherein the target mode value indicated by the fuse signal is determined in the test mode;
  • the oscillator module 112 is further configured to generate a first clock signal according to the fuse signal and the temperature adjustment signal.
  • the fuse module 113 is connected to the oscillator module 112 and is configured to provide a fuse signal to the oscillator module 112.
  • the oscillator module 112 receives the fuse signal and the aforementioned temperature adjustment signal and generates a first clock signal accordingly, wherein the temperature adjustment signal can improve the influence of temperature on the clock cycle, and the fuse signal can improve the influence of process and voltage on the clock cycle.
  • the value indicated by the fuse signal provided by the fuse module 113 is a determined target mode value, which is a specific value determined in the test mode.
  • the oscillator module 112 receives a fixed fuse signal and a temperature adjustment signal that varies with temperature to generate a first clock signal, so that the clock period of the first clock signal is fixed to a preset value.
  • the embodiment of the present disclosure can not only improve the influence of temperature on the clock cycle through the temperature adjustment signal, but also improve the influence of process and voltage on the clock cycle through the fuse signal, so that the period of the first clock signal is stabilized to a preset value.
  • FIG. 7 is a schematic diagram of the composition structure of a clock module 11 provided in an embodiment of the present disclosure.
  • the clock module 11 may further include a selection module 114, wherein:
  • the fuse module 113 is further configured to set the value of the second test mode signal to the first candidate mode value in the test mode, and send the second test mode signal to the oscillator module 112;
  • the oscillator module 112 is further configured to generate a test clock signal according to the second test mode signal;
  • the selection module 114 is configured to receive a first test mode signal and select a test clock signal for output according to the first test mode signal.
  • the fuse module 113 is further configured to use the first candidate mode value as the target mode value and burn it into the preset fuse if the clock period of the test clock signal is equal to the preset value, so that the target mode value indicated by the fuse signal is the same as the value of the second test mode signal.
  • the clock module 11 may further include a selection module 114, which is configured to cooperate with the fuse module 113 and the oscillator module 112 to determine the target mode value indicated by the fuse signal.
  • a selection module 114 configured to cooperate with the fuse module 113 and the oscillator module 112 to determine the target mode value indicated by the fuse signal.
  • the value of the fuse signal in the fuse module 113 has not yet been determined, and different values of the second test mode signal can be generated by sending instructions through the test machine, and the clock period of the test clock signal output by the oscillator module 112 is compared under the value corresponding to each second test mode signal.
  • the corresponding value of the second test mode signal is the determined target mode value.
  • a first input terminal of the selection module 114 is connected to an output terminal of the oscillator module 112 for receiving a test clock signal, a second input terminal of the selection module 114 is connected to a data signal, and a control terminal of the selection module 114 is connected to a first test mode signal, wherein:
  • the selection module 114 is configured to receive a first test mode signal and select one of the test clock signal and the data signal for output according to a value of the first test mode signal;
  • the test clock signal is selected for output; if the value of the first test mode signal is the second value, the data signal is selected for output.
  • the selection module 114 can be a two-to-one selector (2-1MUX), including a first input terminal, a second input terminal, a control terminal and an output terminal, wherein the first input terminal is used to receive the test clock signal sent by the oscillator module 112, the second input terminal is used to receive the data signal (such as the read data signal), the control terminal is used to receive the first test mode signal, and select the test clock signal or the data signal as the output signal of the selection module 114 according to the first test mode signal, and the output terminal of the selection module 114 is used to output the selected signal.
  • the selection module 114 is not limited to a two-to-one selector, and no limitation is made here.
  • the value of the first test mode signal (Test Mode 1, referred to as TM1) is the first value, and the test clock signal is selected as the output of the selection module 114; when not in the test mode, the value of the first test mode signal is the second value, and the data signal is selected as the output of the selection module 114 to achieve other functional requirements of the circuit.
  • the first value can be 1, and the second value can be 0.
  • test clock signal is selectively outputted through the first test mode signal, thereby realizing clock cycle monitoring of the test clock signal.
  • the fuse module 113 first sets the value of the second test mode signal (referred to as TM2) to the first candidate mode value, and then sends the second test mode signal to the oscillator module 112. Based on the second test mode signal, the oscillator module 112 adjusts the performance of the device contained in itself, thereby changing the clock cycle of the clock signal generated by the oscillator module 112, and the clock signal generated by the oscillator module 112 in the test mode is recorded as the test clock signal. After the oscillator module 112 generates the test clock signal, it sends the test clock signal to the selection module 114.
  • TM2 the value of the second test mode signal
  • the selection module 114 receives the first test mode signal and selects the test clock signal for output according to the first test mode signal (when the first test mode signal is the first value). At this time, the clock cycle of the test clock signal output by the selection module 114 can be detected, and it can be determined whether the detected clock cycle is equal to the preset value. If it is equal, the first candidate mode value is burned into the preset fuse as the target mode value, so that the value indicated by the fuse signal provided by the preset fuse is fixed to the target mode value indicated by the second test mode signal.
  • the fuse module 113 is also configured to set the value of the second test mode signal to the second candidate mode value if the clock cycle of the test clock signal is not equal to the preset value, and continue to execute the step of sending the second test mode signal to the oscillator module until the clock cycle of the test clock signal is equal to the preset value, and the current candidate mode value of the second test mode signal is used as the target mode value and burned into the preset fuse, so that the target mode value indicated by the fuse signal is the same as the value of the second test mode signal.
  • the value of the second test mode signal is set to the second candidate mode value, and the second test mode signal is sent to the oscillator module 112.
  • the oscillator module 112 adjusts and generates a test clock signal based on the second test mode signal, and the selection module 114 selects and outputs it.
  • the clock period of the test clock signal output by the selection module 114 is continued to be detected. If it is the same as the preset value, the second candidate mode value is burned into the preset fuse as the target mode value. If the clock period is different from the preset value, the next candidate mode value is continued to be generated until the clock period of the generated test clock signal is the same as the preset value, and the corresponding candidate mode value is burned into the preset fuse.
  • corresponding fuses are prepared for certain test mode signals (TM). Since TM is completed by sending instructions from the test machine, it is not permanent. After the value of TM2 is determined in the test phase, the corresponding value of FUSE2 can be burned into the fuse to make the value of FUSE2 equal to TM2. The value of FUSE2 replaces TM2, plays the same role, and is permanent.
  • the target mode value determined in the test mode is used to improve the impact of process and voltage on the clock period of the clock signal generated by the oscillator module 112. Therefore, the temperature when executing the test mode can be set to a fixed reference temperature. Based on this, when the temperature adjustment module determines whether the temperature is on an upward or downward trend, it can compare the detected temperature with the reference temperature to determine the temperature change trend.
  • the fuse module can provide a fuse signal to the oscillator module. Based on the fuse signal, the influence of voltage and process on the clock cycle can be improved. Finally, under the joint action of the fuse signal and the temperature adjustment signal, the clock cycle of the first clock signal can be unaffected by PVT and thus stabilized to a preset value.
  • the delay module 12 may include M shift registers 121, where M is an integer greater than 0, wherein:
  • the input end of the first shift register 121 is connected to the initial command signal, the input end of the yth shift register 121 is connected to the output end of the y-1th shift register 121, and the output end of the Mth shift register 121 is used to output the target command signal;
  • each shift register 121 is connected to the clock module 11 , wherein y is an integer greater than 1 and less than or equal to M.
  • the delay module 12 can be composed of M shift registers 121 connected in series. Further, taking M equal to 6 as an example, see FIG9 , which shows a schematic diagram of the composition structure of a delay module 12 provided in an embodiment of the present disclosure. As shown in FIG9 , the first to sixth shift registers are respectively recorded as shift register 1, shift register 2, shift register 3, shift register 4, shift register 5 and shift register 6, and the clock end of each shift register is represented by CLK. The clock end of each shift register is connected to the clock module 11, specifically, to the oscillator module 112 in the clock module 11, and is used to receive the first clock signal as the clock used for delay.
  • the input end of shift register 1 is used to receive the initial command signal, and delay the initial command signal with the first clock signal as the clock to obtain the intermediate command signal RD ⁇ 0>, and output it through its output end;
  • the input end of shift register 2 is used to receive the intermediate command signal RD ⁇ 0>, and delay the intermediate command signal RD ⁇ 0> with the first clock signal as the clock to obtain the intermediate command signal RD ⁇ 1>, and output it through its output end;
  • the subsequent shift registers are executed in the same way until the input end of shift register 6 receives the intermediate command signal RD ⁇ 4>, and delays the intermediate command signal RD ⁇ 4> with the first clock signal as the clock to obtain the target command signal, and output it at its output end.
  • the shift register is used to delay the signal received at the input end by a first clock cycle for output; wherein the product of the first clock cycle and M is equal to the time interval.
  • each shift register can be the same, and it can output the signal received at its input end after delaying the first clock cycle. Since there are M shift registers, the time interval between the target command signal and the initial command signal is the product of the first clock cycle and M.
  • the preset timing conditions require that the time interval between the initial command signal and the target command signal is 15ns, and each shift register can delay the input signal therein for four clock cycles before outputting it, then the six shift registers can delay the initial command signal by 24 clock cycles, and it can be calculated that each clock cycle is 0.625ns.
  • the clock module 11 generates a first clock signal with a stable clock cycle of 0.625ns, thereby realizing the delay processing of the initial command signal.
  • the shift register may include L triggers, and the L triggers are connected in series, where L is an integer greater than 0, wherein:
  • the clock terminals of the L triggers are all connected to the clock module for receiving the first clock signal, and the output terminal of the trigger is connected to the input terminal of the next trigger.
  • the trigger can be a D flip-flop (D Flip-Flop, DFF), which can be represented by DFF.
  • DFF D Flip-Flop
  • a trigger is used to delay a signal received at an input terminal by a second clock cycle before outputting it; wherein the first clock cycle is equal to the product of the second clock cycle and L, and the second clock cycle is equal to the clock cycle of the first clock signal.
  • a trigger can output a signal after delaying the clock cycle of the first clock signal.
  • a shift register can be composed of four D flip-flops connected in series.
  • the input end (D) of each D flip-flop is used to receive a signal input to the D flip-flop, and the clock end (represented by CLK) of each D flip-flop is used to receive a first clock signal, and the received signal is delayed by the first clock signal and then output at the output end (Q).
  • the shift register 1 includes a first flip-flop DFF1 , a second flip-flop DFF2 , a third flip-flop DFF3 and a fourth flip-flop DFF4 , wherein:
  • the clock terminals of the first flip-flop DFF1, the second flip-flop DFF2, the third flip-flop DFF3 and the fourth flip-flop DFF4 are all connected to the clock module;
  • An input terminal of the first flip-flop DFF1 is connected to an initial command signal, and an output terminal of the first flip-flop DFF1 is connected to an input terminal of the second flip-flop DFF2;
  • An output terminal of the second flip-flop DFF2 is connected to an input terminal of the third flip-flop DFF3;
  • An output terminal of the third flip-flop DFF3 is connected to an input terminal of the fourth flip-flop DFF4;
  • An output terminal of the fourth flip-flop DFF4 is used to output an output signal of the shift register 1 .
  • each shift register its structure can be as shown in Figure 10, except that for shift registers in different positions, its input and output are different.
  • shift register 1 its input is the initial command signal, and its output is the intermediate command signal RD ⁇ 0>;
  • shift register 2 its input is the intermediate command signal RD ⁇ 0>, and its output is the intermediate command signal RD ⁇ 1>; and so on for other shift registers, and finally the target command signal is obtained at the output end of the last trigger of the last shift register, thereby realizing the delay processing of the initial command signal and obtaining the target command signal that meets the timing conditions.
  • tRCD represents the time interval
  • t represents the clock period of the first clock signal
  • L represents the number of flip-flops in each shift register
  • t ⁇ L represents the time that each shift register can delay the signal.
  • ACT (or represented by ECS_ACT) is the initial command signal
  • CLK (or represented by ECS_CLK) is the first clock signal
  • RD ⁇ 0:4> is the intermediate command signal
  • RD (or represented by ECS_RD) is the target command signal.
  • the output CLK of the oscillator module 112 is used as the clock signal of the delay module 12.
  • the clock signal is not greatly affected by PVT, and its clock cycle is fixed, so the number of shift registers is also determined.
  • each level of shift register delays 4 clock cycles, so a delay of 15ns requires 6 shift registers to be connected in series.
  • the output RD ⁇ 0> of the first shift register is delayed by 4 clock cycles relative to ACT.
  • the output RD ⁇ 1> of the second shift register is delayed by 8 clock cycles relative to ACT
  • the output RD ⁇ 2> of the third shift register is delayed by 12 clock cycles relative to ACT
  • the output RD ⁇ 3> of the fourth shift register is delayed by 16 clock cycles relative to ACT
  • the output RD ⁇ 4> of the fifth shift register is delayed by 20 clock cycles relative to ACT
  • the output RD of the sixth shift register is delayed by 24 clock cycles relative to ACT; that is, the delay from input ACT to output RD is 24 clock cycles (a total of 15ns).
  • the delay control circuit 10 may further include a buffer module 13, wherein:
  • the buffer module 13 is configured to receive the ECS command signal and generate an initial command signal according to the ECS command signal.
  • the initial command signal when the DRAM is in ECS mode and the initial command signal is an activation signal, the initial command signal can be generated based on the ECS signal. Therefore, the initial command signal can also be obtained according to the ECS command signal through the buffer module 13, and the initial command signal can be further processed as described above to finally obtain the target command signal.
  • the buffer module can also be called a "transmission gate”, which not only has a delay function, but also has the function of enhancing the signal driving ability. Specifically, for the ECS command signal and the initial command signal, the initial command signal not only has a time delay compared to the ECS command signal, but also has a stronger driving ability.
  • an external clock signal can be used as the delay clock of the shift register, and then the corresponding number of cycles can be moved to achieve the delay requirement of tRCD between ACT and RD.
  • the embodiment of the present disclosure uses the signal generated by the ring oscillator as the clock signal of the shift register, but the period of the clock generated by the ordinary ring oscillator is greatly affected by PVT.
  • the embodiment of the present disclosure adds temperature control and regulation to the ring oscillator.
  • the temperature sensor inside the DRAM can monitor the temperature change and output a temperature adjustment signal, and the clock cycle generated by the ring oscillator at different temperatures can be adjusted to keep it stable. For example, under high temperature conditions, the delay of a single inverter becomes larger, and the temperature adjustment signal can be used to reduce the number of inverters incorporated into the ring oscillator to keep the total clock cycle unchanged. The same applies to low temperatures.
  • TM1 is used to select and output the test clock signal generated by the ring oscillator to the output end of the selector to monitor the clock period of the test clock signal, and then the clock period of the test clock signal generated by the ring oscillator is adjusted by the second test mode signal (TM2) and the fuse (FUSE2).
  • TM2 the second test mode signal
  • FUSE2 the fuse
  • the clock period of the test clock signal can be adjusted and detected by these two test mode signals to stabilize it at a preset value, reducing the influence of process and voltage.
  • the corresponding FUSE2 is used to burn TM2 into the fuse and fix it.
  • the ECS command signal passes through the buffer module to generate an initial command signal as the input signal of the shift register, and the first clock signal generated by the ring oscillator is used as the clock of the shift register, so that even in Self_Refresh, when there is no external clock, the ring oscillator will generate a clock signal that does not change with PVT. Since the signal generated by the ring oscillator is fixed and not affected by the external frequency, the clock period of the first clock signal is determined, and the number of shift registers is also a determined value.
  • the embodiments of the present disclosure relate to circuits related to the timing between commands generated internally in integrated circuit design, and more particularly to DRAM chips.
  • DRAM requires different command signals to implement different functions, and there are timing requirements between different command signals generated internally.
  • the embodiments of the present disclosure relate to circuits related to the timing control between ACT and RD under automatic ECS operation in DRAM, but are not limited to this scope. Other circuits related to the timing control between different command signals generated internally may adopt this solution.
  • the embodiment of the present disclosure provides a delay control circuit, including a clock module and a delay module, wherein: the clock module is configured to receive a temperature adjustment signal, generate a first clock signal according to the temperature adjustment signal, and the clock period of the first clock signal is a preset value; the delay module is configured to receive the first clock signal and the initial command signal, and delay the initial command signal according to the first clock signal to obtain a target command signal; wherein the time interval between the target command signal and the initial command signal meets the preset timing condition.
  • the clock module generates the first clock signal based on the temperature adjustment signal, so that the clock period of the first clock signal is not affected by the temperature, and is also adjusted by the fuse signal, so that the clock period of the first clock signal is not affected by the process and voltage, and a clock signal with a stable clock period of the preset value is obtained; then the initial command signal is delayed according to the first clock signal, so that the time interval between the delayed target command signal and the initial clock signal meets the preset timing condition; thereby, the delay time between the target command signal and the initial command signal under the first clock signal meets the timing condition, thereby ensuring the accuracy of the delay time and improving the performance of the memory.
  • FIG. 12 a schematic flow chart of a delay control method provided by an embodiment of the present disclosure is shown. As shown in FIG. 12 , the method may include:
  • S1001 Receive a temperature adjustment signal through a clock module, generate a first clock signal according to the temperature adjustment signal, and the clock period of the first clock signal is a preset value.
  • S1002 Receive a first clock signal and an initial command signal through a delay module, and perform delay processing on the initial command signal according to the first clock signal to obtain a target command signal; wherein the time interval between the target command signal and the initial command signal meets a preset timing condition.
  • generating the first clock signal according to the temperature adjustment signal may include:
  • the temperature adjustment signal is received through the oscillator module, and the internal module structure is adjusted according to the temperature adjustment signal to generate a first clock signal.
  • adjusting the internal module structure according to the temperature adjustment signal may include:
  • the number of inverters required for generating the internal clock signal is controlled according to the temperature adjustment signal, so as to adjust the internal module structure so that the clock period of the first clock signal is a preset value.
  • controlling the number of inverters required to generate the clock signal internally according to the temperature adjustment signal may include:
  • the number of inverters required to generate the clock signal internally is increased.
  • the method may further include:
  • the fuse signal is received through the oscillator module, and a first clock signal is generated according to the fuse signal and the temperature adjustment signal.
  • the method may further include:
  • the value of the second test mode signal is set to the first candidate mode value through the fuse module, and the second test mode signal is sent to the oscillator module;
  • the first candidate mode value is used as the target mode value and burned into the preset fuse, so that the target mode value indicated by the fuse signal is the same as the value of the second test mode signal.
  • the method may further include:
  • the value of the second test mode signal is set to the second candidate mode value through the fuse module, and the step of sending the second test mode signal to the oscillator module is continued until the clock period of the test clock signal is equal to the preset value.
  • the current candidate mode value of the second test mode signal is used as the target mode value and burned into the preset fuse, so that the target mode value indicated by the fuse signal is the same as the value of the second test mode signal.
  • receiving the first test mode signal through the selection module and selecting the test clock signal for output according to the first test mode signal may include:
  • the test clock signal is selected for output; if the value of the first test mode signal is the second value, the data signal is selected for output.
  • the initial command signal includes an activation signal and the target command signal includes a read signal, or the initial command signal includes a read signal and the target command signal includes a write signal; or the initial command signal includes a write signal and the target command signal includes a precharge signal.
  • the method may further include: obtaining an initial command signal by buffering an ECS command signal and performing delay and drive enhancement processing on the ECS command signal.
  • An embodiment of the present disclosure provides a delay control method, which is applied to the delay control circuit described in the aforementioned embodiment.
  • the method can obtain a first clock signal whose clock period is not affected by PVT, so that the time interval between the target command signal and the initial clock signal can meet the preset timing conditions, thereby ensuring the accuracy of the delay time and improving the performance of the memory.
  • Fig. 13 shows a schematic diagram of the composition structure of a semiconductor memory 20 provided by the embodiment of the present disclosure.
  • the semiconductor memory 20 at least includes the delay control circuit 10 described in any one of the above embodiments.
  • the semiconductor memory 20 includes DRAM.
  • DRAM can not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, etc., but also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, etc., without any limitation here.
  • the semiconductor memory 20 includes the delay control circuit described in the above embodiment, thereby being able to improve the accuracy of the delay time between internal command signals and achieve timing control between command signals.
  • the embodiment of the present disclosure provides a delay control circuit, method and semiconductor memory, wherein the delay control circuit includes a clock module and a delay module, wherein: the clock module is configured to receive a temperature adjustment signal, generate a first clock signal according to the temperature adjustment signal, and the clock period of the first clock signal is a preset value; the delay module is configured to receive the first clock signal and the initial command signal, and delay the initial command signal according to the first clock signal to obtain a target command signal; wherein the time interval between the target command signal and the initial command signal meets the preset timing condition.
  • the clock module generates the first clock signal based on the temperature adjustment signal, so that the clock period of the first clock signal is not affected by the temperature, and then delays the initial command signal according to the first clock signal, so that the time interval between the delayed target command signal and the initial clock signal meets the preset timing condition; thereby not only improving the influence of temperature on the first clock signal, but also making the delay time between the target command signal and the initial command signal under the first clock signal meet the timing condition, thereby ensuring the accuracy of the delay time and improving the performance of the memory.

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Abstract

本公开实施例提供了一种延时控制电路、方法和半导体存储器，该延时控制电路包括时钟模块和延时模块，其中：时钟模块，配置为接收温度调节信号，根据温度调节信号生成第一时钟信号，且第一时钟信号的时钟周期为预设值；延时模块，配置为接收第一时钟信号和初始命令信号，根据第一时钟信号对初始命令信号进行延时处理，得到目标命令信号；其中，目标命令信号与初始命令信号之间的时间间隔满足预设时序条件。

Description

一种延时控制电路、方法和半导体存储器
相关申请的交叉引用
本公开基于申请号为202211223514.4、申请日为2022年10月08日、发明名称为“一种延时控制电路、方法和半导体存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种延时控制电路、方法和半导体存储器。
背景技术
随着半导体技术的不断发展，人们在制造和使用计算机等设备时，对数据的传输速度提出了越来越高的要求。为了获得更快的数据传输速度，应运而生了一系列数据可以双倍速率(Double Data Rate，DDR)传输的存储器等器件。
以动态随机存取存储器(Dynamic Random Access Memory，DRAM)为例，错误检查与清除(Error Check and Scrub，ECS)模式允许DRAM内部读取、修改检测到的错误码字，并将修正后的数据写回存储阵列。在执行ECS操作的过程中，DRAM需要不同命令来实现不同的功能，内部产生不同命令之间存在时序的要求。但是由于现有技术中时钟周期的不稳定性，导致不同命令之间的时序可能不满足时序条件，影响了存储器的性能。
发明内容
本公开实施例提供了一种延时控制电路、方法和半导体存储器。
第一方面，本公开实施例提供了一种延时控制电路，包括时钟模块和延时模块，其中：
所述时钟模块，配置为接收温度调节信号，根据所述温度调节信号生成第一时钟信号，且所述第一时钟信号的时钟周期为预设值；
所述延时模块，配置为接收所述第一时钟信号和初始命令信号，根据所述第一时钟信号对所述初始命令信号进行延时处理，得到目标命令信号；其中，所述目标命令信号与所述初始命令信号之间的时间间隔满足预设时序条件。
在一些实施例中，所述时钟模块包括温度检测模块和振荡器模块，其中：
所述温度检测模块，配置为监测所述时钟模块的温度变化，根据所述温度变化生成所述温度调节信号；
所述振荡器模块，配置为接收所述温度调节信号，根据所述温度调节信号对内部的模块结构进行调整，生成所述第一时钟信号。
在一些实施例中，所述振荡器模块包括若干个反相器，其中：
所述振荡器模块，配置为根据所述温度调节信号控制内部产生时钟信号所需的反相器数量，以实现对内部的模块结构进行调整，使得所述第一时钟信号的时钟周期为预设值。
在一些实施例中，所述振荡器模块，配置为若所述温度调节信号指示温度变化呈上 升趋势，则减小内部产生时钟信号所需的反相器数量，或者；
所述振荡器模块，配置为若所述温度调节信号指示温度变化呈下降趋势，则增加内部产生时钟信号所需的反相器数量。
在一些实施例中，所述时钟模块还包括熔丝模块，其中：
所述熔丝模块，配置为向所述振荡器模块提供熔丝信号；其中，所述熔丝信号指示的目标模式值是在测试模式下确定的；
所述振荡器模块，还配置为根据所述熔丝信号和所述温度调节信号生成所述第一时钟信号。
在一些实施例中，所述时钟模块还包括选择模块，其中：
所述熔丝模块，还配置为在测试模式下，设置第二测试模式信号的取值为第一候选模式值，并将所述第二测试模式信号发送给所述振荡器模块；
所述振荡器模块，还配置为根据所述第二测试模式信号，生成测试时钟信号；
所述选择模块，配置为接收第一测试模式信号，并根据所述第一测试模式信号选择所述测试时钟信号进行输出。
在一些实施例中，所述熔丝模块，还配置为若所述测试时钟信号的时钟周期等于所述预设值，则将所述第一候选模式值作为所述目标模式值并烧入预设熔丝中，以使得所述熔丝信号指示的目标模式值与所述第二测试模式信号的取值相同。
在一些实施例中，所述熔丝模块，还配置为若所述测试时钟信号的时钟周期不等于所述预设值，则设置第二测试模式信号的取值为第二候选模式值，继续执行将所述第二测试模式信号发送给所述振荡器模块的步骤，直至所述测试时钟信号的时钟周期等于所述预设值，将所述第二测试模式信号当前的候选模式值作为目标模式值并烧入预设熔丝中，以使得所述熔丝信号指示的目标模式值与所述第二测试模式信号的取值相同。
在一些实施例中，所述选择模块的第一输入端与所述振荡器模块的输出端连接，用于接收所述测试时钟信号，所述选择模块的第二输入端与数据信号连接，所述选择模块的控制端与所述第一测试模式信号连接，其中：
所述选择模块，配置为接收所述第一测试模式信号，根据所述第一测试模式信号的取值在所述测试时钟信号和所述数据信号中选择其中一个信号进行输出；
其中，若所述第一测试模式信号的取值为第一值，则选择所述测试时钟信号进行输出；若所述第一测试模式信号的取值为第二值，则选择所述数据信号进行输出。
在一些实施例中，所述延时模块包括M个移位寄存器，M为大于0的整数，其中：
第一个所述移位寄存器的输入端与所述初始命令信号连接，第y个所述移位寄存器的输入端与第y-1个所述移位寄存器的输出端连接，第M个移位寄存器的输出端用于输出所述目标命令信号；
每一个所述移位寄存器的时钟端均与所述时钟模块连接，其中，y为大于1且小于或者等于M的整数。
在一些实施例中，所述移位寄存器，用于将输入端接收到的信号延迟第一时钟周期进行输出；其中，所述第一时钟周期与M的乘积等于所述时间间隔。
在一些实施例中，所述移位寄存器包括L个触发器，且所述L个触发器串接在一起，L为大于0的整数，其中：
所述L个触发器的时钟端均与所述时钟模块连接，用于接收所述第一时钟信号，所述触发器的输出端与下一个所述触发器的输入端连接。
在一些实施例中，所述初始命令信号包括激活信号，所述目标命令信号包括读信号，或者；所述初始命令信号包括读信号，所述目标命令信号包括写信号，或者；所述初始命令信号包括写信号，所述目标命令信号包括预充电信号。
在一些实施例中，所述延时控制电路还包括缓冲模块，其中：
所述缓冲模块，配置为接收ECS命令信号，并根据所述ECS命令信号生成所述初始命令信号。
第二方面，本公开实施例提供了一种延时控制方法，应用于延时控制电路，所述方法包括：
通过时钟模块接收温度调节信号，根据所述温度调节信号生成第一时钟信号，且所述第一时钟信号的时钟周期为预设值；
通过延时模块接收所述第一时钟信号和初始命令信号，根据所述第一时钟信号对所述初始命令信号进行延时处理，得到目标命令信号；其中，所述目标命令信号与所述初始命令信号之间的时间间隔满足预设时序条件。
第三方面，本公开实施例提供了一种半导体存储器，包括如第一方面任一项所述的延时控制电路。
在一些实施例中，所述半导体存储器包括动态随机存取存储器DRAM。
本公开实施例提供了一种延时控制电路、方法和半导体存储器，延时控制电路包括时钟模块和延时模块，其中：时钟模块，配置为接收温度调节信号，根据温度调节信号生成第一时钟信号，且第一时钟信号的时钟周期为预设值；延时模块，配置为接收第一时钟信号和初始命令信号，根据第一时钟信号对初始命令信号进行延时处理，得到目标命令信号；其中，目标命令信号与初始命令信号之间的时间间隔满足预设时序条件。这样，时钟模块基于温度调节信号来产生第一时钟信号，使得第一时钟信号的时钟周期不受温度影响，然后根据第一时钟信号对初始命令信号进行延时处理，使得延时后的目标命令信号和初始时钟信号之间的时间间隔满足预设时序条件；从而不仅改善了温度对第一时钟信号的影响，使得在第一时钟信号下目标命令信号与初始命令信号之间的延迟时间满足时序条件，进而保证了延迟时间的准确度，提升了存储器的性能。
附图说明
图1为一种命令信号之间的时序关系示意图；
图2为本公开实施例提供的一种延时控制电路的组成结构示意图；
图3为本公开实施例提供的另一种延时控制电路的组成结构示意图；
图4A为本公开实施例提供的一种振荡器模块的具体结构示意图；
图4B为本公开实施例提供的一种振荡器模块的震荡波形示意图；
图4C为本公开实施例提供的另一种振荡器模块的具体结构示意图；
图5A为本公开实施例提供的又一种振荡器模块的具体结构示意图；
图5B为本公开实施例提供的另一种振荡器模块的震荡波形示意图；
图5C为本公开实施例提供的再一种振荡器模块的具体结构示意图；
图6为本公开实施例提供的又一种延时控制电路的组成结构示意；
图7为本公开实施例提供的一种时钟模块的组成结构示意图；
图8为本公开实施例提供的再一种延时控制电路的组成结构示意图；
图9为本公开实施例提供的一种延时模块的组成结构示意图；
图10为本公开实施例提供的一种移位寄存器的组成结构示意图；
图11为本公开实施例提供的一种移位寄存器的信号时序示意图；
图12为本公开实施例提供的一种延时控制方法的流程示意图；
图13为本公开实施例提供的一种半导体存储器的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅用于解释相关公开，而非对该公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关公开相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅仅是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
在DRAM等半导体存储器中，通常存在命令信号之间的时序要求，以执行ECS操作为例，在执行ECS操作的过程中，DRAM需要不同命令来实现不同的功能，内部产生不同命令之间存在时序的要求。图1为电子器件工程联合委员会(Joint Electron Device Engineering Council，JEDEC)规定的部分命令信号之间的时序关系示意图，如图1所示，在执行一次ECS操作时，DRAM内部自产生命令信号的顺序为激活信号(Active，ACT)、读操作信号或简称读信号(Read，RD)、写操作信号或简称写信号(Write，WR)和预充电信号(Precharge，PRE)，tRCD表示ACT到RD之间的时间间隔(或称“延时时间”、“延迟时间”)，WL表示RD到WR之间的时间间隔，tWR表示WR到PRE之间的时间间隔。由于所有命令信号均为内部自产生命令，DRAM需要内部控制从ACT到RD以及其它命令信号之间的时序，例如tRCD需要满足15纳秒(nanosecond，ns)。但是，由于DRAM内部的寄存器并没有记录tRCD等的数值，导致无法直接通过时钟移位来实现ACT到RD，以及其它命令信号之间的时序控制。
基于此，本公开实施例提供了一种延时控制电路，包括时钟模块和延时模块，其中：时钟模块，配置为接收温度调节信号，根据温度调节信号生成第一时钟信号，且第一时钟信号的时钟周期为预设值；延时模块，配置为接收第一时钟信号和初始命令信号，根据第一时钟信号对初始命令信号进行延时处理，得到目标命令信号；其中，目标命令信号与初始命令信号之间的时间间隔满足预设时序条件。这样，时钟模块基于温度调节信号来产生第一时钟信号，使得第一时钟信号的时钟周期不受温度影响，然后根据第一时钟信号对初始命令信号进行延时处理，使得延时后的目标命令信号和初始时钟信号之间的时间间隔满足预设时序条件；从而不仅改善了温度对第一时钟信号的影响，使得在第一时钟信号下目标命令信号与初始命令信号之间的延迟时间满足时序条件，进而保证了延迟时间的准确度，提升了存储器的性能。
下面将结合附图对本公开各实施例进行详细说明。
本公开的一实施例中，参见图2，其示出了本公开实施例提供的一种延时控制电路10的组成结构示意图，如图2所示，该延时控制电路10可以包括时钟模块11和延时模块12，其中：
时钟模块11，配置为接收温度调节信号，根据温度调节信号生成第一时钟信号，且第一时钟信号的时钟周期为预设值；
延时模块12，配置为接收第一时钟信号和初始命令信号，根据第一时钟信号对初始命令信号进行延时处理，得到目标命令信号；其中，目标命令信号与初始命令信号之间 的时间间隔满足预设时序条件。
需要说明的是，本公开实施例可以应用于DRAM等存储器中各命令信号之间的时序控制。其中，延时模块12配置为对初始命令信号进行延时处理得到目标命令信号，目标命令信号和初始命令信号之间的时间间隔满足预设时序条件。其中，初始命令信号用于执行第一操作，目标命令信号用于执行第二操作，具体的操作与命令信号的类型有关。例如，本公开实施例可以应用于DRAM在执行手动或者自动ECS操作时，内部自产生的ACT到RD之间的时序控制，或者RD到WR之间的时序控制，或者WR到PRE之间的时序控制。
也就是说，在本公开实施例中，初始命令信号可以包括激活信号，目标命令信号可以包括读信号，或者；初始命令信号可以包括读信号，目标命令信号可以包括写信号，或者；初始命令信号可以包括写信号，目标命令信号可以包括预充电信号。其中，激活信号用于执行激活操作，读信号用于执行读操作，写信号用于执行写操作，预充电信号用于执行预充电操作。
另外，本公开实施例不仅可以应用于自动ECS操作下内部自产生命令之间的时序控制，也可以应用于任意存储器内部产生命令信号之间的时序控制，例如激活/行寻址(Row Address Strobe，RAS)与读/写/列寻址(Column Address Strobe，CAS)之间的时间间隔等。下面仅以ECS过程中命令信号之间的时序控制为例对本公开实施例的实现进行详细描述。
以ACT到RD的时序控制为例，由于ACT和RD均为DRAM内部自产生命令，DRAM需要内部控制从ACT到RD的时间间隔满足预设时序条件(tRCD)，例如tRCD可以为15ns。
在对初始命令信号进行延时处理时，延时模块12需要一时钟信号作为时钟来延迟初始命令信号，对于由多用途命令(Multiple Purpose Command，MPC)产生的手动ECS操作和刷新命令(Refresh)产生的自动ECS操作，在这两种ECS模式下，存在有外部时钟信号，移位寄存器可以利用外部时钟信号作为时钟对初始命令信号进行延时处理。由于在不同频率下的外部时钟信号对应的时钟周期不同，导致所需要的寄存器的数量也不同，而外部时钟信号的具体频率无法得知，这时候需要借助模式寄存器信号MRS OP<3:0>进行译码，才能知道外部时钟信号的时钟周期，进而选择具体数量的移位寄存器，同时需要外部时钟信号(CK_t/CK_c)作为移位寄存器的时钟信号；因此，采用移位寄存器对初始命令信号进行延迟时，需要严格考虑时钟的问题。而对于由自刷新命令(Self Refresh)产生的自动ECS操作，由于没有外部时钟信号，移位寄存器无法通过延迟来实现内部产生tRCD的时序要求。基于此，本公开实施例使用时钟模块11来产生第一时钟信号，作为移位寄存器的时钟信号，在没有外部时钟信号的情况下，为移位寄存器提供时钟信号，使得移位寄存器能够实现对信号的延时。
另外，对于由MPC命令产生的手动ECS操作和刷新命令产生的自动ECS操作，同样可以在电路中增加时钟模块11，利用时钟模块11产生的第一时钟信号作为时钟实现对初始命令信号的延迟处理。也就是说，对于本身就存在外部时钟信号的电路，依然可以采用本公开实施例所提供的延时控制电路自生成第一时钟信号来实现命令信号之间的时序控制。
还需要说明的是，不仅仅是针对ECS操作中各命令信号之间的时序控制，对于存储器中任意两个命令信号或者其它信号之间的时序控制，都可以通过本公开实施例提供的延时控制电路实现。
还需要说明的是，时钟模块11是能够内部自产生时钟信号的模块，但是在实际使用中，温度的变化(包括外界环境温度变化导致存储器温度变化，或者存储器内部运行 导致的温度变化等)会对时钟模块11内部电路的性能产生影响，从而导致时钟模块11产生的时钟信号的时钟周期发生变化。如果延时模块12根据变化后的时钟信号对初始命令信号进行延迟处理，就会导致最终的目标命令信号和初始命令信号之间的时间间隔不满足预设时序条件。
例如：预设时序条件要求初始命令信号和目标命令信号之间的时间间隔为15ns，在温度稳定不变的情况下，时钟模块11生成的时钟信号的时钟周期为0.625ns，则延时模块12需要将初始命令信号延时24个时钟周期。如果温度发生变化，时钟模块11的性能受温度影响，生成的时钟信号的时钟周期变为0.63ns，这时候，延时模块12仍然将初始命令信号延时24个时钟周期，从而目标命令信号和初始命令信号之间的时间间隔为24×0.63＝15.12ns，不满足15ns的预设时序条件。
因此，本公开实施例通过温度调节信号对时钟模块11进行控制调整，使得时钟模块11生成时钟周期稳定为预设值的第一时钟信号。这样，不管温度如何变化，基于温度调节信号的调节，时钟模块11生成的第一时钟信号的时钟周期可以始终不受温度影响，从而延时模块12在根据第一时钟信号对初始命令信号进行延时处理时，保证得到的目标命令信号和初始命令信号的时间间隔满足预设时序条件。
进一步地，对于时钟模块11，参见图3，其示出了本公开实施例提供的另一种延时控制电路10的组成结构示意图。如图3所示，在一些实施例中，时钟模块11可以包括温度检测模块111和振荡器模块112，其中：
温度检测模块111，配置为监测时钟模块11的温度变化，根据温度变化生成温度调节信号；
振荡器模块112，配置为接收温度调节信号，根据温度调节信号对内部的模块结构进行调整，生成第一时钟信号。
需要说明的是，如图3所示，时钟模块11可以包括用于生成温度调节信号的温度检测模块111和用于生成第一时钟信号的振荡器模块112。其中，温度检测模块111可以实时或者间隔一定时间对时钟模块11的温度变化进行监测，并根据温度变化生成温度调节信号发送给振荡器模块112，温度调节模块111可以为温度传感器(Temperature Sensor)；振荡器模块112在接收到温度调节信号之后，根据温度调节信号对自身内部的模块结构进行调整，使得振荡器模块112生成的第一时钟信号的时钟周期稳定为预设值，不会随温度发生变化，从而保证了第一时钟信号作为时钟的可靠性。
进一步地，对于振荡器模块112，参见图4A，其示出了本公开实施例提供的一种振荡器模块112的具体结构示意图。如图4A所示，振荡器模块112可以包括输入端1121、若干个反相器1122和输出端1123；其中，若干个反相器1122的数量为奇数个，且若干个反相器1122串联在一起，最后一个反相器1122的输出端与第一个反相器1122的输入端连接，在输入端1121处给振荡器模块112一输入信号，使振荡器模块112起荡，在输出端1123处会产生具有一定频率的时钟信号，该时钟信号的频率与各反相器1122的延迟值有关，即该时钟信号的时钟周期与各反相器1122的延迟值有关。
在一种具体的实施例中，振荡器模块112可以为一环形振荡器(Ring oscillator，Ring OSC)，也可简称为振荡器。
示例性地，如果在输入端1121处给振荡器模块112输入一个高电平信号(用1表示)，那么经过奇数个反相器1122之后，最后一个反向器1122输出低电平信号(用0表示)，并在输出端1123处输出，同时最后一个反相器1122输出的0还被传输至第一个反向器1122，并经过奇数个反相器输出为1，如此，就能够在输出端1123处得到满足一定频率的时钟信号。
以振荡器模块112包括3个反相器为例，图4B为该振荡器模块的震荡波形示意图。 如图4B所示，CLK1表示第一个反相器输出的信号的波形图，CLK2表示第二个反相器输出的信号的波形图，CLK表示第三个反相器输出的信号的波形图，也即最终得到的第一时钟信号。其中，在输入端1121处给振荡器模块112提供一个低电平信号(即逻辑0)，那么经过第一个反相器后得到的就是高电平信号(即逻辑1)，再经过第二个反相器得到逻辑0，再经过第三个反相器得到逻辑1，逻辑1被输出为第一时钟信号，同时逻辑1又返回输入到第一个反相器，经过三个反相器之后得到逻辑0，逻辑0被输出为第一时钟信号，并返回输入到第一个反相器，同时考虑反相器的延迟效果，最终得到的第一时钟信号如图4B所示。
在此基础上，在一些实施例中，振荡器模块112，配置为根据温度调节信号控制内部产生时钟信号所需的反相器数量，以实现对内部的模块结构进行调整，使得第一时钟信号的时钟周期为预设值。
需要说明的是，当温度发生变化时，反相器1122的延迟值会发生变化，导致生成的时钟信号的时钟周期发生变化，因此，本公开实施例根据温度调节信号对振荡器模块112内部用于产生时钟信号需要的反相器进行数量调节，根据温度调节信号增加或者减少用于产生时钟信号的反相器的数量，以改善温度对第一时钟信号的时钟周期的影响，得到时钟周期稳定的第一时钟信号。
具体来说，在一些实施例中，振荡器模块，配置为若温度调节信号指示温度变化呈上升趋势，则减小内部产生时钟信号所需的反相器数量；或者，
振荡器模块，配置为若温度调节信号指示温度变化呈下降趋势，则增加内部产生时钟信号所需的反相器数量。
需要说明的是，在高温情况下，单个反相器的延时变大，这时候可以根据温度调节信号使并入环形振荡器的反相器的数量减少来使第一时钟信号的时钟周期稳定不变；在低温情况下，单个反相器的延时减小，这时候可以根据温度调节信号使并入环形振荡器的反相器的数量增加，来使第一时钟信号的时钟周期稳定不变。
在图4A的基础上，参见图4C，其示出了本公开实施例提供的另一种振荡器模块112的具体结构示意图，如图4C所示，在一些实施例中，振荡器模块112包括A个反相器1122和B个开关模块1124，A个反相器串联在一起，而且第A个反相器1122的输出端和第一个反相器1122的输入端连接；第b个开关模块1124连接在第a个反相器1122的输出端和第一个反相器1122的输入端之间；A和B均为大于0的整数，a为大于0且小于或者等于A的整数，b为大于0且小于或者等于B的整数，其中：
当B个开关模块1124均断开时，振荡器模块112内部的用于产生时钟信号的反相器的数量为A个；
当第b个开关模块导通，其余的开关模块1124均断开时，振荡器模块112内部的用于产生时钟信号的反向器1122的数量为a个。
需要说明的是，由于需要产生周期性变化的第一时钟信号，因此环形振荡器所包含的反相器的数量通常是奇数个(如果是偶数个，输出就会始终不变，无法得到具有高电平和低电平的时钟信号)。基于此，在对环形振荡器所包含的反相器的数量进行调节时，需要保证调节后的用于产生时钟信号的反相器的数量为奇数个，因此，在本公开实施例中，开关模块1124的数量B通常是小于反相器1122的数量A的，而且第b个开关模块1124连接在第a个反相器1122的输出端和第一个反相器1122的输入端之间，这里的a通常指大于0且小于A的奇数。另外，基于环形震荡器的实际实现，通常不会只包含一个反相器，因此更具体的，这里的a通常不为1。
在图4C所示的示例中，最后一个反相器1122的输出端和第一个反相器1122的输出端之间没有连接开关模块1124，在其它的示例中，这两者之间也可以连接开关模块 1124。如图4C所示，在所有的开关模块1124都断开的情况下，A个反相器1122全部接入电路中，用于产生第一时钟信号；如果第一个开关模块1124导通，其余的开关模块1124均断开，则第1个至第3个反相器1122接入电路中，用于产生第一时钟信号；如果第二个开关模块1124导通，其余的开关模块1124均断开，则第1个至第5个反相器1122接入电路中，用于产生第一时钟信号。
也就是说，在图4C所示的振荡器模块112中，需要几个反相器1122参与生成第一时钟信号，就导通第几个反相器1122的输出端与第一个反相器1122的输入端之间的开关模块1124，其余的开关模块1124均保持断开；如果需要所有反相器1122都接入电路中，将把所有的开关模块1124都断开。另外，也可以在最后一个反相器1122和第一个反相器1122之间也增加一开关模块，当需要所有的反相器1122都并入电路时，就导通最后一个反相器1122和第一个反相器1122之间的开关模块即可。
这样，本公开实施例可以根据温度调节信号来控制开关模块的导通和断开，进而控制振荡器模块内部用于产生时钟信号的反相器的数量，从而保证在温度发生变化的情况下，振荡器模块输出时钟周期稳定的第一时钟信号。
另外，本公开是实施例也可以通过在电路中增加选择器等方式来实现改变接入电路的反相器的数量，图4C仅为一种示例性的实现方式，只要能够实现根据温度变化增加或者减少反相器的数量，就能够满足使第一时钟信号的时钟周期稳定的需求。
在一些实施例中，温度调节信号可以为温度调节码，温度调节码的取值与增加或减少的反相器数量具有对应关系。
需要说明的是，温度调节信号具体可以为温度调节码，温度调节码取值的不同指示增加或者减少的反向器的数量不同。例如，温度调解码的取值为0表示不需要改变反相器的数量，温度调节码的取值为正值则表示需要减小反相器的数量，且正值越大，需要减小的数量就越多，温度调节码的取值为负值则表示需要增加反相器的数量，且负值的绝对值越大，需要增加的数量就越多。或者，也可以是，温度调节码的取值为正值则表示需要增加反相器的数量，温度调节码的取值为负值则表示需要减少反相器的数量等，对此不作具体限定。
另外，温度调节信号还可以与时钟模块的温度值对应，因此，在一些实施例中，温度调节信号的取值与振荡器模块内部产生时钟信号所需的反相器数量具有对应关系。这样，温度调节信号的取值对应一个具体的温度值，与该温度值对应有反相器数量，或者与该温度值所属的温度范围对应有反相器数量，从而也可以直接根据温度调节信号的取值实现对反相器数量的调整。
这样，本公开实施例可以通过不同的方式实现对振荡器模块内部用于产生时钟信号的反相器数量的调整，实现在温度变化的情况下，第一时钟信号的时钟周期不受温度影响，稳定为预设值。
进一步地，在另一些实施例中，振荡器模块还可以通过与非门和缓冲器来实现。参见图5A，其示出了本公开实施例提供的又一种振荡器模块112的具体结构示意图，如图5A所示，在一些实施例中，振荡器模块112可以包括与非门1125和若干个缓冲器1126，其中：
振荡器模块112，配置为根据温度调节信号控制内部产生时钟信号所需的缓冲器数量，以实现对内部的模块结构进行调整，使得第一时钟信号的时钟周期为预设值。
需要说明的是，如图5A所示，一个与非门1125与若干个缓冲器1126组成振荡器模块(环形振荡器)，若干个缓冲器1126的输出端和输入端首尾相接，构成环状。图5B是该振荡器模块的振荡波形示意图，如图5B所示，该振荡器模块在获取Reset(重置)信号后，开始起振，振荡频率与每一级缓冲器的延迟值相关，不考虑Reset信号引入延 迟的影响时，振荡波形如图5B所示，以缓冲器的数量为四个为例，其中，CLK0表示与非门1125输出的信号的波形，CLK1表示第一个缓冲器1126输出的信号的波形，CLK2表示第二个缓冲器1126输出的信号的波形，CLK3表示第三个缓冲器1126输出的信号的波形，CLK表示第四个缓冲器1126输出的信号(即第一时钟信号)的波形。根据该波形图可以看出，前一级缓冲器输出的信号的下降沿或者上升沿依次向后传递，到最后一级后反向重新开始，最终得到周期性的第一时钟信号。
在一些实施例中，振荡器模块112，配置为若温度调节信号指示温度变化呈上升趋势，则减小内部产生时钟信号所需的缓冲器数量，或者；
振荡器模块112，配置为若温度调节信号指示温度变化呈下降趋势，则增加内部产生时钟信号所需的缓冲器数量。
需要说明的是，对于图5A提供的振荡器模块112，可以通过温度调节信号改变其内部产生时钟信号所需的缓冲器数量来使时钟周期稳定，时钟周期与缓冲器的延迟值有关。其调节方式与前述图4A提供的振荡器模块112的调节方式类似，这里不再过多赘述，仅以图5C示出的具体结构示意图进行简单说明。如图5所示，该振荡器模块112还可以包括若干个开关模块1124，且开关模块1124连接在缓冲器1126的输出端和与非门1125的输入端之间。通过控制某一缓冲器和与非门之间的开关模块导通，其余开关模块均断开，从而将该缓冲器以及该缓冲器之前的缓冲器并入环形振荡器中，用于生成第一时钟信号。
结合以上陈述，在本公开实施例中，振荡器模块中可以包括若干个串联的振荡器件(反相器或者缓冲器)，振荡器模块，配置为根据温度调节信号控制内部产生时钟信号所需的振荡器件数量，以实现对内部的模块结构进行调整，使得第一时钟信号的时钟周期为预设值。
具体地，振荡器模块112，配置为若温度调节信号指示温度变化呈上升趋势，则减小内部产生时钟信号所需的振荡器件数量，或者；
振荡器模块112，配置为若温度调节信号指示温度变化呈下降趋势，则增加内部产生时钟信号所需的振荡器件数量。
这样，本公开实施例通过温度调节信号来改变振荡器模块中用于产生时钟信号所需的震荡器件的数量，使得在温度发生变化的情况下，仍然能够生成时钟周期稳定的第一时钟信号。
还需要说明的是，本公开实施例使用振荡器产生的第一时钟信号作为移位寄存器的时钟信号，然而除了温度之外，在器件的制造和使用过程中，工艺、电压等因素也会对器件的性能产生影响，即振荡器会受工艺、电压和温度(Process Voltage Temperature，PVT)的影响。除了考虑温度的影响，本公开实施例还考虑工艺和电压的影响。参见图6，其示出了本公开实施例提供的又一种延时控制电路10的组成结构示意图。如图6所示，在一些实施例中，时钟模块11还可以包括熔丝模块113，其中：
熔丝模块113，配置为向振荡器模块112提供熔丝信号；其中，熔丝信号指示的目标模式值是在测试模式下确定的；
振荡器模块112，还配置为根据熔丝信号和温度调节信号生成第一时钟信号。
需要说明的是，如图6所示，熔丝模块113与振荡器模块112连接，配置为向振荡器模块112提供熔丝信号，振荡器模块112接收熔丝信号和前述的温度调节信号，并据此生成第一时钟信号，其中，温度调节信号能够改善温度对时钟周期的影响，熔丝信号则能够改善工艺和电压对时钟周期的影响。
还需要说明的是，在存储器正式使用的过程中，熔丝模块113提供的熔丝信号所指示的值是已经确定的目标模式值，是在测试模式下确定出来的具体值。也就是说，在存 储器的正式使用过程中，振荡器模块112接收取值固定的熔丝信号和随温度变化的温度调节信号来生成第一时钟信号，使得第一时钟信号的时钟周期固定为预设值。
这样，本公开实施例不仅可以通过温度调节信号改善温度对时钟周期的影响，还可以通过熔丝信号改善工艺和电压对时钟周期的影响，使得第一时钟信号的周期稳定为预设值。
对于熔丝信号的确定方式，参见图7，图7为本公开实施例提供的一种时钟模块11的组成结构示意图，在一些实施例中，如图7所示，时钟模块11还可以包括选择模块114，其中：
熔丝模块113，还配置为在测试模式下，设置第二测试模式信号的取值为第一候选模式值，并将第二测试模式信号发送给振荡器模块112；
振荡器模块112，还配置为根据第二测试模式信号，生成测试时钟信号；
选择模块114，配置为接收第一测试模式信号，并根据第一测试模式信号选择测试时钟信号进行输出。
在一些实施例中，熔丝模块113，还配置为若测试时钟信号的时钟周期等于预设值，则将第一候选模式值作为目标模式值并烧入预设熔丝中，以使得熔丝信号指示的目标模式值与第二测试模式信号的取值相同。
需要说明的是，如图7所示，时钟模块11还可以包括选择模块114，配置为与熔丝模块113和振荡器模块112配合以确定熔丝信号指示的目标模式值。在测试模式下，熔丝模块113中熔丝信号的值还未确定，可以通过测试机台发送指令来生成不同的第二测试模式信号的值，并对比在每种第二测试模式信号对应的值下，振荡器模块112输出的测试时钟信号的时钟周期，当测试时钟信号的时钟周期满足所需的预设值时，所对应的第二测试模式信号的值就是确定出来的目标模式值。
对于选择模块114而言，如图7所示，在一些实施例中，选择模块114的第一输入端与振荡器模块112的输出端连接，用于接收测试时钟信号，选择模块114的第二输入端与数据信号连接，选择模块114的控制端与第一测试模式信号连接，其中：
选择模块114，配置为接收第一测试模式信号，根据第一测试模式信号的取值在测试时钟信号和数据信号中选择其中一个信号进行输出；
其中，若第一测试模式信号的取值为第一值，则选择测试时钟信号进行输出；若第一测试模式信号的取值为第二值，则选择数据信号进行输出。
需要说明的是，选择模块114可以为二选一选择器(2-1MUX)，包括第一输入端、第二输入端、控制端和输出端，其中，第一输入端用于接收振荡器模块112发送的测试时钟信号，第二输入端用于接收数据信号(例如读取到的数据信号)，控制端用于接收第一测试模式信号，并根据第一测试模式信号选择测试时钟信号或者数据信号作为选择模块114的输出信号，选择模块114的输出端用于将被选择的信号进行输出。需要注意的是，选择模块114并不局限于二选一选择器，这里不作任何限定。
还需要说明的是，当处于测试模式时，需要对测试时钟信号的时钟周期进行检测，就需要将测试时钟信号作为选择模块114的输出，这时候第一测试模式信号(Test Mode1，简称为TM1)的取值为第一值，选择测试时钟信号作为选择模块114的输出；当不处于测试模式时，第一测试模式信号的取值为第二值，选择数据信号作为选择模块114的输出，以实现电路的其它功能需求。其中，第一值可以为1，第二值可以为0。
这样，通过第一测试模式信号将测试时钟信号选择性输出，进而实现对测试时钟信号的时钟周期监测。
具体来说，在测试模式下，熔丝模块113首先设置第二测试模式信号(简称为TM2)的取值为第一候选模式值，然后将第二测试模式信号发送给振荡器模块112，基于第二 测试模式信号，振荡器模块112会对自身所包含的器件的性能进行调整，从而改变振荡器模块112生成的时钟信号的时钟周期，将测试模式下振荡器模块112生成的时钟信号记作测试时钟信号。振荡器模块112生成测试时钟信号后，将测试时钟信号发送给选择模块114，选择模块114接收第一测试模式信号，并根据第一测试模式信号选择测试时钟信号进行输出(在第一测试模式信号为第一值的情况下)，这时候可以检测选择模块114输出的测试时钟信号的时钟周期，并判断检测到的时钟周期是否等于预设值，如果等于，就将第一候选模式值烧入预设熔丝中作为目标模式值，从而预设熔丝提供的熔丝信号指示的值就固定为第二测试模式信号指示的目标模式值。
如果检测到的时钟周期不等于预设值，则说明第一候选模式值不满足需求，则继续生成下一个候选模式值发送给振荡器模块112，并检测测试时钟信号的时钟周期。因此，在一些实施例中，熔丝模块113，还配置为若测试时钟信号的时钟周期不等于预设值，则设置第二测试模式信号的取值为第二候选模式值，继续执行将第二测试模式信号发送给振荡器模块的步骤，直至测试时钟信号的时钟周期等于预设值，将第二测试模式信号当前的候选模式值作为目标模式值并烧入预设熔丝中，以使得熔丝信号指示的目标模式值与第二测试模式信号的取值相同。
需要说明的是，如果测试时钟信号的时钟周期不等于预设值，就需要利用下一个候选模式值继续对测试时钟信号的时钟周期进行调整，因此设置第二测试模式信号的取值为第二候选模式值，并将第二测试模式信号发送给振荡器模块112，振荡器模块112基于第二测试模式信号进行调整生成测试时钟信号，并由选择模块114进行选择输出，继续检测选择模块114输出的测试时钟信号的时钟周期，如果与预设值相同，就将第二候选模式值作为目标模式值烧入预设熔丝中，如果时钟周期与预设值不同，就继续生成下一个候选模式值，直到生成的测试时钟信号的时钟周期与预设值相同，将对应的候选模式值烧入预设熔丝中。
也就是说，在一般常用的测试模式下，对应某些测试模式信号(TM)准备了对应的熔丝(FUSE)，由于TM是测试机台发送指令完成的，不具备永久性。当测试阶段确定TM2的数值之后，可以将对应的FUSE2的数值，通过烧入熔丝的方式，使FUSE2的数值等于TM2，FUSE2的数值就替代了TM2，起到了相同的作用，且具有永久性。
还需要说明的是，在测试模式下确定出的目标模式值是用于改善工艺和电压对振荡器模块112产生的时钟信号的时钟周期的影响，因此可以将执行测试模式时的温度设置为固定的基准温度，基于此，温度调节模块在判断温度呈上升趋势还是下降趋势时，可以是将检测到的温度和基准温度进行比较，进而确定温度变化趋势。
这样，熔丝模块可以向振荡器模块提供熔丝信号，基于熔丝信号可以改善电压和工艺对时钟周期的影响，最终在熔丝信号和温度调节信号的共同作用下，第一时钟信号的时钟周期能够不受PVT影响，从而稳定为预设值。
进一步地，对于延时模块12而言，参见图8，其示出了本公开实施例提供的再一种延时控制电路10的组成结构示意图。如图8所示，在一些实施例中，延时模块12可以包括M个移位寄存器121，M为大于0的整数，其中：
第一个移位寄存器121的输入端与初始命令信号连接，第y个移位寄存器121的输入端与第y-1个移位寄存器121的输出端连接，第M个移位寄存器121的输出端用于输出目标命令信号；
每一个移位寄存器121的时钟端均与时钟模块11连接，其中，y为大于1且小于或者等于M的整数。
需要说明的是，如图8所示，延时模块12可以由M个串接在一起的移位寄存器121组成。进一步地，以M等于6为例，参见图9，其示出了本公开实施例提供的一种延时 模块12的组成结构示意图，如图9所示，将第1个至第6个移位寄存器分别记作移位寄存器1、移位寄存器2、移位寄存器3、移位寄存器4、移位寄存器5和移位寄存器6，每个移位寄存器的时钟端用CLK表示，每个移位寄存器的时钟端均与时钟模块11连接，具体是与时钟模块11中的振荡器模块112连接，用于接收第一时钟信号作为延时所用的时钟。
其中，移位寄存器1的输入端用于接收初始命令信号，并以第一时钟信号为时钟对初始命令信号进行延时处理，得到中间命令信号RD<0>，并通过其输出端进行输出；移位寄存器2的输入端用于接收中间命令信号RD<0>，并以第一时钟信号为时钟对中间命令信号RD<0>进行延时处理，得到中间命令信号RD<1>，并通过其输出端进行输出；后面的移位寄存器同理执行，直至移位寄存器6的输入端接收中间命令信号RD<4>，并以第一时钟信号为时钟对中间命令信号RD<4>进行延时处理，得到目标命令信号，并在其输出端进行输出。
对于每一个移位寄存器，在一些实施例中，移位寄存器，用于将输入端接收到的信号延迟第一时钟周期进行输出；其中，第一时钟周期与M的乘积等于时间间隔。
需要说明的是，在本公开实施例中，每一个移位寄存器的组成可以均是相同的，能够将其输入端接收到的信号延迟第一时钟周期后进行输出，由于移位寄存器的数量有M个，目标命令信号和初始命令信号之间的时间间隔即为第一时钟周期和M的乘积。
示例性地，假如预设时序条件要求初始命令信号和目标命令信号之间的时间间隔为15ns，每个移位寄存器能够将输入其中的信号延迟四个时钟周期后输出，那么六个移位寄存器能够实现将初始命令信号延时24个时钟周期，计算可得每个时钟周期为0.625ns，这时候时钟模块11生成时钟周期稳定为0.625ns的第一时钟信号，并以此实现对初始命令信号的延时处理。
进一步地，对于移位寄存器，以移位寄存器1为例，参见图10，其示出了本公开实施例提供的一种移位寄存器的组成结构示意图。如图10所示，在一些实施例中，移位寄存器可以包括L个触发器，且L个触发器串接在一起，L为大于0的整数，其中：
L个触发器的时钟端均与时钟模块连接，用于接收第一时钟信号，触发器的输出端与下一个触发器的输入端连接。
需要说明的是，在本公开实施例中，触发器可以为D触发器(D Flip-Flop，DFF)，可以用DFF表示。
在一些实施例中，触发器，用于将输入端接收到的信号延迟第二时钟周期后进行输出；其中，第一时钟周期等于第二时钟周期与L的乘积，第二时钟周期等于第一时钟信号的时钟周期。也就是说，一个触发器可以实现将信号延时第一时钟信号的时钟周期后输出。
示例性地，以L等于4为例，一个移位寄存器可以由四个D触发器串联组成。每个D触发器的输入端(D)用于接收输入该D触发器的信号，每个D触发器的时钟端(用CLK表示)用于接收第一时钟信号，利用第一时钟信号对接收到的信号进行延时后在输出端(Q)进行输出。
仍以L等于4为例，对于图9中的移位寄存器1，如图10所示，该移位寄存器1包括第一触发器DFF1、第二触发器DFF2、第三触发器DFF3和第四触发器DFF4，其中：
第一触发器DFF1、第二触发器DFF2、第三触发器DFF3和第四触发器DFF4的时钟端均与时钟模块连接；
第一触发器DFF1的输入端初始命令信号连接，第一触发器DFF1的输出端与第二触发器DFF2的输入端连接；
第二触发器DFF2的输出端与第三触发器DFF3的输入端连接；
第三触发器DFF3的输出端与第四触发器DFF4的输入端连接；
第四触发器DFF4的输出端用于输出移位寄存器1的输出信号。
需要说明的是，对于每个移位寄存器，其结构均可以如图10所示，只是对于不同位置的移位寄存器，其输入和输出不同，对于移位寄存器1，其输入为初始命令信号，输出为中间命令信号RD<0>；对于移位寄存器2，其输入为中间命令信号RD<0>，输出为中间命令信号RD<1>；对于其它移位寄存器依次类推，最终在最后一个移位寄存器的最后一个触发器的输出端得到目标命令信号，从而实现对初始命令信号的延时处理，得到满足时序条件的目标命令信号。
这样，由于第一时钟信号的时钟周期是固定的，对于预设时序条件要求的时间间隔，所需移位寄存器的数量固定为：
Figure PCTCN2022127123-appb-000001
其中，tRCD表示时间间隔，t表示第一时钟信号的时钟周期，L表示每个移位寄存器中触发器的数量，t×L表示每个移位寄存器能够将信号延时的时间。
以图9所示的延时模块12为例，其对应的信号时序如图11所示。在图11中，ACT(或者表示为ECS_ACT)为初始命令信号，CLK(或者表示为ECS_CLK)为第一时钟信号，RD<0:4>为中间命令信号，RD(或者表示为ECS_RD)为目标命令信号。具体地，如图11所示，用振荡器模块112的输出CLK作为延时模块12的时钟信号，该时钟信号受PVT的影响不大，其时钟周期是固定的，因此移位寄存器的数量也是确定的。在图11中，以CLK的时钟周期是0.625ns为例，每一级移位寄存器延迟4个时钟周期，因此延迟15ns需要6个移位寄存器进行串联。第1个移位寄存器的输出RD<0>相对ACT延迟4个时钟周期，同样，第2个移位寄存器的输出RD<1>相对ACT延迟8个时钟周期，第3个移位寄存器的输出RD<2>相对ACT延迟12个时钟周期，第4个移位寄存器的输出RD<3>相对ACT延迟16个时钟周期，第5个移位寄存器的输出RD<4>相对ACT延迟20个时钟周期，第6个移位寄存器的输出RD相对ACT延迟24个时钟周期；也就是说，输入ACT到输出RD之间延迟24个时钟周期(共15ns)。
进一步地，如图8所示，在一些实施例中，该延时控制电路10还可以包括缓冲模块13，其中：
缓冲模块13，配置为接收ECS命令信号，并根据ECS命令信号生成初始命令信号。
需要说明的是，当DRAM处于ECS模式时，初始命令信号为激活信号时，初始命令信号可以是基于ECS信号产生的，因此还可以通过缓冲模块13根据ECS命令信号来得到初始命令信号，并进一步对初始命令信号进行如前述的处理，最终得到目标命令信号。
在这里，缓冲模块(Buffer)也可以称为“传输门”，不仅具有延时功能，而且还可以具有增强信号驱动能力的作用。具体地，对于ECS命令信号与初始命令信号而言，初始命令信号相比ECS命令信号不仅存在时延，而且初始命令信号的驱动能力更强。
简言之，以ECS操作为例，对于手动ECS操作，可以使用外部时钟信号作为移位寄存器的延时时钟，然后来移动相应个数的周期，实现ACT到RD之间tRCD的延时需求。但是在Self_Refresh时外部没有时钟，寄存器无法延迟满足内部产生tRCD的时间要求。为了解决在Self_Refresh时外部没有时钟的问题，本公开实施例利用环形振荡器产生的信号作为移位寄存器的时钟信号，但是普通的环形振荡器所产生时钟的周期受PVT影响较大。
为了减少时钟周期受温度的影响，本公开实施例在环形振荡器中加上温度的控制调节，可以通过DRAM内部的温度传感器监测温度的变化并输出温度调节信号，可以调节不同温度下环形振荡器产生的时钟周期，使其保持稳定。例如，在高温情况下，单个 反相器的延时变大，可以通过温度调节信号使并入环形振荡器的反相器减少来使总的时钟周期不变，低温下同理。
在测试模式下，使用TM1将环形振荡器产生的测试时钟信号选择输出到选择器的输出端用来监测测试时钟信号的时钟周期，再通过第二测试模式信号(TM2)和熔丝(FUSE2)来调节环形振荡器所产生的测试时钟信号的时钟周期。在硅片测试过程中，可以通过这两个测试模式信号调整并检测测试时钟信号的时钟周期，使其稳定在预设值，减小工艺和电压的影响。然后在确定TM2之后，利用对应的FUSE2将TM2烧入熔丝固定。
ECS命令信号经过缓冲模块产生初始命令信号作为移位寄存器的输入信号，环形振荡器产生的第一时钟信号作为移位寄存器的时钟，这样即使在Self_Refresh时，外部没有时钟的情况下，环形振荡器也会产生不随PVT变化的时钟信号。由于环形振荡器产生的信号是固定的，不受外部频率影响，因此第一时钟信号的时钟周期是确定的，同时移位寄存器的数量也是确定的值。
本公开实施例涉及集成电路设计中内部产生命令之间的时序的相关电路，特别涉及DRAM芯片中，DRAM需要不同命令信号来实现不同的功能，内部产生不同命令信号之间存在时序的要求，可以应用于DRAM中执行自动ECS操作下ACT到RD之间的时序控制电路，但不局限于此范围，其他内部产生不同命令信号之间时序控制的相关电路均可采用此方案。
本公开实施例提供了一种延时控制电路，包括时钟模块和延时模块，其中：时钟模块，配置为接收温度调节信号，根据温度调节信号生成第一时钟信号，且第一时钟信号的时钟周期为预设值；延时模块，配置为接收第一时钟信号和初始命令信号，根据第一时钟信号对初始命令信号进行延时处理，得到目标命令信号；其中，目标命令信号与初始命令信号之间的时间间隔满足预设时序条件。这样，时钟模块基于温度调节信号来产生第一时钟信号，使得第一时钟信号的时钟周期不受温度影响，同时还通过熔丝信号进行调节，使得第一时钟信号的时钟周期也不会受工艺和电压的影响，得到时钟周期稳定为预设值的时钟信号；然后根据第一时钟信号对初始命令信号进行延时处理，使得延时后的目标命令信号和初始时钟信号之间的时间间隔满足预设时序条件；从而使得在第一时钟信号下目标命令信号与初始命令信号之间的延迟时间满足时序条件，进而保证了延迟时间的准确度，提升了存储器的性能。
本公开的另一实施例中，参见图12，其示出了本公开实施例提供的一种延时控制方法的流程示意图，如图12所示，该方法可以包括：
S1001：通过时钟模块接收温度调节信号，根据温度调节信号生成第一时钟信号，且第一时钟信号的时钟周期为预设值。
S1002：通过延时模块接收第一时钟信号和初始命令信号，根据第一时钟信号对初始命令信号进行延时处理，得到目标命令信号；其中，目标命令信号与初始命令信号之间的时间间隔满足预设时序条件。
需要说明的是，该方法应用于前述实施例提供的延时控制电路。
在一些实施例中，根据温度调节信号生成第一时钟信号，可以包括：
通过温度检测模块监测时钟模块的温度变化，根据温度变化生成温度调节信号；
通过振荡器模块接收温度调节信号，根据温度调节信号对内部的模块结构进行调整，生成第一时钟信号。
在一些实施例中，根据温度调节信号对内部的模块结构进行调整，可以包括：
根据温度调节信号控制内部产生时钟信号所需的反相器数量，以实现对内部的模块结构进行调整，使得第一时钟信号的时钟周期为预设值。
在一些实施例中，根据温度调节信号控制内部产生时钟信号所需的反相器数量，可以包括：
若温度调节信号指示温度变化呈上升趋势，则减小内部产生时钟信号所需的反相器数量；或者，
若温度调节信号指示温度变化呈下降趋势，则增加内部产生时钟信号所需的反相器数量。
在一些实施例中，该方法还可以包括：
通过熔丝模块向振荡器模块提供熔丝信号；其中，熔丝信号指示的目标模式值是在测试模式下确定的；
通过振荡器模块接收熔丝信号，根据熔丝信号和温度调节信号生成第一时钟信号。
在一些实施例中，该方法还可以包括：
在测试模式下，通过熔丝模块设置第二测试模式信号的取值为第一候选模式值，并将第二测试模式信号发送给振荡器模块；
通过振荡器模块接收第二测试模式信号，根据第二测试模式信号，生成测试时钟信号；
通过选择模块接收第一测试模式信号，并根据第一测试模式信号选择测试时钟信号进行输出；
若测试时钟信号的时钟周期等于预设值，则将第一候选模式值作为目标模式值并烧入预设熔丝中，以使得熔丝信号指示的目标模式值与第二测试模式信号的取值相同。
在一些实施例中，该方法还可以包括：
若测试时钟信号的时钟周期不等于预设值，则通过熔丝模块设置第二测试模式信号的取值为第二候选模式值，继续执行将第二测试模式信号发送给振荡器模块的步骤，直至测试时钟信号的时钟周期等于预设值，将第二测试模式信号当前的候选模式值作为目标模式值并烧入预设熔丝中，以使得熔丝信号指示的目标模式值与第二测试模式信号的取值相同。
在一些实施例中，通过选择模块接收第一测试模式信号，并根据第一测试模式信号选择测试时钟信号进行输出，可以包括：
通过选择模块接收第一测试模式信号，根据第一测试模式信号的取值在测试时钟信号和数据信号中选择其中一个信号进行输出；
其中，若第一测试模式信号的取值为第一值，则选择测试时钟信号进行输出；若第一测试模式信号的取值为第二值，则选择数据信号进行输出。
在一些实施例中，初始命令信号包括激活信号，目标命令信号包括读信号，或者，初始命令信号包括读信号，目标命令信号包括写信号；或者；初始命令信号包括写信号，目标命令信号包括预充电信号。
在一些实施例中，该方法还可以包括：通过缓冲模块ECS命令信号，并对ECS命令信号进行延时与驱动增强处理，得到初始命令信号。
本公开实施例提供了一种延时控制方法，应用于前述实施例所述的延时控制电路，该方法能够得到时钟周期不受PVT影响的第一时钟信号，从而能够使得目标命令信号和初始时钟信号之间的时间间隔满足预设时序条件，进而保证了延迟时间的准确度，提升了存储器的性能。
本公开的再一实施例中，参见图13，其示出了本公开实施例提供的一种半导体存储器20的组成结构示意图。如图13所示，该半导体存储器20至少包括前述实施例任一项所述的延时控制电路10。
在一些实施例中，该半导体存储器20包括DRAM。
在本公开实施例中，对于DRAM来说，不仅可以符合DDR、DDR2、DDR3、DDR4、DDR5等内存规格，还可以符合LPDDR、LPDDR2、LPDDR3、LPDDR4、LPDDR5等内存规格，这里不作任何限定。
在本公开实施例中，对于该半导体存储器20而言，由于其包括前述实施例所述的延时控制电路，从而能够提高内部命令信号之间延迟时间的准确度，实现命令信号之间的时序控制。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或电路实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或电路实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种延时控制电路、方法和半导体存储器，延时控制电路包括时钟模块和延时模块，其中：时钟模块，配置为接收温度调节信号，根据温度调节信号生成第一时钟信号，且第一时钟信号的时钟周期为预设值；延时模块，配置为接收第一时钟信号和初始命令信号，根据第一时钟信号对初始命令信号进行延时处理，得到目标命令信号；其中，目标命令信号与初始命令信号之间的时间间隔满足预设时序条件。这样，时钟模块基于温度调节信号来产生第一时钟信号，使得第一时钟信号的时钟周期不受温度影响，然后根据第一时钟信号对初始命令信号进行延时处理，使得延时后的目标命令信号和初始时钟信号之间的时间间隔满足预设时序条件；从而不仅改善了温度对第一时钟信号的影响，使得在第一时钟信号下目标命令信号与初始命令信号之间的延迟时间满足时序条件，进而保证了延迟时间的准确度，提升了存储器的性能。

Claims (17)

  1. 一种延时控制电路，包括时钟模块和延时模块，其中：
    所述时钟模块，配置为接收温度调节信号，根据所述温度调节信号生成第一时钟信号，且所述第一时钟信号的时钟周期为预设值；
    所述延时模块，配置为接收所述第一时钟信号和初始命令信号，根据所述第一时钟信号对所述初始命令信号进行延时处理，得到目标命令信号；其中，所述目标命令信号与所述初始命令信号之间的时间间隔满足预设时序条件。
  2. 根据权利要求1所述的延时控制电路，其中，所述时钟模块包括温度检测模块和振荡器模块，其中：
    所述温度检测模块，配置为监测所述时钟模块的温度变化，根据所述温度变化生成所述温度调节信号；
    所述振荡器模块，配置为接收所述温度调节信号，根据所述温度调节信号对内部的模块结构进行调整，生成所述第一时钟信号。
  3. 根据权利要求2所述的延时控制电路，其中，所述振荡器模块包括若干个反相器，其中：
    所述振荡器模块，配置为根据所述温度调节信号控制内部产生时钟信号所需的反相器数量，以实现对内部的模块结构进行调整，使得所述第一时钟信号的时钟周期为预设值。
  4. 根据权利要求3所述的延时控制电路，其中：
    所述振荡器模块，配置为若所述温度调节信号指示温度变化呈上升趋势，则减小内部产生时钟信号所需的反相器数量，或者；
    所述振荡器模块，配置为若所述温度调节信号指示温度变化呈下降趋势，则增加内部产生时钟信号所需的反相器数量。
  5. 根据权利要求2所述的延时控制电路，其中，所述时钟模块还包括熔丝模块，其中：
    所述熔丝模块，配置为向所述振荡器模块提供熔丝信号；其中，所述熔丝信号指示的目标模式值是在测试模式下确定的；
    所述振荡器模块，还配置为根据所述熔丝信号和所述温度调节信号生成所述第一时钟信号。
  6. 根据权利要求5所述的延时控制电路，其中，所述时钟模块还包括选择模块，其中：
    所述熔丝模块，还配置为在测试模式下，设置第二测试模式信号的取值为第一候选模式值，并将所述第二测试模式信号发送给所述振荡器模块；
    所述振荡器模块，还配置为根据所述第二测试模式信号，生成测试时钟信号；
    所述选择模块，配置为接收第一测试模式信号，并根据所述第一测试模式信号选择所述测试时钟信号进行输出。
  7. 根据权利要求6所述的延时控制电路，其中，所述熔丝模块，还配置为若所述测试时钟信号的时钟周期等于所述预设值，则将所述第一候选模式值作为所述目标模式值并烧入预设熔丝中，以使得所述熔丝信号指示的目标模式值与所述第二测试模式信号的取值相同。
  8. 根据权利要求7所述的延时控制电路，其中，所述熔丝模块，还配置为若所述测试时钟信号的时钟周期不等于所述预设值，则设置第二测试模式信号的取值为第二候选模式值，继续执行将所述第二测试模式信号发送给所述振荡器模块的步骤，直至所述测 试时钟信号的时钟周期等于所述预设值，将所述第二测试模式信号当前的候选模式值作为目标模式值并烧入预设熔丝中，以使得所述熔丝信号指示的目标模式值与所述第二测试模式信号的取值相同。
  9. 根据权利要求6所述的延时控制电路，其中，所述选择模块的第一输入端与所述振荡器模块的输出端连接，用于接收所述测试时钟信号，所述选择模块的第二输入端与数据信号连接，所述选择模块的控制端与所述第一测试模式信号连接，其中：
    所述选择模块，配置为接收所述第一测试模式信号，根据所述第一测试模式信号的取值在所述测试时钟信号和所述数据信号中选择其中一个信号进行输出；
    其中，若所述第一测试模式信号的取值为第一值，则选择所述测试时钟信号进行输出；若所述第一测试模式信号的取值为第二值，则选择所述数据信号进行输出。
  10. 根据权利要求1所述的延时控制电路，其中，所述延时模块包括M个移位寄存器，M为大于0的整数，其中：
    第一个所述移位寄存器的输入端与所述初始命令信号连接，第y个所述移位寄存器的输入端与第y-1个所述移位寄存器的输出端连接，第M个移位寄存器的输出端用于输出所述目标命令信号；
    每一个所述移位寄存器的时钟端均与所述时钟模块连接，其中，y为大于1且小于或者等于M的整数。
  11. 根据权利要求10所述的延时控制电路，其中，所述移位寄存器，用于将输入端接收到的信号延迟第一时钟周期进行输出；其中，所述第一时钟周期与M的乘积等于所述时间间隔。
  12. 根据权利要求10所述的延时控制电路，其中，所述移位寄存器包括L个触发器，且所述L个触发器串接在一起，L为大于0的整数，其中：
    所述L个触发器的时钟端均与所述时钟模块连接，用于接收所述第一时钟信号，所述触发器的输出端与下一个所述触发器的输入端连接。
  13. 根据权利要求1至12任一项所述的延时控制电路，其中：
    所述初始命令信号包括激活信号，所述目标命令信号包括读信号，或者；
    所述初始命令信号包括读信号，所述目标命令信号包括写信号，或者；
    所述初始命令信号包括写信号，所述目标命令信号包括预充电信号。
  14. 根据权利要求1至12任一项所述的延时控制电路，其中，所述延时控制电路还包括缓冲模块，其中：
    所述缓冲模块，配置为接收错误检查与清除ECS命令信号，并根据所述ECS命令信号生成所述初始命令信号。
  15. 一种延时控制方法，应用于延时控制电路，所述方法包括：
    通过时钟模块接收温度调节信号，根据所述温度调节信号生成第一时钟信号，且所述第一时钟信号的时钟周期为预设值；
    通过延时模块接收所述第一时钟信号和初始命令信号，根据所述第一时钟信号对所述初始命令信号进行延时处理，得到目标命令信号；其中，所述目标命令信号与所述初始命令信号之间的时间间隔满足预设时序条件。
  16. 一种半导体存储器，所述半导体存储器包括如权利要求1至14任一项所述的延时控制电路。
  17. 根据权利要求16所述的半导体存储器，其中，所述半导体存储器包括动态随机存取存储器DRAM。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040184303A1 (en) * 2003-01-04 2004-09-23 Nec Plasma Display Corporation Memory circuit and method for operating the same
US20110128794A1 (en) * 2009-11-30 2011-06-02 Hyun-Su Yoon Apparatus and method for controlling operation timing in semiconductor memory device
CN105867510A (zh) * 2016-06-15 2016-08-17 中国电子科技集团公司第五十八研究所 一种减小数字时钟延时单元温漂的架构
JP2017168969A (ja) * 2016-03-15 2017-09-21 株式会社豊田中央研究所 カウンタ回路、時間計測回路及び温度センサ回路
CN109120258A (zh) * 2018-08-03 2019-01-01 北京大学深圳研究生院 一种温度自补偿环形振荡器和一种时钟产生电路
CN114242138A (zh) * 2021-12-01 2022-03-25 海光信息技术股份有限公司 一种延时控制器、内存控制器以及时序控制方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040184303A1 (en) * 2003-01-04 2004-09-23 Nec Plasma Display Corporation Memory circuit and method for operating the same
US20110128794A1 (en) * 2009-11-30 2011-06-02 Hyun-Su Yoon Apparatus and method for controlling operation timing in semiconductor memory device
JP2017168969A (ja) * 2016-03-15 2017-09-21 株式会社豊田中央研究所 カウンタ回路、時間計測回路及び温度センサ回路
CN105867510A (zh) * 2016-06-15 2016-08-17 中国电子科技集团公司第五十八研究所 一种减小数字时钟延时单元温漂的架构
CN109120258A (zh) * 2018-08-03 2019-01-01 北京大学深圳研究生院 一种温度自补偿环形振荡器和一种时钟产生电路
CN114242138A (zh) * 2021-12-01 2022-03-25 海光信息技术股份有限公司 一种延时控制器、内存控制器以及时序控制方法

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