WO2023279482A1 - 一种输入采样方法、输入采样电路及半导体存储器 - Google Patents

一种输入采样方法、输入采样电路及半导体存储器 Download PDF

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Publication number
WO2023279482A1
WO2023279482A1 PCT/CN2021/112921 CN2021112921W WO2023279482A1 WO 2023279482 A1 WO2023279482 A1 WO 2023279482A1 CN 2021112921 W CN2021112921 W CN 2021112921W WO 2023279482 A1 WO2023279482 A1 WO 2023279482A1
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signal
pulse signal
sampled
input
sampling
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PCT/CN2021/112921
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English (en)
French (fr)
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黄泽群
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长鑫存储技术有限公司
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Priority to US17/651,421 priority Critical patent/US11978502B2/en
Publication of WO2023279482A1 publication Critical patent/WO2023279482A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 

Definitions

  • Embodiments of the present application relate to, but are not limited to, an input sampling method, an input sampling circuit, and a semiconductor memory.
  • Dynamic Random Access Memory is a semiconductor storage device commonly used in computers, consisting of many repeated storage units. At present, as DRAM is applied in more and more fields, users have higher and higher requirements for DRAM power consumption indicators.
  • an input sampling method which includes:
  • an input sampling circuit includes:
  • the first signal input terminal is used to receive the first pulse signal
  • the second signal input terminal is used to receive the second pulse signal
  • a logic operator is used to perform logic operations on the first pulse signal and the second pulse signal to obtain a signal to be sampled; wherein, the signal to be sampled is obtained by shielding invalid signals in the second pulse signal according to the result of the logic operation;
  • the first sampling sub-circuit is used to sample the signal to be sampled to obtain the target sampled signal
  • the two input terminals of the logic operator are respectively connected with the first signal input terminal and the second signal input terminal, and the output terminal of the logic operator is connected with the first sampling sub-circuit.
  • an embodiment of the present application provides a semiconductor memory, including the input sampling circuit in the second aspect.
  • FIG. 1 is a schematic structural diagram of an input sampling circuit provided by the related art
  • FIG. 2 is a schematic diagram of signal changes of an input sampling circuit provided by the related art
  • FIG. 3 is a schematic flow diagram of an input sampling method provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an input sampling circuit provided in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another input sampling circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of signal changes of an input sampling circuit provided by an embodiment of the present application.
  • first ⁇ second ⁇ third involved in the embodiment of the present application is only used to distinguish similar objects, and does not represent a specific ordering of objects. Understandably, “first ⁇ second ⁇ third The specific order or sequence of "three” can be interchanged where permitted so that the embodiments of the application described herein can be practiced in other orders than those illustrated or described herein.
  • Sampling Measure the amplitude of the input signal at regular intervals, and convert the time-continuous analog signal into a time-discrete, amplitude-continuous sampling signal.
  • DDR Double Data Rate Synchronous Dynamic Random Access Memory (Double Data Rate SDRAM, DDR SDRAM).
  • Command/Address input sampling system also known as C/A input sampling system, input sampling circuit, which uses standard clock signal to sample C/A signal to facilitate command decoding.
  • DIMM Dual Inline Memory Modules
  • DIMM Dual Inline Memory Modules
  • Decoder Device code for decoding processing.
  • Latch A device that samples at a certain time and holds the sampling result at the output.
  • the first pulse signal or called CS_n signal, indicating the chip select (Chip Select, CS) signal, the chip select signal is used to select whether the current device is the target device.
  • the second pulse signal or called C/A signal, is used to indicate the Command/Address signal.
  • the Command/Address signal is an input signal that contains information such as commands and addresses, and is used to control specific devices in the circuit.
  • Standard clock signal a standard signal involved in the signal processing process, such as CKT signal, CKB signal;
  • C/A Input signal which is used to indicate the calculated signal of the first pulse signal and the second pulse signal
  • Target sampling signal or C/A Output signal, which is used to indicate the signal obtained after sampling the signal to be sampled.
  • the first pulse signal after sampling or called Cs_n Output signal, used to indicate the signal obtained after the first pulse signal is sampled.
  • Target signal or CMD signal, used to indicate the signal obtained after decoding the target sampling signal when the first pulse signal is valid.
  • the C/A signal and the standard clock signal respectively enter the input sampling circuit through the receiver, and then the C/A signal is sampled by the standard clock signal, and then the synchronized sampled C/A signal is output. Signal, used for subsequent instruction decoding.
  • the C/A data bus is shared by multiple DRAMs, and the DRAM targeted by the C/A signal needs to be distinguished by the chip select signal.
  • the chip selection signal also enters through the receiver and is sampled by the standard clock signal. According to the chip selection signal, it can be determined whether the C/A signal is a valid command of the DRAM. That is, it is necessary to determine whether the C/A signal is valid according to the chip select signal.
  • FIG. 1 it shows a schematic structural diagram of an input sampling circuit 10 provided in the related art.
  • the C/A signal and the standard clock signal (CKT signal/CKB signal) are sampled through the first latch 101 to obtain the C/A Output signal, and the CS_n signal and the standard clock signal pass through the second latch 102 is sampled to obtain the Cs_n Output signal; then, the decoder 103 decodes the Cs_n Output signal according to the CS_n Output signal, and finally obtains the CMD signal, and subsequently controls the DRAM by the CMD signal.
  • FIG. 2 it shows a schematic diagram of signal changes of an input sampling circuit provided by the related art.
  • the C/A Output signal will still follow the C/A signal to change.
  • the C/A signal is usually multi-bit, and the C/A Output signal needs to follow the constant change of the C/A signal, resulting in a large amount of useless energy consumption in the input sampling circuit.
  • each specific DRAM will repeat the sampling of the C/A signal, and then many input sampling circuits will have unnecessary energy consumption.
  • an embodiment of the present application provides an input sampling method.
  • the basic idea of the method is: for the input sampling method, it includes: receiving the first pulse signal and the second pulse signal; receiving the first pulse signal and the second pulse signal Carrying out logic operation to determine the signal to be sampled; wherein, the signal to be sampled is obtained by masking the invalid signal in the second pulse signal according to the result of the logic operation; performing sampling processing on the signal to be sampled to obtain the target sampled signal.
  • the input sampling circuit includes a first signal input terminal for receiving the first pulse signal; a second signal input terminal for receiving the second pulse signal; a logic operator for performing the first pulse signal and Perform logical operation on the second pulse signal to obtain the signal to be sampled; wherein, the signal to be sampled is obtained by shielding the invalid signal in the second pulse signal according to the result of the logical operation; the first sampling sub-circuit is used to sample the signal to be sampled , to obtain the target sampling signal; wherein, the two input terminals of the logic operator are respectively connected to the first signal input terminal and the second signal input terminal, and the output terminal of the logic operator is connected to the first sampling sub-circuit.
  • the invalid signal in the second pulse signal can be shielded, and the signal to be sampled will not be flipped along with the invalid input signal, thereby reducing the data sampling rate. loss of functionality of the circuit.
  • FIG. 3 shows a schematic structural diagram of an input sampling method provided in an embodiment of the present application.
  • the method may include:
  • S201 Receive a first pulse signal and a second pulse signal.
  • S202 Perform a logic operation on the first pulse signal and the second pulse signal to determine a signal to be sampled.
  • command/Address input sampling system ie, an input sampling circuit
  • an integrated circuit such as a circuit system in which a fixed clock CKT samples a C/A input in a DRAM chip.
  • the following uses the C/A input sampling circuit of the DRAM as an example to explain the embodiments of the present application, but this does not constitute a limitation to the embodiments of the present application.
  • the methods and circuits provided in the embodiments of the present application can also be applied to any system involving command acquisition or low power consumption.
  • the logic operation is performed on the first pulse signal and the second pulse signal, so as to shield the invalid signal in the second pulse signal, and finally obtain the sample signal. That is to say, the signal to be sampled is obtained by masking the invalid signal in the second pulse signal according to the logic operation result.
  • the first pulse signal can generally indicate whether the second pulse signal is valid, so a corresponding logical operation process can be designed to shield invalid signals in the second pulse signal.
  • the method may also include:
  • the second pulse signal is invalid, the level state of the signal to be sampled can be masked to a preset value; if the second pulse signal is valid, the level state of the signal to be sampled needs to be equal to the level of the second pulse signal The state is the same, so as to ensure that the effective signal in the second pulse signal can normally play a control role.
  • the invalid signal of the second pulse signal is masked as a preset value, so that the signal to be sampled will not be flipped according to the invalid signal in the second pulse signal, thereby avoiding unnecessary energy loss.
  • performing logical operations on the first pulse signal and the second pulse signal to determine the signal to be sampled may include:
  • the specific process of logical operation is: after receiving the first pulse signal and the second pulse signal, logically negating the second pulse signal to obtain the processed second pulse signal ; Then, NOR operation is performed on the first pulse signal and the processed second pulse signal to obtain the signal to be sampled. It should be understood that the above is only a possible manner of logic operation, and does not constitute a limitation to the embodiment of the present application.
  • the following takes the input sampling circuit of the DRAM as an example to describe the logic operation process in detail.
  • the first pulse signal may be a chip select signal (Cs_n signal), and the second pulse signal may be a control signal or an address signal (C/A signal).
  • Cs_n signal the chip select signal
  • C/A signal the corresponding C/A signal of the chip selection signal is a valid signal; when the chip selection signal is 1, the corresponding C/A signal of the chip selection signal is an invalid signal.
  • the chip select signal can be NORed to obtain the processed second pulse signal; the C/A signal and the processed second pulse signal can be NORed, Get the signal to be sampled.
  • the chip select signal is 1, the signal to be sampled is always 0, that is, the signal to be sampled will not be flipped along with the C/A signal; when the chip select signal is 0, the level state of the signal to be sampled Will follow the first pulse signal to change.
  • the logic operation result when the chip selection signal is at a high level, the logic operation result can indicate that the second pulse signal is invalid; when the chip selection signal is at a low level, the logic operation result can indicate that the first The second pulse signal is valid.
  • the signal to be sampled is only inverted along with the valid C/A signal, and the invalid C/A signal is shielded, thereby avoiding meaningless energy consumption.
  • S303 Perform sampling processing on the signal to be sampled to obtain a target sampled signal.
  • sampling processing is performed on the signal to be sampled to obtain a target sampling signal, so as to implement a subsequent control process.
  • the sampling processing of the signal to be sampled to obtain the target sampling signal may include:
  • a standard clock signal is used to sample the signal to be sampled to obtain a target sampled signal.
  • the method may also include:
  • the target sampling signal is decoded to obtain the target signal.
  • the target sampling signal After the target sampling signal is obtained, it is necessary to decode the target sampling signal to obtain the target signal, which is specifically used for controlling the DRAM.
  • performing decoding processing on the target sampling signal to obtain the target signal may include:
  • the first pulse signal after sampling is obtained by sampling the first pulse signal with a standard clock signal
  • the target sampling signal is decoded according to the sampled first pulse signal to obtain the target signal.
  • the target sampled signal is decoded. In order to ensure the correctness of decoding, the target signal is finally obtained.
  • the input sampling circuit can achieve the effect of reducing power consumption by shielding the sampling input when invalid C/A signals are continuously input.
  • An embodiment of the present application provides an input sampling method, the method includes: receiving a first pulse signal and a second pulse signal; performing a logical operation on the first pulse signal and the second pulse signal to determine a signal to be sampled; wherein, the signal to be sampled The signal is obtained by shielding the invalid signal in the second pulse signal according to the logic operation result; the signal to be sampled is sampled and processed to obtain the target sampled signal.
  • the invalid signal in the second pulse signal can be shielded, and the signal to be sampled will not be in a level state along with the invalid signal in the first pulse signal. Inversion, thereby reducing the functional loss of the input sampling circuit.
  • FIG. 4 shows a schematic structural diagram of an input sampling circuit 30 provided in an embodiment of the present application.
  • the input sampling circuit 30 may include:
  • a first signal input terminal 301 configured to receive a first pulse signal
  • the second signal input terminal 302 is used to receive the second pulse signal
  • a logical operator 303 configured to perform logical operations on the first pulse signal and the second pulse signal to obtain a signal to be sampled; wherein the signal to be sampled is obtained by shielding an invalid signal in the second pulse signal according to the result of the logical operation;
  • the first sampling sub-circuit 304 is configured to sample the signal to be sampled to obtain a target sampled signal.
  • the input sampling circuit belongs to an integrated circuit, such as a Command/Address input sampling circuit of a DRAM.
  • the embodiment of the present application provides an input sampling circuit 30.
  • the input sampling circuit 30 includes a first signal input terminal 301, a second signal input terminal 302, a logic operator 303 and a first sampling sub-circuit 304.
  • the specific connection of the above devices The relationship is: the two input terminals of the logic operator 303 are respectively connected to the first signal input terminal 301 and the second signal input terminal 302 , and the output terminal of the logic operator 303 is connected to the first sampling sub-circuit 304 .
  • the signal input terminal 301 is used to receive the first pulse signal and the second pulse signal; then, the logic operator 303 performs logic operations on the first pulse signal and the second pulse signal to obtain the signal to be sampled; finally, the A sampling sub-circuit 304 samples the input signal after operation to obtain a target sampling signal.
  • the input sampling circuit can avoid meaningless level state inversion and reduce the power consumption of the DRAM.
  • the logic operator 303 may include a NOT gate and a NOR gate; wherein,
  • the NOT gate is used to perform a logical NOT operation on the second pulse signal to obtain the processed second pulse signal
  • the NOR gate is used to perform a logical NOR operation on the first pulse signal and the processed second pulse signal to obtain a signal to be sampled.
  • the logic operator 303 includes a NOT gate and a NOR gate, the input terminal of the NOT gate is connected with the second signal input terminal, the first signal input terminal of the NOR gate is connected with the first signal input terminal, and the NOR gate The second signal input end of the second signal is connected with the output end of the NOT gate.
  • the processed second pulse signal can be obtained by performing a NOT operation on the second pulse signal through the NOT gate; then, the NOR operation is performed on the first pulse signal and the processed second pulse signal through the NOR gate, thereby obtaining the Signal.
  • the first pulse signal refers to the chip select signal
  • the second pulse signal refers to the C/A signal. If the chip select signal is 0, the C/A signal is valid. At this time, the level state of the signal to be sampled is the same as that of the C/A signal, which ensures that the effective C/A signal can normally control the DRAM. If the chip select signal is 1, the C/A signal is invalid. At this time, the level state of the signal to be sampled is constant at 0, that is, the signal to be sampled will not be flipped along with the invalid C/A signal, thereby reducing functional loss.
  • the first sampling subcircuit may include a third signal input terminal and a first sampler, the third signal input terminal is connected to the clock port of the first sampler, and the input terminal of the first sampler is connected to the clock port of the first sampler.
  • the output terminal of the logic operator is connected;
  • the third signal input terminal is used for receiving a standard clock signal
  • the first sampler is configured to use a standard clock signal to sample the signal to be sampled to obtain a target sampled signal.
  • the first sampling sub-circuit 304 may include a third signal input and a first sampler.
  • the third signal input terminal is used to receive the standard clock signal; then, the first sampler uses the standard clock signal to sample the input signal after operation to obtain the target sampling signal.
  • the first sampler may be a latch.
  • the input sampling circuit 30 may also include a second sampling subcircuit, the second sampling subcircuit may include a fourth signal input terminal and a second sampler, the fourth signal input terminal is connected to the clock port of the second sampler, and the second sampling subcircuit The input end of the two sampler is connected with the first signal input end;
  • the fourth signal input terminal is used to receive a standard clock signal
  • the second sampler is configured to use a standard clock signal to sample the first pulse signal to obtain the sampled first pulse signal.
  • the input sampling circuit in addition to sampling the second pulse signal, it is also necessary to sample the first pulse signal, so that the first pulse signal can be detected according to the second pulse signal in the subsequent decoding process. correct decoding of the signal.
  • the input sampling circuit 30 also includes a second sampling subcircuit, the second sampling subcircuit includes a fourth signal input terminal and a second sampler, the fourth signal input terminal is used to receive the standard clock signal, and the second sampler is used to use the The standard clock signal implements sampling of the first pulse signal to obtain the sampled first pulse signal.
  • the second sampler may be a latch.
  • the first pulse signal and the second pulse signal need to be sampled based on a standard clock signal with the same frequency. Therefore, one clock signal input terminal can be used as the third signal input terminal and the fourth signal input terminal at the same time.
  • the input sampling circuit 30 further includes a decoder, and the two input terminals of the decoder are respectively connected to the output terminal of the first sampling subcircuit and the output terminal of the second sampling subcircuit; wherein,
  • the decoder is used for decoding the target sampled signal according to the sampled first pulse signal to obtain the target signal.
  • the input sampling circuit 30 may also include a decoder, so as to decode the target sampling signal according to the sampled first pulse signal to obtain the target signal, so that the DRAM can complete corresponding operation instructions according to the target signal.
  • the input sampling circuit provided by the embodiment of the present application, only when the first pulse signal is valid, the signal to be sampled will follow the first pulse signal for state reversal, that is, the input sampling circuit will only The two pulse signals are sampled and consume energy, thereby avoiding meaningless energy consumption.
  • the structure of the logic operator above is only an example.
  • the logic operator 303 can use AND gates, OR gates, NOT gates, NAND gates, NOR gates, XOR gates, XOR gates, etc.
  • a variety of logical combinations are used to achieve the aforementioned effects, and these logical combination methods are all within the protection scope of the embodiments of the present application.
  • An embodiment of the present application provides an input sampling circuit
  • the input sampling circuit includes a first signal input terminal for receiving a first pulse signal; a second signal input terminal for receiving a second pulse signal; a logic operator for Performing logical operations on the first pulse signal and the second pulse signal to obtain the signal to be sampled; wherein the signal to be sampled is obtained by shielding the invalid signal in the second pulse signal according to the result of the logic operation; the first sampling subcircuit, It is used to sample the signal to be sampled to obtain the target sampled signal.
  • the invalid signal in the second pulse signal can be shielded, and the signal to be sampled will not be in a level state along with the invalid signal in the first pulse signal. Inversion, thereby reducing the functional loss of the input sampling circuit.
  • FIG. 5 it shows a schematic structural diagram of another input sampling circuit 30 provided by an embodiment of the present application.
  • the input sampling circuit 30 includes a first signal input terminal 401, a second signal input terminal 402, a logic operator 403, a clock signal input terminal 404, a first latch 405, and a second latch 406. and decoder 407.
  • the clock signal input terminal 404 and the first latch 405 form the aforementioned first sampling subcircuit
  • the clock signal input terminal 404 and the second latch 406 form the aforementioned second sampling subcircuit.
  • the essence of the first signal input end 401 , the second signal input end 102 and the clock signal input end 404 are receivers.
  • the first signal input terminal 401 is used to receive an external CS_n signal and a reference (VREFCA) signal to obtain a received CS_n signal.
  • the second signal input terminal 402 is used to receive an external C/A signal and a reference (VREFCA) signal to obtain a received C/A signal.
  • the clock signal input terminal 404 is used to receive a standard clock signal (CKT signal/CKB signal).
  • the "CS_n signal” is compared with the reference voltage to form the "received CS_n signal", that is, the waveform and function of the CS_n signal and the received CS_n signal are substantially the same, and both refer to the chip select signal. Therefore, similarly, the waveform and function of the C/A signal and the received C/A signal are substantially the same.
  • the logic operator 403 is connected to the first signal input terminal 401 and the second signal input terminal 402, and is used to perform logic operations on the CS_n signal and the received C/A signal to obtain the C/A Input signal.
  • the first latch 405 is connected to the first signal input terminal 401 and the clock signal input terminal 404, and uses a standard clock signal to sample the CS_n Input signal (i.e., the received CS_n signal) to obtain the CS_n Output signal.
  • the received CS_n signal is directly sampled as the CS_n Input signal;
  • the second latch 406 is connected with the logic operator 403 and the clock signal input terminal 404, and uses the standard clock signal to sample the C/A Input signal to obtain the C/A Output signal. That is to say, the received C/A Input signal needs to be processed with the received CS_n signal before being sampled.
  • the decoder 407 is connected to the first latch 405 and the second latch 406, and decodes the C/A Output signal based on the CS_n Output signal to obtain the CMD signal (equivalent to the aforementioned target signal).
  • the logic operator 403 when CS_n is 0, the C/A signal is valid; when CS_n is 1, the C/A signal is invalid. Therefore, the logic operator 403 includes a NOT gate and a NOR gate, thereby performing a NOT operation on the received CS_n signal, and then performing a NOR operation on the result of the operation together with the received C/A signal, and finally obtaining the C/A Input
  • the signal and logic operation formula can be shown in formula (1).
  • FIG. 6 shows a schematic diagram of signal changes of an input sampling circuit provided by an embodiment of the present application.
  • the C/A Input signal when the CS_n signal is 0 (the DRAM is the target chip), the C/A Input signal will follow the change of the C/A signal, and the decoded CMD signal can reflect the instruction content of the C/A signal ;
  • CS_n is 1 (the DRAM is not the target chip), as shown by the dotted circle, the C/A Input is always 0, and will not flip with the C/A signal, avoiding meaningless function consumption.
  • the C/A input signal of the non-target DRAM is shielded by the CS_n chip select signal, so that the value of the C/A Input signal of the non-target DRAM remains unchanged to reduce the power consumption of the C/A sampling system; for the target DRAM
  • the C/A signal needs to be combined with the CS_n chip select signal to make a selection. Therefore, in the C/A input sampling system, if the DRAM does not receive a valid CS_n chip select signal, it will shield the C/A signal and make the C/A signal constant at 0. In this way, when a valid CS_n chip select signal is not received, even if there is an external C/A signal, the internal C/A sampling system does not have data inversion, thereby saving the power consumption of the C/A sampling system.
  • the input sampling circuit can reduce power consumption by shielding the sampling input.
  • the DRAM C/A input sampling system is only a specific application scenario shown in the embodiment of the present application, but the embodiment of the present application is not limited to this scope, and both instruction acquisition and low power consumption systems can adopt this circuit design.
  • the embodiment of the present application provides an input sampling circuit, by inserting a control logic gate related to CS_n Input between the input of the C/A receiver and the C/A sampling circuit, where CS_n Input is 0 When CS_n Input is 1, the C/A Input is masked to a constant value of 0, and the CKT signal will not be sampled afterwards.
  • the embodiment of the present application provides an input sampling circuit. Through this embodiment, the specific implementation methods of the foregoing embodiments are described in detail. It can be seen that, by performing logical operations on the first pulse signal and the second pulse signal, the The invalid signal in the second pulse signal is shielded, so that the level state of the signal to be sampled will not be reversed along with the invalid signal in the first pulse signal, thereby reducing the functional loss of the input sampling circuit.
  • a semiconductor memory which at least includes the aforementioned input sampling circuit 30 .
  • the invalid signal in the second pulse signal can be shielded, and then the signal to be sampled will not follow the first pulse signal.
  • An invalid signal in a pulse signal is flipped in level state, thereby reducing the functional loss of the input sampling circuit.
  • the semiconductor memory may be DRAM.
  • the input sampling method includes: receiving the first pulse signal and the second pulse signal; performing logic operations on the first pulse signal and the second pulse signal to determine the signal to be sampled; wherein the signal to be sampled is based on the logic
  • the calculation result is obtained by masking the invalid signal in the second pulse signal; performing sampling processing on the signal to be sampled to obtain the target sampling signal.

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Abstract

一种输入采样方法、输入采样电路及半导体存储器，该输入采样方法包括：接收第一脉冲信号和第二脉冲信号；对第一脉冲信号和第二脉冲信号进行逻辑运算，确定待采样信号；其中，待采样信号是根据逻辑运算结果将第二脉冲信号中的无效信号进行屏蔽得到的；对待采样信号进行采样处理，得到目标采样信号。这样，通过对第一脉冲信号和第二脉冲信号进行逻辑运算，能够将第二脉冲信号中的无效信号进行屏蔽，进而待采样信号不会随着第一脉冲信号中的无效信号进行电平状态翻转，从而降低输入采样电路的功能损耗。

Description

一种输入采样方法、输入采样电路及半导体存储器
相关申请的交叉引用
本申请要求在2021年07月07日提交中国专利局、申请号为202110766193.1、申请名称为“一种输入采样方法、输入采样电路及半导体存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及但不限于一种输入采样方法、输入采样电路及半导体存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。目前，随着DRAM应用的领域越来越多，用户对于DRAM功耗指标的要求越来越高。
然而，在目前的DRAM中，无效输入信号会引起电平状态翻转，进而导致过多的功率损耗。
发明内容
第一方面，本申请实施例提供了一种输入采样方法，该方法包括：
接收第一脉冲信号和第二脉冲信号；
对第一脉冲信号和第二脉冲信号进行逻辑运算，确定待采样信号；其中，待采样信号是根据逻辑运算结果将第二脉冲信号中的无效信号进行屏蔽得到的；
对待采样信号进行采样处理，得到目标采样信号。
第二方面，本申请实施例提供了一种输入采样电路，该输入采样电路包括：
第一信号输入端，用于接收第一脉冲信号；
第二信号输入端，用于接收第二脉冲信号；
逻辑运算器，用于对第一脉冲信号和第二脉冲信号进行逻辑运算，得到待采样信号；其中，待采样信号是根据逻辑运算结果将第二脉冲信号中的无效信号进行屏蔽得到的；
第一采样子电路，用于对待采样信号进行采样，得到目标采样信号；
其中，逻辑运算器的两个输入端分别与第一信号输入端和第二信号输入端连接，逻辑运算器的输出端与第一采样子电路连接。
第三方面，本申请实施例提供了一种半导体存储器，包括如第二方面的输入采样电路。
附图说明
图1为相关技术提供的一种输入采样电路的结构示意图；
图2为相关技术提供的一种输入采样电路的信号变化示意图；
图3为本申请实施例提供的一种输入采样方法的流程示意图；
图4为本申请实施例提供的一种输入采样电路的结构示意图；
图5为本申请实施例提供的另一种输入采样电路的结构示意图；
图6为本申请实施例提供的一种输入采样电路的信号变化示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本申请实施例的目的，不是旨在限制本申请。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集， 并且可以在不冲突的情况下相互结合。
需要指出，本申请实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本申请实施例能够以除了在这里图示或描述的以外的顺序实施。
以下为本申请实施例中涉及到的专业名词解释以及部分名词的对应关系：
采样：每隔一定的时间测量一次输入信号的幅值，把时间连续的模拟信号转换成时间离散、幅值连续的采样信号。
DDR：双倍速率同步动态随机存储器(Double Data Rate SDRAM，DDR SDRAM)。
Command/Address输入采样系统：也称为C/A输入采样系统、输入采样电路，利用标准时钟信号对C/A信号进行采样，以便于进行指令译码。
DIMM(Dual Inline Memory Modules)：双列直插式存储模块。
译码器(DEC)：用于进行译码处理的器件编码。
锁存器(Latch)：在某时刻采样，输出端保持采样结果的器件。
第一脉冲信号：或称为CS_n信号，指示片选(Chip Select，CS)信号，片选信号用于选择当前器件是否为目标器件。
第二脉冲信号：或称为C/A信号，用于指示Command/Address信号，Command/Address信号是一种输入信号，包含命令、地址等信息，用于对电路中具体的器件进行控制。
标准时钟信号：信号处理过程中涉及到的一种标准信号，例如CKT信号、CKB信号；
待采样信号：或称为C/A Input信号，用于指示第一脉冲信号和第二脉冲信号经过运算后的信号；
目标采样信号：或称为C/A Output信号，用于指示待采样信号经过采样后得到的信号。
采样后第一脉冲信号：或称为Cs_n Output信号，用于指示第一脉冲信号经 过采样后得到的信号。
目标信号：或称为CMD信号，用于指示在第一脉冲信号有效的情况下，对目标采样信号译码后所得到的信号。
目前，在DRAM的C/A输入采样系统中，C/A信号和标准时钟信号分别通过接收器进入输入采样电路，接着由标准时钟信号采样C/A信号，然后输出同步的采样后C/A信号，用于做之后的指令译码。但是，在DRAM DIMM设计中，C/A数据总线是多个DRAM共享的，C/A信号所针对的DRAM需要由片选信号区分开来。
也就是说，在DRAM DIMM中，存在多个DRAM，每个DRAM均存在对应的输入采样电路。对于具体一个DRAM的输入采样电路，除了C/A信号外，片选信号也通过接收器进入并被标准时钟信号采样，根据片选信号能够确定该C/A信号是否为该DRAM的有效指令，即需要根据片选信号确定C/A信号是否有效。
参见图1，其示出了相关技术提供的一种输入采样电路10的结构示意图。如图1所示，C/A信号和标准时钟信号(CKT信号/CKB信号)通过第一锁存器101被采样，得到C/A Output信号，CS_n信号和标准时钟信号通过第二锁存器102被采样，得到Cs_n Output信号；然后，译码器103根据CS_n Output信号对Cs_n Output信号进行译码，最终得到CMD信号，后续由CMD信号对DRAM进行控制。
也就是说，被接收到的所有C/A信号会同CS片选信号一起在指令译码模块进行处理。如果CS_n信号为0，则说明C/A信号是针对本DRAM的，则对C/A信号进行译码，进而指令译码成功，进入后续执行流程；如果CS_n信号为1，则表示本DRAM不是目标DRAM，没有任何指令会被译码，后续不会有任何动作。
然而，即使在CS_n信号为1，C/A信号对本DRAM无效的情况下，输入采样电路10仍然会对C/A信号进行采样动作。参见图2，其示出了相关技术提 供的一种输入采样电路的信号变化示意图。如图2中虚线圈所示，即使CS_n信号为1(该DRAM为非目标芯片)，C/A Output信号仍然会跟随C/A信号进行变化。此时，由于C/A信号通常为多比特，且C/A Output信号需要跟随C/A信号不停变化，从而导致了输入采样电路存在大量的无用能量消耗。
这样，对包含多个DRAM的DRAM DIMM来说，每个具体DRAM都会重复C/A信号的采样，进而很多个输入采样电路的都会有不必要的能量消耗。
基于此，本申请实施例提供了一种输入采样方法，该方法的基本思想为：对于输入采样方法，包括：接收第一脉冲信号和第二脉冲信号；对第一脉冲信号和第二脉冲信号进行逻辑运算，确定待采样信号；其中，待采样信号是根据逻辑运算结果将第二脉冲信号中的无效信号进行屏蔽得到的；对待采样信号进行采样处理，得到目标采样信号。对于输入采样电路，该输入采样电路包括第一信号输入端，用于接收第一脉冲信号；第二信号输入端，用于接收第二脉冲信号；逻辑运算器，用于对第一脉冲信号和第二脉冲信号进行逻辑运算，得到待采样信号；其中，待采样信号是根据逻辑运算结果将第二脉冲信号中的无效信号进行屏蔽得到的；第一采样子电路，用于对待采样信号进行采样，得到目标采样信号；其中，逻辑运算器的两个输入端分别与第一信号输入端和第二信号输入端连接，逻辑运算器的输出端与第一采样子电路连接。这样，通过对第一脉冲信号和第二脉冲信号进行逻辑运算，能够将第二脉冲信号中的无效信号进行屏蔽，待采样信号不会随着无效输入信号进行电平状态翻转，从而降低数据采样电路的功能损耗。
下面将结合附图对本申请各实施例进行详细说明。
在本申请的一实施例中，参见图3，其示出了本申请实施例提供的一种输入采样方法的结构示意图。如图3所示，该方法可以包括：
S201：接收第一脉冲信号和第二脉冲信号。
S202：对第一脉冲信号和第二脉冲信号进行逻辑运算，确定待采样信号。
需要说明的是，本申请实施例应用于集成电路中的Command/Address输入 采样系统(即输入采样电路)，例如DRAM芯片中，固定时钟CKT采样C/A输入的电路系统中。
为了方便说明，以下均以DRAM的C/A输入采样电路为例对本申请实施例进行解释，但是这并不构成对本申请实施例的限制。本申请实施例所提供的方法和电路还可以应用于任何涉及指令采集或低功耗的系统中。
对于输入采样方法来说，在接收第一脉冲信号和第二脉冲信号之后，对第一脉冲信号和第二脉冲信号进行逻辑运算，从而将第二脉冲信号中的无效信号进行屏蔽，最终得到待采样信号。也就是说，待采样信号是根据逻辑运算结果将第二脉冲信号中的无效信号进行屏蔽得到的。
在这里，第一脉冲信号一般能够指示第二脉冲信号是否有效，因此可以设计相应的逻辑运算过程以屏蔽第二脉冲信号中的无效信号。
进一步地，在一些实施例中，该方法还可以包括：
在逻辑运算结果指示第二脉冲信号无效的情况下，确定待采样信号的电平状态被屏蔽为预设值；
在逻辑运算结果指示第二脉冲信号有效的情况下，确定待采样信号与第二脉冲信号的电平状态相同。
需要说明的是，若第二脉冲信号无效，可以将待采样信号的电平状态屏蔽为预设值；若第二脉冲信号有效，待采样信号的电平状态需要与第二脉冲信号的电平状态相同，从而保证第二脉冲信号中的有效信号能够正常发挥控制作用。
这样，在采样过程中，第二脉冲信号的无效信号被屏蔽为预设值，从而待采样信号不会根据第二脉冲信号中的无效信号进行电平状态翻转，从而避免不必要的能量损耗。
进一步地，在一些实施例中，所述对第一脉冲信号和第二脉冲信号进行逻辑运算，确定待采样信号，可以包括：
对第二脉冲信号进行逻辑非运算，得到处理后第二脉冲信号；
将第一脉冲信号和处理后第二脉冲信号进行逻辑或非运算，得到待采样信号。
需要说明的是，在本申请实施例中，逻辑运算的具体过程为：在接收到第一脉冲信号和第二脉冲信号之后，对第二脉冲信号进行逻辑非处理，得到处理后第二脉冲信号；然后，将第一脉冲信号和处理后第二脉冲信号进行或非运算，得到待采样信号。应理解，以上仅为逻辑运算的一种可行方式，并不构成对本申请实施例的限制。
以下以DRAM的输入采样电路为例，对逻辑运算过程进行具体说明。
在DRAM中，第一脉冲信号可以是片选信号(Cs_n信号)，第二脉冲信号可以是控制信号或地址信号(C/A信号)。根据DRAM的行业标准，一般片选信号为0时，该片选信号相应的C/A信号为有效信号；片选信号为1时，该片选信号相应的C/A信号为无效信号。
此时，在接收到片选信号和C/A信号以后，可以对片选信号进行非运算，得到处理后第二脉冲信号；对C/A信号和处理后第二脉冲信号进行或非运算，得到待采样信号。这样，在片选信号为1的时候，待采样信号始终为0，即待采样信号并不会随着C/A信号进行翻转；在片选信号为0的时候，待采样信号的电平状态会跟随第一脉冲信号进行变化。
这样，对逻辑运算过程来说，在片选信号为高电平的情况下，逻辑运算结果能够指示第二脉冲信号无效；在片选信号为低电平的情况下，逻辑运算结果能够指示第二脉冲信号有效。
这样，待采样信号仅会随着有效的C/A信号进行翻转，而无效的C/A信号被屏蔽掉，从而避免无意义的能量消耗。
S303：对待采样信号进行采样处理，得到目标采样信号。
需要说明的是，针对待采样信号进行采样处理，得到目标采样信号，以便于实现后续控制过程。
进一步地，在一些实施例中，所述对待采样信号进行采样处理，得到目标采样信号，可以包括：
接收标准时钟信号；
利用标准时钟信号对待采样信号进行采样，得到目标采样信号。
需要说明的是，在采样处理中，需要接收标准时钟信号，利用标准时钟信号对待采样信号进行采样，最终得到目标采样信号。
进一步地，在一些实施例中，该方法还可以包括：
对目标采样信号进行译码处理，得到目标信号。
需要说明的是，在得到目标采样信号后，还需要对目标采样信号进行译码处理，得到目标信号，该目标信号具体用于对DRAM的控制。
具体地，在一些实施例中，所述对目标采样信号进行译码处理，得到目标信号，可以包括：
确定采样后第一脉冲信号；其中，采样后第一脉冲信号是利用标准时钟信号对第一脉冲信号进行采样得到的；
根据采样后第一脉冲信号对目标采样信号进行译码处理，得到目标信号。
需要说明的是，在译码处理中，需要利用标准时钟信号对第一脉冲信号进行采样，得到采样后第一脉冲信号；然后，基于采样后第一脉冲信号对目标采样信号进行译码处理，以保证译码的正确性，最终得到目标信号。
综上，借助于本申请实施例提供的电路设计，能够达到在无效的C/A信号不停输入时，输入采样电路通过屏蔽采样输入达到降低功耗的效果。
本申请实施例提供了一种输入采样方法，该方法包括：接收第一脉冲信号和第二脉冲信号；对第一脉冲信号和第二脉冲信号进行逻辑运算，确定待采样信号；其中，待采样信号是根据逻辑运算结果将第二脉冲信号中的无效信号进行屏蔽得到的；对待采样信号进行采样处理，得到目标采样信号。这样，通过对第一脉冲信号和第二脉冲信号进行逻辑运算，能够将第二脉冲信号中的无效信号进行屏蔽，进而待采样信号不会随着第一脉冲信号中的无效信号进行电平状态翻转，从而降低输入采样电路的功能损耗。
在本申请的另一实施例中，参见图4，其示出了本申请实施例提供的一种输入采样电路30的结构示意图。如图4所示，输入采样电路30可以包括：
第一信号输入端301，用于接收第一脉冲信号；
第二信号输入端302，用于接收第二脉冲信号；
逻辑运算器303，用于对第一脉冲信号和第二脉冲信号进行逻辑运算，得到待采样信号；其中，待采样信号是根据逻辑运算结果将第二脉冲信号中的无效信号进行屏蔽得到的；
第一采样子电路304，用于对待采样信号进行采样，得到目标采样信号。
需要说明的是，该输入采样电路属于集成电路，例如DRAM的Command/Address输入采样电路。
本申请实施例提供了一种输入采样电路30，输入采样电路30包括第一信号输入端301、第二信号输入端302、逻辑运算器303和第一采样子电路304，以上器件的具体的连接关系为：逻辑运算器303的两个输入端分别与第一信号输入端301和第二信号输入端302连接，逻辑运算器303的输出端与第一采样子电路304连接。
在这里，信号输入端301用于接收第一脉冲信号和第二脉冲信号；然后，由逻辑运算器303对第一脉冲信号和第二脉冲信号进行逻辑运算，得到待采样信号；最后，由第一采样子电路304对运算后输入信号进行采样，得到目标采样信号。这样，由于待采样信号是根据逻辑运算结果将第二脉冲信号中的无效信号进行屏蔽得到的，所以输入采样电路能够避免无意义的电平状态翻转，降低了DRAM的功率损耗。
进一步地，在一些实施例中，逻辑运算器303可以包括非门以及或非门；其中，
非门，用于对第二脉冲信号进行逻辑非运算，得到处理后第二脉冲信号；
或非门，用于对第一脉冲信号和处理后第二脉冲信号进行逻辑或非运算，得到待采样信号。
需要说明的是，逻辑运算器303包括非门和或非门，非门的输入端与第二信号输入端连接，或非门的第一信号输入端与第一信号输入端连接，或非门的第二信号输入端与非门的输出端连接。这样，通过非门对第二脉冲信号进行非运算，能够得到处理后第二脉冲信号；然后，通过或非门对第一脉冲信号和处 理后第二脉冲信号进行或非运算，从而得到待采样信号。
以前述的DRAM为例，第一脉冲信号是指片选信号，第二脉冲信号是指C/A信号。若片选信号为0，则C/A信号有效，此时待采样信号的电平状态与C/A信号相同，保证了有效C/A信号能够正常对DRAM发挥控制作用。若片选信号为1，则C/A信号无效，此时待采样信号的电平状态恒定为0，即待采样信号不会随着无效C/A信号进行翻转，从而降低了功能损耗。
进一步地，在一些实施例中，第一采样子电路可以包括第三信号输入端和第一采样器，第三信号输入端与第一采样器的时钟端口连接，第一采样器的输入端与逻辑运算器的输出端连接；其中，
第三信号输入端，用于接收标准时钟信号；
第一采样器，用于利用标准时钟信号对待采样信号进行采样，得到目标采样信号。
需要说明的是，由于采样过程需要利用标准时钟信号为基准进行。因此，第一采样子电路304可以包括第三信号输入端和第一采样器。此时，第三信号输入端用于接收标准时钟信号；然后，第一采样器利用标准时钟信号对运算后输入信号进行采样，得到目标采样信号。在这里，第一采样器可以为锁存器。
进一步地，输入采样电路30还可以包括第二采样子电路，第二采样子电路可以包括第四信号输入端和第二采样器，第四信号输入端与第二采样器的时钟端口连接，第二采样器的输入端与第一信号输入端连接；其中，
第四信号输入端，用于接收标准时钟信号；
第二采样器，用于利用标准时钟信号对第一脉冲信号进行采样，得到采样后第一脉冲信号。
需要说明的是，对于输入采样电路而言，除了对第二脉冲信号的采样，还需要对第一脉冲信号进行采样，从而在后续译码过程中才能够根据第二脉冲信号实现对第一脉冲信号的正确译码。
因此，输入采样电路30还包括第二采样子电路，第二采样子电路包括第四信号输入端和第二采样器，第四信号输入端用于接收标准时钟信号，第二采样 器用于利用该标准时钟信号实现对第一脉冲信号的采样，以得到采样后第一脉冲信号。在这里，第二采样器可以为锁存器。
一般来说，第一脉冲信号和第二脉冲信号需要基于同样频率的标准时钟信号进行采样。因此，可以利用一个时钟信号输入端同时作为第三信号输入端和第四信号输入端。
经过上述处理，在第二脉冲信号有效的情况下，能够确定第二脉冲信号经采样后得到的目标采样信号，以及确定第一脉冲信号经采样后得到的采样后第一脉冲信号。因此，在一些实施例中，输入采样电路30还包括译码器，译码器的两个输入端分别与第一采样子电路的输出端和第二采样子电路的输出端连接；其中，
译码器，用于根据采样后第一脉冲信号对目标采样信号进行译码处理，得到目标信号。
需要说明的是，输入采样电路30还可以包括译码器，从而根据采样后第一脉冲信号对目标采样信号进行译码处理，得到目标信号，以便于DRAM根据目标信号完成相应的操作指令。
综上所述，在本申请实施例提供的输入采样电路中，只有在第一脉冲信号有效时，待采样信号才会跟随第一脉冲信号进行状态翻转，即输入采样电路仅会对有效的第二脉冲信号进行采样并消耗能量，从而避免无意义的能量消耗。应理解，以上逻辑运算器的结构仅为一种示例，实际上，逻辑运算器303可以利用与门、或门、非门、与非门、或非门、同或门、异或门等进行多种逻辑组合以实现前述的效果，这些逻辑组合方式均在本申请实施例的保护范围之内。
本申请实施例提供了一种输入采样电路，该输入采样电路包括第一信号输入端，用于接收第一脉冲信号；第二信号输入端，用于接收第二脉冲信号；逻辑运算器，用于对第一脉冲信号和第二脉冲信号进行逻辑运算，得到待采样信号；其中，待采样信号是根据逻辑运算结果将第二脉冲信号中的无效信号进行屏蔽得到的；第一采样子电路，用于对待采样信号进行采样，得到目标采样信号。这样，通过对第一脉冲信号和第二脉冲信号进行逻辑运算，能够将第二脉 冲信号中的无效信号进行屏蔽，进而待采样信号不会随着第一脉冲信号中的无效信号进行电平状态翻转，从而降低输入采样电路的功能损耗。
在本申请的又一实施例中，以DRAM中的C/A输入采样电路为例，对前述方法以及电路结构进行具体说明。参见图5，其示出了本申请实施例提供的另一种输入采样电路30的结构示意图。
如图5所示，该输入采样电路30包括第一信号输入端401、第二信号输入端402、逻辑运算器403、时钟信号输入端404、第一锁存器405、第二锁存器406和译码器407。其中，时钟信号输入端404和第一锁存器405构成前述的第一采样子电路，时钟信号输入端404和第二锁存器406构成前述的第二采样子电路。
第一信号输入端401、第二信号输入端102和时钟信号输入端404的本质均为接收器。在这里，第一信号输入端401用于接收外部的CS_n信号和参考(VREFCA)信号，得到接收后的CS_n信号。第二信号输入端402用于接收外部的C/A信号和参考(VREFCA)信号，得到接收后的C/A信号。时钟信号输入端404用于接收标准时钟信号(CKT信号/CKB信号)。应理解，“CS_n信号”经过与参考电压比较形成“接收后的CS_n信号”，即CS_n信号和接收后的CS_n信号的波形和功能是实质相同的，均是指片选信号。因此，类似的，C/A信号和接收后的C/A信号的波形和功能是实质相同的。
逻辑运算器403，与第一信号输入端401和第二信号输入端402相连，用于对CS_n信号和接收后的C/A信号进行逻辑运算，得到C/A Input信号。
第一锁存器405，与第一信号输入端401和时钟信号输入端404相连，利用标准时钟信号对CS_n Input信号(即接收后的CS_n信号)进行采样，得到CS_n Output信号。也就是说，接收后的CS_n信号直接作为CS_n Input信号被采样处理；
第二锁存器406，与逻辑运算器403和时钟信号输入端404相连，利用标准时钟信号采样C/A Input信号，得到C/A Output信号。也就是说，接收后的 C/A Input信号需要与接收后的CS_n信号进行运算后被采样处理。
译码器407，与第一锁存器405和第二锁存器406相连，基于CS_n Output信号对C/A Output信号进行译码，得到CMD信号(相当于前述的目标信号)。
在本申请实施例中，当CS_n为0时，C/A信号有效；CS_n为1时，C/A信号无效。因此，逻辑运算器403包括一个非门以及或非门，从而对接收后的CS_n信号进行非运算，然后将运算结果与接收后的C/A信号一起进行或非运算，最终得到C/A Input信号，逻辑运算公式可如式(1)所示。
Figure PCTCN2021112921-appb-000001
以图6为例，其示出了本申请实施例提供的一种输入采样电路的信号变化示意图。如图6所示，当CS_n信号为0(该DRAM为目标芯片)时，C/A Input信号将跟随C/A信号变化，经过译码后的CMD信号能够反映出C/A信号的指令内容；当CS_n为1(该DRAM为非目标芯片)时，如虚线圈所示，C/A Input始终为0，不会随着C/A信号进行翻转，避免了无意义的功能消耗。
也就是说，通过CS_n片选信号屏蔽非目标DRAM的C/A输入信号，使非目标DRAM的C/A Input信号的数值不变，来降低C/A采样系统的功耗；对于目标DRAM的C/A信号，需要和CS_n片选信号做一个选择的组合逻辑。因此，在C/A输入采样系统中，如果该DRAM未接收到有效CS_n片选信号，便会屏蔽C/A信号，使C/A信号恒定为0。这样在未接收到有效CS_n片选信号的时候，即使外部有C/A信号，内部C/A采样系统也没有数据翻转，从而节省C/A采样系统的功耗。
这样，借助于本申请实施例提供的电路设计，能够达到在无效的C/A信号不停输入时，输入采样电路通过屏蔽采样输入达到降低功耗的目的。应理解，DRAM C/A输入采样系统仅为本申请实施例示出的一个具体应用场景，但是本申请实施例并不但不局限于此范围，指令采集和低功耗系统均可采用此电路设计。
综上所述，本申请实施例提供了一种输入采样电路，通过在C/A接收器的 输入和C/A采样电路的中间插入一个涉及到CS_n Input的控制逻辑门，在CS_n Input为0的时候，C/A Input正常传输，并被之后的CKT信号采样；在CS_n Input为1的时候，C/A Input被屏蔽为恒定值0，之后CKT信号不会发生采样翻转。
这样，在CS_n片选信号为1，该DRAM不是目标芯片时，C/A输入信号在被CKT采样之前就会被屏蔽，使之恒定为0，从而减少C/A采样过程中因无效输入的信号翻转导致的电流消耗。由于C/A数据总线中，每个DRAM都存在单独的输入采样电路，即存在很多重复的采样模块，因此本申请实施例可以大量降低电路功耗。
本申请实施例提供了一种输入采样电路，通过本实施例对前述实施例的具体实施方法进行了详细阐述，从中可以看出，通过对第一脉冲信号和第二脉冲信号进行逻辑运算，能够将第二脉冲信号中的无效信号进行屏蔽，进而待采样信号不会随着第一脉冲信号中的无效信号进行电平状态翻转，从而降低输入采样电路的功能损耗。
在本申请的又一实施例中，提供了一种半导体存储器，该半导体存储器至少包括前述的输入采样电路30。
对于该半导体存储器，由于其包括输入采样电路30，通过对第一脉冲信号和第二脉冲信号进行逻辑运算，能够将第二脉冲信号中的无效信号进行屏蔽，进而待采样信号不会随着第一脉冲信号中的无效信号进行电平状态翻转，从而降低输入采样电路的功能损耗。
进一步地，该半导体存储器可以为DRAM。
以上，仅为本申请的较佳实施例而已，并非用于限定本申请的保护范围。
需要说明的是，在本申请中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由 语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
本申请所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本申请所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本申请所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。
工业实用性
本申请实施例中，该输入采样方法包括：接收第一脉冲信号和第二脉冲信号；对第一脉冲信号和第二脉冲信号进行逻辑运算，确定待采样信号；其中，待采样信号是根据逻辑运算结果将第二脉冲信号中的无效信号进行屏蔽得到的；对待采样信号进行采样处理，得到目标采样信号。这样，通过对第一脉冲信号和第二脉冲信号进行逻辑运算，能够将第二脉冲信号中的无效信号进行屏蔽，进而待采样信号不会随着第一脉冲信号中的无效信号进行电平状态翻转，从而降低输入采样电路的功能损耗。

Claims (14)

  1. 一种输入采样方法，所述方法包括：
    接收第一脉冲信号和第二脉冲信号；
    对所述第一脉冲信号和所述第二脉冲信号进行逻辑运算，确定待采样信号；其中，所述待采样信号是根据逻辑运算结果将所述第二脉冲信号中的无效信号进行屏蔽得到的；
    对所述待采样信号进行采样处理，得到目标采样信号。
  2. 根据权利要求1所述的输入采样方法，其中，所述对所述第一脉冲信号和所述第二脉冲信号进行逻辑运算，确定待采样信号，包括：
    对所述第二脉冲信号进行逻辑非运算，得到处理后第二脉冲信号；
    将所述第一脉冲信号和所述处理后第二脉冲信号进行逻辑或非运算，得到所述待采样信号。
  3. 根据权利要求1所述的输入采样方法，其中，所述对所述待采样信号进行采样处理，得到目标采样信号，包括：
    接收标准时钟信号；
    利用所述标准时钟信号对所述待采样信号进行采样，得到所述目标采样信号。
  4. 根据权利要求1所述的输入采样方法，所述方法还包括：
    对所述目标采样信号进行译码处理，得到目标信号。
  5. 根据权利要求4所述的输入采样方法，其中，所述对所述目标采样信号进行译码处理，得到目标信号，包括：
    确定采样后第一脉冲信号；其中，所述采样后第一脉冲信号是利用标准时钟信号对所述第一脉冲信号进行采样得到的；
    根据所述采样后第一脉冲信号对所述目标采样信号进行译码处理，得到所述目标信号。
  6. 根据权利要求1所述的输入采样方法，所述方法还包括：
    在所述逻辑运算结果指示所述第二脉冲信号无效的情况下，确定所述待采样信号的电平状态被屏蔽为预设值；
    在所述逻辑运算结果指示所述第二脉冲信号有效的情况下，确定所述待采样信号与所述第二脉冲信号的电平状态相同。
  7. 根据权利要求6所述的输入采样方法，其中，所述第一脉冲信号为片选信号；
    相应地，所述方法还包括：
    在所述片选信号为高电平的情况下，确定所述逻辑运算结果指示所述第二脉冲信号无效；
    在所述片选信号为低电平的情况下，确定所述逻辑运算结果指示所述第二脉冲信号有效。
  8. 根据权利要求1-7任一项所述的输入采样方法，其中，所述第二脉冲信号为控制信号或地址信号。
  9. 一种输入采样电路，所述输入采样电路包括：
    第一信号输入端，用于接收第一脉冲信号；
    第二信号输入端，用于接收第二脉冲信号；
    逻辑运算器，用于对所述第一脉冲信号和所述第二脉冲信号进行逻辑运算，得到待采样信号；其中，所述待采样信号是根据逻辑运算结果将所述第二脉冲信号中的无效信号进行屏蔽得到的；
    第一采样子电路，用于对所述待采样信号进行采样，得到目标采样信号；
    其中，所述逻辑运算器的两个输入端分别与所述第一信号输入端和所述第二信号输入端连接，所述逻辑运算器的输出端与所述第一采样子电路连接。
  10. 根据权利要求9所述的输入采样电路，其中，所述逻辑运算器包括非门以及或非门；其中，
    所述非门，用于对所述第二脉冲信号进行逻辑非运算，得到处理后第二脉冲信号；
    所述或非门，用于对所述第一脉冲信号和所述处理后第二脉冲信号进行逻 辑或非运算，得到所述待采样信号；
    其中，所述非门的输入端与所述第二信号输入端连接，所述或非门的第一输入端与所述第一信号输入端连接，所述或非门的第二输入端与所述非门的输出端连接。
  11. 根据权利要求9所述的输入采样电路，其中，所述第一采样子电路包括第三信号输入端和第一采样器，所述第三信号输入端与所述第一采样器的时钟端口连接，所述第一采样器的输入端与所述逻辑运算器的输出端连接；其中，
    所述第三信号输入端，用于接收标准时钟信号；
    所述第一采样器，用于利用所述标准时钟信号对所述待采样信号进行采样，得到所述目标采样信号。
  12. 根据权利要求9所述的输入采样电路，其中，所述输入采样电路还包括第二采样子电路，所述第二采样子电路包括第四信号输入端和第二采样器，所述第四信号输入端与所述第二采样器的时钟端口连接，所述第二采样器的输入端与所述第一信号输入端连接；其中，
    所述第四信号输入端，用于接收标准时钟信号；
    所述第二采样器，用于利用所述标准时钟信号对所述第一脉冲信号进行采样，得到采样后第一脉冲信号。
  13. 根据权利要求12所述的输入采样电路，其中，所述输入采样电路还包括译码器，所述译码器的两个输入端分别与所述第一采样子电路的输出端和所述第二采样子电路的输出端连接；其中，
    所述译码器，用于根据所述采样后第一脉冲信号对所述目标采样信号进行译码处理，得到目标信号。
  14. 一种半导体存储器，包括如权利要求9至13任一项所述的输入采样电路。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1737896A (zh) * 2004-08-20 2006-02-22 精工爱普生株式会社 电光装置的驱动电路及驱动方法,电光装置和电子设备
US20070101177A1 (en) * 2005-10-27 2007-05-03 Elpida Memory, Inc Synchronous type semiconductor device
CN102347813A (zh) * 2011-09-26 2012-02-08 华为技术有限公司 一种选取采样时钟信号的方法和设备
CN106055496A (zh) * 2016-05-20 2016-10-26 北京智芯微电子科技有限公司 一种eeprom控制器的信号生成电路及控制方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1737896A (zh) * 2004-08-20 2006-02-22 精工爱普生株式会社 电光装置的驱动电路及驱动方法,电光装置和电子设备
US20070101177A1 (en) * 2005-10-27 2007-05-03 Elpida Memory, Inc Synchronous type semiconductor device
CN102347813A (zh) * 2011-09-26 2012-02-08 华为技术有限公司 一种选取采样时钟信号的方法和设备
CN106055496A (zh) * 2016-05-20 2016-10-26 北京智芯微电子科技有限公司 一种eeprom控制器的信号生成电路及控制方法

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