WO2023221230A1 - 一种延时电路和存储器 - Google Patents

一种延时电路和存储器 Download PDF

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Publication number
WO2023221230A1
WO2023221230A1 PCT/CN2022/100189 CN2022100189W WO2023221230A1 WO 2023221230 A1 WO2023221230 A1 WO 2023221230A1 CN 2022100189 W CN2022100189 W CN 2022100189W WO 2023221230 A1 WO2023221230 A1 WO 2023221230A1
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Prior art keywords
self
shielding
flip
gate
initial
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PCT/CN2022/100189
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English (en)
French (fr)
Inventor
陆天辰
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长鑫存储技术有限公司
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Priority to US18/155,212 priority Critical patent/US20230378956A1/en
Publication of WO2023221230A1 publication Critical patent/WO2023221230A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay

Definitions

  • the present disclosure relates to the field of integrated circuits, and in particular, to a delay circuit and a memory.
  • the frequency of the clock signal is one of the important indicators of chip performance.
  • the frequency of clock signals in chips is also constantly increasing.
  • the clock signal frequency under the DDR5 specification has doubled compared to the clock signal frequency under the DDR4 specification.
  • the higher the frequency of the signal the worse its anti-interference ability. Therefore, the increase in the frequency of the clock signal also makes the signal processing performed by the clock signal more likely to cause errors.
  • the frequency-divided clock signal can be used. Since the frequency of the divided clock signal is lower than the frequency of the clock signal, the probability of error can be reduced.
  • embodiments of the present disclosure provide a delay circuit and a memory, which can improve the accuracy of signal processing.
  • the embodiment of the present disclosure provides a delay circuit, including:
  • the self-shielding module is configured to receive an initial command signal and N initial clock signals, and register the initial command signal according to the first initial clock signal among the N initial clock signals that first triggers the initial command signal, Mask other N-1 second initial clock signals among the N initial clock signals, and output N intermediate command signals, where N is an integer greater than or equal to 2; the frequencies of the N initial clock signals are the same, and Different phases;
  • a delay module electrically connected to the self-shielding module, is configured to receive N intermediate command signals and N initial clock signals, delay output of the N intermediate command signals, and obtain a delay command. Signal.
  • the self-shielding module includes: a shielding unit configured to receive N initial clock signals and output N intermediate clock signals; wherein the N intermediate clock signals include an effective first intermediate clock signal. clock signal and N-1 invalid second intermediate clock signals; a register unit, electrically connected to the shielding unit, is configured to receive the initial command signal and N intermediate clock signals, according to the first intermediate clock The signal registers the initial command signal, and obtains and outputs N intermediate command signals.
  • the register unit includes: N self-shielding flip-flops; the N self-shielding flip-flops are all D flip-flops; the N intermediate command signals include a valid first intermediate command signal and N- 1 invalid second intermediate command signal; the first input terminals of the N self-shielding flip-flops all receive the initial command signal, and the second input terminals of the N self-shielding flip-flops are all connected to the shielding unit
  • An output terminal outputs N-1 second intermediate command signals in one-to-one correspondence.
  • the shielding unit includes: N AND gates, each of the AND gates includes a first input terminal and N-1 second input terminals; the first input terminals of the N AND gates correspond one to one.
  • Receive N initial clock signals, and the output terminals of the N AND gates are connected to the second input terminals of the N self-shielding flip-flops in one-to-one correspondence; the N-1 second input terminals of each AND gate are One is connected to the second output terminals of N-1 other self-shielding flip-flops other than its corresponding self-shielding flip-flop.
  • the shielding unit includes: N inverters and N NOR gates; each of the NOR gates includes a first input terminal and N-1 second input terminals; N inverters The input terminals of the N inverters receive the N initial clock signals in one-to-one correspondence, and the output terminals of the N inverters are connected to the first input terminals of the N NOR gates in one-to-one correspondence.
  • the output terminals are connected to the second input terminals of N self-shielding flip-flops in one-to-one correspondence; the N-1 second input terminals of each NOR gate are connected to the N-1 second input terminals outside its corresponding self-shielding flip-flop in one-to-one correspondence.
  • the first output terminal of another self-shielding flip-flop is a self-shielding flip-flop.
  • the delay module includes: M-level second register units, where M is an integer greater than or equal to 2; each level of the second register unit includes: N delay flip-flops; the N delay flip-flops are all is a D flip-flop; the N delay flip-flops in the second register unit of each stage receive N initial clock signals at their second input terminals in one-to-one correspondence; the N delay flip-flops in the second register unit of the first stage Delay flip-flops, whose first input terminals are connected to the first output terminals of N self-shielding flip-flops in one-to-one correspondence; N delay flip-flops in the i-th second register unit, whose first input terminals are One corresponds to connecting the output terminals of N delay flip-flops in the second register unit of the upper level, i is greater than 1 and less than or equal to M.
  • M (CL-A)/N, where CL is the maximum number of delay cycles, and A is the number of cycles corresponding to the command pre-operation.
  • the delay module also includes: an OR gate, the OR gate includes N input terminals; N delay flip-flops in the M-th second register unit, the first output terminals of which are connected in a one-to-one correspondence.
  • the N input terminals of the OR gate; the output terminal of the OR gate outputs the delay command signal.
  • the N initial clock signals are odd-even frequency-divided clock signals
  • the odd-even frequency-divided clock signals include: odd clock signals and even clock signals; the odd clock signals and the even clock signals
  • the frequencies are the same and the phases are opposite.
  • the self-shielding module includes: a shielding unit and a register unit; the register unit includes: a first self-shielding flip-flop and a second self-shielding flip-flop; the first self-shielding flip-flop and the second The self-shielding flip-flops are both D flip-flops; the first input terminal of the first self-shielding flip-flop and the first input terminal of the second self-shielding flip-flop both receive the command signal.
  • the shielding unit includes: a first AND gate and a second AND gate; both the first AND gate and the second AND gate are two-input AND gates; the first AND gate of the first AND gate The input terminal receives the even clock signal, the output terminal of the first AND gate is connected to the second input terminal of the first self-shielding flip-flop, and the second input terminal of the first AND gate is connected to the second self-shielding flip-flop.
  • the second output terminal of the shielding flip-flop; the first input terminal of the second AND gate receives the odd clock signal, and the output terminal of the second AND gate is connected to the second input terminal of the second self-shielding flip-flop.
  • the second input terminal of the second AND gate is connected to the second output terminal of the first self-shielding flip-flop.
  • the shielding unit includes: a first inverter, a second inverter, a first NOR gate and a second NOR gate; both the first NOR gate and the second NOR gate It is a two-input NOR gate; the input terminal of the first inverter receives the even clock signal, and the output terminal of the first inverter is connected to the first input terminal of the first NOR gate; so The output terminal of the first NOR gate is connected to the second input terminal of the first self-shielding flip-flop, and the second input terminal of the first NOR gate is connected to the first output terminal of the second self-shielding flip-flop.
  • the input terminal of the second inverter receives the odd clock signal, and the output terminal of the second inverter is connected to the first input terminal of the second NOR gate; the second NOR gate The output terminal is connected to the second input terminal of the second self-shielding flip-flop, and the second input terminal of the second NOR gate is connected to the first output terminal of the first self-shielding flip-flop.
  • An embodiment of the present disclosure also provides a memory, which is characterized in that the memory includes the delay circuit in the above solution.
  • the memory is electrically connected to the control module, wherein the memory meets the DDR4 specification and the control module meets the DDR5 specification; the memory also includes a frequency dividing circuit; the memory receives from the control module The standard clock signal is divided into an initial clock signal by the frequency dividing circuit, and the initial clock signal is transmitted to the delay circuit.
  • the embodiment of the present disclosure provides a delay circuit and memory, including: a self-shielding module and a delay module.
  • the self-shielding module is configured to receive an initial command signal and N initial clock signals, register the initial command signal according to the first initial clock signal that first triggers the initial command signal among the N initial clock signals, and shield the N initial clock signals. other N-1 second initial clock signals, and output N intermediate command signals, where N is an integer greater than or equal to 2; the N initial clock signals have the same frequency and different phases.
  • the delay module is electrically connected to the self-shielding module, and is configured to receive N intermediate command signals and N initial clock signals, and delay output of the N intermediate command signals to obtain a delayed command signal. In this way, the delay circuit only controls the registration and delay of the command signal through the first initial clock signal and shields the second initial clock signal, avoiding errors caused by the simultaneous action of N initial clock signals and improving the accuracy of signal processing. .
  • Figure 1 is a schematic structural diagram of a delay circuit provided by an embodiment of the present disclosure
  • Figure 2 is a signal schematic diagram 1 of a delay circuit provided by an embodiment of the present disclosure
  • Figure 3 is a schematic second structural diagram of a delay circuit provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram three of a delay circuit provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram 4 of a delay circuit provided by an embodiment of the present disclosure.
  • Figure 6 is a second signal schematic diagram of a delay circuit provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram 5 of a delay circuit provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram 6 of a delay circuit provided by an embodiment of the present disclosure.
  • Figure 9 is a signal diagram 3 of the delay circuit provided by an embodiment of the present disclosure.
  • Figure 10 is a signal diagram 4 of the delay circuit provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic structural diagram 7 of a delay circuit provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic structural diagram 8 of a delay circuit provided by an embodiment of the present disclosure.
  • Figure 13 is a signal diagram 5 of a delay circuit provided by an embodiment of the present disclosure.
  • Figure 14 is a schematic structural diagram 9 of a delay circuit provided by an embodiment of the present disclosure.
  • Figure 15 is a signal diagram 6 of the delay circuit provided by an embodiment of the present disclosure.
  • Figure 16 is a schematic structural diagram of a delay circuit provided by an embodiment of the present disclosure.
  • Figure 17 is a schematic structural diagram 11 of a delay circuit provided by an embodiment of the present disclosure.
  • Figure 18 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure.
  • Figure 19 is a second structural schematic diagram of a memory provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a delay circuit provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a delay circuit 10, which includes a self-shielding module 101 and a delay module 102.
  • the self-shielding module 101 is configured to receive the initial command signal CMD and N initial clock signals CLK ⁇ 1:N> (ie, initial clock signals CLK ⁇ 1> ⁇ CLK ⁇ N>).
  • N initial clock signals CLK ⁇ 1: The first initial clock signal in N> that first triggers the initial command signal CMD registers the initial command signal CMD and masks the effect of the other N-1 second initial clock signals among the N initial clock signals CLK ⁇ 1:N>.
  • N intermediate command signals CMD_i i is greater than or equal to 1, and less than or equal to N
  • the N initial clock signals have the same frequency and different phases.
  • the delay module 102 is electrically connected to the self-shielding module 101 and is configured to receive N intermediate command signals CMD_i and N initial clock signals CLK ⁇ 1:N>, and pair N intermediate command signals are delayed and output, and a delayed command signal CMD_SHIFT is obtained.
  • the initial clock signal may be a frequency-divided clock signal.
  • the frequency-divided clock signal is obtained by dividing the clock signal in the chip, and its period is a multiple of the period of the clock signal; for example, the period of the divided-by-four clock signal is 4 times the period of the clock signal, that is to say , the frequency of the four-divided clock signal is one-quarter of the frequency of the clock signal; another example, the period of the odd-even divided clock signal (i.e., the two-divided clock signal) is twice the period of the clock signal, that is to say, the odd-even divided clock signal.
  • the frequency of the frequency clock signal is one-half the frequency of the clock signal.
  • the initial command signal can be active at a high level or at a low level.
  • a "read command” is active at a high level
  • a "write command” is active at a low level.
  • the present disclosure There are no restrictions here.
  • the command signal CMD shown in Figure 2 is active at high level.
  • the initial command signal CMD is low level in the normal state. When the initial command signal CMD contains a high level pulse, a control effect occurs.
  • the initial command signal CMD is triggered and registered. Since the phases of the N initial clock signals CLK ⁇ 1:N> are different, the N initial clock signals CLK ⁇ 1:N >The moment when the trigger edge corresponding to the initial command signal CMD is reached is not the same.
  • the initial clock signals CLK ⁇ 1>, CLK ⁇ 2>, CLK ⁇ 3> and CLK ⁇ 4> are frequency-divided signals of the clock signal CLK, and their phases differ by 90° in sequence.
  • the initial command signal CMD is rising edge triggered.
  • the initial clock signal CLK ⁇ 1> is the first to reach the rising edge (as shown by the dotted arrow in Figure 2). That is to say, the initial clock signal CLK ⁇ 1> is the first to reach the initial The trigger edge corresponding to the command signal CMD becomes the first initial clock signal.
  • the initial command signal CMD can also be set to fall edge trigger, then in the effective pulse width of the initial command signal CMD, the initial clock signal that reaches the falling edge first becomes the first initial clock signal, which is not done here. limit.
  • the self-shielding module 101 can shield the second initial clock signal except the first initial clock signal among the N initial clock signals CLK ⁇ 1:N>.
  • shielding the second initial clock signal means that the second initial clock signal is shielded.
  • the second initial clock signal will not trigger the initial command signal CMD register.
  • the effective pulse width of the command signal is greater than or equal to the period length of each initial clock signal. In this way, within the effective pulse width of the command signal, each initial clock signal can reach the trigger edge at least once, ensuring that the command The signal can always be registered and delayed by the delay circuit provided by the embodiment of the present disclosure.
  • the delay circuit provided by the present disclosure only controls the registration and delay of the command signal through the first initial clock signal, shields the second initial clock signal, and avoids errors caused by the simultaneous action of N initial clock signals. Improved signal processing accuracy.
  • the delay circuit provided by the present disclosure registers the command signal based on the first initial clock signal that first triggers the command signal among the N initial clock signals, this ensures that the delay caused by the command signal being registered is guaranteed It is the shortest, that is, it shortens the relative delay between the delayed command signal and the command signal.
  • the self-shielding module 101 includes: a shielding unit 201 and a register unit 202.
  • the shielding unit 201 is configured to receive N initial clock signals CLK ⁇ 1:N>, shield the effects of other N-1 second initial clock signals among the N initial clock signals CLK ⁇ 1:N>, and output N intermediate Clock signal /CLK ⁇ 1:N> (i.e. intermediate clock signal /CLK ⁇ 1> ⁇ /CLK ⁇ N>).
  • the N intermediate clock signals /CLK ⁇ 1:N> include a valid first intermediate clock signal and N-1 invalid second intermediate clock signals.
  • the register unit 202 is electrically connected to the shielding unit 201 and is configured to receive the initial command signal CMD and N intermediate clock signals /CLK ⁇ 1:N>, register the initial command signal CMD according to the first intermediate clock signal, and obtain and output N intermediate clock signals.
  • Command signal CMD_i is electrically connected to the shielding unit 201 and is configured to receive the initial command signal CMD and N intermediate clock signals /CLK ⁇ 1:N>, register the initial command signal CMD according to the first intermediate clock signal, and obtain and output N intermediate clock signals.
  • Command signal CMD_i is electrically connected to the shielding unit 201 and is configured to receive the initial command signal CMD and N intermediate clock signals /CLK ⁇ 1:N>, register the initial command signal CMD according to the first intermediate clock signal, and obtain and output N intermediate clock signals.
  • Command signal CMD_i is electrically connected to the shielding unit 201 and is configured to receive the initial command signal CMD and N intermediate clock signals /CLK ⁇ 1:N>, register the initial command signal
  • the first intermediate clock signal is a valid signal, that is, the first intermediate clock signal can trigger the registration of the initial command signal CMD; the first intermediate clock signal has the same waveform as the first initial clock signal, that is, the first The initial clock signal triggers the registration of the initial command signal CMD.
  • the N-1 second intermediate clock signals are invalid signals, that is, none of the N-1 second intermediate clock signals can trigger the registration of the initial command signal CMD; the N-1 second intermediate clock signals correspond to N-1 Second initial clock signals, that is, the effects of N-1 second initial clock signals are shielded.
  • the shielding unit shields the effect of N-1 second initial clock signals, and the register unit only controls the registration of the command signal through the first initial clock signal. In this way, the effects of the simultaneous action of N initial clock signals are avoided. error, improving the accuracy of signal processing.
  • the register unit 202 includes: N self-shielding flip-flops 30 , and the N self-shielding flip-flops 30 are all D flip-flops.
  • the N intermediate command signals CMD_1 to CMD_N include a valid first intermediate command signal and N-1 invalid second intermediate command signals.
  • the first input terminals D of the N self-shielding flip-flops 30 all receive the initial command signal CMD, and the second input terminals C of the N self-shielding flip-flops 30 are all connected to the output terminals of the shielding unit 201 .
  • the first self-shielding flip-flop that receives the first intermediate clock signal among the N self-shielding flip-flops 30 registers the initial command signal according to the first intermediate clock signal, and outputs the first intermediate command signal at its first output terminal Q.
  • the other N-1 second self-shielding flip-flops among the N self-shielding flip-flops 30 receive the N-1 second intermediate clock signals in one-to-one correspondence, and output the N-1 second intermediate clock signals at their first output terminals Q in one-to-one correspondence. 2. Intermediate command signal.
  • the first intermediate command signal is triggered by the first intermediate clock signal and is output.
  • the first intermediate command signal contains pulses and is a valid signal. Since the effect of the N-1 second initial clock signals is shielded, the N-1 second intermediate command signals are not pulse signals that are triggered and output. Therefore, the N-1 second intermediate command signals do not contain pulses. is an invalid signal.
  • the shielding unit includes: N AND gates; the N AND gates are all N-input AND gates, and each AND gate includes a first input terminal and N-1 second input terminals.
  • the first input terminals of the N AND gates receive N initial clock signals in a one-to-one correspondence, and the output terminals of the N AND gates are connected to the second input terminals of the N self-shielding flip-flops in a one-to-one correspondence.
  • the N-1 second input terminals of each AND gate are connected to the second output terminals of N-1 other self-shielding flip-flops other than its corresponding self-shielding flip-flop in one-to-one correspondence.
  • the shielding unit 201 may include four AND gates, namely AND gate 401, AND gate 402, AND gate 403 and AND gate 404. These four AND gates are all 4-input AND gates. Each AND gate Each gate includes a first input terminal and three second input terminals. The first input terminals of the four AND gates receive four initial clock signals in a one-to-one correspondence. That is to say, the first input terminal of the AND gate 401 receives the initial clock signal CLK ⁇ 1>, and the first input terminal of the AND gate 402 receives the initial clock signal CLK ⁇ 1>. The clock signal CLK ⁇ 2>, the first input terminal of the AND gate 403 receives the initial clock signal CLK ⁇ 3>, and the first input terminal of the AND gate 404 receives the initial clock signal CLK ⁇ 4>.
  • the output terminals of the four AND gates are connected to the second input terminals C of the four self-shielding flip-flops in a one-to-one correspondence. That is to say, the output terminal of the AND gate 401 is connected to the second input terminal C of the self-shielding flip-flop 301, and the AND gate 402
  • the output terminal of the AND gate 403 is connected to the second input terminal C of the self-shielding flip-flop 302
  • the output terminal of the AND gate 403 is connected to the second input terminal C of the self-shielding flip-flop 303
  • the output terminal of the AND gate 404 is connected to the second input terminal C of the self-shielding flip-flop 304.
  • Input terminal C where the output terminal of the AND gate 401 transmits the intermediate clock signal /CLK ⁇ 1> to the second input terminal C of the self-shielding flip-flop 301, and the output terminal of the AND gate 402 transmits the intermediate clock signal /CLK ⁇ 2> to The second input terminal C of the self-shielding flip-flop 302 and the output terminal of the AND gate 403 transmit the intermediate clock signal /CLK ⁇ 3> to the second input terminal C of the self-shielding flip-flop 303.
  • the output terminal of the AND gate 404 transmits the intermediate clock signal. /CLK ⁇ 4> to the second input terminal C of the self-shielding flip-flop 304.
  • each AND gate is connected to the second output terminals of three other self-shielding flip-flops except its corresponding self-shielding flip-flop in one-to-one correspondence. That is to say, the three second input terminals of the AND gate 401 are connected to the second output terminal of the self-shielding flip-flop 302 in one-to-one correspondence.
  • the second output terminal of the self-shielding flip-flop 303 and the second output terminal of the self-shielding flip-flop 304 The three second input terminals of the AND gate 402 are connected to the second output terminal of the self-shielding flip-flop 301 in one-to-one correspondence.
  • the second output terminal of the self-shielding flip-flop 303 and the second output terminal of the self-shielding flip-flop 304 The three second input terminals of the AND gate 403 are connected to the second output terminal of the self-shielding flip-flop 301 in one-to-one correspondence.
  • the second output terminal of the self-shielding flip-flop 302 and the second output terminal of the self-shielding flip-flop 304 The three second input terminals of the AND gate 404 are connected to the second output terminal of the self-shielding flip-flop 301 in one-to-one correspondence.
  • initial command signal CMD initial clock signals CLK ⁇ 1>, CLK ⁇ 2>, CLK ⁇ 3> and CLK ⁇ 4> shown in Figure 6 are corresponding to the input map The circuit shown in 5.
  • each of the AND gates 401, 402, 403 and 404 has its three second input terminals receiving a high level.
  • AND gates 401, 402, 403 and 404 will not produce a shielding effect
  • the intermediate clock signal /CLK ⁇ 1> and the initial clock signal CLK ⁇ 1> have the same waveforms
  • the signal CLK ⁇ 2> has the same waveform
  • the intermediate clock signal /CLK ⁇ 3> and the initial clock signal CLK ⁇ 3> have the same waveform
  • the intermediate clock signal /CLK ⁇ 4> and the initial clock signal CLK ⁇ 4> have the same waveform.
  • the initial clock signal CLK ⁇ 1> reaches the rising edge first, that is, the initial clock signal CLK ⁇ 1> becomes the first initial clock signal.
  • the self-shielding flip-flop 301 is triggered by the intermediate clock signal /CLK ⁇ 1>, registers the initial command signal CMD, and outputs the first intermediate command signal CMD_1 at its first output terminal Q.
  • the first intermediate command The inverted signal of signal CMD_1 is transmitted to AND gates 402, 403 and 404, that is, the intermediate clock signal /CLK ⁇ 1> becomes the effective first intermediate clock signal.
  • the intermediate clock signals /CLK ⁇ 2>, / Both CLK ⁇ 3> and /CLK ⁇ 4> remain low, that is, within the duration b, the intermediate clock signals /CLK ⁇ 2>, /CLK ⁇ 3> and /CLK ⁇ 4> are all masked, That is, the intermediate clock signals /CLK ⁇ 2>, /CLK ⁇ 3> and /CLK ⁇ 4> are all invalid second intermediate clock signals.
  • the intermediate clock signals /CLK ⁇ 2>, /CLK ⁇ 3> and /CLK ⁇ 4> will not generate rising edges to trigger the self-shielding flip-flops 302, 303 and 304
  • Registering the initial command signal CMD, CMD_2, CMD_3 and CMD_4 output by the first output terminals Q of the self-masking flip-flops 302, 303 and 304 remain low without including any pulse (not shown in FIG. 6).
  • the first initial clock signal triggers the initial command signal registration to obtain the shift command signal. Furthermore, the N-1 AND gates that have not received the first initial clock signal will change the second initial clock according to the shift command signal. Signal shielding, thereby avoiding errors caused by the simultaneous action of N initial clock signals, improves the accuracy of signal processing.
  • the shielding unit includes: N inverters and N NOR gates; the N NOR gates are all N-input terminal NOR gates, and each NOR gate includes a first input terminal and N-1 second input terminals.
  • the input terminals of the N inverters receive N initial clock signals one by one, the output terminals of the N inverters are connected to the first input terminals of the N NOR gates one by one, and the output terminals of the N NOR gates are connected one by one.
  • One corresponds to the second input terminal of N self-shielding flip-flops.
  • the N-1 second input terminals of each NOR gate are connected to the first output terminals of N-1 other self-shielding flip-flops other than its corresponding self-shielding flip-flop in one-to-one correspondence.
  • the shielding unit 201 may include: four inverters 411, 412, 413 and 414, and four NOR gates, namely inverter 411, inverter 412, inverter 413, inverter 414, NOR gate 421, NOR gate 422, NOR gate 423 and NOR gate 424.
  • These four NOR gates are all 4-input terminal NOR gates.
  • Each NOR gate includes a first input terminal and 3 second inputs.
  • the input terminals of the four inverters receive four initial clock signals in one-to-one correspondence. That is to say, the input terminal of the inverter 411 receives the initial clock signal CLK ⁇ 1>, and the input terminal of the inverter 412 receives the initial clock signal CLK. ⁇ 2>, the input terminal of the inverter 413 receives the initial clock signal CLK ⁇ 3>, and the input terminal of the inverter 414 receives the initial clock signal CLK ⁇ 4>.
  • the output terminals of the four inverters are connected to the first input terminals of the four NOR gates in a one-to-one correspondence. That is to say, the output terminal of the inverter 411 is connected to the first input terminal of the NOR gate 421, and the output terminal of the inverter 412 is connected to the first input terminal of the NOR gate 421.
  • the output terminal is connected to the first input terminal of the NOR gate 422 , the output terminal of the inverter 413 is connected to the first input terminal of the NOR gate 423 , and the output terminal of the inverter 414 is connected to the first input terminal of the NOR gate 424 .
  • the output terminals of the four NOR gates are connected to the second input terminals C of the four self-shielding flip-flops in a one-to-one correspondence. That is to say, the output terminal of the NOR gate 421 is connected to the second input terminal C of the self-shielding flip-flop 301, or The output terminal of the NOT gate 422 is connected to the second input terminal C of the self-shielding flip-flop 302, the output terminal of the NOR gate 423 is connected to the second input terminal C of the self-shielding flip-flop 303, and the output terminal of the NOR gate 424 is connected to the self-shielding trigger.
  • the second input terminal C of the switch 304 wherein the output terminal of the NOR gate 421 transmits the intermediate clock signal /CLK ⁇ 1> to the second input terminal C of the self-masking flip-flop 301, and the output terminal of the NOR gate 422 transmits the intermediate clock signal
  • the signal /CLK ⁇ 2> is sent to the second input terminal C of the self-shielding flip-flop 302, and the output terminal of the NOR gate 423 transmits the intermediate clock signal /CLK ⁇ 3> to the second input terminal C of the self-shielding flip-flop 303.
  • the output of gate 424 transmits the intermediate clock signal /CLK ⁇ 4> to the second input C of self-masking flip-flop 304 .
  • each NOR gate is connected to the first output terminals Q of three other self-shielding flip-flops except the corresponding self-shielding flip-flop in one-to-one correspondence.
  • the three second input terminals of the NOR gate 421 The second input terminal is connected to the first output terminal Q of the self-shielding flip-flop 302, the first output terminal Q of the self-shielding flip-flop 303, and the first output terminal Q of the self-shielding flip-flop 304 in one-to-one correspondence; 3 of the NOR gate 422
  • the second input terminals are connected to the first output terminal Q of the self-shielding flip-flop 301, the first output terminal Q of the self-shielding flip-flop 303, and the first output terminal Q of the self-shielding flip-flop 304 in one-to-one correspondence;
  • the three second input terminals are connected to the first output terminal Q of the self-shielding flip-flop 301, the first output terminal
  • initial command signal CMD initial clock signals CLK ⁇ 1>, CLK ⁇ 2>, CLK ⁇ 3> and CLK ⁇ 4> shown in Figure 6 are corresponding to the input map The circuit shown in 7.
  • each of the NOR gates 421, 422, 423 and 424 has its three second input terminals receiving low levels.
  • NOR gates 421, 422, 423 and 424 will not produce a shielding effect
  • the intermediate clock signal /CLK ⁇ 1> and the initial clock signal CLK ⁇ 1> have the same waveforms
  • the intermediate clock signal /CLK ⁇ 2> and the initial The clock signal CLK ⁇ 2> has the same waveform
  • the intermediate clock signal /CLK ⁇ 3> and the initial clock signal CLK ⁇ 3> have the same waveform
  • the intermediate clock signal /CLK ⁇ 4> and the initial clock signal CLK ⁇ 4> have the same waveform.
  • the initial clock signal CLK ⁇ 1> reaches the rising edge first, that is, the initial clock signal CLK ⁇ 1> becomes the first initial clock signal.
  • the self-shielding flip-flop 301 is triggered by the intermediate clock signal /CLK ⁇ 1>, registers the initial command signal CMD, and outputs the first intermediate command signal CMD_1 at its first output terminal Q.
  • the first intermediate command The signal CMD_1 is transmitted to the NOR gates 422, 423 and 424, that is, the intermediate clock signal /CLK ⁇ 1> becomes the effective first intermediate clock signal.
  • the intermediate clock signals /CLK ⁇ 2>, /CLK ⁇ 3 output by the NOR gates 422, 423 and 424 > and /CLK ⁇ 4> both remain low, that is to say, within the duration b, the intermediate clock signals /CLK ⁇ 2>, /CLK ⁇ 3> and /CLK ⁇ 4> are all masked, that is, the intermediate clock Signals /CLK ⁇ 2>, /CLK ⁇ 3> and /CLK ⁇ 4> are all invalid second intermediate clock signals.
  • the intermediate clock signals /CLK ⁇ 2>, /CLK ⁇ 3> and /CLK ⁇ 4> will not generate rising edges to trigger the self-shielding flip-flops 302, 303 and 304
  • Registering the initial command signal CMD, CMD_2, CMD_3 and CMD_4 output by the first output terminals Q of the self-masking flip-flops 302, 303 and 304 remain low without including any pulse (not shown in FIG. 6).
  • the first initial clock signal triggers the initial command signal registration to obtain the shift command signal. Furthermore, the N-1 NOR gates that do not receive the first initial clock signal through the inverter will, according to the shift command signal The second initial clock signal is shielded, thereby avoiding errors caused by the simultaneous action of N initial clock signals and improving the accuracy of signal processing.
  • the delay module 102 includes M-level second register units 203, where M is an integer greater than or equal to 2.
  • Each stage of the second register unit 203 includes N delay flip-flops 31, and the N delay flip-flops 31 are all D flip-flops.
  • the first input terminals D of the N delay flip-flops 31 in the first-level second register unit 203 are connected to the first output terminals Q of the N self-shielding flip-flops 30 in one-to-one correspondence.
  • the second input terminals C of the N delay flip-flops 31 in the second register unit 203 of each stage receive N initial clock signals CLK ⁇ 1>, CLK ⁇ 2>...CLK ⁇ N> (that is, CLK ⁇ 1:N>).
  • the first input terminals D of the N delay flip-flops 31 in the i-th second register unit 203 are connected to the upper-level second register unit in one-to-one correspondence.
  • the first output terminals Q, i of the N delay flip-flops 31 in 203 are greater than 1 and less than or equal to M.
  • the first input terminals D of the N delay flip-flops 31 in the second-level second register unit 203 are connected to the N delay flip-flops 31 in the first-level second register unit 203 in one-to-one correspondence.
  • the first output terminal Q of The first output terminal Q of the flip-flop 31 is
  • the number of stages of the second register unit 203 M (CL-A)/N, where CL is the maximum number of delay cycles, and A is the number of cycles corresponding to the command pre-operation. Both CL and A meet the requirements of integrated circuit design standards.
  • the clock cycle corresponding to CL and A may be the cycle of the external clock, that is, one-Nth of the cycle of the initial clock signal.
  • a1 corresponds to the clock cycle of preamble (prefetch)
  • a2 corresponds to offset (clock signal deviation margin) of the clock period.
  • the delay module 102 also includes an OR gate 32 , and the OR gate 32 includes N input terminals.
  • the first output terminals Q of the N delay flip-flops 31 in the M-th second register unit 203 are connected to the N input terminals of the OR gate 32 in one-to-one correspondence.
  • the output terminal of the OR gate 32 serves as the output terminal of the delay module 102 and outputs the delay command signal CMD_SHIFT.
  • the initial command signal CMD is registered as the first intermediate command signal CMD_1. Therefore, the first intermediate command signal After CMD_1 passes through the M-level second register unit 203, it is delayed into a signal CMD_1m and input to the OR gate 32.
  • the waveforms of the initial command signal CMD, the first intermediate command signal CMD_1 and the signal CMD_1m are as shown in Figure 9.
  • the second intermediate command signals CMD_2 to CMD_N will remain low level and do not include any pulses.
  • the M-th level second register corresponding to the second intermediate command signals CMD_2 to CMD_N The first output terminal Q of the delay flip-flop 31 in the unit 203 is still low level and does not include any pulses.
  • one input terminal of the OR gate 32 receives the signal CMD_1m, and the second input terminal receives a continuous low level. Therefore, the delayed command signal CMD_SHIFT output by the OR gate 32 has the same waveform as the signal CMD_1m, and the delayed command signal
  • the effective pulse width of CMD_SHIFT is equal to the effective pulse width of the initial command signal CMD.
  • the self-shielding module shields the effect of the second initial clock signal and only outputs a single shift command signal. Furthermore, the delay module can delay a single shift command signal, thus ensuring The effective pulse width of the finally obtained delayed command signal is equal to the effective pulse width of the initial command signal, which improves the accuracy of signal processing.
  • the N initial clock signals are odd-even frequency-divided clock signals.
  • the odd-even frequency-divided clock signals include: odd clock signal CLK_O and even clock signal CLK_E.
  • the odd clock signal CLK_O and the even clock signal CLK_E have the same frequency and opposite phases.
  • the odd clock signal CLK_O and the even clock signal CLK_E are frequency-divided signals of the clock signal CLK. Their period is twice the period of the clock signal CLK, and their frequency is half of the frequency of the clock signal CLK.
  • the self-shielding module 101 includes: a shielding unit 201 and a register unit 202, wherein the register unit 202 includes: a first self-shielding flip-flop 501 and a second self-shielding flip-flop 502. 10 and 11, the first self-shielding flip-flop 501 and the second self-shielding flip-flop 502 are both D flip-flops.
  • the first input terminal D of the first self-shielding flip-flop 501 and the second self-shielding flip-flop 502 are The first input terminals D both receive the initial command signal CMD; the shielding unit 201 receives the odd clock signal CLK_O and the even clock signal CLK_E respectively, and are respectively connected to the second input terminal C and the second self-shielding trigger of the first self-shielding flip-flop 501
  • the shielding unit 101 includes: a first AND gate A1 and a second AND gate A2.
  • the first AND gate A1 and the second AND gate A2 are both two-input AND gates. .
  • the first input terminal of the first AND gate A1 receives the even clock signal CLK_E
  • the output terminal of the first AND gate A1 is connected to the second input terminal C of the first self-shielding flip-flop 501
  • the second input terminal of the first AND gate A1 is connected to The second output terminal of the second self-shielding flip-flop 502
  • the first AND gate A1 outputs the intermediate clock signal CLK_E1.
  • the first input terminal of the second AND gate A2 receives the odd clock signal CLK_O
  • the output terminal of the second AND gate A2 is connected to the second input terminal C of the second self-shielding flip-flop 502
  • the second input terminal of the second AND gate A2 is connected to The second output terminal of the first self-shielding flip-flop 501
  • the second AND gate A2 outputs the intermediate clock signal CLK_O1.
  • the CMD_E output by the first output terminal Q of the first self-shielding flip-flop 501 and the first output terminal of the second self-shielding flip-flop 502
  • the CMD_O output by Q is both low level, then the second input terminal of the second AND gate A2 and the second input terminal of the first AND gate A1 both receive a high level.
  • the first AND gate A1 and the second AND gate A2 will not produce a shielding effect, the intermediate clock signal CLK_E1 and the even clock signal CLK_E have the same waveforms, and the intermediate clock signal CLK_O1 and the odd clock signal CLK_O have the same waveforms.
  • the even clock signal CLK_E reaches the rising edge earlier than the odd clock signal CLK_O (as shown by the dotted arrow in Figure 13), that is, the even clock signal CLK_E becomes the first initial clock signal.
  • the first self-shielding flip-flop 501 is triggered by the intermediate clock signal CLK_E1, registers the initial command signal CMD, and outputs the shift command signal CMD_E at its first output terminal Q, and at the same time, outputs the inverse of the shift command signal CMD_E.
  • the phase signal is output to the second input terminal of the second AND gate A2.
  • the intermediate clock signal CLK_O1 output by the second AND gate A2 remains low, that is, The second AND gate A2 masks the odd clock signal CLK_O within the duration d. Furthermore, the intermediate clock signal CLK_O1 will not generate a rising edge to trigger the second self-shielding flip-flop 502 to register the initial command signal CMD, and the CMD_O output by the first output terminal Q of the second self-shielding flip-flop 502 remains low level without including any pulses.
  • the second self-shielding flip-flop 502 is triggered by the intermediate clock signal CLK_O1 and registers the initial command signal CMD, and the first output of the first self-shielding flip-flop 501 CMD_E output by terminal Q remains low without including any pulses.
  • the delay module 102 may include M-level second register units 203, where M is an integer greater than or equal to 2.
  • the second register unit 203 of each stage includes delay flip-flops 511 and 512, and both delay flip-flops 511 and 512 are D flip-flops.
  • the first input terminal D of the delay flip-flop 511 is connected to the first output terminal Q of the self-shielding flip-flop 501
  • the first input terminal D of the delay flip-flop 512 is connected to the self-shielding flip-flop.
  • the second input terminal C of the delay flip-flop 511 receives the even clock signal CLK_E
  • the second input terminal C of the delay flip-flop 512 receives the odd clock signal CLK_O.
  • M is greater than or equal to 2
  • the first input terminal D of the delay flip-flop 511 in the second register unit 203 of the i-th stage is connected to the first input terminal D of the delay flip-flop 511 in the second register unit 203 of the previous stage.
  • An output terminal Q, the first input terminal D of the delay flip-flop 512 in the second register unit 203 of the i-th stage is connected to the first output terminal Q, i of the delay flip-flop 512 in the second register unit 203 of the previous stage. Greater than 1 and less than or equal to M.
  • the delay module 102 also includes an OR gate 52, which is a two-input OR gate.
  • the first output terminals Q of the delay flip-flops 511 and 512 in the M-th second register unit 203 are connected to the two input terminals of the OR gate 52 in one-to-one correspondence.
  • the output terminal of the OR gate 52 serves as the output terminal of the delay module 102 and outputs the delay command signal CMD_SHIFT.
  • the initial command signal CMD is registered as the shift command signal CMD_E, so that the shift command signal CMD_E passes through the M-th level After the second register unit 203, it is delayed to the signal CMD_Em and input to the OR gate 52.
  • the waveforms of the initial command signal CMD, the shift command signal CMD_E and the signal CMD_Em are as shown in Figure 15.
  • the signal CMD_O output by the self-shielding flip-flop 502 will remain low and does not include any pulses.
  • the delay flip-flop 512 in the M-th second register unit 203 The output signal CMD_Om is still low level and does not include any pulses.
  • one input terminal of the OR gate 52 receives the signal CMD_Em, and the other input terminal receives a continuous low level. Therefore, the delayed command signal CMD_SHIFT output by the OR gate 52 has the same waveform as the signal CMD_Em, and the delayed command signal
  • the effective pulse width of CMD_SHIFT is equal to the effective pulse width of the initial command signal CMD.
  • the first initial clock signal triggers the initial command signal registration to obtain the shift command signal.
  • the AND gate that does not receive the first initial clock signal will shield the other frequency-divided clock signal according to the shift command signal, so that the The shielding module only outputs a single shift command signal; furthermore, the delay module can delay a single shift command signal, thereby avoiding errors caused by the simultaneous action of odd and even clock signals and ensuring the final delay.
  • the effective pulse width of the command signal is equal to the effective pulse width of the initial command signal, which improves the accuracy of signal processing.
  • the shielding unit 101 includes: a first inverter N1, a second inverter N2, a first NOR gate NOR1 and a second NOR gate NOR2;
  • the NOR gate NOR1 and the second NOR gate NOR2 are both two-input NOR gates.
  • the input terminal of the first inverter N1 receives the even clock signal CLK_E, and the output terminal of the first inverter N1 is connected to the first input terminal of the first NOR gate NOR1.
  • the output terminal of the first NOR gate NOR1 is connected to the second input terminal C of the first self-shielding flip-flop 501 , and the second input terminal of the first NOR gate NOR1 is connected to the first output terminal Q of the second self-shielding flip-flop 502 .
  • the input terminal of the second inverter N2 receives the odd clock signal CLK_O, and the output terminal of the second inverter N2 is connected to the first input terminal of the second NOR gate NOR2.
  • the output terminal of the second NOR gate NOR2 is connected to the second input terminal C of the second self-shielding flip-flop 502 , and the second input terminal of the second NOR gate NOR2 is connected to the first output terminal Q of the first self-shielding flip-flop 501 .
  • the even clock signal CLK_E reaches the rising edge earlier than the odd clock signal CLK_O (as shown by the dotted arrow in Figure 13), that is, the even clock signal CLK_E becomes the first initial clock signal.
  • the first self-shielding flip-flop 501 is triggered by the first intermediate clock signal CLK_E1, registers the initial command signal CMD, and outputs the shift command signal CMD_E at its first output terminal Q to the second NOR gate NOR2. Two input terminals.
  • the shift command signal CMD_E includes a high-level pulse
  • the second intermediate clock signal CLK_O1 output by the second NOR gate NOR2 remains low, that is, odd
  • the clock signal CLK_O is masked for the duration d.
  • the second intermediate clock signal CLK_O1 will not generate a rising edge to trigger the second self-shielding flip-flop 502 to register the initial command signal CMD, and the CMD_O output by the first output terminal Q of the second self-shielding flip-flop 502 remains low. without including any pulses.
  • the second self-shielding flip-flop 502 is triggered by the second intermediate clock signal CLK_O1 and registers the initial command signal CMD, and the first self-shielding flip-flop 501 CMD_E output by an output terminal Q remains low without including any pulses.
  • the delay module 102 may include M-level second register units 203, where M is an integer greater than or equal to 2.
  • the second register unit 203 of each stage includes delay flip-flops 511 and 512, and both delay flip-flops 511 and 512 are D flip-flops.
  • the first input terminal D of the delay flip-flop 511 is connected to the first output terminal Q of the self-shielding flip-flop 501
  • the first input terminal D of the delay flip-flop 512 is connected to the self-shielding flip-flop.
  • the second input terminal C of the delay flip-flop 511 receives the even clock signal CLK_E
  • the second input terminal C of the delay flip-flop 512 receives the odd clock signal CLK_O.
  • M is greater than or equal to 2
  • the first input terminal D of the delay flip-flop 511 in the second register unit 203 of the i-th stage is connected to the first input terminal D of the delay flip-flop 511 in the second register unit 203 of the previous stage.
  • An output terminal Q, the first input terminal D of the delay flip-flop 512 in the second register unit 203 of the i-th stage is connected to the first output terminal Q, i of the delay flip-flop 512 in the second register unit 203 of the previous stage. Greater than 1 and less than or equal to M.
  • the delay module 102 also includes an OR gate 52, which is a two-input OR gate.
  • the first output terminals Q of the delay flip-flops 511 and 512 in the M-th second register unit 203 are connected to the two input terminals of the OR gate 52 in one-to-one correspondence.
  • the output terminal of the OR gate 52 serves as the output terminal of the delay module 102 and outputs the delay command signal CMD_SHIFT.
  • the initial command signal CMD is registered as the shift command signal CMD_E, so that the shift command signal CMD_E passes through the M-th level After the second register unit 203, it is delayed to the signal CMD_Em and input to the OR gate 52.
  • the waveforms of the initial command signal CMD, the shift command signal CMD_E and the signal CMD_Em are as shown in Figure 15.
  • the signal CMD_O output by the self-shielding flip-flop 502 will remain low and does not include any pulses. Therefore, after passing through the M-level second register unit 203, the delay flip-flop 512 in the M-th second register unit 203 The output signal CMD_Om is still low level and does not include any pulses.
  • the OR gate 52 receives the signal CMD_Em, and the other input terminal receives a continuous low level. Therefore, the delayed command signal CMD_SHIFT output by the OR gate 52 has the same waveform as the signal CMD_Em, and the delayed command signal
  • the effective pulse width of CMD_SHIFT is equal to the effective pulse width of the initial command signal CMD.
  • the first initial clock signal triggers the initial command signal register to obtain the shift command signal. If the NOR gate does not receive the first initial clock signal through the inverter, another divided clock will be generated according to the shift command signal.
  • Signal shielding allows the self-shielding module to only output a single shift command signal; furthermore, the delay module can delay a single shift command signal, thus avoiding errors caused by the simultaneous action of odd and even clock signals, ensuring The effective pulse width of the finally obtained delayed command signal is equal to the effective pulse width of the initial command signal, which improves the accuracy of signal processing.
  • the initial command signal is active at a high level, and the effective pulse width of the initial command signal is greater than or equal to the period length of each initial clock signal.
  • the initial command signal is a read command from the memory.
  • the initial command signal is low level in a normal state, and a control effect occurs when the initial command signal contains a high level pulse.
  • the effective pulse width of the initial command signal is greater than or equal to the period length of each initial clock signal. In this way, within the effective pulse width of the initial command signal, each initial clock signal can reach the trigger edge at least once, ensuring that the initial command signal always It can be registered and delayed by the delay circuit provided by the embodiment of the present disclosure.
  • the initial command signal may be a read command in the memory, that is, the initial command signal may be used to control the reading of data in the memory.
  • the embodiment of the present disclosure also provides a memory 80.
  • the memory 80 includes the delay circuit 10 provided in the previous embodiment.
  • the memory 80 shown in FIG. 18 may be a dynamic random access memory DRAM.
  • the memory 80 is electrically connected to the control module 90 , where the memory 80 meets the DDR4 specification and the control module 90 meets the DDR5 specification.
  • the memory 80 also includes a frequency dividing circuit 81 .
  • the memory 80 receives the standard clock signal from the control module 90 , divides the standard clock signal into an initial clock signal through the frequency dividing circuit 81 , and transmits the initial clock signal to the delay circuit 10 .
  • the memory 80 meets the DDR4 specification
  • the control module 90 meets the DDR5 specification
  • the clock signal frequency under the DDR5 specification is doubled compared to the clock signal frequency under the DDR4 specification. Therefore, the standard clock signal received by the memory 80 from the control module 90 meets the requirements of the DDR5 specification.
  • the delay circuit 10 can complete the delay of the initial command signal under the DDR4 specification. That is to say, the memory 80 can be compatible with the external control module 90 of the DDR5 standard under the DDR4 standard, which increases the usage range of the memory 80 .
  • the delay circuit 10 provided in the aforementioned embodiment can ensure that before and after delay The read command has the same effective pulse width, which improves the accuracy of signal processing.
  • Embodiments of the present disclosure provide a delay circuit and a memory.
  • the delay circuit includes: a self-shielding module and a delay module.
  • the self-shielding module is configured to receive an initial command signal and N initial clock signals, register the initial command signal according to the first initial clock signal that first triggers the initial command signal among the N initial clock signals, and shield the N initial clock signals. other N-1 second initial clock signals, and output N intermediate command signals, where N is an integer greater than or equal to 2; the N initial clock signals have the same frequency and different phases.
  • the delay module is electrically connected to the self-shielding module, and is configured to receive N intermediate command signals and N initial clock signals, and delay output of the N intermediate command signals to obtain a delayed command signal.
  • the delay circuit only controls the registration and delay of the command signal through the first initial clock signal, shielding the second initial clock signal, avoiding errors caused by the simultaneous action of N initial clock signals, and improving signal quality. Processing accuracy.

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Abstract

本公开实施例公开了一种延时电路和存储器，包括：自屏蔽模块和延时模块。自屏蔽模块，被配置为接收初始命令信号和N个初始时钟信号，根据N个初始时钟信号中最先触发初始命令信号的第一初始时钟信号，对初始命令信号寄存，屏蔽N个初始时钟信号中其他N-1个第二初始时钟信号，并输出N个中间命令信号，其中，N为大于等于2的整数；N个初始时钟信号的频率相同，且相位不同；延时模块，与自屏蔽模块电连接，被配置为接收N个中间命令信号和N个初始时钟信号，对N个中间命令信号进行延时输出，得到延时命令信号。本公开可以提高信号处理的准确度。

Description

一种延时电路和存储器
相关申请的交叉引用
本公开基于申请号为202210557966.X、申请日为2022年05月19日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及集成电路领域，尤其涉及一种延时电路和存储器。
背景技术
在芯片中，时钟信号的频率是芯片性能的重要指标之一。随着集成电路技术的不断发展，芯片中时钟信号的频率也在不断提升，例如，DDR5规格下的时钟信号频率相比DDR4规格下的时钟信号频率提升了一倍。然而，信号频率越高，其抗干扰能力越差，从而，时钟信号频率的提升，也使得借由时钟信号进行的信号处理有更大的出错概率。
因此，在部分信号处理的过程中，例如对命令信号的寄存和延时，可以采用分频时钟信号。由于分频时钟信号的频率低于时钟信号的频率，从而能够降低出错概率。
发明内容
有鉴于此，本公开实施例提供了一种延时电路和存储器，能够提高信号处理的准确度。
本公开实施例的技术方案是这样实现的：
本公开实施例提供了一种延时电路，包括：
自屏蔽模块，被配置为接收初始命令信号和N个初始时钟信号，根据N个所述初始时钟信号中最先触发所述初始命令信号的第一初始时钟信号，对所述初始命令信号寄存，屏蔽N个所述初始时钟信号中其他N-1个第二初始时钟信号，并输出N个中间命令信号，其中，N为大于等于2的整数；N个所述初始时钟信号的频率相同，且相位不同；
延时模块，与所述自屏蔽模块电连接，被配置为接收N个所述中间命令信号和N个所述初始时钟信号，对N个所述中间命令信号进行延时输出，得到延时命令信号。
上述方案中，所述自屏蔽模块包括：屏蔽单元，被配置为接收N个所述初始时钟信号，并输出N个中间时钟信号；其中，N个所述中间时钟信号包括一个有效的第一中间时钟信号和N-1个无效的第二中间时钟信号；寄存单元，电连接所述屏蔽单元，被配置为接收所述初始命令信号和N个所述中间时钟信号，根据所述第一中间时钟信号对所述初始命令信号寄存，得到并输出N个所述中间命令信号。
上述方案中，所述寄存单元包括：N个自屏蔽触发器；N个所述自屏蔽触发器均为D触发器；N个所述中间命令信号包括一个有效的第一中间命令信号和N-1个无效的第二中间命令信号；N个所述自屏蔽触发器的第一输入端均接收所述初始命令信号，N个所述自屏蔽触发器的第二输入端均连接所述屏蔽单元的输出端；N个所述自屏蔽触发器中接收所述第一中间时钟信号的第一自屏蔽触发器，根据所述第一中间时钟信号对所述初始命令信号寄存，在其第一输出端输出所述第一中间命令信号；N个所述自屏蔽触发器中其他N-1个第二自屏蔽触发器，一一对应接收N-1个所述第二中间时钟信号，在其第一输出端一一对应输出N-1个所述第二中间命令信号。
上述方案中，所述屏蔽单元包括：N个与门，所述与门均包括一个第一输入端和N-1个第二输入端；N个所述与门的第一输入端一一对应接收N个所述初始时钟信号，N个所述与门的输出端一一对应连接N个所述自屏蔽触发器的第二输入端；每个与门的N-1个第 二输入端一一对应连接其对应的自屏蔽触发器外的N-1个其他自屏蔽触发器的第二输出端。
上述方案中，所述屏蔽单元包括：N个反相器和N个或非门；所述或非门均包括第一输入端和N-1个第二输入端；N个所述反相器的输入端一一对应接收N个所述初始时钟信号，N个所述反相器的输出端一一对应连接N个所述或非门的第一输入端，N个所述或非门的输出端一一对应连接N个所述自屏蔽触发器的第二输入端；每个或非门的N-1个第二输入端一一对应连接其对应的自屏蔽触发器外的N-1个其他自屏蔽触发器的第一输出端。
上述方案中，所述延时模块包括：M级第二寄存单元，M为大于等于2的整数；每级第二寄存单元包括：N个延时触发器；所述N个延时触发器均为D触发器；每级第二寄存单元中的N个所述延时触发器，其第二输入端一一对应接收N个所述初始时钟信号；第1级第二寄存单元中的N个延时触发器，其第一输入端一一对应连接N个所述自屏蔽触发器的第一输出端；第i级第二寄存单元中的N个延时触发器，其第一输入端一一对应连接上一级第二寄存单元中N个延时触发器的输出端，i大于1且小于等于M。
上述方案中，M＝(CL-A)/N，其中，CL为最大的延时周期数，A为命令预操作对应的周期数。
上述方案中，所述延时模块还包括：或门，所述或门包括N个输入端；第M级第二寄存单元中的N个延时触发器，其第一输出端一一对应连接所述或门的N个输入端；所述或门的输出端输出所述延时命令信号。
上述方案中，N＝2，所述N个初始时钟信号为奇偶分频时钟信号，所述奇偶分频时钟信号包括：奇时钟信号和偶时钟信号；所述奇时钟信号和所述偶时钟信号频率相同，且相位相反。
上述方案中，所述自屏蔽模块包括：屏蔽单元和寄存单元；所述寄存单元包括：第一自屏蔽触发器和第二自屏蔽触发器；所述第一自屏蔽触发器和所述第二自屏蔽触发器均为D触发器；所述第一自屏蔽触发器的第一输入端和所述第二自屏蔽触发器的第一输入端均接收所述命令信号。
上述方案中，所述屏蔽单元包括：第一与门和第二与门；所述第一与门和所述第二与门均为两输入端与门；所述第一与门的第一输入端接收所述偶时钟信号，所述第一与门的输出端连接所述第一自屏蔽触发器的第二输入端，所述第一与门的第二输入端连接所述第二自屏蔽触发器的第二输出端；所述第二与门的第一输入端接收所述奇时钟信号，所述第二与门的输出端连接所述第二自屏蔽触发器的第二输入端，所述第二与门的第二输入端连接所述第一自屏蔽触发器的第二输出端。
上述方案中，所述屏蔽单元包括：第一反相器、第二反相器、第一或非门和第二或非门；所述第一或非门和所述第二或非门均为两输入端或非门；所述第一反相器的输入端接收所述偶时钟信号，所述第一反相器的输出端连接所述第一或非门的第一输入端；所述第一或非门的输出端连接所述第一自屏蔽触发器的第二输入端，所述第一或非门的第二输入端连接所述第二自屏蔽触发器的第一输出端；所述第二反相器的输入端接收所述奇时钟信号，所述第二反相器的输出端连接所述第二或非门的第一输入端；所述第二或非门的输出端连接所述第二自屏蔽触发器的第二输入端，所述第二或非门的第二输入端连接所述第一自屏蔽触发器的第一输出端。
本公开实施例还提供了一种存储器，其特征在于，所述存储器包括上述方案中的延时电路。
上述方案中，所述存储器电连接控制模组，其中，所述存储器满足DDR4规格，所述控制模组满足DDR5规格；所述存储器还包括分频电路；所述存储器从所述控制模组接收标准时钟信号，通过所述分频电路将所述标准时钟信号分频为初始时钟信号，并将所述初始时钟信号传输到所述延时电路。
由此可见，本公开实施例提供了一种延时电路和存储器，包括：自屏蔽模块和延时模 块。自屏蔽模块，被配置为接收初始命令信号和N个初始时钟信号，根据N个初始时钟信号中最先触发初始命令信号的第一初始时钟信号，对初始命令信号寄存，屏蔽N个初始时钟信号中其他N-1个第二初始时钟信号，并输出N个中间命令信号，其中，N为大于等于2的整数；N个初始时钟信号的频率相同，且相位不同。延时模块，与自屏蔽模块电连接，被配置为接收N个中间命令信号和N个初始时钟信号，对N个中间命令信号进行延时输出，得到延时命令信号。这样，延时电路仅通过第一初始时钟信号控制命令信号的寄存和延时，屏蔽第二初始时钟信号，避免了N个初始时钟信号同时作用下带来的误差，提高了信号处理的准确度。
附图说明
图1是本公开实施例提供的延时电路的结构示意图一；
图2是本公开实施例提供的延时电路的信号示意图一；
图3是本公开实施例提供的延时电路的结构示意图二；
图4是本公开实施例提供的延时电路的结构示意图三；
图5是本公开实施例提供的延时电路的结构示意图四；
图6是本公开实施例提供的延时电路的信号示意图二；
图7是本公开实施例提供的延时电路的结构示意图五；
图8是本公开实施例提供的延时电路的结构示意图六；
图9是本公开实施例提供的延时电路的信号示意图三；
图10是本公开实施例提供的延时电路的信号示意图四；
图11是本公开实施例提供的延时电路的结构示意图七；
图12是本公开实施例提供的延时电路的结构示意图八；
图13是本公开实施例提供的延时电路的信号示意图五；
图14是本公开实施例提供的延时电路的结构示意图九；
图15是本公开实施例提供的延时电路的信号示意图六；
图16是本公开实施例提供的延时电路的结构示意图十；
图17是本公开实施例提供的延时电路的结构示意图十一；
图18是本公开实施例提供的存储器的结构示意图一；
图19是本公开实施例提供的存储器的结构示意图二。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面结合附图和实施例对本公开的技术方案进一步详细阐述，所描述的实施例不应视为对本公开的限制，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
如果申请文件中出现“第一/第二”的类似描述则增加以下的说明，在以下的描述中，所涉及的术语“第一/第二/第三”仅仅是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一/第二/第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
图1是本公开实施例提供的一种延时电路的结构示意图，如图1所示，本公开实施例提供了一种延时电路10，包括：自屏蔽模块101和延时模块102。自屏蔽模块101被配置 为接收初始命令信号CMD和N个初始时钟信号CLK<1:N>(即初始时钟信号CLK<1>～CLK<N>)，根据N个初始时钟信号CLK<1:N>中最先触发初始命令信号CMD的第一初始时钟信号，对初始命令信号CMD寄存，屏蔽N个初始时钟信号CLK<1:N>中其他N-1个第二初始时钟信号的作用，并输出N个中间命令信号CMD_i(i大于等于1，且小于等于N)，其中，N为大于等于2的整数；N个初始时钟信号的频率相同，且相位不同。
延时模块102与所述自屏蔽模块101电连接，被配置为接收N个中间命令信号CMD_i和N个初始时钟信号CLK<1:N>，根据N个初始时钟信号CLK<1:N>对N个中间命令信号进行延时输出，得到延时命令信号CMD_SHIFT。
本公开实施例中，初始时钟信号可以是分频时钟信号。分频时钟信号是对芯片中的时钟信号进行分频后而得到的，其周期与时钟信号的周期呈倍数关系；例如，四分频时钟信号的周期是时钟信号周期的4倍，也就是说，四分频时钟信号的频率是时钟信号频率的四分之一；又如，奇偶分频时钟信号(即二分频时钟信号)的周期是时钟信号周期的2倍，也就是说，奇偶分频时钟信号的频率是时钟信号频率的二分之一。在使用时，可以将多个不同相位的分频时钟信号同时使用，以满足各种不同的需求。
需要说明的是，初始命令信号可以为高电平有效或者低电平有效，例如，在存储器中，通常“读命令”为高电平有效，而“写命令”为低电平有效，本公开在此不做限制。图2示出的命令信号CMD为高电平有效，如图2所示，在通常状态下初始命令信号CMD为低电平，当初始命令信号CMD包含高电平脉冲时产生控制作用。
本公开实施例中，在自屏蔽模块101中，初始命令信号CMD受触发而寄存，由于N个初始时钟信号CLK<1:N>的相位不同，因此，N个初始时钟信号CLK<1:N>达到初始命令信号CMD对应的触发沿的时刻并不相同。以图2为例，初始时钟信号CLK<1>、CLK<2>、CLK<3>和CLK<4>为时钟信号CLK的四分频信号，其相位依次相差90°，同时，初始命令信号CMD为上升沿触发。则在初始命令信号CMD的有效脉冲宽度中，初始时钟信号CLK<1>最先到达上升沿(如图2中虚线箭头所示)，也就是说，初始时钟信号CLK<1>最先达到初始命令信号CMD对应的触发沿，成为第一初始时钟信号。
需要说明的是，初始命令信号CMD也可以被设置为下降沿触发，则在初始命令信号CMD的有效脉冲宽度中，最先达到下降沿的初始时钟信号成为第一初始时钟信号，在此不做限制。
本公开实施例中，自屏蔽模块101可以屏蔽N个初始时钟信号CLK<1:N>中除第一初始时钟信号外的第二初始时钟信号，这里，屏蔽第二初始时钟信号，意味着第二初始时钟信号不会触发初始命令信号CMD寄存。
本公开实施例中，命令信号的有效脉冲宽度大于或等于每个初始时钟信号的周期长度，这样，在命令信号的有效脉冲宽度中，每个初始时钟信号能够至少一次到达触发沿，保证了命令信号总是能够被本公开实施例提供的延时电路进行寄存和延时。
可以理解的是，本公开提供的延时电路仅通过第一初始时钟信号控制命令信号的寄存和延时，屏蔽第二初始时钟信号，避免了N个初始时钟信号同时作用下带来的误差，提高了信号处理的准确度。同时，由于本公开提供的延时电路是根据N个初始时钟信号中最先触发命令信号的第一初始时钟信号，对命令信号进行寄存的，这样，保证了命令信号被寄存而产生的延时是最短的，即缩短了延时命令信号与命令信号之间的相对延时。
在申请的一些实施例中，如图3所示，自屏蔽模块101包括：屏蔽单元201和寄存单元202。屏蔽单元201被配置为接收N个初始时钟信号CLK<1:N>，屏蔽N个初始时钟信号CLK<1:N>中其他N-1个第二初始时钟信号的作用，并输出N个中间时钟信号/CLK<1:N>(即中间时钟信号/CLK<1>～/CLK<N>)。其中，N个中间时钟信号/CLK<1:N>包括一个有效的第一中间时钟信号和N-1个无效的第二中间时钟信号。
寄存单元202电连接屏蔽单元201，被配置为接收初始命令信号CMD和N个中间时 钟信号/CLK<1:N>，根据第一中间时钟信号对初始命令信号CMD寄存，得到并输出N个中间命令信号CMD_i。
本公开实施例中，第一中间时钟信号为有效的信号，即第一中间时钟信号能够触发对初始命令信号CMD的寄存；第一中间时钟信号与第一初始时钟信号波形相同，也即第一初始时钟信号触发了对初始命令信号CMD的寄存。而N-1个第二中间时钟信号为无效的信号，即N-1个第二中间时钟信号均不能够触发对初始命令信号CMD的寄存；N-1个第二中间时钟信号对应N-1个第二初始时钟信号，也即N-1个第二初始时钟信号的作用被屏蔽。
可以理解的是，屏蔽单元屏蔽N-1个第二初始时钟信号的作用，寄存单元仅通过第一初始时钟信号控制命令信号的寄存，这样，避免了N个初始时钟信号同时作用下带来的误差，提高了信号处理的准确度。
在申请的一些实施例中，如图4所示，寄存单元202包括：N个自屏蔽触发器30，N个自屏蔽触发器30均为D触发器。N个中间命令信号CMD_1～CMD_N包括一个有效的第一中间命令信号和N-1个无效的第二中间命令信号。
N个自屏蔽触发器30的第一输入端D均接收初始命令信号CMD，N个自屏蔽触发器30的第二输入端C均连接屏蔽单元201的输出端。N个自屏蔽触发器30中接收第一中间时钟信号的第一自屏蔽触发器，根据第一中间时钟信号对初始命令信号寄存，在其第一输出端Q输出第一中间命令信号。N个自屏蔽触发器30中其他N-1个第二自屏蔽触发器，一一对应接收N-1个第二中间时钟信号，在其第一输出端Q一一对应输出N-1个第二中间命令信号。
本公开实施例中，第一中间命令信号由第一中间时钟信号触发而被输出，第一中间命令信号中包含了脉冲，为有效的信号。由于N-1个第二初始时钟信号的作用被屏蔽，N-1个第二中间命令信号并非受到触发而被输出的脉冲信号，因此，N-1个第二中间命令信号中不包含脉冲，为无效的信号。
在申请的一些实施例中，屏蔽单元包括：N个与门；N个与门均为N输入端与门，每个与门均包括第一输入端和N-1个第二输入端。N个与门的第一输入端一一对应接收N个初始时钟信号，N个与门的输出端一一对应连接N个自屏蔽触发器的第二输入端。每个与门的N-1个第二输入端一一对应连接其对应的自屏蔽触发器外的N-1个其他自屏蔽触发器的第二输出端。
以图5为例，屏蔽单元201可以包括4个与门，分别为与门401、与门402、与门403和与门404，这4个与门均为4输入端与门，每个与门均包括第一输入端和3个第二输入端。4个与门的第一输入端一一对应接收4个初始时钟信号，也就是说，与门401的第一输入端接收初始时钟信号CLK<1>，与门402的第一输入端接收初始时钟信号CLK<2>，与门403的第一输入端接收初始时钟信号CLK<3>，与门404的第一输入端接收初始时钟信号CLK<4>。
4个与门的输出端一一对应连接4个自屏蔽触发器的第二输入端C，也就是说，与门401的输出端连接自屏蔽触发器301的第二输入端C，与门402的输出端连接自屏蔽触发器302的第二输入端C，与门403的输出端连接自屏蔽触发器303的第二输入端C，与门404的输出端连接自屏蔽触发器304的第二输入端C，其中，与门401的输出端传输中间时钟信号/CLK<1>到自屏蔽触发器301的第二输入端C，与门402的输出端传输中间时钟信号/CLK<2>到自屏蔽触发器302的第二输入端C，与门403的输出端传输中间时钟信号/CLK<3>到自屏蔽触发器303的第二输入端C，与门404的输出端传输中间时钟信号/CLK<4>到自屏蔽触发器304的第二输入端C。
每个与门的3个第二输入端一一对应连接其对应的自屏蔽触发器外的3个其他自屏蔽触发器的第二输出端
Figure PCTCN2022100189-appb-000001
也就是说，与门401的3个第二输入端一一对应连接自屏蔽触发 器302的第二输出端
Figure PCTCN2022100189-appb-000002
自屏蔽触发器303的第二输出端
Figure PCTCN2022100189-appb-000003
和自屏蔽触发器304的第二输出端
Figure PCTCN2022100189-appb-000004
与门402的3个第二输入端一一对应连接自屏蔽触发器301的第二输出端
Figure PCTCN2022100189-appb-000005
自屏蔽触发器303的第二输出端
Figure PCTCN2022100189-appb-000006
和自屏蔽触发器304的第二输出端
Figure PCTCN2022100189-appb-000007
与门403的3个第二输入端一一对应连接自屏蔽触发器301的第二输出端
Figure PCTCN2022100189-appb-000008
自屏蔽触发器302的第二输出端
Figure PCTCN2022100189-appb-000009
和自屏蔽触发器304的第二输出端
Figure PCTCN2022100189-appb-000010
与门404的3个第二输入端一一对应连接自屏蔽触发器301的第二输出端
Figure PCTCN2022100189-appb-000011
自屏蔽触发器302的第二输出端
Figure PCTCN2022100189-appb-000012
和自屏蔽触发器303的第二输出端
Figure PCTCN2022100189-appb-000013
本公开实施例中，结合图5和图6，将图6示出的初始命令信号CMD、初始时钟信号CLK<1>、CLK<2>、CLK<3>和CLK<4>，对应输入图5所示电路。
在初始命令信号CMD未被触发而寄存的情况下，自屏蔽触发器301、302、303和304的第一输出端Q输出的CMD_1、CMD_2、CMD_3和CMD_4均为低电平(CMD_2、CMD_3和CMD_4在图6中未示出)，则与门401、402、403和404中的每个，其3个第二输入端均接收到高电平。在该情况下，与门401、402、403和404不会产生屏蔽效果，中间时钟信号/CLK<1>和初始时钟信号CLK<1>波形相同，中间时钟信号/CLK<2>和初始时钟信号CLK<2>波形相同，中间时钟信号/CLK<3>和初始时钟信号CLK<3>波形相同，中间时钟信号/CLK<4>和初始时钟信号CLK<4>波形相同。
在初始命令信号CMD的有效脉冲宽度a中，初始时钟信号CLK<1>最先到达上升沿，即初始时钟信号CLK<1>成为第一初始时钟信号。此时，自屏蔽触发器301受到中间时钟信号/CLK<1>的触发，将初始命令信号CMD寄存，并在其第一输出端Q输出第一中间命令信号CMD_1，同时，将第一中间命令信号CMD_1的反相信号传输到与门402、403和404，即中间时钟信号/CLK<1>成为有效的第一中间时钟信号。由于第一中间命令信号CMD_1的反相信号包括了低电平脉冲，则在该低电平脉冲的持续时间b内，与门402、403和404输出的中间时钟信号/CLK<2>、/CLK<3>和/CLK<4>均保持低电平，也就是说，在持续时间b内，中间时钟信号/CLK<2>、/CLK<3>和/CLK<4>均被屏蔽，即中间时钟信号/CLK<2>、/CLK<3>和/CLK<4>均为无效的第二中间时钟信号。进而，在初始命令信号CMD的有效脉冲宽度a中，中间时钟信号/CLK<2>、/CLK<3>和/CLK<4>不会产生上升沿来触发自屏蔽触发器302、303和304将初始命令信号CMD寄存，自屏蔽触发器302、303和304的第一输出端Q所输出的CMD_2、CMD_3和CMD_4保持低电平而不包括任何脉冲(图6中未示出)。
可以理解的是，第一初始时钟信号触发初始命令信号寄存，得到移位命令信号，进而，未接收第一初始时钟信号的N-1个与门，则根据移位命令信号将第二初始时钟信号屏蔽，从而，避免了N个初始时钟信号同时作用下带来的误差，提高了信号处理的准确度。
在申请的一些实施例中，屏蔽单元包括：N个反相器和N个或非门；N个或非门均为N输入端或非门，每个或非门均包括第一输入端和N-1个第二输入端。N个反相器的输入端一一对应接收N个初始时钟信号，N个反相器的输出端一一对应连接N个或非门的第一输入端，N个或非门的输出端一一对应连接N个自屏蔽触发器的第二输入端。每个或非门的N-1个第二输入端一一对应连接其对应的自屏蔽触发器外的N-1个其他自屏蔽触发器的第一输出端。
以图7为例，屏蔽单元201可以包括：4个反相器411、412、413和414，4个或非门，分别为反相器411、反相器412、反相器413、反相器414、或非门421、或非门422、或非门423和或非门424，这4个或非门均为4输入端或非门，每个或非门均包括第一输入端和3个第二输入端。4个反相器的输入端一一对应接收4个初始时钟信号，也就是说，反相器411的输入端接收初始时钟信号CLK<1>，反相器412的输入端接收初始时钟信号CLK<2>，反相器413的输入端接收初始时钟信号CLK<3>，反相器414的输入端接收初 始时钟信号CLK<4>。
4个反相器的输出端一一对应连接4个或非门的第一输入端，也就是说，反相器411的输出端连接或非门421的第一输入端，反相器412的输出端连接或非门422的第一输入端，反相器413的输出端连接或非门423的第一输入端，反相器414的输出端连接或非门424的第一输入端。
4个或非门的输出端一一对应连接4个自屏蔽触发器的第二输入端C，也就是说，或非门421的输出端连接自屏蔽触发器301的第二输入端C，或非门422的输出端连接自屏蔽触发器302的第二输入端C，或非门423的输出端连接自屏蔽触发器303的第二输入端C，或非门424的输出端连接自屏蔽触发器304的第二输入端C，其中，或非门421的输出端传输中间时钟信号/CLK<1>到自屏蔽触发器301的第二输入端C，或非门422的输出端传输中间时钟信号/CLK<2>到自屏蔽触发器302的第二输入端C，或非门423的输出端传输中间时钟信号/CLK<3>到自屏蔽触发器303的第二输入端C，或非门424的输出端传输中间时钟信号/CLK<4>到自屏蔽触发器304的第二输入端C。
每个或非门的3个第二输入端一一对应连接其对应的自屏蔽触发器外的3个其他自屏蔽触发器的第一输出端Q，也就是说，或非门421的3个第二输入端一一对应连接自屏蔽触发器302的第一输出端Q、自屏蔽触发器303的第一输出端Q和自屏蔽触发器304的第一输出端Q；或非门422的3个第二输入端一一对应连接自屏蔽触发器301的第一输出端Q、自屏蔽触发器303的第一输出端Q和自屏蔽触发器304的第一输出端Q；或非门423的3个第二输入端一一对应连接自屏蔽触发器301的第一输出端Q、自屏蔽触发器302的第一输出端Q和自屏蔽触发器304的第一输出端Q；或非门424的3个第二输入端一一对应连接自屏蔽触发器301的第一输出端Q、自屏蔽触发器302的第一输出端Q和自屏蔽触发器303的第一输出端Q。
本公开实施例中，结合图6和图7，将图6示出的初始命令信号CMD、初始时钟信号CLK<1>、CLK<2>、CLK<3>和CLK<4>，对应输入图7所示电路。
在初始命令信号CMD未被触发而寄存的情况下，自屏蔽触发器301、302、303和304的第一输出端Q输出的CMD_1、CMD_2、CMD_3和CMD_4均为低电平(CMD_2、CMD_3和CMD_4在图6中未示出)，则或非门421、422、423和424中的每个，其3个第二输入端均接收到低电平。在该情况下，或非门421、422、423和424不会产生屏蔽效果，中间时钟信号/CLK<1>和初始时钟信号CLK<1>波形相同，中间时钟信号/CLK<2>和初始时钟信号CLK<2>波形相同，中间时钟信号/CLK<3>和初始时钟信号CLK<3>波形相同，中间时钟信号/CLK<4>和初始时钟信号CLK<4>波形相同。
在初始命令信号CMD的有效脉冲宽度a中，初始时钟信号CLK<1>最先到达上升沿，即初始时钟信号CLK<1>成为第一初始时钟信号。此时，自屏蔽触发器301受到中间时钟信号/CLK<1>的触发，将初始命令信号CMD寄存，并在其第一输出端Q输出第一中间命令信号CMD_1，同时，将第一中间命令信号CMD_1传输到或非门422、423和424，即中间时钟信号/CLK<1>成为有效的第一中间时钟信号。由于第一中间命令信号CMD_1包括了高电平脉冲，则在该高电平脉冲的持续时间b内，或非门422、423和424输出的中间时钟信号/CLK<2>、/CLK<3>和/CLK<4>均保持低电平，也就是说，在持续时间b内，中间时钟信号/CLK<2>、/CLK<3>和/CLK<4>均被屏蔽，即中间时钟信号/CLK<2>、/CLK<3>和/CLK<4>均为无效的第二中间时钟信号。进而，在初始命令信号CMD的有效脉冲宽度a中，中间时钟信号/CLK<2>、/CLK<3>和/CLK<4>不会产生上升沿来触发自屏蔽触发器302、303和304将初始命令信号CMD寄存，自屏蔽触发器302、303和304的第一输出端Q所输出的CMD_2、CMD_3和CMD_4保持低电平而不包括任何脉冲(图6中未示出)。
可以理解的是，第一初始时钟信号触发初始命令信号寄存，得到移位命令信号，进而，未通过反相器接收第一初始时钟信号的N-1个或非门，则根据移位命令信号将第二初始时 钟信号屏蔽，从而避免了N个初始时钟信号同时作用下带来的误差，提高了信号处理的准确度。
在本公开的一些实施例中，如图8所示，延时模块102包括M级第二寄存单元203，M为大于等于2的整数。每级第二寄存单元203包括N个延时触发器31，N个延时触发器31均为D触发器。第1级第二寄存单元203中的N个延时触发器31，其第一输入端D一一对应连接N个自屏蔽触发器30的第一输出端Q。每级第二寄存单元203中的N个延时触发器31，其第二输入端C一一对应接收N个初始时钟信号CLK<1>、CLK<2>…CLK<N>(即CLK<1:N>)。
本公开实施例中，在M大于等于2的情况下，第i级第二寄存单元203中的N个延时触发器31，其第一输入端D一一对应连接上一级第二寄存单元203中N个延时触发器31的第一输出端Q，i大于1且小于等于M。如图8所示例，第2级第二寄存单元203中的N个延时触发器31，其第一输入端D一一对应连接第1级第二寄存单元203中N个延时触发器31的第一输出端Q；第M级第二寄存单元203中的N个延时触发器31，其第一输入端D一一对应连接第M-1级第二寄存单元203中N个延时触发器31的第一输出端Q。
本公开实施例中，第二寄存单元203的级数M＝(CL-A)/N，其中，CL为最大的延时周期数，A为命令预操作对应的周期数。CL和A均满足集成电路设计标准的要求。
这里，CL和A对应的时钟周期可以是外部时钟的周期，即初始时钟信号的周期的N分之一。命令预操作包括了预写和预读，从而，A＝a1+a2，当初始命令信号为“读命令”时，a1对应的是preamble(预取)的时钟周期，a2对应的是offset(时钟信号的偏差余量)的时钟周期。
本公开实施例中，如图8所示，延时模块102还包括或门32，或门32包括N个输入端。第M级第二寄存单元203中的N个延时触发器31，其第一输出端Q一一对应连接或门32的N个输入端。或门32的输出端作为延时模块102的输出端，输出延时命令信号CMD_SHIFT。
本公开实施例中，结合图8和图9，若初始时钟信号CLK<1>成为第一初始时钟信号，则初始命令信号CMD被寄存为第一中间命令信号CMD_1，从而，第一中间命令信号CMD_1经过M级第二寄存单元203后，被延时为信号CMD_1m，并被输入到或门32，初始命令信号CMD、第一中间命令信号CMD_1和信号CMD_1m的波形如图9所示。同时，第二中间命令信号CMD_2至CMD_N会保持低电平，不包括任何脉冲，从而，在经过M级第二寄存单元203后，第二中间命令信号CMD_2至CMD_N对应的第M级第二寄存单元203中的延时触发器31，其第一输出端Q输出的仍然为低电平，不包括任何脉冲。这样，或门32的一个输入端接收到信号CMD_1m，第二输入端接收到持续的低电平，因此，或门32输出的延时命令信号CMD_SHIFT与信号CMD_1m具有相同的波形，延时命令信号CMD_SHIFT的有效脉冲宽度与初始命令信号CMD的有效脉冲宽度相等。
可以理解的是，自屏蔽模块屏蔽了第二初始时钟信号的作用，仅输出了单一的移位命令信号，进而，延时模块能够进对单一的移位命令信号进行延时，从而，保证了最终得到的延时命令信号的有效脉冲宽度与初始命令信号的有效脉冲宽度相等，提高了信号处理的准确度。
在本公开的一些实施例中，N＝2，N个初始时钟信号为奇偶分频时钟信号，如图10所示，奇偶分频时钟信号包括：奇时钟信号CLK_O和偶时钟信号CLK_E。奇时钟信号CLK_O和偶时钟信号CLK_E频率相同，且相位相反。奇时钟信号CLK_O和偶时钟信号CLK_E是时钟信号CLK的二分频信号，它们的周期是时钟信号CLK的周期的2倍，它们的频率是时钟信号CLK的频率的二分之一。
在本公开的一些实施例中，如图11所示，自屏蔽模块101包括：屏蔽单元201和寄存单元202，其中，寄存单元202包括：第一自屏蔽触发器501和第二自屏蔽触发器502。 结合图10和图11，第一自屏蔽触发器501和第二自屏蔽触发器502均为D触发器，第一自屏蔽触发器501的第一输入端D和第二自屏蔽触发器502的第一输入端D均接收初始命令信号CMD；屏蔽单元201分别接收奇时钟信号CLK_O和偶时钟信号CLK_E，并分别连接到第一自屏蔽触发器501的第二输入端C和第二自屏蔽触发器502的第二输入端C。
在本公开的一些实施例中，如图12所示，屏蔽单元101包括：第一与门A1和第二与门A2，第一与门A1和第二与门A2均为两输入端与门。第一与门A1的第一输入端接收偶时钟信号CLK_E，第一与门A1的输出端连接第一自屏蔽触发器501的第二输入端C，第一与门A1的第二输入端连接第二自屏蔽触发器502的第二输出端
Figure PCTCN2022100189-appb-000014
第一与门A1输出中间时钟信号CLK_E1。第二与门A2的第一输入端接收奇时钟信号CLK_O，第二与门A2的输出端连接第二自屏蔽触发器502的第二输入端C，第二与门A2的第二输入端连接第一自屏蔽触发器501的第二输出端
Figure PCTCN2022100189-appb-000015
第二与门A2输出中间时钟信号CLK_O1。
结合图12和图13，在初始命令信号CMD未被触发而寄存的情况下，第一自屏蔽触发器501的第一输出端Q输出的CMD_E和第二自屏蔽触发器502的第一输出端Q输出的CMD_O均为低电平，则第二与门A2的第二输入端和第一与门A1的第二输入端均接收到高电平。在该情况下，第一与门A1和第二与门A2不会产生屏蔽效果，中间时钟信号CLK_E1和偶时钟信号CLK_E波形相同，中间时钟信号CLK_O1和奇时钟信号CLK_O波形相同。
在初始命令信号CMD的有效脉冲宽度c中，偶时钟信号CLK_E比奇时钟信号CLK_O更先到达上升沿(如图13中虚线箭头所示)，即偶时钟信号CLK_E成为第一初始时钟信号。此时，第一自屏蔽触发器501受到中间时钟信号CLK_E1的触发，将初始命令信号CMD寄存，并在其第一输出端Q输出移位命令信号CMD_E，同时，将移位命令信号CMD_E的反相信号输出到第二与门A2的第二输入端。由于移位命令信号CMD_E的反相信号包括了低电平脉冲，则在该低电平脉冲的持续时间d内，第二与门A2输出的中间时钟信号CLK_O1保持低电平，也就是说，第二与门A2在持续时间d内将奇时钟信号CLK_O屏蔽。进而，中间时钟信号CLK_O1不会产生上升沿来触发第二自屏蔽触发器502将初始命令信号CMD寄存，第二自屏蔽触发器502的第一输出端Q所输出的CMD_O保持低电平而不包括任何脉冲。
相应的，若奇时钟信号CLK_O成为第一初始时钟信号，则第二自屏蔽触发器502受到中间时钟信号CLK_O1的触发，将初始命令信号CMD寄存，而第一自屏蔽触发器501的第一输出端Q所输出的CMD_E保持低电平而不包括任何脉冲。
本公开实施例中，如图14所示，延时模块102可以包括M级第二寄存单元203，M为大于等于2的整数。每级第二寄存单元203包括延时触发器511和512，延时触发器511和512均为D触发器。第1级第二寄存单元203中，延时触发器511的第一输入端D连接自屏蔽触发器501的第一输出端Q，延时触发器512的第一输入端D连接自屏蔽触发器502的第一输出端Q。每级第二寄存单元203中，延时触发器511的第二输入端C接收偶时钟信号CLK_E，延时触发器512的第二输入端C接收奇时钟信号CLK_O。其中，在M大于等于2的情况下，第i级第二寄存单元203中的延时触发器511的第一输入端D连接上一级第二寄存单元203中的延时触发器511的第一输出端Q，第i级第二寄存单元203中的延时触发器512的第一输入端D连接上一级第二寄存单元203中的延时触发器512的第一输出端Q，i大于1且小于等于M。
如图14所示，延时模块102还包括或门52，或门52为二输入端或门。第M级第二寄存单元203中的延时触发器511和512，其第一输出端Q一一对应连接或门52的两个输入端。或门52的输出端作为延时模块102的输出端，输出延时命令信号CMD_SHIFT。
本公开实施例中，结合图14和图15，若偶时钟信号CLK_E成为第一初始时钟信号，则初始命令信号CMD被寄存为移位命令信号CMD_E，从而，移位命令信号CMD_E经过 M级第二寄存单元203后，被延时为信号CMD_Em，并被输入到或门52，初始命令信号CMD、移位命令信号CMD_E和信号CMD_Em的波形如图15所示。同时，自屏蔽触发器502输出的信号CMD_O会保持低电平，不包括任何脉冲，从而，在经过M级第二寄存单元203后，第M级第二寄存单元203中的延时触发器512输出的信号CMD_Om仍然为低电平，不包括任何脉冲。这样，或门52的一个输入端接收到信号CMD_Em，另一个输入端接收到持续的低电平，因此，或门52输出的延时命令信号CMD_SHIFT与信号CMD_Em具有相同的波形，延时命令信号CMD_SHIFT的有效脉冲宽度与初始命令信号CMD的有效脉冲宽度相等。
可以理解的是，第一初始时钟信号触发初始命令信号寄存，得到移位命令信号，未接收第一初始时钟信号的与门，则根据移位命令信号将另一个分频时钟信号屏蔽，使得自屏蔽模块仅输出单一的移位命令信号；进而，延时模块能够进对单一的移位命令信号进行延时，从而，避免了奇偶时钟信号同时作用下带来的误差，保证了最终得到的延时命令信号的有效脉冲宽度与初始命令信号的有效脉冲宽度相等，提高了信号处理的准确度。
在本公开的一些实施例中，如图16所示，屏蔽单元101包括：第一反相器N1、第二反相器N2、第一或非门NOR1和第二或非门NOR2；第一或非门NOR1和第二或非门NOR2均为两输入端或非门。第一反相器N1的输入端接收偶时钟信号CLK_E，第一反相器N1的输出端连接第一或非门NOR1的第一输入端。第一或非门NOR1的输出端连接第一自屏蔽触发器501的第二输入端C，第一或非门NOR1的第二输入端连接第二自屏蔽触发器502的第一输出端Q。第二反相器N2的输入端接收奇时钟信号CLK_O，第二反相器N2的输出端连接第二或非门NOR2的第一输入端。第二或非门NOR2的输出端连接第二自屏蔽触发器502的第二输入端C，第二或非门NOR2的第二输入端连接第一自屏蔽触发器501的第一输出端Q。
结合图16和图13，在初始命令信号CMD未被触发而寄存的情况下，第一自屏蔽触发器501的第一输出端Q输出的CMD_E和第二自屏蔽触发器502的第一输出端Q输出的CMD_O均为低电平，即第二或非门NOR2的第二输入端和第一或非门NOR1的第二输入端均接收到低电平。在该情况下，第一或非门NOR1和第二或非门NOR2不会产生屏蔽效果，第一中间时钟信号CLK_E1和偶时钟信号CLK_E波形相同，第二中间时钟信号CLK_O1和奇时钟信号CLK_O波形相同。
在初始命令信号CMD的有效脉冲宽度c中，偶时钟信号CLK_E比奇时钟信号CLK_O更先到达上升沿(如图13中虚线箭头所示)，即偶时钟信号CLK_E成为第一初始时钟信号。此时，第一自屏蔽触发器501受到第一中间时钟信号CLK_E1的触发，将初始命令信号CMD寄存，并在其第一输出端Q输出移位命令信号CMD_E到第二或非门NOR2的第二输入端。由于移位命令信号CMD_E包括了高电平脉冲，则在该高电平脉冲的持续时间d内，第二或非门NOR2输出的第二中间时钟信号CLK_O1保持低电平，也就是说，奇时钟信号CLK_O在持续时间d内被屏蔽。进而，第二中间时钟信号CLK_O1不会产生上升沿来触发第二自屏蔽触发器502将初始命令信号CMD寄存，第二自屏蔽触发器502的第一输出端Q所输出的CMD_O保持低电平而不包括任何脉冲。
相应的，若奇时钟信号CLK_O成为第一初始时钟信号，则第二自屏蔽触发器502受到第二中间时钟信号CLK_O1的触发，将初始命令信号CMD寄存，而第一自屏蔽触发器501的第一输出端Q所输出的CMD_E保持低电平而不包括任何脉冲。
本公开实施例中，如图17所示，延时模块102可以包括M级第二寄存单元203，M为大于等于2的整数。每级第二寄存单元203包括延时触发器511和512，延时触发器511和512均为D触发器。第1级第二寄存单元203中，延时触发器511的第一输入端D连接自屏蔽触发器501的第一输出端Q，延时触发器512的第一输入端D连接自屏蔽触发器502的第一输出端Q。每级第二寄存单元203中，延时触发器511的第二输入端C接收偶时钟 信号CLK_E，延时触发器512的第二输入端C接收奇时钟信号CLK_O。其中，在M大于等于2的情况下，第i级第二寄存单元203中的延时触发器511的第一输入端D连接上一级第二寄存单元203中的延时触发器511的第一输出端Q，第i级第二寄存单元203中的延时触发器512的第一输入端D连接上一级第二寄存单元203中的延时触发器512的第一输出端Q，i大于1且小于等于M。
如图17所示，延时模块102还包括或门52，或门52为二输入端或门。第M级第二寄存单元203中的延时触发器511和512，其第一输出端Q一一对应连接或门52的两个输入端。或门52的输出端作为延时模块102的输出端，输出延时命令信号CMD_SHIFT。
本公开实施例中，结合图17和图15，若偶时钟信号CLK_E成为第一初始时钟信号，则初始命令信号CMD被寄存为移位命令信号CMD_E，从而，移位命令信号CMD_E经过M级第二寄存单元203后，被延时为信号CMD_Em，并被输入到或门52，初始命令信号CMD、移位命令信号CMD_E和信号CMD_Em的波形如图15所示。
同时，自屏蔽触发器502输出的信号CMD_O会保持低电平，不包括任何脉冲，从而，在经过M级第二寄存单元203后，第M级第二寄存单元203中的延时触发器512输出的信号CMD_Om仍然为低电平，不包括任何脉冲。
这样，或门52的一个输入端接收到信号CMD_Em，另一个输入端接收到持续的低电平，因此，或门52输出的延时命令信号CMD_SHIFT与信号CMD_Em具有相同的波形，延时命令信号CMD_SHIFT的有效脉冲宽度与初始命令信号CMD的有效脉冲宽度相等。
可以理解的是，第一初始时钟信号触发初始命令信号寄存，得到移位命令信号，未通过反相器接收第一初始时钟信号的或非门，则根据移位命令信号将另一个分频时钟信号屏蔽，使得自屏蔽模块仅输出单一的移位命令信号；进而，延时模块能够进对单一的移位命令信号进行延时，从而，避免了奇偶时钟信号同时作用下带来的误差，保证了最终得到的延时命令信号的有效脉冲宽度与初始命令信号的有效脉冲宽度相等，提高了信号处理的准确度。
在本公开的一些实施例中，初始命令信号为高电平有效，初始命令信号的有效脉冲宽度大于或等于每个初始时钟信号的周期长度。初始命令信号为存储器中的读命令。
本公开实施例中，初始命令信号在通常状态下为低电平，当初始命令信号包含高电平脉冲时产生控制作用。
初始命令信号的有效脉冲宽度大于或等于每个初始时钟信号的周期长度，这样，在初始命令信号的有效脉冲宽度中，每个初始时钟信号能够至少一次到达触发沿，保证了初始命令信号总是能够被本公开实施例提供的延时电路进行寄存和延时。初始命令信号可以为存储器中的读命令，即初始命令信号可以用于控制存储器中数据的读取。
本公开实施例还提供了一种存储器80，如图18所示，存储器80包括了前述实施例提供的延时电路10。图18示出的存储器80可以为动态随机存取存储器DRAM。
在本公开的一些实施例中，如图19所示，存储器80电连接控制模组90，其中，存储器80满足DDR4规格，控制模组90满足DDR5规格。存储器80还包括分频电路81。存储器80从控制模组90接收标准时钟信号，通过分频电路81将标准时钟信号分频为初始时钟信号，并将初始时钟信号传输到延时电路10。
本公开实施例中，存储器80满足DDR4规格，控制模组90满足DDR5规格，而DDR5规格下的时钟信号频率相比DDR4规格下的时钟信号频率提升了一倍。从而，存储器80从控制模组90接收的标准时钟信号符合DDR5规格的要求。而分频电路81将标准时钟信号分频为初始时钟信号后，延时电路10可以在DDR4规格下完成对初始命令信号的延时。也就是说，存储器80可以在DDR4规格下兼容于DDR5规格的外部控制模组90，提高了存储器80的使用范围。
同时，由于DDR5规格下，时钟信号频率过高，会采用分频时钟信号对读命令进行寄 存和延时，这样，通过前述实施例提供的延时电路10，可以保证延时前和延时后的读命令，其有效脉冲宽度相等，提高了信号处理的准确度。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种延时电路和存储器，该延时电路包括：自屏蔽模块和延时模块。自屏蔽模块，被配置为接收初始命令信号和N个初始时钟信号，根据N个初始时钟信号中最先触发初始命令信号的第一初始时钟信号，对初始命令信号寄存，屏蔽N个初始时钟信号中其他N-1个第二初始时钟信号，并输出N个中间命令信号，其中，N为大于等于2的整数；N个初始时钟信号的频率相同，且相位不同。延时模块，与自屏蔽模块电连接，被配置为接收N个中间命令信号和N个初始时钟信号，对N个中间命令信号进行延时输出，得到延时命令信号。本公开实施例中，延时电路仅通过第一初始时钟信号控制命令信号的寄存和延时，屏蔽第二初始时钟信号，避免了N个初始时钟信号同时作用下带来的误差，提高了信号处理的准确度。

Claims (14)

  1. 一种延时电路，包括：
    自屏蔽模块，被配置为接收初始命令信号和N个初始时钟信号，根据N个所述初始时钟信号中最先触发所述初始命令信号的第一初始时钟信号，对所述初始命令信号寄存，屏蔽N个所述初始时钟信号中其他N-1个第二初始时钟信号，并输出N个中间命令信号，其中，N为大于等于2的整数；N个所述初始时钟信号的频率相同，且相位不同；
    延时模块，与所述自屏蔽模块电连接，被配置为接收N个所述中间命令信号和N个所述初始时钟信号，对N个所述中间命令信号进行延时输出，得到延时命令信号。
  2. 根据权利要求1所述的延时电路，其中，所述自屏蔽模块包括：
    屏蔽单元，被配置为接收N个所述初始时钟信号，并输出N个中间时钟信号；其中，N个所述中间时钟信号包括一个有效的第一中间时钟信号和N-1个无效的第二中间时钟信号；
    寄存单元，电连接所述屏蔽单元，被配置为接收所述初始命令信号和N个所述中间时钟信号，根据所述第一中间时钟信号对所述初始命令信号寄存，得到并输出N个所述中间命令信号。
  3. 根据权利要求2所述的延时电路，其中，所述寄存单元包括：N个自屏蔽触发器；N个所述自屏蔽触发器均为D触发器；N个所述中间命令信号包括一个有效的第一中间命令信号和N-1个无效的第二中间命令信号；
    N个所述自屏蔽触发器的第一输入端均接收所述初始命令信号，N个所述自屏蔽触发器的第二输入端均连接所述屏蔽单元的输出端；
    N个所述自屏蔽触发器中接收所述第一中间时钟信号的第一自屏蔽触发器，根据所述第一中间时钟信号对所述初始命令信号寄存，在其第一输出端输出所述第一中间命令信号；
    N个所述自屏蔽触发器中其他N-1个第二自屏蔽触发器，一一对应接收N-1个所述第二中间时钟信号，在其第一输出端一一对应输出N-1个所述第二中间命令信号。
  4. 根据权利要求3所述的延时电路，其中，所述屏蔽单元包括：N个与门，所述与门均包括一个第一输入端和N-1个第二输入端；
    N个所述与门的第一输入端一一对应接收N个所述初始时钟信号，N个所述与门的输出端一一对应连接N个所述自屏蔽触发器的第二输入端；
    每个与门的N-1个第二输入端一一对应连接其对应的自屏蔽触发器外的N-1个其他自 屏蔽触发器的第二输出端。
  5. 根据权利要求3所述的延时电路，其中，所述屏蔽单元包括：N个反相器和N个或非门；所述或非门均包括第一输入端和N-1个第二输入端；
    N个所述反相器的输入端一一对应接收N个所述初始时钟信号，N个所述反相器的输出端一一对应连接N个所述或非门的第一输入端，N个所述或非门的输出端一一对应连接N个所述自屏蔽触发器的第二输入端；
    每个所述或非门的N-1个第二输入端一一对应连接其对应的自屏蔽触发器外的N-1个其他自屏蔽触发器的第一输出端。
  6. 根据权利要求3所述的延时电路，其中，所述延时模块包括：M级第二寄存单元，M为大于等于2的整数；每级第二寄存单元包括：N个延时触发器；所述N个延时触发器均为D触发器；
    每级第二寄存单元中的N个所述延时触发器，其第二输入端一一对应接收N个所述初始时钟信号；
    第1级第二寄存单元中的N个延时触发器，其第一输入端一一对应连接N个所述自屏蔽触发器的第一输出端；
    第i级第二寄存单元中的N个延时触发器，其第一输入端一一对应连接上一级第二寄存单元中N个延时触发器的输出端，i大于1且小于等于M。
  7. 根据权利要求6所述的延时电路，其中，M＝(CL-A)/N，其中，CL为最大的延时周期数，A为命令预操作对应的周期数。
  8. 根据权利要求6所述的延时电路，其中，所述延时模块还包括：或门，所述或门包括N个输入端；
    第M级第二寄存单元中的N个延时触发器，其第一输出端一一对应连接所述或门的N个输入端；所述或门的输出端输出所述延时命令信号。
  9. 根据权利要求1所述的延时电路，其中，N＝2，所述N个初始时钟信号为奇偶分频时钟信号，所述奇偶分频时钟信号包括：奇时钟信号和偶时钟信号；所述奇时钟信号和所述偶时钟信号频率相同，且相位相反。
  10. 根据权利要求9所述的延时电路，其中，所述自屏蔽模块包括：屏蔽单元和寄存单元；
    所述寄存单元包括：第一自屏蔽触发器和第二自屏蔽触发器；所述第一自屏蔽触发器和所述第二自屏蔽触发器均为D触发器；
    所述第一自屏蔽触发器的第一输入端和所述第二自屏蔽触发器的第一输入端均接收所述命令信号。
  11. 根据权利要求10所述的延时电路，其中，所述屏蔽单元包括：第一与门和第二与门；所述第一与门和所述第二与门均为两输入端与门；
    所述第一与门的第一输入端接收所述偶时钟信号，所述第一与门的输出端连接所述第一自屏蔽触发器的第二输入端，所述第一与门的第二输入端连接所述第二自屏蔽触发器的第二输出端；
    所述第二与门的第一输入端接收所述奇时钟信号，所述第二与门的输出端连接所述第二自屏蔽触发器的第二输入端，所述第二与门的第二输入端连接所述第一自屏蔽触发器的第二输出端。
  12. 根据权利要求10所述的延时电路，其中，所述屏蔽单元包括：第一反相器、第二反相器、第一或非门和第二或非门；所述第一或非门和所述第二或非门均为两输入端或非门；
    所述第一反相器的输入端接收所述偶时钟信号，所述第一反相器的输出端连接所述第一或非门的第一输入端；
    所述第一或非门的输出端连接所述第一自屏蔽触发器的第二输入端，所述第一或非门的第二输入端连接所述第二自屏蔽触发器的第一输出端；
    所述第二反相器的输入端接收所述奇时钟信号，所述第二反相器的输出端连接所述第二或非门的第一输入端；
    所述第二或非门的输出端连接所述第二自屏蔽触发器的第二输入端，所述第二或非门的第二输入端连接所述第一自屏蔽触发器的第一输出端。
  13. 一种存储器，所述存储器包括如权利要求1至12任一项所述的延时电路。
  14. 根据权利要求13所述的存储器，其中，
    所述存储器电连接控制模组，其中，所述存储器满足DDR4规格，所述控制模组满足DDR5规格；
    所述存储器还包括分频电路；所述存储器从所述控制模组接收标准时钟信号，通过所述分频电路将所述标准时钟信号分频为初始时钟信号，并将所述初始时钟信号传输到所述延时电路。
PCT/CN2022/100189 2022-05-19 2022-06-21 一种延时电路和存储器 WO2023221230A1 (zh)

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