WO2023178848A1 - 一种信号采样电路以及半导体存储器 - Google Patents

一种信号采样电路以及半导体存储器 Download PDF

Info

Publication number
WO2023178848A1
WO2023178848A1 PCT/CN2022/099265 CN2022099265W WO2023178848A1 WO 2023178848 A1 WO2023178848 A1 WO 2023178848A1 CN 2022099265 W CN2022099265 W CN 2022099265W WO 2023178848 A1 WO2023178848 A1 WO 2023178848A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
clock
odd
chip select
circuit
Prior art date
Application number
PCT/CN2022/099265
Other languages
English (en)
French (fr)
Inventor
黄泽群
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US18/449,060 priority Critical patent/US20230386553A1/en
Publication of WO2023178848A1 publication Critical patent/WO2023178848A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/415—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Definitions

  • the present disclosure relates to, but is not limited to, a signal sampling circuit and a semiconductor memory.
  • DDR Double Data Rate
  • the command address signal not only needs to be sampled as an address signal, but also needs to be sampled and decoded as an instruction signal.
  • the command address signal is designed as a 2 clock cycle signal, not only is the timing deviation likely to occur between the address signal and the instruction decoding signal, but also the number of address buses involved results in a large circuit area.
  • embodiments of the present disclosure provide a signal sampling circuit, which includes an input sampling circuit, a logic operation circuit, an instruction decoding circuit and a combined output circuit; wherein,
  • the input sampling circuit is used to sample the first chip select signal and the first command address signal respectively according to the first clock signal to obtain the second chip select signal and the second command address signal; wherein, the second command The address signal includes an initial command signal, and the second command address signal is composed of a second command address odd signal and a second command address even signal;
  • the logic operation circuit is used to perform logical operations on the first clock signal and the second chip select signal to obtain a chip select clock signal; wherein the chip select clock signal includes a chip select clock odd signal and a chip select signal. Clock even signal;
  • the instruction decoding circuit is used to decode and sample the initial instruction signal according to the second chip select signal and the chip select clock signal to obtain a target instruction signal;
  • the combined output circuit is configured to perform sampling processing on the second command address odd signal and the second command address even signal respectively according to the chip select clock even signal and the chip select clock odd signal to obtain the first Target address signal; and perform sampling processing on the second command address odd signal and the second command address even signal respectively according to the chip select clock odd signal and the chip select clock even signal to obtain a second target address signal.
  • the signal sampling circuit further includes a receiving circuit, and the receiving circuit includes a first receiving circuit, a second receiving circuit, and a third receiving circuit; wherein,
  • the first receiving circuit is used to receive an initial command address signal and output the first command address signal
  • the second receiving circuit is used to receive the initial chip select signal and output the first chip select signal
  • the third receiving circuit is used to receive an initial clock signal and perform frequency division processing on the initial clock signal to obtain an odd clock signal and an even clock signal;
  • the clock period of the odd clock signal and the even clock signal is twice the clock period of the initial clock signal, and the phase difference between the odd clock signal and the even signal is 180 degrees.
  • the odd clock signal and the even clock signal constitute the first clock signal.
  • the input sampling circuit includes a command address sampling circuit
  • the command address sampling circuit includes a first sampling circuit and a second sampling circuit
  • the first sampling circuit is used to sample the first command address signal according to the clock odd signal to obtain the second command address odd signal;
  • the second sampling circuit is used to sample the first command address signal through the clock even signal to obtain the second command address even signal
  • the initial command signal is composed of an initial command even signal and an initial command odd signal
  • the second command address even signal includes an initial command even signal
  • the second command address odd signal includes an initial command odd signal
  • the input sampling circuit further includes a chip select sampling circuit, and the chip select sampling circuit includes a third sampling circuit, a fourth sampling circuit, a fifth sampling circuit and a sixth sampling circuit;
  • the third sampling circuit is used to sample the first chip select signal according to the clock odd signal to obtain an intermediate sampling odd signal
  • the fourth sampling circuit is used to sample the intermediate sampling odd signal according to the clock even signal to obtain a second chip selection even signal
  • the fifth sampling circuit is used to sample the first chip select signal according to the clock even signal to obtain an intermediate sampled even signal
  • the sixth sampling circuit is used to sample the intermediate sampling even signal through the clock odd signal to obtain a second chip select odd signal
  • the second chip select signal is composed of the second chip select even signal and the second chip select odd signal.
  • the logic operation circuit includes a first logic circuit and a second logic circuit; wherein,
  • the first logic circuit is used to receive the clock even signal and the second chip select even signal, and perform logical operations on the clock even signal and the second chip select even signal to obtain the chip select Clock even signal;
  • the second logic circuit is configured to receive the odd clock signal and the second odd chip select signal, and perform logical operations on the odd clock signal and the second odd chip select signal to obtain the chip select Clock odd signal.
  • the first logic circuit includes a first buffer and a first AND gate; wherein,
  • the first buffer is used to perform delay processing on the clock even signal to obtain an intermediate clock even signal
  • the first AND gate is used to perform an AND operation on the second chip select even signal and the intermediate clock even signal to obtain the chip select clock even signal.
  • the second logic circuit includes a second buffer and a second AND gate; wherein,
  • the second buffer is used to delay the odd clock signal to obtain an intermediate odd clock signal
  • the second AND gate is used to perform an AND operation on the second chip select odd signal and the intermediate clock odd signal to obtain the chip select clock odd signal.
  • the instruction decoding circuit includes a first instruction decoding circuit, a second instruction decoding circuit, and an OR gate; wherein,
  • the first instruction decoding circuit is used to decode and sample the initial instruction odd signal according to the chip select clock even signal and the second chip select even signal to obtain an instruction even signal;
  • the second instruction decoding circuit is used to decode and sample the initial instruction even signal according to the chip select clock odd signal and the second chip select odd signal to obtain an instruction odd signal;
  • the OR gate is used to perform an OR operation on the instruction even signal and the instruction odd signal to obtain the target instruction signal.
  • the first instruction decoding circuit includes a first decoding circuit, a seventh sampling circuit and a third AND gate; wherein,
  • the first decoding circuit is used to decode the initial instruction odd signal to obtain an instruction decoding odd signal
  • the seventh sampling circuit is used to sample the instruction decoding odd signal according to the chip select clock even signal to obtain an instruction sampling even signal
  • the third AND gate is used to perform an AND operation on the second chip selection even signal and the instruction sampling even signal to obtain the instruction even signal.
  • the second instruction decoding circuit includes a second decoding circuit, an eighth sampling circuit, and a fourth AND gate; wherein,
  • the second decoding circuit is used to decode the initial instruction even signal to obtain an instruction decoding even signal
  • the eighth sampling circuit is used to sample the instruction decoding even signal according to the chip select clock odd signal to obtain an instruction sampling odd signal
  • the fourth AND gate is used to perform an AND operation on the second chip select odd signal and the instruction sampling odd signal to obtain the instruction odd signal.
  • the combined output circuit includes a first combined output circuit and a second combined output circuit; wherein,
  • the first combined output circuit is configured to sample the second command address even signal according to the chip select clock odd signal to obtain the first target address signal; or, to sample the even signal according to the chip select clock The second command address odd signal is sampled to obtain the first target address signal;
  • the second combined output circuit is configured to sample the second command address odd signal according to the chip select clock odd signal to obtain the second target address signal; or, to sample the second command address odd signal according to the chip select clock even signal.
  • the second command address even signal is sampled to obtain the second target address signal;
  • the first data terminal, the second data terminal, the first clock terminal and the second clock terminal of the first combined output circuit and the second command address odd signal, the second command address even signal, the The even signal of the chip select clock and the odd signal of the chip select clock are connected correspondingly, and the first data terminal, the second data terminal, the first clock terminal and the second clock terminal of the second combined output circuit are connected to the second command address
  • the odd signal, the second command address even signal, the chip select clock odd signal and the chip select clock even signal are connected correspondingly.
  • the first combined output circuit includes a third logic circuit, a fourth logic circuit and a ninth sampling circuit; wherein,
  • the third logic circuit is used to perform logical operations on the chip select clock odd signal to obtain a first enabled odd signal and a second enabled odd signal, and the first enabled odd signal and the second enabled odd signal
  • the phase difference between odd signals is enabled to be 180 degrees
  • the fourth logic circuit is used to perform logical operations on the chip select clock even signal to obtain a first enable even signal and a second enable even signal, and the first enable even signal and the second enable even signal
  • the phase difference between the enabled even signals is 180 degrees
  • the ninth sampling circuit is used to analyze the second enable even signal according to the first enable even signal, the second enable even signal, the first enable odd signal and the second enable odd signal.
  • the command address even signal and the second command address odd signal are sampled to obtain the first target address signal.
  • the ninth sampling circuit is specifically configured to, when the chip select clock even signal is a high-level active pulse signal, according to the first enable even signal and the second enable even signal.
  • the even signal can sample the second command address odd signal to obtain the first target address signal; or, in the case where the chip select clock odd signal is a high-level active pulse signal, according to the third An enable odd signal and the second enable odd signal perform sampling processing on the second command address even signal to obtain the first target address signal.
  • the second combined output circuit includes a fifth logic circuit, a sixth logic circuit and a tenth sampling circuit; wherein,
  • the fifth logic circuit is used to perform logical operations on the chip select clock even signal to obtain a third enable even signal and a fourth enable even signal, and the third enable even signal and the fourth enable even signal
  • the phase difference between the enabled even signals is 180 degrees
  • the sixth logic circuit is used to perform logical operations on the chip select clock odd signal to obtain a third enable odd signal and a fourth enable odd signal; and the third enable odd signal and the fourth enable odd signal
  • the phase difference between odd signals is enabled to be 180 degrees;
  • the tenth sampling circuit is used to analyze the second signal according to the third enable even signal, the fourth enable even signal, the third enable odd signal and the fourth enable odd signal.
  • the command address even signal and the second command address odd signal are sampled to obtain the second target address signal.
  • the tenth sampling circuit is specifically configured to, when the chip select clock even signal is a high-level active pulse signal, according to the third enable even signal and the fourth enable signal.
  • the second command address even signal is sampled by the energy even signal to obtain the second target address signal; or, in the case where the chip select clock odd signal is a high-level pulse signal, the second command address even signal is sampled according to the third target address signal.
  • the third enable odd signal and the fourth enable odd signal perform sampling processing on the second command address odd signal to obtain the second target address signal.
  • the first chip select signal is a signal indicating that the target chip is selected, and the first chip select signal is an active low-level pulse signal;
  • the second chip select odd signal is a high-level pulse signal
  • the chip select clock odd signal is a high-level pulse signal.
  • the first target address signal includes information of the first command address signal in a first clock cycle
  • the second target address signal includes information of the first command address signal in a second clock cycle.
  • information therein and the first clock cycle refers to the clock cycle when the first chip select signal is low level, and the second clock cycle is the next clock cycle of the first clock cycle.
  • an embodiment of the present disclosure provides a semiconductor memory, including the signal sampling circuit as described in any one of the first aspects.
  • the semiconductor memory is a dynamic random access memory DRAM chip.
  • Figure 1 is a schematic diagram of the signal timing of the two clock cycle commands
  • Figure 2 is a schematic structural diagram of a signal sampling circuit
  • Figure 3 is a schematic structural diagram of an instruction decoder
  • Figure 4 is a signal timing diagram of a signal sampling circuit
  • Figure 5 is a schematic structural diagram of a signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of another signal sampling circuit provided by an embodiment of the present disclosure.
  • FIG. 7A is a schematic structural diagram of the first instruction decoding circuit provided by an embodiment of the present disclosure.
  • Figure 7B is a schematic structural diagram of the first instruction decoding circuit provided by an embodiment of the present disclosure.
  • Figure 8A is a schematic structural diagram of the first combined output circuit provided by an embodiment of the present disclosure.
  • Figure 8B is a schematic structural diagram of the first combined output circuit provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram of a specific circuit structure of an enabled inverter provided by an embodiment of the present disclosure.
  • Figure 10 is a detailed structural schematic diagram of a signal sampling circuit provided by an embodiment of the present disclosure.
  • Figure 11 is a signal timing diagram of a signal sampling circuit provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first ⁇ second ⁇ third” Where permitted, the specific order or sequence may be interchanged so that the embodiments of the disclosure described herein can be practiced in an order other than that illustrated or described herein.
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • Command address input (Command/Address, CMD/ADD or CA for short)
  • DFF Data Flip-Flop or Delay Flip-Flop
  • CA can be used as both an address for sampling and an instruction for sampling and decoding.
  • CA here is the collective name for various command address signals of DRAM, which can include row address strobe (RAS), column address strobe (Column Address Strobe, CAS), and write command (Write, WE).
  • RAS row address strobe
  • CAS Column address strobe
  • WE write command
  • activation command active, ACT
  • other command signals and may also include address signals from A13 to A0, etc.
  • the command address signal includes several address signals, which may be determined according to the specifications of the DRAM, and the embodiment of the present disclosure does not make any limitation.
  • FIG. 1 shows the signal timing diagram of the two clock cycle commands.
  • CK_t and CK_c are a pair of input complementary clock signals
  • CA[13:0] is the CA input
  • CMD is the command signal obtained after CA decoding
  • CS_n is the chip select signal indicating that CA is valid.
  • CA[13:0] is a signal that lasts for two clock cycles.
  • the CA of the first clock cycle and the CA of the second clock cycle need to be sampled as address signals.
  • the CA of the first clock cycle CA also requires command signals to be sampled and decoded.
  • CA[4:0] of the first clock cycle needs to be decoded and sampled as a command signal.
  • the clock cycle refers to the clock cycle of CK_t/CK_c.
  • the signal sampling circuit includes a first receiver 101, a second receiver 102, a third receiver 103, a first sampling circuit 104, a second sampling circuit 105, a third sampling circuit 106, and a fourth sampling circuit.
  • the first sampling circuit 104, the second sampling circuit 105, the fifth sampling circuit 108, the sixth sampling circuit 109, the seventh sampling circuit 110 and the eighth sampling circuit 111 may be composed of D-type flip-flops
  • the third sampling circuit 106 and the fourth sampling circuit 107 may be composed of a D-type flip-flop and an inverter
  • the instruction decoder 108 may be composed of three-input NAND gates, two-input NOR gates, buffers and other logical components, as shown in FIG. 3 for details.
  • the input signal of the first receiver 101 is the initial command address signal (represented by CA[13:0]) and the reference signal (represented by VREFCA), and the output signal is the first command address signal (represented by CA) ;
  • the input signal of the second receiver 102 is the initial chip select signal (represented by CS_n) and the reference signal (represented by VREFCA), and the output signal is the first chip select signal (represented by PCS);
  • the input signal of the third receiver 103 is the initial clock signal (represented by CK_t/CK_c), and after frequency division processing, the even clock signal (represented by PCLK_E) and the odd clock signal (represented by PCLK_O) are obtained.
  • CA[13:0] here represents a group of signals, the combined collective name of CA[0], CA[1], ..., CA[13].
  • the first receiver 101 actually includes 14 receiving circuits, as well as output lines, and even the subsequent sampling circuit. There are also 14 long wiring paths, and CA[0], CA[1],..., CA[13] has a one-to-one correspondence.
  • the first command address signal CA is subjected to one-level sampling processing using the clock even signal PCLK_E to obtain the second address even signal (represented by CA[13:0]_1T_E), and through the fifth sampling Circuit 108 uses the clock odd signal PCLK_O to perform secondary sampling processing on the second address even signal CA[13:0]_1T_E to obtain the third address odd signal (shown in the table CA[13:0]_0T_O).
  • the first command address signal CA is sampled using the clock odd signal PCLK_O to obtain the second address odd signal (represented by CA[13:0]_1T_O), and through the sixth sampling circuit 109, using The clock even signal PCLK_E performs secondary sampling processing on the second address odd signal CA[13:0]_1T_O to obtain the third address even signal (represented by CA[13:0]_0T_E).
  • the third address even signal CA[13:0]_OT_E includes the initial command even signal (represented by CA[4:0]_0T_E)
  • the third address odd signal CA[13:0]_0T_O includes the initial command odd signal ( Represented by CA[4:0]_0T_O).
  • CA[4:0]_0T_E and CA[4:0]_0T_O are used to decode and form command signals, which are CA[0]_0T_E ⁇ CA[4]_0T_E and CA[0]_0T_O ⁇ CA[ respectively 4]_0T_O's combined collective name.
  • the clock even signal PCLK_E is used to perform one-level sampling and inversion processing on the first chip select signal PCS to obtain an intermediate sampled even signal (represented by PCS_E), and through the seventh sampling circuit 110, using The odd clock signal PCLK_O performs two-level sampling on the intermediate sampled even signal PCS_E to obtain the second odd chip select signal (represented by PCS_OD); through the fourth sampling circuit 107, the odd clock signal PCLK_O is used to perform one-level sampling on the first chip select signal PCS. Sampling and inversion processing are performed to obtain the intermediate sampling odd signal (represented by PCS_O), and the eighth sampling circuit 111 performs secondary sampling on the intermediate sampling odd signal PCS_O to obtain the second chip selection even signal (represented by PCS_ED).
  • the initial instruction even signal CA[4:0]_OT_E, the initial instruction odd signal CA[4:0]_OT_O, the second chip select even signal PCS_ED and the second chip select odd signal PCS_OD are processed.
  • the target command signal CMD, the second address odd signal CA[13:0]_1T_O, the second address even signal CA[13:0]_1T_E, the third address odd signal CA[13:0]_0T_O and the third address even signal There are long wiring paths between the signal CA[13:0]_OT_E and the first functional module 114, the second functional module 115 and the third functional module 116; in this way, the target command signal CMD and the second address odd signal CA[ 13:0]_1T_O, the second address even signal CA[13:0]_1T_E, the third address odd signal CA[13:0]_0T_O and the third address even signal CA[13:0]_0T_E are routed through different layouts After the path, different functional modules will be reached together to realize the next level function.
  • the corresponding signal timing diagram is shown in Figure 4.
  • the initial clock signal is represented by CK_t/CK_c
  • the even clock signal is represented by PCLK_E
  • the odd clock signal is represented by PCLK_O.
  • the clock cycle of CK_t/CK_c is the preset clock cycle
  • the clock cycles of PCLK_E/PCLK_O are both preset clock cycles.
  • the first command address signal is represented by CA, and CA can include Cy, Cz, C0, C1, C2 and C3;
  • the initial chip select signal is represented by CS_n, the first chip select signal is represented by PCS, PCS
  • the signal is an active low-level pulse signal, and the pulse width is a preset clock period.
  • PCS is used to represent the signal that the target chip is selected.
  • the first command address signal CA (CA information in the first clock cycle) whose content is C0 and the low-level first chip select signal PCS are sampled by the clock even signal PCLK_E in one stage to generate an intermediate sampling even signal.
  • the CA whose content is C1 (CA information in the second clock cycle) is sampled by the odd clock signal PCLK_O in one level, generating the second odd clock signal CA[13:0]_1T_O.
  • the second chip select odd signal PCS_OD, the second address odd signal CA[13:0]_1T_O and the third address odd signal CA[13:0]_0T_O are all sampled and output by the clock odd signal PCLK_O.
  • the three sets of signals are Alignment.
  • the second chip select odd signal PCS_OD and the initial command odd signal CA[4:0]_0T_O also need to enter the command decoder 112 and the OR gate 113 for logic decoding to obtain the target command signal CMD. Therefore, there is a certain timing deviation (Skew) between the target command signal CMD, the second address odd signal CA[13:0]_1T_O, and the third address odd signal CA[13:0]_0T_O, causing errors in subsequent circuits.
  • the initial clock signal CK_t/CK_c is divided into parity clock PCLK_E/PCLK_O after the receiver to sample the first command address signal CA.
  • the DDR5 design requires two levels of sampling, which are then used as address signals for two clock cycles respectively.
  • the first command address signal CA after the second stage sampling needs to be decoded as an instruction signal. In this way, the instruction path has more logic circuits for the decoding part than the address path.
  • Subsequent address signals and instruction signals go through different The layout routing paths jointly reach different modules to implement next-level functions.
  • the address signal can be obtained, but after the first command address signal CA signal is sampled, it still needs to be decoded to obtain the instruction signal, causing the instruction signal and the address signal to arrive at the next
  • the timing of each stage has a large timing deviation (Skew), and this Skew will be different under different PVT conditions, resulting in errors in the next-level function due to timing deviation.
  • Skw timing deviation
  • 2T CMD for one bit of the first command address signal CA, four different address buses need to be set up to transmit it backwards, which takes up a large layout area and reduces the cost. improve the electrical performance of the memory.
  • the signal sampling circuit includes an input sampling circuit, a logic operation circuit, an instruction decoding circuit, and a combined output circuit; wherein the input sampling circuit is configured to operate according to the first clock signal.
  • the first chip select signal and the first command address signal are sampled and processed respectively to obtain the second chip select signal and the second command address signal; wherein the second command address signal includes the initial command signal, and the second command address signal is generated by the first command address signal.
  • a logic operation circuit is used to perform logical operations on the first clock signal and the second chip select signal to obtain a chip select clock signal; wherein, the chip select clock signal includes chip select The clock odd signal and the chip select clock even signal; the instruction decoding circuit is used to decode and sample the initial instruction signal according to the second chip select signal and the chip select clock signal to obtain the target instruction signal; the combined output circuit is used Yu performs sampling processing on the second command address odd signal and the second command address even signal respectively according to the chip select clock even signal and the chip select clock odd signal to obtain the first target address signal; and according to the chip select clock odd signal and the chip select clock The even signal samples the second command address odd signal and the second command address even signal respectively to obtain the second target address signal.
  • the timing between the target instruction signal, the first target address signal and the second target address signal is aligned.
  • the timing alignment of the target instruction signal, the first target address signal and the second target address signal can be achieved, so that there is no gap between the decoded instruction signal and the address signal.
  • FIG. 5 shows a schematic structural diagram of a signal sampling circuit 40 provided by an embodiment of the present disclosure.
  • the signal sampling circuit 40 may include an input sampling circuit 41, a logic operation circuit 42, an instruction decoding circuit 43 and a combined output circuit 44; wherein,
  • the input sampling circuit 41 is used to sample the first chip select signal and the first command address signal respectively according to the first clock signal to obtain the second chip select signal and the second command address signal; wherein the second command address signal includes The initial command signal, and the second command address signal is composed of the second command address odd signal and the second command address even signal;
  • the logic operation circuit 42 is used to perform logical operations on the first clock signal and the second chip select signal to obtain a chip select clock signal; wherein the chip select clock signal includes an odd signal of the chip select clock and an even signal of the chip select clock;
  • the instruction decoding circuit 43 is used to decode and sample the initial instruction signal according to the second chip select signal and the chip select clock signal to obtain the target instruction signal;
  • the combined output circuit 44 is used to sample the second command address odd signal and the second command address even signal respectively according to the chip select clock even signal and the chip select clock odd signal to obtain the first target address signal; and according to the chip select clock
  • the odd signal and the even signal of the chip select clock respectively sample and process the second command address odd signal and the second command address even signal to obtain the second target address signal.
  • the signal sampling circuit 40 in the embodiment of the present disclosure is used in the sampling and decoding process of address and instruction signals, and can be specifically applied in a variety of circuit scenarios.
  • the embodiments of the present disclosure will be explained and described later using CA decoding in DRAM, but this does not constitute a relevant limitation.
  • the signal sampling circuit 40 of the embodiment of the present disclosure is applied to the command signal of two clock cycles (ie, 2T CMD).
  • the first command address signal here includes a valid signal for two clock cycles.
  • the target instruction signal includes a valid command for two clock cycles, as shown in FIG. 1 .
  • the CS_n signal is an active low-level pulse signal, and the pulse width is one clock cycle.
  • the CA[13:0] signal corresponding to this clock cycle and the next clock cycle of this clock cycle is valid (Valid) of.
  • the CA of the first clock cycle and the second clock cycle need to be sampled as an address signal, and the CA of the first clock cycle also needs to be sampled and decoded into an instruction signal.
  • the instruction decoding circuit 43 is used to output the target instruction signal
  • the combining output circuit 44 is used to output the first target address signal and the second target address signal
  • the first target address signal indicates the first clock
  • the second target address signal is used to indicate the CA information in the second clock cycle.
  • the second command address signal is composed of a second command address even signal and a second command address odd signal
  • the chip select clock signal is also composed of a chip select clock odd signal and a chip select clock even signal.
  • the combined output circuit 44 performs cross-sampling processing on the second command address signal using the chip select clock signal to obtain the first target address signal; at the same time, performs corresponding sampling processing on the second command address signal using the chip select clock signal to obtain the second target address signal. Destination address signal.
  • the cross-sampling process means: using the even signal of the chip select clock to sample the odd signal of the second command address, and using the odd signal of the chip select clock to sample the even signal of the second command address.
  • the corresponding sampling processing refers to: using the even signal of the chip select clock to sample the even signal of the second command address, and using the odd signal of the chip select clock to sample the odd signal of the second command address.
  • the target command signal is sampled and output by the instruction decoding circuit 43 according to the chip select clock odd signal; the first target address signal is sampled and output by the combining output circuit 44 according to the chip select clock odd signal.
  • the signal is sampled and output to the second command address even signal, and the second target address signal is sampled and output by the combining output circuit 44 according to the odd signal of the chip select clock to the second command address odd signal.
  • the target instruction signal is sampled and output by the instruction decoding circuit 43 according to the chip select clock even signal; the first target address signal is sampled and output by the combining output circuit 44 according to the chip select clock even signal.
  • the second command address odd signal is sampled and output, and the second target address signal is sampled and output by the combining output circuit 44 according to the even signal of the chip select clock to the second command address even signal.
  • timing alignment means that the target instruction signal, the first target address signal and the second target address signal change from a low level state to a high level state at the same time, or from a high level state to a low level state at the same time.
  • timing alignment and “simultaneity” described in the embodiments of this application mean that the timing deviation is within a preset accuracy range.
  • the signal sampling circuit 40 may also include a receiving circuit 45.
  • the receiving circuit 45 includes a first receiving circuit 451 and a second receiving circuit 452. and the third receiving circuit 453; wherein,
  • the first receiving circuit 451 is used to receive the initial command address signal and output the first command address signal
  • the second receiving circuit 452 is used to receive the initial chip select signal and output the first chip select signal
  • the third receiving circuit 453 is used to receive the initial clock signal and perform frequency division processing on the initial clock signal to obtain an odd clock signal and an even clock signal.
  • the odd clock signal and the even clock signal constitute the aforementioned first clock signal.
  • the clock odd signal and the clock even signal are obtained by frequency division of the initial clock signal, so the clock periods of the clock odd signal and the clock even signal are twice the clock period of the initial clock signal.
  • the phase difference between the odd clock signal and the even clock signal is 180 degrees.
  • the first command address signal, the first chip select signal and the first clock signal can be obtained, and then input to the input sampling circuit 41 for sampling and subsequent logical operations.
  • either the first receiving circuit 451, the second receiving circuit 452 or the third receiving circuit 453 may be a receiver (denoted by Recevier) or a buffer (denoted by Buffer).
  • the initial command address signal here can be represented by CA[13:0], and the first command address signal is represented by CA; the initial chip select signal can be represented by CS_n, and the first chip select signal Represented by PCS; the initial clock signal can be represented by CK_t and CK_c, the even clock signal is represented by PCLK_E, and the odd clock signal is represented by PCLK_O.
  • the first receiving circuit 451 may include 14 receiving circuits for receiving 14 signals such as CA[0], CA[1],..., CA[13]. Only one receiving circuit is shown in the figure. As a hint.
  • the input sampling circuit 41 includes a command address sampling circuit 411, and the command address sampling circuit 411 includes a first sampling circuit and a second sampling circuit; wherein,
  • the first sampling circuit is used to sample the first command address signal according to the clock odd signal to obtain the second command address odd signal;
  • the second sampling circuit is used to sample the first command address signal through the clock even signal to obtain the second command address even signal
  • the initial command signal is composed of an initial command even signal and an initial command odd signal
  • the second command address even signal includes the initial command even signal
  • the second command address odd signal includes the initial command odd signal
  • the second command address even signal can be represented by CA[13:0]_1T_E
  • the second command address odd signal can be represented by CA[13:0]_1T_O
  • the initial command even signal is represented by CA [4:0]_1T_E represents
  • the initial command odd signal is represented by CA[4:0]_1T_O.
  • "1T" does not have a particularly limited meaning.
  • CA[13:0]_1T_E is not a signal, but represents a set of command address signals, namely CA[0]_1T_E ⁇ CA[13]_1T_E, and CA[4:0]_1T_E represents CA[0]_1T_E ⁇ CA[4]_1T_E in this group of signals;
  • CA[13:0]_1T_O is not a signal, but represents a group of command address signals, namely CA[0]_1T_O ⁇ CA[13 ]_1T_O, and CA[4:0]_1T_O represents CA[0]_1T_O ⁇ CA[4]_1T_O in this group of signals.
  • the first sampling circuit and the second sampling circuit may be composed of D-type flip-flops; wherein, for the first sampling circuit, the clock end of the D-type flip-flop is connected to the odd clock signal PCLK_O, and the D-type flip-flop The input end of the flip-flop is connected to the first command address signal CA, the output end of the D-type flip-flop is used to output the second command address odd signal CA[13:0]_1T_O, and the second command address odd signal CA[13:0 ]_1T_O includes the initial command odd signal CA[4:0]_1T_O.
  • the clock terminal of the D-type flip-flop is connected to the clock signal PCLK_E
  • the input terminal of the D-type flip-flop is connected to the first command address signal CA
  • the output terminal of the D-type flip-flop is used to output the second
  • the second command address even signal CA[13:0]_1T_E includes the initial command even signal CA[4:0]_1T_E.
  • the input sampling circuit 41 further includes a chip select sampling circuit 412, and the chip select sampling circuit 412 includes a third sampling circuit, a fourth sampling circuit, a fifth sampling circuit and a sixth sampling circuit;
  • the third sampling circuit is used to sample the first chip select signal according to the clock odd signal to obtain the middle sampling odd signal;
  • the fourth sampling circuit is used to sample the intermediate sampling odd signal according to the clock even signal to obtain the second chip selection even signal;
  • the fifth sampling circuit is used to sample the first chip select signal according to the clock even signal to obtain the intermediate sampled even signal
  • the sixth sampling circuit is used to sample the intermediate sampled even signal through the clock odd signal to obtain the second chip select odd signal.
  • the middle sampling odd signal can be represented by PCS_O
  • the second chip selection even signal can be represented by PCS_ED
  • the middle sampling even signal can be represented by PCS_E
  • the second chip selection odd signal can be represented by PCS_OD .
  • the third sampling circuit may be composed of a D-type flip-flop and an inverter
  • the fourth sampling circuit may be composed of a D-type flip-flop.
  • the clock terminal of the D-type flip-flop is connected to the clock odd signal PCLK_O
  • the input terminal of the D-type flip-flop is connected to the first chip select signal PCS
  • the output terminal of the D-type flip-flop is connected to the inverting
  • the input end of the inverter is connected, and the output end of the inverter is used to output the intermediate sampling odd signal PCS_O
  • the clock end of the D-type flip-flop is connected to PCLK_E
  • the input end of the D-type flip-flop is connected to the intermediate sampling
  • the odd signal PCS_O is connected, and the output end of the D-type flip-flop is used to output the second chip select even signal PCS_ED.
  • the fifth sampling circuit may be composed of a D-type flip-flop and an inverter
  • the sixth sampling circuit may be composed of a D-type flip-flop.
  • the clock terminal of the D-type flip-flop is connected to the clock even signal PCLK_E
  • the input terminal of the D-type flip-flop is connected to the first chip select signal PCS
  • the output terminal of the D-type flip-flop is connected to the inverting
  • the input end of the inverter is connected, and the output end of the inverter is used to output the intermediate sampling even signal PCS_E signal
  • the clock end of the D-type flip-flop is connected to the clock odd signal PCLK_O, and the input of the D-type flip-flop
  • the terminal is connected to the intermediate sampling even signal PCS_E signal, and the output terminal of the D-type flip-flop is used to output the second chip select odd signal PCS_OD.
  • the first chip select signal PCS is an active low-level pulse signal
  • an inverter needs to be set in the third sampling circuit or the fifth sampling circuit so that the intermediate sampling even signal PCS_E or the intermediate sampling odd signal PCS_O It becomes a high-level active pulse signal for subsequent logic operations.
  • the third sampling circuit and the fifth sampling circuit may not need an inverter, and subsequent logic operations need to be adjusted accordingly to achieve the same effect.
  • the clock even signal, the clock odd signal, the second chip select even signal, the second chip select odd signal, the second command address even signal, and the second command address odd signal can be obtained.
  • the clock even signal, the clock odd signal, the second chip select even signal, and the second chip select odd signal are calculated to obtain the chip select clock odd signal and the chip select clock even signal.
  • the second command address even signal and the second command address odd signal are sampled through the effective chip select clock signal, and the initial command even signal or the initial command odd signal is decoded and sampled, so that the final output address Timing alignment of signals and command signals.
  • the logic operation circuit 42 includes a first logic circuit 421 and a second logic circuit 422; wherein,
  • the first logic circuit 421 is used to receive the clock even signal and the second chip select even signal, and perform logical operations on the clock even signal and the second chip select even signal to obtain the chip select clock even signal;
  • the second logic circuit 422 is used to receive the odd clock signal and the second odd chip select signal, and perform logical operations on the odd clock signal and the second odd chip select signal to obtain the odd chip select clock signal.
  • the first logic circuit 421 may include a first buffer and a first AND gate; wherein,
  • the first buffer is used to delay the clock even signal to obtain the intermediate clock even signal
  • the first AND gate is used to perform an AND operation on the second chip select even signal and the intermediate clock even signal to obtain the chip select clock even signal.
  • the second logic circuit 422 may include a second buffer and a second AND gate; wherein,
  • the second buffer is used to delay the odd clock signal to obtain the intermediate odd clock signal
  • the second AND gate is used to AND the second chip select odd signal and the intermediate clock odd signal to obtain the chip select clock odd signal.
  • the buffer whether it is the first buffer or the second buffer, not only has a delay function, but also has the function of enhancing the signal driving capability. Specifically, for the intermediate clock even signal and the clock even signal, the intermediate clock even signal not only has a delay compared with the clock even signal, but also the intermediate clock even signal has a stronger driving ability; while for the intermediate clock odd signal and the clock odd signal Generally speaking, the odd clock signal in the middle has a delay compared with the odd clock signal, and the odd clock signal in the middle has a stronger driving ability.
  • the chip select clock even signal CS_CLK_E is obtained through the first logic circuit 421
  • the chip select clock odd signal CS_CLK_O is obtained through the second logic circuit 422 .
  • the instruction decoding circuit 43 and the combined output circuit 44 are relatedly processed according to the two signals of the chip select clock even signal CS_CLK_E and the chip select clock odd signal CS_CLK_O, so that the first target address signal is finally output , timing alignment of the second target address signal and the target command signal.
  • the first chip select signal is a signal indicating that the target chip is selected, and the first chip select signal is an active low-level pulse signal;
  • the middle sampled even signal and the second chip select odd signal are high-level pulse signals, and the chip select clock odd signal is high level.
  • the even clock period or the odd clock period refers to the clock period of the initial clock signal CK_t/CK_c.
  • the odd clock signal PCLK_E and the even clock signal PCLK_O can be obtained; then the clock cycle where the rising edge of the even clock signal PCLK_E is located is regarded as the even clock cycle, and the odd clock signal PCLK_E is The clock cycle where the rising edge of PCLK_O is located is regarded as the odd clock cycle.
  • the first logic circuit 421 and the second logic circuit 422 are used so that when the chip select clock is odd, Among the two signals, signal CS_CLK_O and chip select clock even signal CS_CLK_E, only one signal is a valid signal with a high level, and the other signal is an invalid signal (low level signal). In this way, by shielding the first clock signal (even clock signal PCLK_E or odd clock signal PCLK_O) when the second chip select signal is low level (ie, no command), unnecessary clock signal oscillation can be reduced and power consumption can be saved. function.
  • the instruction decoding circuit 43 may include a first instruction decoding circuit 431, a second instruction decoding circuit 432, and an OR gate 433; wherein,
  • the first instruction decoding circuit 431 is used to decode and sample the initial instruction odd signal according to the chip select clock even signal and the second chip select even signal to obtain the instruction even signal;
  • the second instruction decoding circuit 432 is used to decode and sample the initial instruction even signal according to the chip select clock odd signal and the second chip select odd signal to obtain the instruction odd signal;
  • the OR gate 433 is used to perform an OR operation on the even command signal and the odd command signal to obtain the target command signal.
  • the target command signal here can be represented by CMD
  • the even command signal can be represented by CMD_E
  • the odd command signal can be represented by CMD_O.
  • the target command signal CMD is obtained by performing an OR logic operation on the command even signal CMD_E and the command odd signal CMD_O.
  • the even command signal CMD_E is decoded and sampled by the first command decoding circuit 431
  • the odd command signal CMD_O is decoded and sampled by the second command decoding circuit 432 .
  • the first instruction decoding circuit 431 may include a first decoding circuit, a seventh sampling circuit and a third AND gate; wherein,
  • the first decoding circuit is used to decode the initial instruction odd signal to obtain the instruction decoding odd signal
  • the seventh sampling circuit is used to sample the instruction decoding odd signal according to the even signal of the chip select clock to obtain the instruction sampling even signal;
  • the third AND gate is used to perform an AND operation on the second chip selection even signal and the instruction sampling even signal to obtain the instruction even signal.
  • the initial command odd signal CA[4:0]_1T_O can include command signals such as CA[0]_O, CA[1]_O, CA[2]_O, CA[3]_O, CA[4]_O etc.
  • the first decoding circuit is also composed of a two-input NAND gate, a three-input NAND gate and a two-input NOR gate.
  • CA[0]_O and CA[1]_O are input to the two-input NAND gate
  • CA[2]_O, CA[3]_O and CA[4]_O are input to the three-input NAND gate.
  • the output of the two-input NAND gate and the output of the three-input NAND gate will be connected to the input of the two-input NOR gate, and the output of the two-input NOR gate is used to output the instruction decoding odd signal, Thus, the decoding of the initial instruction odd signal is achieved.
  • the specific design of the first instruction decoding circuit 431 and the second instruction decoding circuit 432 is determined based on the instruction decoding rules. For different products/different application scenarios/different instructions, the decoding rules may be different. , then the logic of the instruction decoding circuit can also be adjusted accordingly.
  • the seventh sampling circuit may also be a D-type flip-flop.
  • the clock terminal of the D-type flip-flop is connected to the chip select clock even signal CS_CLK_E, and the input terminal of the D-type flip-flop is connected to the output terminal of the two-input NOR gate, which is used to receive the instruction decoding odd signal.
  • the output terminal of the D-type flip-flop is connected to one input terminal of the third AND gate, and the second chip select signal PCS_ED is connected to the other input terminal of the third AND gate, so that the output terminal of the third AND gate is used for output Command even signal CMD_E, so that after sampling the instruction decoding odd signal, the third AND gate can also ensure that only when the second chip select even signal PCS_ED is high level, the command even signal CMD_E can be obtained.
  • the second instruction decoding circuit 432 includes a second decoding circuit, an eighth sampling circuit, and a fourth AND gate; wherein,
  • the second decoding circuit is used to decode the initial instruction even signal to obtain the instruction decoding even signal
  • the eighth sampling circuit is used to sample the instruction decoding even signal according to the chip select clock odd signal to obtain the instruction sampling odd signal;
  • the fourth AND gate is used to AND the second chip select odd signal and the instruction sampling odd signal to obtain the instruction odd signal.
  • the initial command even signal CA[4:0]_1T_E can include command signals such as CA[0]_E, CA[1]_E, CA[2]_E, CA[3]_E, CA[4]_E etc.
  • the first decoding circuit may be composed of a two-input NAND gate, a three-input NAND gate and a two-input NOR gate.
  • CA[0]_E and CA[1]_E are input to the two-input NAND gate
  • CA[2]_E, CA[3]_E and CA[4]_E are input to the three-input NAND gate.
  • the output terminal of the two-input NAND gate and the output terminal of the three-input NAND gate are respectively connected to the input terminal of the two-input NOR gate, and the output terminal of the two-input NOR gate is used to output the instruction decoding even signal,
  • the decoding of the initial command even signal CA[4:0]_1T_E is achieved.
  • the eighth sampling circuit may also be a D-type flip-flop.
  • the clock terminal of the D-type flip-flop is connected to the chip select clock odd signal CS_CLK_O, and the input terminal of the D-type flip-flop is connected to the output terminal of the two-input NOR gate, which is used to receive the instruction decoding even signal.
  • the output terminal of the D-type flip-flop is connected to one input terminal of the fourth AND gate, and the second chip select odd signal PCS_OD is connected to the other input terminal of the fourth AND gate, so that the output terminal of the fourth AND gate is used for output
  • the command odd signal CMD_O so that after sampling the command decoding even signal, the fourth AND gate can also ensure that only when the second chip select odd signal PCS_OD is high level, the command odd signal CMD_O can be obtained, which ensures that the command even signal There is only one valid signal among the signal CMD_E and the command odd signal CMD_O.
  • the chip select clock even signal CS_CLK_E and the chip select clock odd signal CS_CLK_O is a high-level active pulse signal. If the chip select clock even signal CS_CLK_E is a high-level valid pulse signal, at this time, because the chip select clock odd signal CS_CLK_O is a low-level signal, the sampling process of the second instruction decoding circuit 432 will not be executed, that is, the instruction odd signal CMD_O is a low-level signal, then the command even signal CMD_E and the low-level signal obtained at this time are ORed through the OR gate 433, and the output is still the command even signal CMD_E signal; in other words, the command even signal CMD_E signal obtained at this time is is the target command signal CMD.
  • the chip select clock odd signal CS_CLK_O is a high-level valid pulse signal
  • the chip select clock even signal CS_CLK_E is a low-level signal
  • the sampling process of the first instruction decoding circuit 431 will not be executed, that is, the instruction even signal will not be executed.
  • the signal CMD_E is a low-level signal
  • the command odd signal CMD_O and the low-level signal obtained at this time are ORed through the OR gate 433, and the output is still the command odd signal CMD_O signal; in other words, the command odd signal CMD_O obtained at this time
  • the signal is the target command signal CMD.
  • the combined output circuit 44 includes a first combined output circuit 441 and a second combined output circuit 442; wherein,
  • the first combined output circuit 441 is used to sample the second command address even signal according to the chip select clock odd signal to obtain the first target address signal; or, to sample the second command address odd signal according to the chip select clock even signal, Get the first target address signal;
  • the second combined output circuit 442 is used to sample the second command address odd signal according to the chip select clock odd signal to obtain the second target address signal; or, to sample the second command address even signal according to the chip select clock even signal, Get the second target address signal.
  • the first combined output circuit 441 and the second combined output circuit 442 can also be called combined output flip-flops, represented by Output Combined DFF.
  • the internal circuit structures of the two are the same, but the pins and signal connections are different.
  • the combined output flip-flop includes two data terminals and two clock terminals. While using the signal of the first clock terminal to sample the signal of the first data terminal, it also uses the signal of the second clock terminal to sample the second The signal at the data end is sampled.
  • the first target address signal here is represented by CA[13:0]_0T
  • the second target address signal here is represented by CA[13:0]_1T.
  • the first data terminal is connected to the second command address odd signal CA[13:0]_1T_O
  • the second data terminal is connected to the second command address even signal CA[13 :0]_1T_E is connected
  • the first clock terminal is connected to the chip select clock even signal CS_CLK_E
  • the second clock terminal is connected to the chip select clock odd signal CS_CLK_O.
  • the chip select clock even signal CS_CLK_E can be used to sample the second command address odd signal CA[13:0]_1T_O
  • the chip select clock odd signal CS_CLK_O can be used to sample the second command address even signal CA[13:0]_1T_E.
  • Sampling is performed to obtain the first target address signal CA[13:0]_0T. It should be understood that since only one of the chip select clock even signal CS_CLK_E and the chip select clock odd signal CS_CLK_O is valid, the first combining circuit 441 will only output one valid sampling result, so that it can be used to transmit the odd and even sampling results respectively. The parity and even address outputs are combined into a single sample output, thus reducing the address bus in half.
  • the first data terminal is connected to the second command address odd signal CA[13:0]_1T_O
  • the second data terminal is connected to the second command address even signal CA[13 :0]_1T_E is connected
  • the first clock terminal is connected to the chip select clock odd signal CS_CLK_O
  • the second clock terminal is connected to the chip select clock even signal CS_CLK_E.
  • the chip select clock odd signal CS_CLK_O can be used to sample the chip select clock odd signal CA[13:0]_1T_O
  • the chip select clock even signal CS_CLK_E can be used to sample the chip select clock even signal CA[13:0]_1T_E.
  • the second target address signal CA[13:0]_1T is obtained. It should be understood that since only one of the chip select clock even signal CS_CLK_E and the chip select clock odd signal CS_CLK_O is valid, the second combining circuit 442 will also only output one valid sampling result, so that the parity and even samples can be transmitted separately. The resulting parity and even address outputs are combined into a single sample output, thus reducing the address bus by half.
  • the first combining output circuit 441 outputs the sampling result of the first command address signal CA in the first clock cycle
  • the second combining output circuit 442 outputs the sampling result of the first command address signal CA in the second clock cycle.
  • the sampling results are as follows:
  • the first chip select signal PCS is in an active low state in the even-numbered clock cycle corresponding to C0, it means that C0 and C1 are valid first command address signals CA.
  • the second command address even signal CA[13:0]_1T_E obtained by sampling the even clock signal includes C0 and C2
  • the second command address odd signal CA[13:0]_1T_O obtained by sampling the odd clock signal includes C1 and C3.
  • the second command address even signal CA[13:0]_1T_E is sampled through the chip select clock odd signal CS_CLK_O to obtain C0, and the chip select clock odd signal CS_CLK_O is used to sample CA[13: 0]_1T_O sampling will get C1.
  • the first combining output circuit 441 samples the valid information C0 of CA in the first clock cycle
  • the second combining output circuit 442 samples the valid information C1 of CA in the second clock cycle.
  • the first chip select signal PCS is in the active low state in the odd clock cycle corresponding to C1, it means that C1 and C2 are valid CA signals.
  • the second command address even signal CA[13:0]_1T_E obtained by sampling the even clock signal includes C2 and C4
  • the second command address odd signal CA[13:0]_1T_O obtained by sampling the odd clock signal includes C1 and C3.
  • the chip select clock even signal CS_CLK_E since the chip select clock even signal CS_CLK_E is valid, the second command address odd signal CA[13:0]_1T_O is sampled through the chip select clock even signal CS_CLK_E to obtain C1, and the second command address is sampled through the chip select clock even signal CS_CLK_E.
  • Even signal CA[13:0]_1T_E sampling will get C2.
  • the first combined output circuit 441 samples the valid information C1 of the first command address signal CA in the first clock cycle
  • the second combined output circuit 442 samples the second command address odd signal CA in the second clock cycle. Valid information of the cycle C2.
  • the even clock period or the odd clock period refers to the clock period of the initial clock signal CK_t/CK_c.
  • the odd clock signal PCLK_E and the even clock signal PCLK_O can be obtained; then the clock cycle where the rising edge of the even clock signal PCLK_E is located is regarded as the even clock cycle, and the odd clock signal PCLK_O is The clock cycle where the rising edge is located is regarded as the odd clock cycle.
  • the first combining output circuit 441 always outputs the valid information of CA in the first clock cycle, that is, the first target address signal CA[13:0]_OT; the second combining output circuit 442 always outputs the valid information of CA in the second clock cycle.
  • the valid information of the clock cycle is the second target address signal CA[13:0]_1T.
  • the first combined output circuit 441 includes a third logic circuit, a fourth logic circuit and a ninth sampling circuit; wherein,
  • the third logic circuit is used to perform logical operations on the chip select clock odd signal to obtain the first enabled odd signal and the second enabled odd signal, and the phase between the first enabled odd signal and the second enabled odd signal The difference is 180 degrees;
  • the fourth logic circuit is used to perform logical operations on the chip select clock even signal to obtain the first enable even signal and the second enable even signal, and the phase between the first enable even signal and the second enable even signal The difference is 180 degrees;
  • the ninth sampling circuit is used to perform sampling on the second command address even signal and the second command address odd signal according to the first enable even signal, the second enable even signal, the first enable odd signal and the second enable odd signal. Sampling processing is performed to obtain the first target address signal.
  • the third logic circuit may be composed of an inverter and a buffer.
  • the first enable even signal can be represented by CLKB_E
  • the second enable even signal can be represented by CLKT_E
  • the phase difference between the first enable even signal and the second enable even signal is 180 degrees.
  • the fourth logic circuit may also be composed of an inverter and a buffer.
  • the first enabled odd signal can be represented by CLKB_O
  • the second enabled odd signal can be represented by CLKT_O
  • the phase difference between the first enabled odd signal and the second enabled odd signal is 180 degrees.
  • CA_E which represents CA[0]_E, CA[1]_E, CA[2]_E, ..., CA[13]_E, etc. 14 signals
  • CA_O represents a total of 14 signals such as CA[0]_O, CA[1]_O, CA[2]_O,..., CA[13]_O, etc.
  • the ninth sampling circuit may be composed of several enable inverters and several inverters.
  • the first enable even signal CLKB_E and the second enable even signal CLKT_E are used to sample the CA[0]_O signal; and the first enable odd signal CLKB_O and the second enable odd signal CLKT_O are used to perform sampling processing on the CA[0 ]_E signal is sampled and processed, and the final output first target address signal is represented by CA[0]_0T.
  • Figure 9 shows a schematic diagram of a specific circuit structure of an enable inverter (represented by Enable Inverter).
  • an enable inverter represented by Enable Inverter
  • (a) is the device symbol of the enabled inverter
  • (b) is the specific composition of the enabled inverter.
  • the input signal is represented by IN
  • the output signal is represented by OUT
  • the enable signal is represented by EN.
  • the enable signal EN is high level
  • the inverter is enabled to work, that is, the input signal IN needs to be inverted to obtain the output signal OUT
  • the input signal EN is low level
  • the inverter is enabled to turn off, and the inverter output is in a high impedance state.
  • the ninth sampling circuit is specifically used to perform the processing according to the first pulse signal when the chip select clock even signal is a high-level pulse signal.
  • the first enable even signal and the second enable even signal sample and process the second command address odd signal to obtain the first target address signal; or, when the chip select clock odd signal is a high-level pulse signal, according to
  • the first enable odd signal and the second enable odd signal perform sampling processing on the second command address even signal to obtain the first target address signal.
  • the working principle of the ninth sampling circuit shown in Figure 8A is as follows: when the CLKB_O signal is high level, the CA[0]_E signal is received through an enabled inverter and the subsequent inverter Inverter, transmit the signal to the node after the inverter, and then output the signal when the CLKT_O signal is high level, so it shows the effect of sampling on the rising edge of the CLKT_O signal; or, when the CLKB_E signal is high level, Receive the CA[0]_O signal, transmit the signal to the node after the inverter through an enable inverter and the following inverter, and then output the signal when the CLKT_E signal is high level, Therefore, the effect of sampling on the rising edge of the CLKT_E signal is shown; finally, the two inverters connected end to end at the CA[0]_0T signal play the role of maintaining the signal.
  • the CLKT_E sampling part and the Among the CLKT_O sampling parts only one part works, and the other part outputs a high-impedance state.
  • the final CA[0]_0T can output the result of the working part.
  • the second combined output circuit 442 includes a fifth logic circuit, a sixth logic circuit, and a tenth sampling circuit; wherein,
  • the fifth logic circuit is used to perform logical operations on the chip select clock even signal to obtain the third enable even signal and the fourth enable even signal;
  • the sixth logic circuit is used to perform logical operations on the chip select clock odd signal to obtain the third enable odd signal and the fourth enable odd signal;
  • the tenth sampling circuit is used to perform sampling on the second command address even signal and the second command address odd signal according to the third enable even signal, the fourth enable even signal, the third enable odd signal and the fourth enable odd signal. Sampling processing is performed to obtain the second target address signal.
  • the fifth logic circuit may be composed of an inverter and a buffer.
  • the third enable even signal can be represented by CLKB_E
  • the fourth enable even signal can be represented by CLKT_E
  • the phase difference between the third enable even signal and the fourth enable even signal is 180 degrees.
  • the sixth logic circuit may also be composed of an inverter and a buffer.
  • the third enabled odd signal can be represented by CLKB_O
  • the fourth enabled odd signal can be represented by CLKT_O
  • the phase difference between the third enabled odd signal and the fourth enabled odd signal is 180 degrees.
  • the tenth sampling circuit is specifically used to perform the processing according to the first pulse signal when the even signal of the chip select clock is a high-level pulse signal.
  • the third enable even signal and the fourth enable even signal sample and process the second command address even signal to obtain the second target address signal; or, when the odd signal of the chip select clock is a high-level pulse signal, according to
  • the third enable odd signal and the fourth enable odd signal sample and process the second command address odd signal to obtain the second target address signal.
  • CA_E which represents CA[0]_E, CA[1]_E, CA[2]_E, ..., CA[13]_E, etc. 14 signals
  • CA_O represents a total of 14 signals such as CA[0]_O, CA[1]_O, CA[2]_O,..., CA[13]_O, etc.
  • the tenth sampling circuit may be composed of several enabled inverters and several inverters.
  • the third enable even signal CLKB_E and the fourth enable even signal CLKT_E are used to sample the CA[0]_E signal; and the third enable odd signal CLKB_O and the fourth enable odd signal CLKT_O are used to perform sampling processing on the CA[0 ]_O signal is sampled and processed, and the final output second target address signal is represented by CA[0]_1T.
  • the first target signal and the second target address signal are output through the first combining output circuit 441 and the second combining output circuit 442.
  • the first target address signal includes the information of the first command address signal in the first clock cycle
  • the second target address signal includes the information of the first command address signal in the second clock cycle
  • the first clock cycle refers to The clock cycle when the first chip select signal is low level
  • the second clock cycle is the next clock cycle of the first clock cycle.
  • the signal sampling circuit 40 provided by the embodiment of the present disclosure is applied to the instruction signal of 2 clock cycles.
  • the first command address signal CA includes valid signals of two clock cycles
  • the first target address signal CA_[13:0]_OT is the sampling result of the valid signal of the first command address signal CA in the first clock cycle
  • the second target address signal CA_[13:0]_1T is the sampling result of the valid signal of CA in the second clock cycle. It should be understood that the clock cycle is determined based on the initial clock signal CK_t/CK_c before frequency division.
  • the first command address signal can be sampled and decoded according to the effective chip select clock signal to obtain the target instruction signal; through the first combined output
  • the circuit can sample the first command address signal according to the effective chip select clock signal to obtain the first target address signal; through the second combined output circuit, the first command address signal can be sampled according to the effective chip select clock signal,
  • the second target address signal is obtained so that the first target address signal, the second target address signal and the target instruction signal are timing aligned.
  • the odd and even sampled address buses can also be combined, thereby halving the number of address buses.
  • Embodiments of the present disclosure provide a signal sampling circuit.
  • the signal sampling circuit includes an input sampling circuit, a logic operation circuit, an instruction decoding circuit and a combined output circuit; wherein the input sampling circuit is used to separately analyze the first clock signal according to the first clock signal.
  • the chip select signal and the first command address signal are sampled and processed to obtain the second chip select signal and the second command address signal; wherein the second command address signal includes the initial command signal, and the second command address signal is composed of the second command address signal.
  • a logic operation circuit is used to perform logical operations on the first clock signal and the second chip select signal to obtain a chip select clock signal; wherein, the chip select clock signal includes an odd signal of the chip select clock and the chip select clock even signal; the instruction decoding circuit is used to decode and sample the initial instruction signal according to the second chip select signal and the chip select clock signal to obtain the target instruction signal; and the combined output circuit is used to decode and sample the initial instruction signal according to the chip select signal.
  • the even signal of the select clock and the odd signal of the chip select clock respectively sample and process the odd signal of the second command address and the even signal of the second command address to obtain the first target address signal; and respectively use the odd signal of the chip select clock and the even signal of the chip select clock to obtain the first target address signal.
  • the second command address odd signal and the second command address even signal are sampled and processed to obtain a second target address signal.
  • the timing between the target instruction signal, the first target address signal and the second target address signal is aligned. In this way, based on the signal sampling circuit, under the sampling of the same clock cycle, the timing alignment of the target instruction signal, the first target address signal and the second target address signal can be achieved, so that there is no gap between the decoded instruction signal and the address signal.
  • the signal sampling circuit 40 may include a first receiver 601, a second receiver 602, a third receiver 603, a first sampling circuit 604, a second sampling circuit 605, a third sampling circuit 606, a fourth Sampling circuit 607, fifth sampling circuit 608, sixth sampling circuit 609, first buffer 610, first AND gate 611, second buffer 612, second AND gate 613, instruction decoding flip-flop 614, OR gate 615 , the first combined output flip-flop 616, the second combined output flip-flop 617, the first functional module 618, the second functional module 619 and the third functional module 620.
  • the first sampling circuit 604, the second sampling circuit 605, the fourth sampling circuit 607 and the sixth sampling circuit 609 are composed of D-type flip-flops
  • the third sampling circuit 606 and the fifth sampling circuit 608 are composed of D-type flip-flops.
  • an inverter in addition, the instruction decoding flip-flop 614 may include a first instruction decoding circuit and a second instruction decoding circuit.
  • the specific structure is shown in Figure 7A and Figure 7B; the first combined output flip-flop 617
  • the internal structure of the second combined output flip-flop 618 is shown in FIG. 8A for details.
  • the internal structure of the second combined output flip-flop 618 is shown in FIG. 8B for details.
  • the input signal of the first receiver 601 is the initial command address signal (expressed by CA[13:0]) and the reference signal (expressed by VREFCA), and the output signal is the first command address signal (expressed by CA represents);
  • the initial command address signal CA[13:0] is not a signal, but represents a group of signals, that is, CA[13:0] includes CA[13] ⁇ CA[0 ];
  • Each signal requires a first receiver 601, so the embodiment of the present disclosure requires 14 first receivers 601, and only one first receiver 601 is shown in the figure as an illustration;
  • the input of the second receiver 602 The signals are the initial chip select signal (expressed by CS_n) and the reference signal (expressed by VREFCA), and the output signal is the first chip select signal (expressed by PCS);
  • the input signal of the third receiver 603 is the initial clock signal (expressed by CK_t/ CK_c), after frequency division processing, the output signal is an even clock signal (represented by PCLK_E) and an
  • the first command address signal is sampled using the clock odd signal to obtain the second command address odd signal (represented by CA[13:0]_1T_O), and the second command address odd signal includes The initial command odd signal (represented by CA[4:0]_1T_O);
  • the first command address signal is sampled using the clock even signal to obtain the second command address even signal (represented by CA[13: 0]_1T_E), and the second command address even signal includes the initial command even signal (represented by CA[4:0]_1T_E);
  • the clock odd signal is used to sample the first chip select signal and Invert the phase processing to obtain the intermediate sampling odd signal (represented by PCS_O).
  • the intermediate sampling odd signal is sampled using the clock even signal to obtain the second chip selection even signal (represented by PCS_ED); through the fourth sampling circuit 607,
  • the five-sampling circuit 608 uses the clock even signal to sample and invert the first chip select signal to obtain an intermediate sampled even signal (represented by PCS_E).
  • the sixth sampling circuit 609 uses the clock odd signal to perform sampling and inversion processing on the intermediate sampled even signal.
  • Sampling process to obtain the second chip select odd signal (represented by PCS_OD); then use the first buffer 610 and the first AND gate 611 to perform logical operations on the clock even signal and the second chip select even signal to obtain the chip select clock even signal (denoted by CS_CLK_E); use the second buffer 612 and the second AND gate 613 to perform logical operations on the odd clock signal and the second odd chip select signal to obtain the odd chip select clock signal (denoted by CS_CLK_O).
  • the even signal of the chip select clock and the odd signal of the chip select clock are used to decode and decode the initial instruction even signal, the initial instruction odd signal, the second chip select even signal and the second chip select odd signal.
  • Sampling processing is performed to obtain the instruction even signal (represented by CMD_E) and the instruction odd signal (represented by CMD_O), and then the OR gate 615 is used to perform an OR logic operation on the instruction even signal and the instruction odd signal to obtain the target instruction signal (represented by CMD).
  • the specific working principle of the instruction decoder 614 can be referred to the foregoing embodiments and will not be described in detail here; and through the first combined output flip-flop 616, the even signal of the chip select clock is used to sample the odd signal of the second command address, and at the same time, the odd signal of the second command address is sampled.
  • the odd signal of the chip select clock samples the even signal of the second command address, and the effective sampling result obtained is the first target address signal (represented by CA[13:0]_0T); through the second combined output flip-flop 617, the second combined output flip-flop 617 is used.
  • the even signal of the second command address samples the even signal of the second command address, and the odd signal of the second command address is used to sample the odd signal of the second command address at the same time.
  • the effective sampling result obtained is the second target address signal (using CA[13 :0]_1T means).
  • the target command signal CMD, the first target address signal CA[13:0]_0T and the second target address signal CA[13:0]_1T are all based on the effective chip select clock signal (chip select clock odd signal CS_CLK_O or The chip select clock even signal CS_CLK_E) is sampled and output, so the timing of the target command signal CMD, the first target address signal CA[13:0]_OT and the second target address signal CA[13:0]_1T are aligned.
  • the target command signal CMD, the first target address signal CA[13:0]_0T and the second target address signal CA[13:0]_1T all reach the first functional module 618, The second functional module 619 and the third functional module 620.
  • the target command signal CMD, the first target address signal CA[13:0]_0T and the second target address signal CA[13:0]_1T have been time-aligned, it is necessary to control the target command signal CMD and the first target address signal
  • the long trace paths of CA[13:0]_0T and the second target address signal CA[13:0]_1T should be as consistent in length and width as possible.
  • the target command signal CMD, the first target address signal CA[13:0]_OT and the second target address signal CA[13:0]_1T are aligned, the target command signal CMD, the first target address signal When CA[13:0]_0T and the second target address signal CA[13:0]_1T reach different functional modules to implement the next level function, there will be no errors due to timing deviation.
  • the initial chip select signal is sampled at an even-numbered clock cycle and exhibits an active low level.
  • the signal timing diagram of the signal sampling circuit shown in Figure 10 is as shown in Figure 11.
  • the first command address signal CA may include Cy, Cz, C0, C1, C2 and C3
  • the initial chip select signal is represented by CS_n
  • the first chip select signal is represented by PCS
  • the PCS signal is low-level active Pulse signal
  • the pulse width is the preset clock cycle.
  • PCS is used to represent the signal that the target chip is selected; for the description of other signals, please refer to the above.
  • the even clock period or the odd clock period refers to the clock period of the initial clock signal CK_t/CK_c.
  • the odd clock signal PCLK_E and the even clock signal PCLK_O can be obtained; then the clock cycle where the rising edge of the even clock signal PCLK_E is located is regarded as the even clock cycle, and the odd clock signal PCLK_E is The clock cycle where the rising edge of PCLK_O is located is regarded as the odd clock cycle.
  • the second command address even signal CA[13:0]_1T_E is obtained, which includes C0 and C2; after using the rising edge of the clock odd signal PCLK_O After sampling the CA signal along the edge, the second command address odd signal CA[13:0]_1T_O is obtained, which includes C1 and C3.
  • the initial command even signal CA[4:0]_1T_E is included in CA[13:0]_1T_E.
  • the intermediate sampling even signal PCS_E is obtained, and the rising edge of the clock odd signal PCLK_O is used to sample the intermediate sampling even signal PCS_E.
  • the second chip select odd signal PCS_OD is obtained.
  • the intermediate sampling odd signal PCS_O is obtained; and using the rising edge of the clock even signal PCLK_E to sample the intermediate sampling odd signal PCS_O, we get The second chip select signal PCS_ED.
  • the first chip select signal PCS is active at low level when sampled in even clock cycles, so the middle sampled even signal PCS_E and the second odd chip select signal PCS_OD are both active high level pulse signals, and the pulse width is 2 clock cycles.
  • the chip select clock odd signal CS_CLK_O is obtained, which is a high-level active pulse signal.
  • the pulse width is 1 clock cycle.
  • the aforementioned instruction decoding flip-flop 614 is used, the chip select clock odd signal CS_CLK_O is used as the effective clock signal, the decoded CA[4:0]_1T_E is sampled, and the target instruction signal CMD signal is output; the aforementioned first combination is used
  • the output flip-flop 616 uses the chip select clock odd signal CS_CLK_O as the effective clock signal, samples the second command address even signal CA[13:0]_1T_E, and outputs the first target address signal CA[13:0]_0T; using the aforementioned third
  • the two combined output flip-flops 617 use the chip select clock odd signal CS_CLK_O as the effective clock signal, sample the second command address odd signal CA[13:0]_1T_O, and output the second target address signal CA[13:0]_1T, so that the target Timing alignment between the command signal CMD, the first target address signal CA[13:0]_OT and the second target address signal CA[13:0]_
  • the initial chip select signal is active low when sampled in even clock cycles, so the middle sampled odd signal PCS_O and the second chip select even signal PCS_ED are both invalid signals.
  • the chip select clock even signal CS_CLK_E is also an invalid signal. From the instruction decoding flip-flop 614 and the first combination The output flip-flop 617 and the second combined output flip-flop 618 do not use the chip select clock even signal CS_CLK_E to perform sampling output.
  • the middle sampling odd signal PCS_O, the second chip select even signal PCS_ED, and the chip select clock even signal CS_CLK_E will be in a valid state, from the instruction decoding flip-flop 614, the first combined output flip-flop 616 and the second combined output flip-flop 617 Sampling and output will be performed according to the chip select clock even signal CS_CLK_E to obtain the target command signal CMD, the first target address signal CA[13:0]_0T and the second target address signal CA[13:0]_1T respectively.
  • the target command signal CMD, the first target address signal CA[13:0]_OT, and the second target address signal CA[13:0]_1T are also time-aligned.
  • the chip select clock odd signal CS_CLK_O or the chip select clock even signal CS_CLK_E can be used for sampling, so that the target command signal CMD, the first target address signal CA[13:0]_OT and the second target address signal CA[13:0]
  • the output timing between _1T is aligned, thereby allowing the target command signal CMD, the first target address signal CA[13:0]_0T and the second target address signal CA[13:0]_1T to reach different functional modules to implement the next level There will be no errors due to timing deviation during function.
  • the embodiment of the present disclosure provides a signal sampling circuit.
  • the specific implementation of the foregoing embodiment is described in detail through this embodiment. It can be seen that the embodiment of the present disclosure is optimized based on the existing direct sampling decoding. , so that there is no Skew that changes with PVT between the decoded instruction (target instruction signal) and the sampled address (first target address signal and second target address signal).
  • the target command signal CMD, the first target address signal CA[13:0]_OT and the second target address signal CA[13:0]_1T can be aligned; and through the first combined output flip-flop and the first combined output flip-flop provided by the embodiment of the present disclosure, The two-merging output flip-flop merges the odd and even sampled address buses and retains only the valid address buses, thus halving the number of address buses.
  • FIG. 12 shows a schematic structural diagram of a semiconductor memory 120 provided by an embodiment of the present disclosure.
  • the semiconductor memory 120 may include the signal sampling circuit 40 described in any of the previous embodiments.
  • the semiconductor memory 120 may be a DRAM chip.
  • the DRAM chip complies with DDR5 memory specifications.
  • the embodiments of the present disclosure mainly relate to circuits related to input signal sampling and instruction decoding in integrated circuit design, especially in DRAM chips, where the CA signal input is used as instruction and address sampling respectively, and the control and adjustment circuit after decoding. .
  • the embodiment of the present disclosure is optimized for 2T CMD based on the existing direct sampling decoding, so that the decoded target command signal CMD and the sampled first target address signal CA[13:0] There is no deviation with PVT between _OT and the second target address signal CA[13:0]_1T.
  • the semiconductor memory 120 includes the signal sampling circuit 40. Therefore, under the sampling of the same clock cycle, the target instruction signal, the first target address signal and the second target address can be realized.
  • the timing alignment of the signals ensures that there is no deviation between the decoded command signal and the address signal following PVT changes, thereby avoiding problems in the next-level functional modules due to timing deviations.
  • Embodiments of the present disclosure provide a signal sampling circuit and a semiconductor memory, including: an input sampling circuit that samples the first chip select signal and the first command address signal according to the first clock signal to obtain the second chip select signal and the first command address signal.
  • the second command address signal ;
  • the logic operation circuit performs logical operations on the first clock signal and the second chip select signal to obtain the chip select clock signal;
  • the instruction decoding circuit performs the initial instruction according to the second chip select signal and the chip select clock signal.
  • the signal is decoded and sampled to obtain the target command signal;
  • the output circuit is combined to sample the second command address odd signal and the second command address even signal according to the chip select clock even signal and the chip select clock odd signal to obtain the first target address.
  • signal sample the second command address odd signal and the second command address even signal according to the chip select clock odd signal and the chip select clock even signal to obtain the second target address signal.
  • Embodiments of the present disclosure can improve signal timing deviation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本公开实施例提供了一种信号采样电路以及半导体存储器，包括：输入采样电路，根据第一时钟信号分别对第一片选信号和第一命令地址信号进行采样处理，得到第二片选信号和第二命令地址信号；逻辑运算电路，对第一时钟信号和第二片选信号进行逻辑运算，得到片选时钟信号；指令译码电路，根据第二片选信号和片选时钟信号对初始指令信号进行译码和采样，得到目标指令信号；合并输出电路，根据片选时钟偶信号和片选时钟奇信号对第二命令地址奇信号和第二命令地址偶信号进行采样，得到第一目标地址信号；根据片选时钟奇信号和片选时钟偶信号对第二命令地址奇信号和第二命令地址偶信号进行采样，得到第二目标地址信号。本公开实施例能够改善信号时序偏差。

Description

一种信号采样电路以及半导体存储器
相关申请的交叉引用
本公开要求在2022年03月23日提交中国专利局、申请号为202210291688.8、申请名称为“一种信号采样电路以及半导体存储器”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种信号采样电路以及半导体存储器。
背景技术
随着半导体技术的不断发展，人们在制造和使用计算机等设备时，对数据的传输速度提出了越来越高的要求。为了获得更快的数据传输速度，应运而生了一系列数据可以双倍速率(Double Data Rate，DDR)传输的存储器等器件。
在动态随机存取存储器(Dynamic Random Access Memory，DRAM)中，命令地址信号不仅需要作为地址信号被采样，还需要作为指令信号被采样和译码。特别地，在命令地址信号被设计为2个时钟周期信号的情况下，不仅地址信号和指令译码信号之间容易产生时序偏差，而且涉及的地址总线数量多，造成电路面积大。
发明内容
第一方面，本公开实施例提供了一种信号采样电路，所述信号采样电路包括输入采样电路、逻辑运算电路、指令译码电路和合并输出电路；其中，
所述输入采样电路，用于根据第一时钟信号分别对第一片选信号和第一命令地址信号进行采样处理，得到第二片选信号和第二命令地址信号；其中，所述第二命令地址信号包括初始指令信号，且所述第二命令地址信号由第二命令地址奇信号和第二命令地址偶信号组成；
所述逻辑运算电路，用于对所述第一时钟信号和所述第二片选信号进行逻辑运算，得到片选时钟信号；其中，所述片选时钟信号包含片选时钟奇信号和片选时钟偶信号；
所述指令译码电路，用于根据所述第二片选信号和所述片选时钟信号对所述初始指令信号进行译码处理和采样处理，得到目标指令信号；
所述合并输出电路，用于根据所述片选时钟偶信号和所述片选时钟奇信号分别对所述第二命令地址奇信号和所述第二命令地址偶信号进行采样处理，得到第一目标地址信号；并根据所述片选时钟奇信号和所述片选时钟偶信号分别对所述第二命令地址奇信号和所述第二命令地址偶信号进行采样处理，得到第二目标地址信号。
在一些实施例中，所述信号采样电路还包括接收电路，且所述接收电路包括第一接收电路、第二接收电路和第三接收电路；其中，
所述第一接收电路，用于接收初始命令地址信号，输出所述第一命令地址信号；
所述第二接收电路，用于接收初始片选信号，输出所述第一片选信号；
所述第三接收电路，用于接收初始时钟信号，并对所述初始时钟信号进行分频处理，得到时钟奇信号和时钟偶信号；
其中，所述时钟奇信号和所述时钟偶信号的时钟周期均是所述初始时钟信号的时钟周期的两倍，且所述时钟奇信号和所述时钟偶信号之间的相位差为180度，所述时钟奇信号和所述时钟偶信号组成所述第一时钟信号。
在一些实施例中，所述输入采样电路包括命令地址采样电路，且所述命令地址采样电路包括第一采样电路和第二采样电路；其中，
所述第一采样电路，用于根据所述时钟奇信号对所述第一命令地址信号进行采样，得到所述第二命令 地址奇信号；
所述第二采样电路，用于通过所述时钟偶信号对所述第一命令地址信号进行采样，得到所述第二命令地址偶信号；
其中，所述初始指令信号是由初始指令偶信号和初始指令奇信号组成，且所述第二命令地址偶信号包括初始指令偶信号，所述第二命令地址奇信号包括初始指令奇信号。
在一些实施例中，所述输入采样电路还包括片选采样电路，且所述片选采样电路包括第三采样电路、第四采样电路、第五采样电路和第六采样电路；
所述第三采样电路，用于根据所述时钟奇信号对所述第一片选信号进行采样，得中间采样奇信号；
所述第四采样电路，用于根据所述时钟偶信号对所述中间采样奇信号进行采样，得到第二片选偶信号；
所述第五采样电路，用于根据所述时钟偶信号对所述第一片选信号进行采样，得到中间采样偶信号；
所述第六采样电路，用于通过所述时钟奇信号对所述中间采样偶信号进行采样，得到第二片选奇信号；
其中，所述第二片选信号由所述第二片选偶信号和所述第二片选奇信号组成。
在一些实施例中，所述逻辑运算电路包括第一逻辑电路和第二逻辑电路；其中，
所述第一逻辑电路，用于接收所述时钟偶信号和所述第二片选偶信号，并对所述时钟偶信号和所述第二片选偶信号进行逻辑运算，得到所述片选时钟偶信号；
所述第二逻辑电路，用于接收所述时钟奇信号和所述第二片选奇信号，并对所述时钟奇信号和所述第二片选奇信号进行逻辑运算，得到所述片选时钟奇信号。
在一些实施例中，所述第一逻辑电路包括第一缓冲器和第一与门；其中，
所述第一缓冲器，用于对所述时钟偶信号进行延时处理，得到中间时钟偶信号；
所述第一与门，用于对所述第二片选偶信号和所述中间时钟偶信号进行与运算，得到所述片选时钟偶信号。
在一些实施例中，所述第二逻辑电路包括第二缓冲器和第二与门；其中，
所述第二缓冲器，用于对所述时钟奇信号进行延时处理，得到中间时钟奇信号；
所述第二与门，用于对所述第二片选奇信号和所述中间时钟奇信号进行与运算，得到所述片选时钟奇信号。
在一些实施例中，所述指令译码电路包括第一指令译码电路、第二指令译码电路以及或门；其中，
所述第一指令译码电路，用于根据所述片选时钟偶信号和所述第二片选偶信号对所述初始指令奇信号进行译码和采样处理，得到指令偶信号；
所述第二指令译码电路，用于根据所述片选时钟奇信号和所述第二片选奇信号对所述初始指令偶信号进行译码和采样处理，得到指令奇信号；
所述或门，用于对所述指令偶信号和所述指令奇信号进行或运算，得到所述目标指令信号。
在一些实施例中，所述第一指令译码电路包括第一译码电路、第七采样电路和第三与门；其中，
所述第一译码电路，用于对所述初始指令奇信号进行译码处理，得到指令译码奇信号；
所述第七采样电路，用于根据所述片选时钟偶信号对所述指令译码奇信号进行采样处理，得到指令采样偶信号；
所述第三与门，用于对所述第二片选偶信号与所述指令采样偶信号进行与运算，得到所述指令偶信号。
在一些实施例中，所述第二指令译码电路包括第二译码电路、第八采样电路和第四与门；其中，
所述第二译码电路，用于对所述初始指令偶信号进行译码处理，得到指令译码偶信号；
所述第八采样电路，用于根据所述片选时钟奇信号对所述指令译码偶信号进行采样处理，得到指令采样奇信号；
所述第四与门，用于对所述第二片选奇信号与所述指令采样奇信号进行与运算，得到所述指令奇信号。
在一些实施例中，所述合并输出电路包括第一合并输出电路和第二合并输出电路；其中，
所述第一合并输出电路，用于根据所述片选时钟奇信号对所述第二命令地址偶信号进行采样，得到所述第一目标地址信号；或者，根据所述片选时钟偶信号对所述第二命令地址奇信号进行采样，得到所述第一目标地址信号；
所述第二合并输出电路，用于根据所述片选时钟奇信号对所述第二命令地址奇信号进行采样，得到所述第二目标地址信号；或者，根据所述片选时钟偶信号对所述第二命令地址偶信号进行采样，得到所述第二目标地址信号；
其中，所述第一合并输出电路的第一数据端、第二数据端、第一时钟端和第二时钟端与所述第二命令 地址奇信号、所述第二命令地址偶信号、所述片选时钟偶信号和所述片选时钟奇信号对应连接，所述第二合并输出电路的第一数据端、第二数据端、第一时钟端和第二时钟端与所述第二命令地址奇信号、所述第二命令地址偶信号、所述片选时钟奇信号和所述片选时钟偶信号对应连接。
在一些实施例中，所述第一合并输出电路包括第三逻辑电路、第四逻辑电路和第九采样电路；其中，
所述第三逻辑电路，用于对所述片选时钟奇信号进行逻辑运算，得到第一使能奇信号和第二使能奇信号，且所述第一使能奇信号和所述第二使能奇信号之间的相位差为180度；
所述第四逻辑电路，用于对所述片选时钟偶信号进行逻辑运算，得到第一使能偶信号和第二使能偶信号，且所述第一使能偶信号和所述第二使能偶信号之间的相位差为180度；
所述第九采样电路，用于根据所述第一使能偶信号、所述第二使能偶信号、所述第一使能奇信号和所述第二使能奇信号对所述第二命令地址偶信号和所述第二命令地址奇信号进行采样处理，得到所述第一目标地址信号。
在一些实施例中，所述第九采样电路，具体用于在所述片选时钟偶信号为高电平有效的脉冲信号情况下，根据所述第一使能偶信号和所述第二使能偶信号对所述第二命令地址奇信号进行采样处理，得到所述第一目标地址信号；或者，在所述片选时钟奇信号为高电平有效的脉冲信号情况下，根据所述第一使能奇信号和所述第二使能奇信号对所述第二命令地址偶信号进行采样处理，得到所述第一目标地址信号。
在一些实施例中，所述第二合并输出电路包括第五逻辑电路、第六逻辑电路和第十采样电路；其中，
所述第五逻辑电路，用于对所述片选时钟偶信号进行逻辑运算，得到第三使能偶信号和第四使能偶信号，且所述第三使能偶信号和所述第四使能偶信号之间的相位差为180度；
所述第六逻辑电路，用于对所述片选时钟奇信号进行逻辑运算，得到第三使能奇信号和第四使能奇信号；且所述第三使能奇信号和所述第四使能奇信号之间的相位差为180度；
所述第十采样电路，用于根据所述第三使能偶信号、所述第四使能偶信号、所述第三使能奇信号和所述第四使能奇信号对所述第二命令地址偶信号和所述第二命令地址奇信号进行采样处理，得到所述第二目标地址信号。
在一些实施例中，所述第十采样电路，具体用于在所述片选时钟偶信号为高电平有效的脉冲信号情况下，根据所述第三使能偶信号和所述第四使能偶信号对所述第二命令地址偶信号进行采样处理，得到所述第二目标地址信号；或者，在所述片选时钟奇信号为高电平有效的脉冲信号情况下，根据所述第三使能奇信号和所述第四使能奇信号对所述第二命令地址奇信号进行采样处理，得到所述第二目标地址信号。
在一些实施例中，所述第一片选信号是表征目标芯片被选中的信号，且所述第一片选信号为低电平有效的脉冲信号；其中，
若所述第一片选信号在偶数时钟周期的上升沿采样为低电平，则所述第二片选奇信号为高电平有效的脉冲信号，以及所述片选时钟奇信号为高电平有效的脉冲信号；或者，若所述第一片选信号在奇数时钟周期的上升沿采样为低电平，则所述第二片选偶信号为高电平有效的脉冲信号，以及所述片选时钟偶信号为高电平有效的脉冲信号。
在一些实施例中，所述第一目标地址信号包括所述第一命令地址信号在第一时钟周期里的信息，所述第二目标地址信号包括所述第一命令地址信号在第二时钟周期里的信息，且所述第一时钟周期是指所述第一片选信号为低电平时的时钟周期，所述第二时钟周期是所述第一时钟周期的下一时钟周期。
第二方面，本公开实施例提供了一种半导体存储器，包括如第一方面中任一项所述的信号采样电路。
在一些实施例中，该半导体存储器为动态随机存取存储器DRAM芯片。
附图说明
图1为两个时钟周期命令的信号时序示意图；
图2为一种信号采样电路的组成结构示意图；
图3为一种指令译码器的组成结构示意图；
图4为一种信号采样电路的信号时序示意图；
图5为本公开实施例提供的一种信号采样电路的组成结构示意图；
图6为本公开实施例提供的另一种信号采样电路的组成结构示意图；
图7A为本公开实施例提供的第一指令译码电路的组成结构示意图；
图7B为本公开实施例提供的第一指令译码电路的组成结构示意图；
图8A为本公开实施例提供的第一合并输出电路的组成结构示意图；
图8B为本公开实施例提供的第一合并输出电路的组成结构示意图；
图9为本公开实施例提供的一种使能反相器的具体电路结构示意图；
图10为本公开实施例提供的一种信号采样电路的详细结构示意图；
图11为本公开实施例提供的一种信号采样电路的信号时序示意图；
图12为本公开实施例提供的一种半导体存储器的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
以下为本公开实施例中涉及到的专业名词解释以及部分名词的对应关系：
动态随机存取存储器(Dynamic Random Access Memory，DRAM)
同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)
双倍速率(Double Data Rate，DDR)
第四代DDR(4th DDR，DDR4)
第五代DDR(5th DDR，DDR5)
命令地址输入(Command/Address，CMD/ADD或简称为CA)
时钟输入(Clock Input，CLK)
片选输入(Chip Select Input，CS)
缓冲器(Buffer/Repeater，RPT)
指令译码器(Command Decoder，CMD DEC)
D型触发器(Data Flip-Flop或Delay Flip-Flop，DFF)
工艺、电压、温度(Process、Voltage、Temperature，PVT)
可以理解，以DDR5 DRAM设计为例，CA输入既可以作为地址进行采样又可以作为指令进行采样译码。其中，这里的CA是DRAM各种命令地址信号的统称，可以包括行地址选通脉冲(Row Address Strobe，RAS)、列地址选通脉冲(Column Address Strobe，CAS)、写命令(Write，WE)、激活命令(Active，ACT)等命令信号，以及还可以包括有A13～A0的地址信号等。另外，在实际应用中，该命令地址信号包括几位地址信号，具体可以是根据DRAM的规格确定，本公开实施例不作任何限定。
对于DDR5 DRAM的2T CMD，参见图1，其示出了两个时钟周期命令的信号时序示意图。在图1中，CK_t、CK_c为一对输入的互补时钟信号，CA[13:0]就是CA输入，CMD为CA译码后得到的指令信号，CS_n为指示CA有效的片选信号。如图1所示，CA[13:0]为持续两个时钟周期的信号，第1个时钟周期的CA和第2个时钟周期的CA需要作为地址信号进行采样，同时第1个时钟周期的CA还需要指令信号进行采样和译码。具体地，在DDR5中，第1个时钟周期的CA[4:0]需要作为指令信号进行译码和采样。另外，时钟周期是指CK_t/CK_c的时钟周期。
示例性地，参见图2，其示出了一种信号采样电路的组成结构示意图。如图2所示，该信号采样电路包括第一接收器101、第二接收器102、第三接收器103、第一采样电路104、第二采样电路105、第三采样电路106、第四采样电路107、第五采样电路108、第六采样电路109、第七采样电路110、第八采样电路111、指令译码器112、或门113、第一功能模块114、第二功能模块115和第三功能模块116。其中，第一采样电路104、第二采样电路105、第五采样电路108、第六采样电路109、第七采样电路110和第八采样电路111可以是由D型触发器组成，第三采样电路106和第四采样电路107可以是由D型触发器和反相器组成。另外，对于指令译码器108而言，其可以是由三输入与非门、二输入或非门和缓冲器等逻辑部件组成，详见图3所示。
在图1中，第一接收器101的输入信号为初始命令地址信号(用CA[13:0]表示)和参考信号(用VREFCA表示)，输出信号为第一命令地址信号(用CA表示)；第二接收器102的输入信号为初始片选信号(用CS_n表示)和参考信号(用VREFCA表示)，输出信号为第一片选信号(用PCS表示)；第三接收器103的输入信号为初始时钟信号(用CK_t/CK_c表示)，经过分频处理后得到时钟偶信号(用PCLK_E表示)和时钟奇信号(用PCLK_O表示)。在这里，PCLK_E_/PCLK_O的时钟周期是CK_t/CK_c的时钟周期的两倍，PCLK_E_/PCLK_O的频率是CK_t/CK_c的频率的一半。需要注意的是，这里的 CA[13:0]表示一组信号，CA[0]、CA[1]、…、CA[13]的合并统称。相应的，第一接收器101中其实包括有14个接收电路，以及输出的线路，甚至包括后面的采样电路，长走线路径也是14根，与CA[0]、CA[1]、…、CA[13]是一一对应的。
然后，通过第一采样电路104，利用时钟偶信号PCLK_E对第一命令地址信号CA进行一级采样处理，得到第二地址偶信号(用CA[13:0]_1T_E表示)，以及通过第五采样电路108，利用时钟奇信号PCLK_O对第二地址偶信号CA[13:0]_1T_E进行二级采样处理，得到第三地址奇信号(用表CA[13:0]_0T_O示)。通过第二采样电路105，利用时钟奇信号PCLK_O对第一命令地址信号CA进行采样处理，得到第二地址奇信号(用CA[13:0]_1T_O表示)，以及通过第六采样电路109，利用时钟偶信号PCLK_E对第二地址奇信号CA[13:0]_1T_O进行二级采样处理，得到第三地址偶信号(用CA[13:0]_0T_E表示)。在这里，第三地址偶信号CA[13:0]_0T_E包括初始指令偶信号(用CA[4:0]_0T_E表示)，第三地址奇信号CA[13:0]_0T_O包括初始指令奇信号(用CA[4:0]_0T_O表示)。需要注意的是，CA[4:0]_0T_E和CA[4:0]_0T_O用于译码形成指令信号，分别是CA[0]_0T_E～CA[4]_0T_E和CA[0]_0T_O～CA[4]_0T_O的合并统称。
同时，通过第三采样电路106，利用时钟偶信号PCLK_E对第一片选信号PCS进行一级采样及反相处理，得到中间采样偶信号(用PCS_E表示)，并通过第七采样电路110，利用时钟奇信号PCLK_O对中间采样偶信号PCS_E进行二级采样，得到第二片选奇信号(用PCS_OD表示)；通过第四采样电路107，利用时钟奇信号PCLK_O对第一片选信号PCS进行一级采样及反相处理，得到中间采样奇信号(用PCS_O表示)，并通过第八采样电路111对中间采样奇信号PCS_O进行二级采样，得到第二片选偶信号(用PCS_ED表示)。
最后，通过指令译码器112，对初始指令偶信号CA[4:0]_0T_E、初始指令奇信号CA[4:0]_0T_O、第二片选偶信号PCS_ED和第二片选奇信号PCS_OD进行译码，得到指令偶信号(用CMD_E表示)和指令奇信号(用CMD_O表示)；最后，通过或门109对指令偶信号CMD_E和指令偶信号CMD_O进行或逻辑运算，得到目标指令信号(用CMD表示)。另外，目标指令信号CMD、第二地址奇信号CA[13:0]_1T_O、第二地址偶信号CA[13:0]_1T_E、第三地址奇信号CA[13:0]_0T_O和第三地址偶信号CA[13:0]_0T_E与第一功能模块114、第二功能模块115和第三功能模块116之间均存在有长走线路径；如此，目标指令信号CMD、第二地址奇信号CA[13:0]_1T_O、第二地址偶信号CA[13:0]_1T_E、第三地址奇信号CA[13:0]_0T_O和第三地址偶信号CA[13:0]_0T_E在经过不同的版图布线路径后将共同到达不同的功能模块去实现下一级功能。
基于图2和图3所示的信号采样电路，其对应的信号时序图如图4所示。在图4中，初始时钟信号用CK_t/CK_c表示，时钟偶信号用PCLK_E表示，时钟奇信号用PCLK_O表示，且CK_t/CK_c的时钟周期为预设时钟周期，PCLK_E/PCLK_O的时钟周期均为预设时钟周期的两倍；第一命令地址信号用CA表示，且CA可以包括Cy、Cz、C0、C1、C2和C3；初始片选信号用CS_n表示，第一片选信号用PCS表示，PCS信号为低电平有效的脉冲信号，且脉冲宽度为预设时钟周期，PCS用于表征目标芯片被选中的信号。换句话说，内容为C0的第一命令地址信号CA(第一时钟周期中的CA信息)和低电平的第一片选信号PCS被时钟偶信号PCLK_E进行一级采样，产生中间采样偶信号PCS_E和第二地址奇信号CA[13:0]_1T_E；然后这些输出再被时钟奇信号PCLK_O进行二级采样，产生第二片选奇信号PCS_OD和第三地址奇信号CA[13:0]_0T_O。同时内容为C1的CA(第二时钟周期中的CA信息)被时钟奇信号PCLK_O进行一级采样，产生第二时钟奇信号CA[13:0]_1T_O。此时，第二片选奇信号PCS_OD、第二地址奇信号CA[13:0]_1T_O和第三地址奇信号CA[13:0]_0T_O都是被时钟奇信号PCLK_O采样输出，三组信号为对齐。另外，第二片选奇信号PCS_OD和初始指令奇信号CA[4:0]_0T_O还需要进入指令译码器112和或门113中进行逻辑译码，得到目标指令信号CMD。因此，目标指令信号CMD、第二地址奇信号CA[13:0]_1T_O和第三地址奇信号CA[13:0]_0T_O之间存在一定的时序偏差(Skew)，导致后续电路出现错误。
简单来说，初始时钟信号CK_t/CK_c在接收器之后分频为奇偶时钟PCLK_E/PCLK_O去采样第一命令地址信号CA。对DDR5的2T CMD来说，需要用第一个时钟周期的第一命令地址信号CA作为指令和地址，然后用第二个时钟周期的第一命令地址信号CA作为剩下的地址。因此，DDR5设计需要两级采样，然后分别作为两个时钟周期的地址信号。但同时第二级采样后的第一命令地址信号CA还需要作为指令信号进行译码处理，这样指令路径就比地址路径多出来译码部分的逻辑电路，后续地址信号和指令信号再经过不同的版图布线路径共同到达不同的模块去实现下一级功能。换句话说，在第一命令地址信号CA被采样之后可以获得地址信号，但是第一命令地址信号CA信号被采样后还需要进行译码才能获得指令信号，导致指令信号和地址信号在到达下一级时的时序就有较大的时序偏差(Skew)，并且这个Skew在不同PVT条件下也会不一样，从而导致下一级功能会因时序偏差而出现错误。除此之外，如图2所示，对2T CMD来说，针对第一命令地址信号CA中的一位信号，需要设置四条不同的地址总线才能够向后传输，占用的版图面积大，降低了存储器的电学性能。
基于此，本公开实施例提供了一种信号采样电路，该信号采样电路包括输入采样电路、逻辑运算电路、指令译码电路和合并输出电路；其中，输入采样电路，用于根据第一时钟信号分别对第一片选信号和第一命令地址信号进行采样处理，得到第二片选信号和第二命令地址信号；其中，第二命令地址信号包括初始指令信号，且第二命令地址信号由第二命令地址奇信号和第二命令地址偶信号组成；逻辑运算电路，用于对第一时钟信号和第二片选信号进行逻辑运算，得到片选时钟信号；其中，片选时钟信号包含片选时钟奇信号和片选时钟偶信号；指令译码电路，用于根据第二片选信号和片选时钟信号对初始指令信号进行译码处理和采样处理，得到目标指令信号；合并输出电路，用于根据片选时钟偶信号和片选时钟奇信号分别对第二命令地址奇信号和第二命令地址偶信号进行采样处理，得到第一目标地址信号；并根据片选时钟奇信号和片选时钟偶信号分别对第二命令地址奇信号和第二命令地址偶信号进行采样处理，得到第二目标地址信号。其中，目标指令信号、第一目标地址信号和第二目标地址信号之间的时序对齐。这样，基于该信号采样电路，在同一时钟周期的采样下，能够实现目标指令信号、第一目标地址信号和第二目标地址信号的时序对齐，使得译码之后的指令信号和地址信号之间没有跟随PVT变化的偏差，从而可以避免下一级功能模块因时序偏差而出现问题；另外，通过合并输出处理，还可以将奇偶地址线进行合并，从而减半地址线的数量。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图5，其示出了本公开实施例提供的一种信号采样电路40的组成结构示意图。如图5所示，该信号采样电路40可以包括输入采样电路41、逻辑运算电路42、指令译码电路43和合并输出电路44；其中，
输入采样电路41，用于根据第一时钟信号分别对第一片选信号和第一命令地址信号进行采样处理，得到第二片选信号和第二命令地址信号；其中，第二命令地址信号包括初始指令信号，且第二命令地址信号由第二命令地址奇信号和第二命令地址偶信号组成；
逻辑运算电路42，用于对第一时钟信号和第二片选信号进行逻辑运算，得到片选时钟信号；其中，片选时钟信号包含片选时钟奇信号和片选时钟偶信号；
指令译码电路43，用于根据第二片选信号和片选时钟信号对初始指令信号进行译码处理和采样处理，得到目标指令信号；
合并输出电路44，用于根据片选时钟偶信号和片选时钟奇信号分别对第二命令地址奇信号和第二命令地址偶信号进行采样处理，得到第一目标地址信号；并根据片选时钟奇信号和片选时钟偶信号分别对第二命令地址奇信号和第二命令地址偶信号进行采样处理，得到第二目标地址信号。
需要说明的是，本公开实施例的信号采样电路40应用于地址和指令信号的采样和译码过程，具体可以应用在多种电路场景中。本公开实施例后续以DRAM中CA的译码进行解释和说明，但这并不构成相关限定。
本公开实施例的信号采样电路40应用于两个时钟周期的指令信号(即2T CMD)。换言之，这里的第一命令地址信号包括两个时钟周期的有效信号，相应地，目标指令信号包括两个时钟周期的有效命令，具体如图1所示。在图1中，CS_n信号为低电平有效的脉冲信号，且脉冲宽度为一个时钟周期，该时钟周期和该时钟周期的下一时钟周期对应的CA[13:0]信号是有效(Valid)的。对于2T CMD来说，第一个时钟周期和第二个时钟周期的CA需要被采样为地址信号，且第一个时钟周期的CA还需要被采样和译码为指令信号。
相应地，在本公开实施例中，指令译码电路43用于输出目标指令信号，合并输出电路44用于输出第一目标地址信号和第二目标地址信号，第一目标地址信号指示第一时钟周期里的CA信息，第二目标地址信号用于指示第二时钟周期里的CA信息。
需要说明的是，第二命令地址信号由第二命令地址偶信号和第二命令地址奇信号组成，片选时钟信号也是由片选时钟奇信号和片选时钟偶信号构成的。合并输出电路44通过利用片选时钟信号对第二命令地址信号进行交叉采样处理，得到第一目标地址信号；同时，通过利用片选时钟信号对第二命令地址信号进行对应采样处理，得到第二目标地址信号。
在这里，交叉采样处理是指：利用片选时钟偶信号采样第二命令地址奇信号，利用片选时钟奇信号采样第二命令地址偶信号。对应采样处理是指：利用片选时钟偶信号采样第二命令地址偶信号，利用片选时钟奇信号采样第二命令地址奇信号。
需要说明的是，经过逻辑运算电路42之后，片选时钟奇信号和片选时钟偶信号之间仅有一个有效。这样，在片选时钟奇信号有效的情况下，目标指令信号是由指令译码电路43根据片选时钟奇信号进行采样输出的；第一目标地址信号是由合并输出电路44根据片选时钟奇信号对第二命令地址偶信号采样输出的，第二目标地址信号是由合并输出电路44根据片选时钟奇信号对第二命令地址奇信号采样输出的。在片选时钟偶信号有效的情况下，目标指令信号是由指令译码电路43根据片选时钟偶信号进行采样输出的；第一目标地址信号是由合并输出电路44根据片选时钟偶信号对第二命令地址奇信号采样输出的，第二目 标地址信号是由合并输出电路44根据片选时钟偶信号对第二命令地址偶信号采样输出的。
也就是说，目标指令信号、第一目标地址信号和第二目标地址信号均是通过一个相同的信号(片选时钟奇信号或者片选时钟偶信号)采样输出的，所以目标指令信号、第一目标地址信号和第二目标地址信号之间的时序对齐，从而能避免指令信号和地址信号之间的时序偏差问题，且指令信号和地址信号之间的时序偏差不会跟随PVT进行变化，从而可以避免下一级功能模块因时序偏差而出现问题。在这里，时序对齐是指目标指令信号、第一目标地址信号和第二目标地址信号同时由低电平状态变化为高电平状态，或者同时由高电平状态变化为低电平状态。其中，本申请实施例所述的“时序对齐”和“同时”指的是时序偏差在预设精度范围内。
在一些实施例中，在图5所示信号采样电路40的基础上，参见图6，该信号采样电路40还可以包括接收电路45，接收电路45包括第一接收电路451、第二接收电路452和第三接收电路453；其中，
第一接收电路451，用于接收初始命令地址信号，输出第一命令地址信号；
第二接收电路452，用于接收初始片选信号，输出第一片选信号；
第三接收电路453，用于接收初始时钟信号，并对初始时钟信号进行分频处理，得到时钟奇信号和时钟偶信号。
在这里，时钟奇信号和时钟偶信号组成前述的第一时钟信号。特别地，时钟奇信号和时钟偶信号是由初始时钟信号进行分频后得到的，因此时钟奇信号和时钟偶信号的时钟周期均是初始时钟信号的时钟周期的两倍。另外，时钟奇信号和时钟偶信号之间的相位差为180度。
需要说明的是，通过接收电路45，可以获得第一命令地址信号、第一片选信号和第一时钟信号，然后将其输入到输入采样电路41进行采样以及后续的逻辑运算。
在这里，无论是第一接收电路451，还是第二接收电路452或第三接收电路453，均可以是接收器(用Recevier表示)，或者也可以是缓冲器(用Buffer表示)。
还需要说明的是，在图6中，这里的初始命令地址信号可以用CA[13:0]表示，第一命令地址信号用CA表示；初始片选信号可以用CS_n表示，第一片选信号用PCS表示；初始时钟信号可以用CK_t和CK_c表示，时钟偶信号用PCLK_E表示，时钟奇信号用PCLK_O表示。
另外，还需要注意的是，无论是初始命令地址信号还是第一命令地址信号，其并非是一个信号，而是代表一组命令地址信号，即CA[0]～CA[13]；因此，对于第一接收电路451而言，这里可以包括有14个接收电路，用于接收CA[0]、CA[1]、…、CA[13]等14个信号的，图中仅示出一个接收电路作为示意。
在一些实施例中，输入采样电路41包括命令地址采样电路411，且命令地址采样电路411包括第一采样电路和第二采样电路；其中，
第一采样电路，用于根据时钟奇信号对第一命令地址信号进行采样，得到第二命令地址奇信号；
第二采样电路，用于通过时钟偶信号对第一命令地址信号进行采样，得到第二命令地址偶信号；
需要说明的是，初始指令信号是由初始指令偶信号和初始指令奇信号组成，且第二命令地址偶信号包括初始指令偶信号，第二命令地址奇信号包括初始指令奇信号。
在这里，在图6中，第二命令地址偶信号可以用CA[13:0]_1T_E进行表示，第二命令地址奇信号可以用CA[13:0]_1T_O进行表示，初始指令偶信号用CA[4:0]_1T_E表示，初始指令奇信号用CA[4:0]_1T_O表示。特别地，以上符号中，“1T”并不具有特别限定意义。
需要注意的是，CA[13:0]_1T_E也并非是一个信号，而是代表一组命令地址信号，即CA[0]_1T_E～CA[13]_1T_E，而CA[4:0]_1T_E表示的这一组信号中的CA[0]_1T_E～CA[4]_1T_E；CA[13:0]_1T_O也并非是一个信号，而是代表一组命令地址信号，即CA[0]_1T_O～CA[13]_1T_O，而CA[4:0]_1T_O表示的这一组信号中的CA[0]_1T_O～CA[4]_1T_O。
如图6所示，第一采样电路和第二采样电路可以是由D型触发器组成；其中，对于第一采样电路来说，D型触发器的时钟端与时钟奇信号PCLK_O连接，D型触发器的输入端与第一命令地址信号CA连接，D型触发器的输出端用于输出第二命令地址奇信号CA[13:0]_1T_O，且第二命令地址奇信号CA[13:0]_1T_O包括初始指令奇信号CA[4:0]_1T_O。对于第二采样电路来说，D型触发器的时钟端与时钟偶信号PCLK_E连接，D型触发器的输入端与第一命令地址信号CA连接，D型触发器的输出端用于输出第二命令地址偶信号CA[13:0]_1T_E，第二命令地址偶信号CA[13:0]_1T_E包括初始指令偶信号CA[4:0]_1T_E。
在一些实施例中，输入采样电路41还包括片选采样电路412，且片选采样电路412包括第三采样电路、第四采样电路、第五采样电路和第六采样电路；
第三采样电路，用于根据时钟奇信号对第一片选信号进行采样，得中间采样奇信号；
第四采样电路，用于根据时钟偶信号对中间采样奇信号进行采样，得到第二片选偶信号；
第五采样电路，用于根据时钟偶信号对第一片选信号进行采样，得到中间采样偶信号；
第六采样电路，用于通过时钟奇信号对中间采样偶信号进行采样，得到第二片选奇信号。
还需要说明的是，在图6中，中间采样奇信号可以用PCS_O表示，第二片选偶信号可以用PCS_ED表示；中间采样偶信号可以用PCS_E表示，第二片选奇信号可以用PCS_OD表示。
具体地，如图6所示，第三采样电路可以是由D型触发器和反相器组成，第四采样电路可以是由D型触发器组成。其中，对于第三采样电路来说，D型触发器的时钟端与时钟奇信号PCLK_O连接，D型触发器的输入端与第一片选信号PCS连接，D型触发器的输出端与反相器的输入端连接，反相器的输出端用于输出中间采样奇信号PCS_O；对于第四采样电路来说，D型触发器的时钟端与PCLK_E连接，D型触发器的输入端与中间采样奇信号PCS_O连接，D型触发器的输出端用于输出第二片选偶信号PCS_ED。
第五采样电路可以是由D型触发器和反相器组成，第六采样电路可以是由D型触发器组成。其中，对于第五采样电路来说，D型触发器的时钟端与时钟偶信号PCLK_E连接，D型触发器的输入端与第一片选信号PCS连接，D型触发器的输出端与反相器的输入端连接，反相器的输出端用于输出中间采样偶信号PCS_E信号；对于第六采样电路来说，D型触发器的时钟端与时钟奇信号PCLK_O连接，D型触发器的输入端与中间采样偶信号PCS_E信号连接，D型触发器的输出端用于输出第二片选奇信号PCS_OD。
应理解，由于第一片选信号PCS为低电平有效的脉冲信号，因此需要在第三采样电路或者第五采样电路中设置反相器，以使得中间采样偶信号PCS_E或者中间采样奇信号PCS_O变成高电平有效的脉冲信号，以便后续的逻辑运算。另外，第三采样电路和第五采样电路也可以不需要反相器，那么后续的逻辑运算则需进行相应调整，从而达到相同效果。
这样，在经过接收电路45和输入采样电路41之后，可以获得时钟偶信号、时钟奇信号、第二片选偶信号、第二片选奇信号、第二命令地址偶信号、第二命令地址奇信号、初始指令偶信号和初始指令奇信号。然后，对时钟偶信号、时钟奇信号、第二片选偶信号、第二片选奇信号进行计算，得到片选时钟奇信号和片选时钟偶信号。最后，通过有效的片选时钟信号对第二命令地址偶信号和第二命令地址奇信号进行采样，以及对初始指令偶信号或者初始指令奇信号进行译码及采样，从而能够使得最终输出的地址信号和指令信号的时序对齐。
在本公开实施例中，对时钟偶信号、时钟奇信号、第二片选偶信号和第二片选奇信号进行逻辑运算，从而获得片选时钟信号，以便后续能够对指令译码电路43和合并输出电路44进行奇偶采样，以实现地址总线数量减半。因此，在一些实施例中，如图6所示，逻辑运算电路42包括第一逻辑电路421和第二逻辑电路422；其中，
第一逻辑电路421，用于接收时钟偶信号和第二片选偶信号，并对时钟偶信号和第二片选偶信号进行逻辑运算，得到片选时钟偶信号；
第二逻辑电路422，用于接收时钟奇信号和第二片选奇信号，并对时钟奇信号和第二片选奇信号进行逻辑运算，得到片选时钟奇信号。
需要说明的是，在图6中，这里的片选时钟偶信号可以用CS_CLK_E表示，片选时钟奇信号可以用CS_CLK_O表示。
在一种具体的实施例中，对于第一逻辑电路421而言，第一逻辑电路421可以包括第一缓冲器和第一与门；其中，
第一缓冲器，用于对时钟偶信号进行延时处理，得到中间时钟偶信号；
第一与门，用于对第二片选偶信号和中间时钟偶信号进行与运算，得到片选时钟偶信号。
在另一种具体的实施例中，对于第二逻辑电路422而言，第二逻辑电路422可以包括第二缓冲器和第二与门；其中，
第二缓冲器，用于对时钟奇信号进行延时处理，得到中间时钟奇信号；
第二与门，用于对第二片选奇信号和中间时钟奇信号进行与运算，得到片选时钟奇信号。
需要说明的是，对于缓冲器而言，无论是第一缓冲器还是第二缓冲器，不仅具有延时功能，而且还可以具有增强信号驱动能力的作用。具体地，对于中间时钟偶信号与时钟偶信号而言，中间时钟偶信号相比时钟偶信号不仅存在时延，而且中间时钟偶信号的驱动能力更强；而对于中间时钟奇信号与时钟奇信号而言，中间时钟奇信号相比时钟奇信号存在时延，而且中间时钟奇信号的驱动能力更强。
还需要说明的是，如图6所示，片选时钟偶信号CS_CLK_E是通过第一逻辑电路421得到的，片选时钟奇信号CS_CLK_O是通过第二逻辑电路422得到的。在本公开实施例中，根据片选时钟偶信号CS_CLK_E和片选时钟奇信号CS_CLK_O这两个信号对指令译码电路43和合并输出电路44进行相关处理，从而使得最终输出的第一目标地址信号、第二目标地址信号和目标指令信号的时序对齐。
还需要说明的是，在一些实施例中，第一片选信号是表征目标芯片被选中的信号，且第一片选信号为低电平有效的脉冲信号；其中，
若第一片选信号在偶数时钟周期的上升沿采样为低电平，则中间采样偶信号和第二片选奇信号为高电平有效的脉冲信号，以及片选时钟奇信号为高电平有效的脉冲信号；或者，若第一片选信号在奇数时钟周期的上升沿采样为低电平，则中间采样奇信号和第二片选偶信号为高电平有效的脉冲信号，以及片选时 钟偶信号为高电平有效的脉冲信号。
在这里，偶数时钟周期或者奇数时钟周期是指初始时钟信号CK_t/CK_c的时钟周期。具体来说，经过第三接收电路453的分频处理之后，可以得到时钟奇信号PCLK_E和时钟偶信号PCLK_O；然后将时钟偶信号PCLK_E的上升沿所在的时钟周期作为偶数时钟周期，将时钟奇信号PCLK_O的上升沿所在的时钟周期作为奇数时钟周期。
需要说明的是，由于第二片选奇信号PCS_OD和第二片选偶信号PCS_ED中只有一个信号处于高电平，因此利用第一逻辑电路421和第二逻辑电路422，使得在片选时钟奇信号CS_CLK_O和片选时钟偶信号CS_CLK_E这两个信号中，同样只有一个信号为具有高电平的有效信号，另一个信号则为无效信号(低电平信号)。这样，通过屏蔽第二片选信号为低电平(即无命令)时的第一时钟信号(时钟偶信号PCLK_E或时钟奇信号PCLK_O)，能够减少不必要的时钟信号振荡，能够实现节省功耗的功能。
在一些实施例中，对于指令译码电路43而言，根据片选时钟偶信号和片选时钟奇信号，需要对初始指令信号中的奇偶信号分别进行采样和译码。因此，在一些实施例中，如图6所示，指令译码电路43可以包括第一指令译码电路431、第二指令译码电路432以及或门433；其中，
第一指令译码电路431，用于根据片选时钟偶信号和第二片选偶信号对初始指令奇信号进行译码和采样处理，得到指令偶信号；
第二指令译码电路432，用于根据片选时钟奇信号和第二片选奇信号对初始指令偶信号进行译码和采样处理，得到指令奇信号；
或门433，用于对指令偶信号和指令奇信号进行或运算，得到目标指令信号。
需要说明的是，在图6中，这里的目标指令信号可以用CMD表示，指令偶信号可以用CMD_E表示，指令奇信号可以用CMD_O表示。
需要说明的是，如图6所示，目标指令信号CMD是由指令偶信号CMD_E和指令奇信号CMD_O进行或逻辑运算得到的。其中，指令偶信号CMD_E是通过第一指令译码电路431进行译码和采样得到的，指令奇信号CMD_O是通过第二指令译码电路432进行译码和采样得到的。
在一种具体的实施例中，如图7A所示，第一指令译码电路431可以包括第一译码电路、第七采样电路和第三与门；其中，
第一译码电路，用于对初始指令奇信号进行译码处理，得到指令译码奇信号；
第七采样电路，用于根据片选时钟偶信号对指令译码奇信号进行采样处理，得到指令采样偶信号；
第三与门，用于对第二片选偶信号与指令采样偶信号进行与运算，得到指令偶信号。
需要说明的是，初始指令奇信号CA[4:0]_1T_O可以包括CA[0]_O、CA[1]_O、CA[2]_O、CA[3]_O、CA[4]_O等指令信号，而且第一译码电路也是由二输入与非门、三输入与非门和二输入或非门组成。其中，如图7A所示，CA[0]_O和CA[1]_O输入到二输入与非门，CA[2]_O、CA[3]_O和CA[4]_O输入到三输入与非门，然后二输入与非门的输出端以及三输入与非门的输出端将与二输入或非门的输入端连接，而二输入或非门的输出端用于输出指令译码奇信号，从而实现对初始指令奇信号的译码。
需要说明的是，第一指令译码电路431和第二指令译码电路432的具体设计是根据指令译码规则确定，对于不同的产品/不同的应用场景/不同的指令，译码规则可能不同，那么指令译码电路的逻辑也可以相应调整。
还需要说明的是，第七采样电路也可以为D型触发器。其中，如图7A所示，D型触发器的时钟端与片选时钟偶信号CS_CLK_E连接，D型触发器的输入端与二输入或非门的输出端连接，用于接收指令译码奇信号；D型触发器的输出端和第三与门的一个输入端连接，且第二片选偶信号PCS_ED与第三与门的另一个输入端连接，从而第三与门的输出端用于输出指令偶信号CMD_E，从而在对指令译码奇信号进行采样之后，通过第三与门还能够保证只有第二片选偶信号PCS_ED为高电平时，可以得到指令偶信号CMD_E。
在一些实施例中，如图7B所示，第二指令译码电路432包括第二译码电路、第八采样电路和第四与门；其中，
第二译码电路，用于对初始指令偶信号进行译码处理，得到指令译码偶信号；
第八采样电路，用于根据片选时钟奇信号对指令译码偶信号进行采样处理，得到指令采样奇信号；
第四与门，用于对第二片选奇信号与指令采样奇信号进行与运算，得到指令奇信号。
需要说明的是，初始指令偶信号CA[4:0]_1T_E可以包括CA[0]_E、CA[1]_E、CA[2]_E、CA[3]_E、CA[4]_E等指令信号，而且第一译码电路可以是由二输入与非门、三输入与非门和二输入或非门组成。其中，如图7B所示，CA[0]_E和CA[1]_E输入到二输入与非门，CA[2]_E、CA[3]_E和CA[4]_E输入到三输入与非门，然后二输入与非门的输出端以及三输入与非门的输出端分别与二输入或非门的输入端连接，而二输入或非门的输出端用于输出指令译码偶信号，从而实现对初始指令偶信号CA[4:0]_1T_E的译码。
还需要说明的是，第八采样电路也可以为D型触发器。其中，如图7B所示，D型触发器的时钟端与 片选时钟奇信号CS_CLK_O连接，D型触发器的输入端与二输入或非门的输出端连接，用于接收指令译码偶信号；D型触发器的输出端和第四与门的一个输入端连接，且第二片选奇信号PCS_OD与第四与门的另一个输入端连接，从而第四与门的输出端用于输出指令奇信号CMD_O，从而在对指令译码偶信号进行采样之后，通过第四与门还能够保证只有第二片选奇信号PCS_OD为高电平时，可以得到指令奇信号CMD_O，即保证了指令偶信号CMD_E和指令奇信号CMD_O中仅有一个有效信号。
这样，片选时钟偶信号CS_CLK_E和片选时钟奇信号CS_CLK_O中仅有一个为高电平有效的脉冲信号。如果片选时钟偶信号CS_CLK_E为高电平有效的脉冲信号，这时候由于片选时钟奇信号CS_CLK_O为低电平信号而不会执行第二指令译码电路432的采样处理，即指令奇信号CMD_O为低电平信号，那么此时得到的指令偶信号CMD_E与低电平信号通过或门433进行或运算，输出的仍为指令偶信号CMD_E信号；换言之，这时候得到的指令偶信号CMD_E信号即为目标指令信号CMD。反之，如果片选时钟奇信号CS_CLK_O为高电平有效的脉冲信号，这时候由于片选时钟偶信号CS_CLK_E为低电平信号而不会执行第一指令译码电路431的采样处理，即指令偶信号CMD_E为低电平信号，那么此时得到的指令奇信号CMD_O与低电平信号通过或门433进行或运算，输出的仍为指令奇信号CMD_O信号；换言之，这时候得到的指令奇信号CMD_O信号即为目标指令信号CMD。
在一些实施例中，合并输出电路44包括第一合并输出电路441和第二合并输出电路442；其中，
第一合并输出电路441，用于根据片选时钟奇信号对第二命令地址偶信号进行采样，得到第一目标地址信号；或者，根据片选时钟偶信号对第二命令地址奇信号进行采样，得到第一目标地址信号；
第二合并输出电路442，用于根据片选时钟奇信号对第二命令地址奇信号进行采样，得到第二目标地址信号；或者，根据片选时钟偶信号对第二命令地址偶信号进行采样，得到第二目标地址信号。
需要说明的是，第一合并输出电路441和第二合并输出电路442也可称为合并输出触发器，用Output Combined DFF表示，两者的内在电路结构相同，但是引脚与信号的接法不同。在这里，合并输出触发器包括两个数据端和两个时钟端，在利用第一个时钟端的信号对第一个数据端的信号进行采样的同时，也利用第二个时钟端的信号对第二个数据端的信号进行采样。
需要说明的是，在图6中，这里的第一目标地址信号用CA[13:0]_0T表示，这里的第二目标地址信号用CA[13:0]_1T表示。
如图6所示，对于第一合并输出电路441来说，第一数据端与第二命令地址奇信号CA[13:0]_1T_O连接，第二数据端与第二命令地址偶信号CA[13:0]_1T_E连接，第一时钟端与片选时钟偶信号CS_CLK_E连接，第二时钟端与片选时钟奇信号CS_CLK_O连接。如此，能够利用片选时钟偶信号CS_CLK_E对第二命令地址奇信号CA[13:0]_1T_O进行采样，同时利用片选时钟奇信号CS_CLK_O对第二命令地址偶信号CA[13:0]_1T_E进行采样，得到第一目标地址信号CA[13:0]_0T。应理解，由于片选时钟偶信号CS_CLK_E和片选时钟奇信号CS_CLK_O之中仅有一个有效，因此第一合并电路441仅会输出一个有效的采样结果，从而可以将原本用于分别传输奇偶采样结果的奇偶地址输出合并为一个采样输出，从而减少一半的地址总线。
如图6所示，对于第二合并输出电路442来说，第一数据端与第二命令地址奇信号CA[13:0]_1T_O连接，第二数据端与第二命令地址偶信号CA[13:0]_1T_E连接，第一时钟端与片选时钟奇信号CS_CLK_O连接，第二时钟端与片选时钟偶信号CS_CLK_E连接。如此，能够利用片选时钟奇信号CS_CLK_O对片选时钟奇信号CA[13:0]_1T_O进行采样，同时利用片选时钟偶信号CS_CLK_E对片选时钟偶信号CA[13:0]_1T_E进行采样，得到第二目标地址信号CA[13:0]_1T。应理解，由于片选时钟偶信号CS_CLK_E和片选时钟奇信号CS_CLK_O之中仅有一个有效，因此第二合并电路442同样仅会输出一个有效的采样结果，从而可以将原本用于分别传输奇偶采样结果的奇偶地址输出合并为一个采样输出，从而减少一半的地址总线。
基于前述的电路结构，第一合并输出电路441输出的是第一命令地址信号CA在第一时钟周期的采样结果，第二合并输出电路442输出的是第一命令地址信号CA在第二时钟周期的采样结果，以下为具体说明：
假设第一命令地址信号CA在连续7个时钟周期的内容分别是Cy、Cz、C0、C1、C2、C3和C4。
在2T CMD模式下，若第一片选信号PCS在C0对应的偶数时钟周期为低电平有效状态，说明C0和C1是有效的第一命令地址信号CA。此时，利用时钟偶信号采样得到的第二命令地址偶信号CA[13:0]_1T_E包括C0和C2，利用时钟奇信号采样得到的第二命令地址奇信号CA[13:0]_1T_O包括C1和C3。此时，由于片选时钟奇信号CS_CLK_O有效，经过片选时钟奇信号CS_CLK_O对第二命令地址偶信号CA[13:0]_1T_E采样会得到C0，经过片选时钟奇信号CS_CLK_O对CA[13:0]_1T_O采样会得到C1。如此，第一合并输出电路441采样得到的是CA在第一时钟周期的有效信息C0，而第二合并输出电路442采样得到的是CA在第二时钟周期的有效信息C1。
若第一片选信号PCS在C1对应的奇数时钟周期为低电平有效状态，说明C1和C2是有效的CA信 号。此时，利用时钟偶信号采样得到的第二命令地址偶信号CA[13:0]_1T_E包括C2和C4，利用时钟奇信号采样得到的第二命令地址奇信号CA[13:0]_1T_O包括C1和C3。此时，由于片选时钟偶信号CS_CLK_E有效，经过片选时钟偶信号CS_CLK_E对第二命令地址奇信号CA[13:0]_1T_O采样会得到C1，经过片选时钟偶信号CS_CLK_E对第二命令地址偶信号CA[13:0]_1T_E采样会得到C2。如此，第一合并输出电路441采样得到的是第一命令地址信号CA在第一时钟周期的有效信息C1，而第二合并输出电路442采样得到的是第二命令地址奇信号CA在第二时钟周期的有效信息C2。
在这里，偶数时钟周期或者奇数时钟周期是指初始时钟信号CK_t/CK_c的时钟周期。具体来说，对初始时钟信号经过分频处理之后，可以得到时钟奇信号PCLK_E和时钟偶信号PCLK_O；然后将时钟偶信号PCLK_E的上升沿所在的时钟周期作为偶数时钟周期，将时钟奇信号PCLK_O的上升沿所在的时钟周期作为奇数时钟周期。
因此，第一合并输出电路441输出的始终是CA在第一时钟周期的有效信息，即第一目标地址信号CA[13:0]_0T；第二合并输出电路442输出的始终是CA在第二时钟周期的有效信息，即第二目标地址信号CA[13:0]_1T。
在一些实施例中，如图8A所示，第一合并输出电路441包括第三逻辑电路、第四逻辑电路和第九采样电路；其中，
第三逻辑电路，用于对片选时钟奇信号进行逻辑运算，得到第一使能奇信号和第二使能奇信号，且第一使能奇信号和第二使能奇信号之间的相位差为180度；
第四逻辑电路，用于对片选时钟偶信号进行逻辑运算，得到第一使能偶信号和第二使能偶信号，且第一使能偶信号和第二使能偶信号之间的相位差为180度；
第九采样电路，用于根据第一使能偶信号、第二使能偶信号、第一使能奇信号和第二使能奇信号对第二命令地址偶信号和第二命令地址奇信号进行采样处理，得到第一目标地址信号。
需要说明的是，如图8A所示，第三逻辑电路可以是由一个反相器和一个缓冲器组成。其中，第一使能偶信号可以用CLKB_E表示，第二使能偶信号可以用CLKT_E表示，且第一使能偶信号和第二使能偶信号之间的相位差为180度。
如图8A所示，第四逻辑电路也可以是由一个反相器和一个缓冲器组成。其中，第一使能奇信号可以用CLKB_O表示，第二使能奇信号可以用CLKT_O表示，且第一使能奇信号和第二使能奇信号之间的相位差为180度。
还需要说明的是，对于第二命令地址偶信号而言，用CA_E表示，其代表了CA[0]_E、CA[1]_E、CA[2]_E、…、CA[13]_E等共14个信号；对于第二命令地址奇信号而言，用CA_O表示，其代表了CA[0]_O、CA[1]_O、CA[2]_O、…、CA[13]_O等共14个信号；也就是说，对于每一组信号(例如，CA[0]_E和CA[0]_O、CA[1]_E和CA[1]_O、…、CA[13]_E和CA[13]_O)都需要一个第九采样电路，即本公开实施例总共需要14个第九采样电路。以用CA[0]_E和CA[0]_O这一组信号为例，如图8A所示，第九采样电路可以是由若干个使能反相器和若干个反相器组成。其中，利用第一使能偶信号CLKB_E和第二使能偶信号CLKT_E对CA[0]_O信号进行采样处理；以及利用第一使能奇信号CLKB_O和第二使能奇信号CLKT_O对CA[0]_E信号进行采样处理，最终输出的第一目标地址信号用CA[0]_0T表示。
另外，参见图9，其示出了一种使能反相器(用Enable Inverter表示)的具体电路结构示意图。其中，(a)为使能反相器的器件符号，(b)为使能反相器的具体组成。如图9所示，输入信号用IN表示，输出信号用OUT表示，使能信号用EN表示。具体地，在本公开实施例中，若使能信号EN为高电平，则使能反相器工作，即需要对输入信号IN进行反相处理以得到输出信号OUT；若输入信号EN为低电平，则使能反相器关断，反相器输出端呈现高阻态。
还需要说明的是，基于第一合并输出电路441的电路结构，在一些实施例中，第九采样电路，具体用于在片选时钟偶信号为高电平有效的脉冲信号情况下，根据第一使能偶信号和第二使能偶信号对第二命令地址奇信号进行采样处理，得到第一目标地址信号；或者，在片选时钟奇信号为高电平有效的脉冲信号情况下，根据第一使能奇信号和第二使能奇信号对第二命令地址偶信号进行采样处理，得到第一目标地址信号。
换句话说，针对图8A所示的第九采样电路的工作原理，具体为：在CLKB_O信号为高电平时，把CA[0]_E信号接收，通过一个使能反相器以及紧接着的反相器，把信号传输到该反相器之后这个节点，等CLKT_O信号为高电平时，再把该信号输出，所以呈现出CLKT_O信号上升沿采样的效果；或者，在CLKB_E信号为高电平时，把CA[0]_O信号接收，通过一个使能反相器以及紧接着的反相器，把信号传输到该反相器之后这个节点，等CLKT_E信号为高电平时，再把该信号输出，所以呈现出CLKT_E信号上升沿采样的效果；最后，在CA[0]_0T信号处的两个首尾相接的反相器则是起到了保持信号的作用。
在本公开实施例中，由于片选时钟偶信号CS_CLK_E和片选时钟奇信号CS_CLK_O中仅有一个为高电平有效的脉冲信号，因此，对于第九采样电路来说，利用CLKT_E采样部分和和CLKT_O采样部分之 中，只有一部分工作，另一部分输出高阻态，最终的CA[0]_0T就可以输出工作的那一部分的结果。
类似地，在一些实施例中，如图8B所示，第二合并输出电路442包括第五逻辑电路、第六逻辑电路和第十采样电路；其中，
第五逻辑电路，用于对片选时钟偶信号进行逻辑运算，得到第三使能偶信号和第四使能偶信号；
第六逻辑电路，用于对片选时钟奇信号进行逻辑运算，得到第三使能奇信号和第四使能奇信号；
第十采样电路，用于根据第三使能偶信号、第四使能偶信号、第三使能奇信号和第四使能奇信号对第二命令地址偶信号和第二命令地址奇信号进行采样处理，得到第二目标地址信号。
需要说明的是，如图8B所示，第五逻辑电路可以是由一个反相器和一个缓冲器组成。其中，第三使能偶信号可以用CLKB_E表示，第四使能偶信号可以用CLKT_E表示，且第三使能偶信号和第四使能偶信号之间的相位差为180度。
如图8B所示，第六逻辑电路也可以是由一个反相器和一个缓冲器组成。其中，第三使能奇信号可以用CLKB_O表示，第四使能奇信号可以用CLKT_O表示，且第三使能奇信号和第四使能奇信号之间的相位差为180度。
还需要说明的是，基于第二合并输出电路442的电路结构，在一些实施例中，第十采样电路，具体用于在片选时钟偶信号为高电平有效的脉冲信号情况下，根据第三使能偶信号和第四使能偶信号对第二命令地址偶信号进行采样处理，得到第二目标地址信号；或者，在片选时钟奇信号为高电平有效的脉冲信号情况下，根据第三使能奇信号和第四使能奇信号对第二命令地址奇信号进行采样处理，得到第二目标地址信号。
还需要说明的是，对于第二命令地址偶信号而言，用CA_E表示，其代表了CA[0]_E、CA[1]_E、CA[2]_E、…、CA[13]_E等共14个信号；对于第二命令地址奇信号而言，用CA_O表示，其代表了CA[0]_O、CA[1]_O、CA[2]_O、…、CA[13]_O等共14个信号；也就是说，对于每一组信号(例如，CA[0]_E和CA[0]_O、CA[1]_E和CA[1]_O、…、CA[13]_E和CA[13]_O)都需要一个第十采样电路，即本公开实施例总共需要14个第十采样电路。以用CA[0]_E和CA[0]_O这一组信号为例，如图8B所示，第十采样电路可以是由若干个使能反相器和若干个反相器组成。其中，利用第三使能偶信号CLKB_E和第四使能偶信号CLKT_E对CA[0]_E信号进行采样处理；以及利用第三使能奇信号CLKB_O和第四使能奇信号CLKT_O对CA[0]_O信号进行采样处理，最终输出的第二目标地址信号用CA[0]_1T表示。
第二合并输出电路442的具体电路原理可以参照第一合并输出电路441进行理解，本公开实施例在此不作赘述。
这样，通过第一合并输出电路441和第二合并输出电路442，输出第一目标信号和第二目标地址信号。在这里，第一目标地址信号包括第一命令地址信号在第一时钟周期里的信息，第二目标地址信号包括第一命令地址信号在第二时钟周期里的信息，且第一时钟周期是指第一片选信号为低电平时的时钟周期，第二时钟周期是第一时钟周期的下一时钟周期。
换句话说，本公开实施例提供的信号采样电路40应用于2个时钟周期的指令信号。具体地，第一命令地址信号CA包括两个时钟周期的有效信号，第一目标地址信号CA_[13:0]_0T是第一命令地址信号CA在第一个时钟周期的有效信号的采样结果，第二目标地址信号CA_[13:0]_1T是CA在第二个时钟周期的有效信号的采样结果。应理解，时钟周期均以分频前的初始时钟信号CK_t/CK_c为基准进行确定。
这样，一方面，针对两个时钟周期的CA输入，通过指令译码电路，能够根据有效的片选时钟信号对第一命令地址信号进行采样和译码，获得目标指令信号；通过第一合并输出电路，能够根据有效的片选时钟信号对第一命令地址信号进行采样，获得第一目标地址信号；通过第二合并输出电路，能够根据有效的片选时钟信号对第一命令地址信号进行采样，获得第二目标地址信号，从而第一目标地址信号、第二目标地址信号和目标指令信号时序对齐。另一方面，通过屏蔽第一片选信号无效时的第一时钟信号，还可以将奇偶采样的地址总线合并，从而能够实现减半地址总线数量。
本公开实施例提供了一种信号采样电路，该信号采样电路包括输入采样电路、逻辑运算电路、指令译码电路和合并输出电路；其中，输入采样电路，用于根据第一时钟信号分别对第一片选信号和第一命令地址信号进行采样处理，得到第二片选信号和第二命令地址信号；其中，第二命令地址信号包括初始指令信号，且第二命令地址信号由第二命令地址奇信号和第二命令地址偶信号组成；逻辑运算电路，用于对第一时钟信号和第二片选信号进行逻辑运算，得到片选时钟信号；其中，片选时钟信号包含片选时钟奇信号和片选时钟偶信号；指令译码电路，用于根据第二片选信号和片选时钟信号对初始指令信号进行译码处理和采样处理，得到目标指令信号；合并输出电路，用于根据片选时钟偶信号和片选时钟奇信号分别对第二命令地址奇信号和第二命令地址偶信号进行采样处理，得到第一目标地址信号；并根据片选时钟奇信号和片选时钟偶信号分别对第二命令地址奇信号和第二命令地址偶信号进行采样处理，得到第二目标地址信号。其中，目标指令信号、第一目标地址信号和第二目标地址信号之间的时序对齐。这样，基于该信号采样电路，在同一时钟周期的采样下，能够实现目标指令信号、第一目标地址信号和第二目标地址信号的时序对 齐，使得译码之后的指令信号和地址信号之间没有跟随PVT变化的偏差，从而可以避免下一级功能模块因时序偏差而出现问题。
在本公开的另一实施例中，基于前述实施例所述的信号采样电路40，参见图10，其示出了本公开实施例提供的一种信号采样电路的详细结构示意图。如图10所示，信号采样电路40可以包括第一接收器601、第二接收器602、第三接收器603、第一采样电路604、第二采样电路605、第三采样电路606、第四采样电路607、第五采样电路608、第六采样电路609、第一缓冲器610、第一与门611、第二缓冲器612、第二与门613、指令译码触发器614、或门615、第一合并输出触发器616、第二合并输出触发器617、第一功能模块618、第二功能模块619和第三功能模块620。其中，第一采样电路604、第二采样电路605、第四采样电路607和第六采样电路609是由D型触发器组成，第三采样电路606和第五采样电路608是由D型触发器和反相器组成；另外，指令译码触发器614可以包括第一指令译码电路和第二指令译码电路，具体结构详见图7A图和图7B所示；第一合并输出触发器617的内部结构详见图8A所示，第二合并输出触发器618的内部结构详见图8B所示。
在图10中，首先，第一接收器601的输入信号为初始命令地址信号(用CA[13:0]表示)和参考信号(用VREFCA表示)，输出信号为第一命令地址信号(用CA表示)；需要注意的是，对于初始命令地址信号CA[13:0]，其并非是一个信号，而是代表一组信号，即CA[13:0]包括了CA[13]～CA[0]；针对每一个信号都需要一个第一接收器601，故本公开实施例需要14个第一接收器601，图中仅示出一个第一接收器601作为示意；第二接收器602的输入信号为初始片选信号(用CS_n表示)和参考信号(用VREFCA表示)，输出信号为第一片选信号(用PCS表示)；第三接收器603的输入信号为初始时钟信号(用CK_t/CK_c)，经过分频处理后输出信号为时钟偶信号(用PCLK_E表示)和时钟奇信号(用PCLK_O表示)。在这里，PCLK_E_/PCLK_O的时钟周期是CK_t/CK_c的时钟周期的两倍，PCLK_E_/PCLK_O的频率是CK_t/CK_c的频率的一半。
然后，通过第一采样电路604，利用时钟奇信号对第一命令地址信号进行采样处理，得到第二命令地址奇信号(用CA[13:0]_1T_O表示)，且第二命令地址奇信号包括初始指令奇信号(用CA[4:0]_1T_O表示)；通过第二采样电路605，利用时钟偶信号对第一命令地址信号进行采样处理，得到第二命令地址偶信号(用CA[13:0]_1T_E表示)，且第二命令地址偶信号包括初始指令偶信号(用CA[4:0]_1T_E表示)；通过第三采样电路606，利用时钟奇信号对第一片选信号进行采样及反相处理，得到中间采样奇信号(用PCS_O表示)，通过第四采样电路607，利用时钟偶信号对中间采样奇信号进行采样处理，得到第二片选偶信号(用PCS_ED表示)；通过第五采样电路608，利用时钟偶信号对第一片选信号进行采样及反相处理，得到中间采样偶信号(用PCS_E表示)，通过第六采样电路609，利用时钟奇信号对中间采样偶信号进行采样处理，得到第二片选奇信号(用PCS_OD表示)；再利用第一缓冲器610和第一与门611对时钟偶信号和第二片选偶信号进行逻辑运算，得到片选时钟偶信号(用CS_CLK_E表示)；利用第二缓冲器612和第二与门613对时钟奇信号和第二片选奇信号进行逻辑运算，得到片选时钟奇信号(用CS_CLK_O表示)。
最后，通过指令译码触发器614，利用片选时钟偶信号、片选时钟奇信号对初始指令偶信号、初始指令奇信号、第二片选偶信号和第二片选奇信号进行译码及采样处理，得到指令偶信号(用CMD_E表示)和指令奇信号(用CMD_O表示)，再通过或门615对指令偶信号和指令奇信号进行或逻辑运算，得到目标指令信号(用CMD表示)，另外，指令译码器614的具体工作原理可参见前述实施例，在此不作赘述；以及通过第一合并输出触发器616，利用片选时钟偶信号对第二命令地址奇信号进行采样，同时利用片选时钟奇信号对第二命令地址偶信号进行采样，所得到的有效采样结果就是第一目标地址信号(用CA[13:0]_0T表示)；通过第二合并输出触发器617，利用第二命令地址偶信号对第二命令地址偶信号进行采样，同时利用第二命令地址奇信号对第二命令地址奇信号进行采样，所得到的有效采样结果就是第二目标地址信号(用CA[13:0]_1T表示)。
这样，由于目标指令信号CMD、第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T均是根据有效的片选时钟信号(片选时钟奇信号CS_CLK_O或者片选时钟偶信号CS_CLK_E)采样输出的，因此目标指令信号CMD、第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T的时序对齐。
此外，目标指令信号CMD、第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T均通过长走线路径(Long Routing Line)到达第一功能模块618、第二功能模块619和第三功能模块620。在这里，由于目标指令信号CMD、第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T已经时序对齐，需要控制目标指令信号CMD、第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T的长走线路径尽可能的长度和宽度一致。这样，由于目标指令信号CMD、第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T的输出时序对齐，从而使得目标指令信号CMD、第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T到达不同的功能模块去实现下一级功能时 不会因为时序偏差出现错误。
在一种具体的场景中，假设初始片选信号在偶数时钟周期采样呈现低电平有效，此时图10所示的信号采样电路的信号时序图如图11所示。在图11中，第一命令地址信号CA可以包括Cy、Cz、C0、C1、C2和C3，初始片选信号用CS_n表示，第一片选信号用PCS表示，PCS信号为低电平有效的脉冲信号，且脉冲宽度为预设时钟周期，PCS用于表征目标芯片被选中的信号；其他信号的说明请参见前述。在这里，偶数时钟周期或者奇数时钟周期是指初始时钟信号CK_t/CK_c的时钟周期。具体来说，经过第三接收器603的分频处理之后，可以得到时钟奇信号PCLK_E和时钟偶信号PCLK_O；然后将时钟偶信号PCLK_E的上升沿所在的时钟周期作为偶数时钟周期，将时钟奇信号PCLK_O的上升沿所在的时钟周期作为奇数时钟周期。
在利用时钟偶信号PCLK_E的上升沿对第一命令地址信号CA进行采样处理后，得到第二命令地址偶信号CA[13:0]_1T_E，其包括C0和C2；在利用时钟奇信号PCLK_O的上升沿对CA信号进行采样处理后，得到第二命令地址奇信号CA[13:0]_1T_O，其包括C1和C3。特别地，CA[13:0]_1T_E中包括初始指令偶信号CA[4:0]_1T_E。
在利用时钟偶信号PCLK_E的上升沿对第一片选信号PCS信号进行采样及反相处理后，得到中间采样偶信号PCS_E，并利用时钟奇信号PCLK_O的上升沿对中间采样偶信号PCS_E进行采样，得到第二片选奇信号PCS_OD。在利用时钟奇信号PCLK_O的上升沿对第一片选信号PCS进行采样及反相处理后，得到中间采样奇信号PCS_O；并利用时钟偶信号PCLK_E的上升沿对中间采样奇信号PCS_O进行采样，得到第二片选偶信号PCS_ED。
在本场景中，第一片选信号PCS在偶数时钟周期采样呈现低电平有效，因此中间采样偶信号PCS_E和第二片选奇信号PCS_OD均为高电平有效的脉冲信号，而且脉冲宽度为2个时钟周期。另外，利用第二缓冲器612和第二与门613对时钟奇信号PCLK_O和第二片选奇信号PCS_OD进行逻辑运算后，得到的片选时钟奇信号CS_CLK_O，其为高电平有效的脉冲信号，而且脉冲宽度为1个时钟周期。这样，利用前述的指令译码触发器614，以片选时钟奇信号CS_CLK_O为有效时钟信号，采样译码后的CA[4:0]_1T_E，输出目标指令信号CMD信号；利用前述的第一合并输出触发器616，以片选时钟奇信号CS_CLK_O为有效时钟信号，采样第二命令地址偶信号CA[13:0]_1T_E，输出第一目标地址信号CA[13:0]_0T；利用前述的第二合并输出触发器617，以片选时钟奇信号CS_CLK_O为有效时钟信号，采样第二命令地址奇信号CA[13:0]_1T_O，输出第二目标地址信号CA[13:0]_1T，从而目标指令信号CMD、第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T信号之间的时序对齐。
另外，在本场景中，初始片选信号在偶数时钟周期采样呈现低电平有效，因此中间采样奇信号PCS_O和第二片选偶信号PCS_ED均为无效信号。而利用第一缓冲器610和第一与门611对时钟偶信号PCLK_E和PCS_ED信号进行逻辑运算后，得到片选时钟偶信号CS_CLK_E同样为无效信号，从对指令译码触发器614、第一合并输出触发器617和第二合并输出触发器618并不会利用片选时钟偶信号CS_CLK_E进行采样输出。
当然，在另一场景中，假设初始片选信号在奇数时钟沿采样呈现低电平有效，此时中间采样偶信号PCS_E、第二片选奇信号PCS_OD、片选时钟奇信号CS_CLK_O将处于无效状态；中间采样奇信号PCS_O、第二片选偶信号PCS_ED、片选时钟偶信号CS_CLK_E将处于有效状态，从对指令译码触发器614、第一合并输出触发器616和第二合并输出触发器617将根据片选时钟偶信号CS_CLK_E进行采样输出，分别得到目标指令信号CMD、第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T。此时，目标指令信号CMD、第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T同样是时序对齐的。
需要注意的是，在图11中，在同一个时钟周期，对于时钟奇信号PCLK_O的上升沿和片选时钟奇信号CS_CLK_O的上升沿之间的延时，则是由第二缓冲器612和第二与门613等逻辑器件自身产生的。
综上所述，在本公开实施例中，为了避免目标指令信号CMD、第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T之间的输出偏差，这里可以利用片选时钟奇信号CS_CLK_O或者片选时钟偶信号CS_CLK_E进行采样，从而使得目标指令信号CMD、第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T之间的输出时序对齐，进而使得目标指令信号CMD、第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T到达不同的功能模块去实现下一级功能时不会因为时序偏差出现错误。
本公开实施例提供了一种信号采样电路，通过本实施例对前述实施例的具体实现进行详细阐述，从中可以看出，本公开实施例是在已有的直接采样译码的基础上进行优化，使得译码后的指令(目标指令信号)和采样的地址(第一目标地址信号和第二目标地址信号)之间没有随PVT变化的Skew。具体来说，在本公开实施例中，通过增加指令译码触发器、第一合并输出触发器和第二合并触发器，并且利用同一个片选时钟信号(CS_CLK_E或CS_CLK_O)来进行一次采样，从而能够对齐目标指令信号CMD、第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T；而且通过本公开实施例提供的第一合并输出触发 器和第二合并输出触发器，将奇偶采样的地址总线合并，仅保留有效地址总线，从而还能够实现减半地址总线数量。
在本公开的又一实施例中，参见图12，其示出了本公开实施例提供的一种半导体存储器120的组成结构示意图。如图12所示，半导体存储器120可以包括前述实施例任一项所述的信号采样电路40。
在本公开实施例中，半导体存储器120可以为DRAM芯片。
进一步地，在一些实施例中，DRAM芯片符合DDR5内存规格。
需要说明的是，本公开实施例主要涉及集成电路设计中输入信号采样及指令译码的相关电路，特别涉及DRAM芯片中，CA信号输入分别作为指令和地址采样，以及译码之后的控制调节电路。具体来说，本公开实施例是针对2T CMD，在已有的直接采样译码的基础上进行优化，使得译码后的目标指令信号CMD和采样的第一目标地址信号CA[13:0]_0T和第二目标地址信号CA[13:0]_1T之间没有随PVT变化的偏差。
还需要说明的是，本公开实施例可以应用于DRAM芯片中CA信号采样和译码的控制电路，但并不局限于此范围，其他输入信号采样及指令译码的相关电路均可采用此设计。
这样，在本公开实施例中，对于半导体存储器120而言，其包括有信号采样电路40，因此，在同一时钟周期的采样下，能够实现目标指令信号、第一目标地址信号和第二目标地址信号的时序对齐，使得译码之后的指令信号和地址信号之间没有跟随PVT变化的偏差，从而可以避免下一级功能模块因时序偏差而出现问题。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种信号采样电路以及半导体存储器，包括：输入采样电路，根据第一时钟信号分别对第一片选信号和第一命令地址信号进行采样处理，得到第二片选信号和第二命令地址信号；逻辑运算电路，对第一时钟信号和第二片选信号进行逻辑运算，得到片选时钟信号；指令译码电路，根据第二片选信号和片选时钟信号对初始指令信号进行译码和采样，得到目标指令信号；合并输出电路，根据片选时钟偶信号和片选时钟奇信号对第二命令地址奇信号和第二命令地址偶信号进行采样，得到第一目标地址信号；根据片选时钟奇信号和片选时钟偶信号对第二命令地址奇信号和第二命令地址偶信号进行采样，得到第二目标地址信号。本公开实施例能够改善信号时序偏差。

Claims (19)

  1. 一种信号采样电路，所述信号采样电路包括输入采样电路、逻辑运算电路、指令译码电路和合并输出电路；其中，
    所述输入采样电路，用于根据第一时钟信号分别对第一片选信号和第一命令地址信号进行采样处理，得到第二片选信号和第二命令地址信号；其中，所述第二命令地址信号包括初始指令信号，且所述第二命令地址信号由第二命令地址奇信号和第二命令地址偶信号组成；
    所述逻辑运算电路，用于对所述第一时钟信号和所述第二片选信号进行逻辑运算，得到片选时钟信号；其中，所述片选时钟信号包含片选时钟奇信号和片选时钟偶信号；
    所述指令译码电路，用于根据所述第二片选信号和所述片选时钟信号对所述初始指令信号进行译码处理和采样处理，得到目标指令信号；
    所述合并输出电路，用于根据所述片选时钟偶信号和所述片选时钟奇信号分别对所述第二命令地址奇信号和所述第二命令地址偶信号进行采样处理，得到第一目标地址信号；并根据所述片选时钟奇信号和所述片选时钟偶信号分别对所述第二命令地址奇信号和所述第二命令地址偶信号进行采样处理，得到第二目标地址信号。
  2. 根据权利要求1所述的信号采样电路，其中，所述信号采样电路还包括接收电路，且所述接收电路包括第一接收电路、第二接收电路和第三接收电路；其中，
    所述第一接收电路，用于接收初始命令地址信号，输出所述第一命令地址信号；
    所述第二接收电路，用于接收初始片选信号，输出所述第一片选信号；
    所述第三接收电路，用于接收初始时钟信号，并对所述初始时钟信号进行分频处理，得到时钟奇信号和时钟偶信号；
    其中，所述时钟奇信号和所述时钟偶信号的时钟周期均是所述初始时钟信号的时钟周期的两倍，且所述时钟奇信号和所述时钟偶信号之间的相位差为180度，所述时钟奇信号和所述时钟偶信号组成所述第一时钟信号。
  3. 根据权利要求2所述的信号采样电路，其中，所述输入采样电路包括命令地址采样电路，且所述命令地址采样电路包括第一采样电路和第二采样电路；其中，
    所述第一采样电路，用于根据所述时钟奇信号对所述第一命令地址信号进行采样，得到所述第二命令地址奇信号；
    所述第二采样电路，用于通过所述时钟偶信号对所述第一命令地址信号进行采样，得到所述第二命令地址偶信号；
    其中，所述初始指令信号是由初始指令偶信号和初始指令奇信号组成，且所述第二命令地址偶信号包括初始指令偶信号，所述第二命令地址奇信号包括初始指令奇信号。
  4. 根据权利要求3所述的信号采样电路，其中，所述输入采样电路还包括片选采样电路，且所述片选采样电路包括第三采样电路、第四采样电路、第五采样电路和第六采样电路；
    所述第三采样电路，用于根据所述时钟奇信号对所述第一片选信号进行采样，得中间采样奇信号；
    所述第四采样电路，用于根据所述时钟偶信号对所述中间采样奇信号进行采样，得到第二片选偶信号；
    所述第五采样电路，用于根据所述时钟偶信号对所述第一片选信号进行采样，得到中间采样偶信号；
    所述第六采样电路，用于通过所述时钟奇信号对所述中间采样偶信号进行采样，得到第二片选奇信号；
    其中，所述第二片选信号由所述第二片选偶信号和所述第二片选奇信号组成。
  5. 根据权利要求4所述的信号采样电路，其中，所述逻辑运算电路包括第一逻辑电路和第二逻辑电路；其中，
    所述第一逻辑电路，用于接收所述时钟偶信号和所述第二片选偶信号，并对所述时钟偶信号和所述第二片选偶信号进行逻辑运算，得到所述片选时钟偶信号；
    所述第二逻辑电路，用于接收所述时钟奇信号和所述第二片选奇信号，并对所述时钟奇信号和所述第二片选奇信号进行逻辑运算，得到所述片选时钟奇信号。
  6. 根据权利要求5所述的信号采样电路，其中，所述第一逻辑电路包括第一缓冲器和第一与门；其中，
    所述第一缓冲器，用于对所述时钟偶信号进行延时处理，得到中间时钟偶信号；
    所述第一与门，用于对所述第二片选偶信号和所述中间时钟偶信号进行与运算，得到所述片选时钟偶信号。
  7. 根据权利要求5所述的信号采样电路，其中，所述第二逻辑电路包括第二缓冲器和第二与门；其中，
    所述第二缓冲器，用于对所述时钟奇信号进行延时处理，得到中间时钟奇信号；
    所述第二与门，用于对所述第二片选奇信号和所述中间时钟奇信号进行与运算，得到所述片选时钟奇信号。
  8. 根据权利要求4所述的信号采样电路，其中，所述指令译码电路包括第一指令译码电路、第二指令译码电路以及或门；其中，
    所述第一指令译码电路，用于根据所述片选时钟偶信号和所述第二片选偶信号对所述初始指令奇信号进行译码和采样处理，得到指令偶信号；
    所述第二指令译码电路，用于根据所述片选时钟奇信号和所述第二片选奇信号对所述初始指令偶信号进行译码和采样处理，得到指令奇信号；
    所述或门，用于对所述指令偶信号和所述指令奇信号进行或运算，得到所述目标指令信号。
  9. 根据权利要求8所述的信号采样电路，其中，所述第一指令译码电路包括第一译码电路、第七采样电路和第三与门；其中，
    所述第一译码电路，用于对所述初始指令奇信号进行译码处理，得到指令译码奇信号；
    所述第七采样电路，用于根据所述片选时钟偶信号对所述指令译码奇信号进行采样处理，得到指令采样偶信号；
    所述第三与门，用于对所述第二片选偶信号与所述指令采样偶信号进行与运算，得到所述指令偶信号。
  10. 根据权利要求8所述的信号采样电路，其中，所述第二指令译码电路包括第二译码电路、第八采样电路和第四与门；其中，
    所述第二译码电路，用于对所述初始指令偶信号进行译码处理，得到指令译码偶信号；
    所述第八采样电路，用于根据所述片选时钟奇信号对所述指令译码偶信号进行采样处理，得到指令采样奇信号；
    所述第四与门，用于对所述第二片选奇信号与所述指令采样奇信号进行与运算，得到所述指令奇信号。
  11. 根据权利要求3所述的信号采样电路，其中，所述合并输出电路包括第一合并输出电路和第二合并输出电路；其中，
    所述第一合并输出电路，用于根据所述片选时钟奇信号对所述第二命令地址偶信号进行采样，得到所述第一目标地址信号；或者，根据所述片选时钟偶信号对所述第二命令地址奇信号进行采样，得到所述第一目标地址信号；
    所述第二合并输出电路，用于根据所述片选时钟奇信号对所述第二命令地址奇信号进行采样，得到所述第二目标地址信号；或者，根据所述片选时钟偶信号对所述第二命令地址偶信号进行采样，得到所述第二目标地址信号；
    其中，所述第一合并输出电路的第一数据端、第二数据端、第一时钟端和第二时钟端与所述第二命令地址奇信号、所述第二命令地址偶信号、所述片选时钟偶信号和所述片选时钟奇信号对应连接，所述第二合并输出电路的第一数据端、第二数据端、第一时钟端和第二时钟端与所述第二命令地址奇信号、所述第二命令地址偶信号、所述片选时钟奇信号和所述片选时钟偶信号对应连接。
  12. 根据权利要求11所述的信号采样电路，其中，所述第一合并输出电路包括第三逻辑电路、第四逻辑电路和第九采样电路；其中，
    所述第三逻辑电路，用于对所述片选时钟奇信号进行逻辑运算，得到第一使能奇信号和第二使能奇信号，且所述第一使能奇信号和所述第二使能奇信号之间的相位差为180度；
    所述第四逻辑电路，用于对所述片选时钟偶信号进行逻辑运算，得到第一使能偶信号和第二使能偶信号，且所述第一使能偶信号和所述第二使能偶信号之间的相位差为180度；
    所述第九采样电路，用于根据所述第一使能偶信号、所述第二使能偶信号、所述第一使能奇信号和所述第二使能奇信号对所述第二命令地址偶信号和所述第二命令地址奇信号进行采样处理，得到所述第一目标地址信号。
  13. 根据权利要求12所述的信号采样电路，其中，
    所述第九采样电路，具体用于在所述片选时钟偶信号为高电平有效的脉冲信号情况下，根据所述第一使能偶信号和所述第二使能偶信号对所述第二命令地址奇信号进行采样处理，得到所述第一目标地址信号；或者，在所述片选时钟奇信号为高电平有效的脉冲信号情况下，根据所述第一使能奇信号和所述第二使能奇信号对所述第二命令地址偶信号进行采样处理，得到所述第一目标地址信号。
  14. 根据权利要求11所述的信号采样电路，其中，所述第二合并输出电路包括第五逻辑电路、第六 逻辑电路和第十采样电路；其中，
    所述第五逻辑电路，用于对所述片选时钟偶信号进行逻辑运算，得到第三使能偶信号和第四使能偶信号，且所述第三使能偶信号和所述第四使能偶信号之间的相位差为180度；
    所述第六逻辑电路，用于对所述片选时钟奇信号进行逻辑运算，得到第三使能奇信号和第四使能奇信号；且所述第三使能奇信号和所述第四使能奇信号之间的相位差为180度；
    所述第十采样电路，用于根据所述第三使能偶信号、所述第四使能偶信号、所述第三使能奇信号和所述第四使能奇信号对所述第二命令地址偶信号和所述第二命令地址奇信号进行采样处理，得到所述第二目标地址信号。
  15. 根据权利要求14所述的信号采样电路，其中，
    所述第十采样电路，具体用于在所述片选时钟偶信号为高电平有效的脉冲信号情况下，根据所述第三使能偶信号和所述第四使能偶信号对所述第二命令地址偶信号进行采样处理，得到所述第二目标地址信号；或者，在所述片选时钟奇信号为高电平有效的脉冲信号情况下，根据所述第三使能奇信号和所述第四使能奇信号对所述第二命令地址奇信号进行采样处理，得到所述第二目标地址信号。
  16. 根据权利要求5所述的信号采样电路，其中，所述第一片选信号是表征目标芯片被选中的信号，且所述第一片选信号为低电平有效的脉冲信号；其中，
    若所述第一片选信号在偶数时钟周期的上升沿采样为低电平，则所述第二片选奇信号为高电平有效的脉冲信号，以及所述片选时钟奇信号为高电平有效的脉冲信号；或者，若所述第一片选信号在奇数时钟周期的上升沿采样为低电平，则所述第二片选偶信号为高电平有效的脉冲信号，以及所述片选时钟偶信号为高电平有效的脉冲信号。
  17. 根据权利要求16所述的信号采样电路，其中，所述第一目标地址信号包括所述第一命令地址信号在第一时钟周期里的信息，所述第二目标地址信号包括所述第一命令地址信号在第二时钟周期里的信息，且所述第一时钟周期是指所述第一片选信号为低电平时的时钟周期，所述第二时钟周期是所述第一时钟周期的下一时钟周期。
  18. 一种半导体存储器，包括如权利要求1至17任一项所述的信号采样电路。
  19. 根据权利要求18所述的半导体存储器，其中，所述半导体存储器为动态随机存取存储器DRAM芯片。
PCT/CN2022/099265 2022-03-23 2022-06-16 一种信号采样电路以及半导体存储器 WO2023178848A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/449,060 US20230386553A1 (en) 2022-03-23 2023-08-14 Signal sampling circuit and semiconductor memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210291688.8A CN116844605B (zh) 2022-03-23 2022-03-23 一种信号采样电路以及半导体存储器
CN202210291688.8 2022-03-23

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/449,060 Continuation US20230386553A1 (en) 2022-03-23 2023-08-14 Signal sampling circuit and semiconductor memory

Publications (1)

Publication Number Publication Date
WO2023178848A1 true WO2023178848A1 (zh) 2023-09-28

Family

ID=88099698

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/099265 WO2023178848A1 (zh) 2022-03-23 2022-06-16 一种信号采样电路以及半导体存储器

Country Status (3)

Country Link
US (1) US20230386553A1 (zh)
CN (1) CN116844605B (zh)
WO (1) WO2023178848A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140253188A1 (en) * 2013-03-06 2014-09-11 Samsung Electronics Co., Ltd. Divided clock generation device and divided clock generation method
US20180059764A1 (en) * 2016-08-30 2018-03-01 Micron Technology, Inc. Apparatuses for reducing clock path power consumption in low power dynamic random access memory
CN109903793A (zh) * 2017-12-08 2019-06-18 三星电子株式会社 半导体存储装置和存储系统
CN110574111A (zh) * 2017-07-13 2019-12-13 美光科技公司 半频命令路径

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6675272B2 (en) * 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
JP2003085999A (ja) * 2001-09-07 2003-03-20 Mitsubishi Electric Corp 半導体記憶装置
KR102222968B1 (ko) * 2014-09-01 2021-03-04 삼성전자주식회사 어드레스 정렬기 및 이를 포함하는 메모리 장치
KR102634315B1 (ko) * 2016-05-11 2024-02-13 삼성전자주식회사 패리티 에러 검출 회로를 포함하는 메모리 장치
CN109754841B (zh) * 2017-11-08 2023-03-24 三星电子株式会社 包括奇偶校验错误检测电路的存储器件
KR20200088650A (ko) * 2019-01-15 2020-07-23 에스케이하이닉스 주식회사 클럭 신호에 동기되는 신호 생성 회로 및 이를 이용하는 반도체 장치
KR20210020584A (ko) * 2019-08-16 2021-02-24 에스케이하이닉스 주식회사 클럭 신호에 동기되는 신호 생성 회로 및 이를 이용하는 반도체 장치
CN114038492B (zh) * 2021-11-11 2024-04-16 桂林电子科技大学 一种多相采样存内计算电路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140253188A1 (en) * 2013-03-06 2014-09-11 Samsung Electronics Co., Ltd. Divided clock generation device and divided clock generation method
US20180059764A1 (en) * 2016-08-30 2018-03-01 Micron Technology, Inc. Apparatuses for reducing clock path power consumption in low power dynamic random access memory
CN110574111A (zh) * 2017-07-13 2019-12-13 美光科技公司 半频命令路径
CN109903793A (zh) * 2017-12-08 2019-06-18 三星电子株式会社 半导体存储装置和存储系统

Also Published As

Publication number Publication date
CN116844605A (zh) 2023-10-03
CN116844605B (zh) 2024-05-03
US20230386553A1 (en) 2023-11-30

Similar Documents

Publication Publication Date Title
US20230307023A1 (en) Signal sampling circuit and semiconductor memory
US8700818B2 (en) Packet based ID generation for serially interconnected devices
US11150686B2 (en) Apparatuses for reducing clock path power consumption in low power dynamic random access memory
US9166579B2 (en) Methods and apparatuses for shifting data signals to match command signal delay
US20230009525A1 (en) Signal sampling circuit and semiconductor memory
US7974145B2 (en) Semiconductor memory device using bus inversion scheme
WO2023178805A1 (zh) 一种信号采样电路以及半导体存储器
WO2023178848A1 (zh) 一种信号采样电路以及半导体存储器
US20180130516A1 (en) Training controller, and semiconductor device and system including the same
US20230013811A1 (en) Signal sampling circuit and semiconductor memory device
WO2023178803A1 (zh) 一种信号采样电路以及半导体存储器
TWI828248B (zh) 一種信號取樣電路以及半導體記憶體
TWI846103B (zh) 訊號採樣電路以及半導體記憶體
TWI828279B (zh) 一種信號取樣電路以及半導體記憶體
US9659617B2 (en) Clock control device
US20230017682A1 (en) Signal sampling circuit and semiconductor memory
US20240128935A1 (en) Differential signaling circuit for correcting for duty change due to nbti degradation, operating method thereof, and semiconductor device including the same
KR100853465B1 (ko) 내부리드신호 생성회로와 이를 포함하는 반도체 메모리장치
JP2022082288A (ja) 半導体装置
JP2013073660A (ja) 半導体装置
JPH07248928A (ja) 選択回路
KR20080047027A (ko) 반도체 메모리 장치 및 그 구동 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22932900

Country of ref document: EP

Kind code of ref document: A1