WO2023162965A1 - 配線基板 - Google Patents

配線基板 Download PDF

Info

Publication number
WO2023162965A1
WO2023162965A1 PCT/JP2023/006187 JP2023006187W WO2023162965A1 WO 2023162965 A1 WO2023162965 A1 WO 2023162965A1 JP 2023006187 W JP2023006187 W JP 2023006187W WO 2023162965 A1 WO2023162965 A1 WO 2023162965A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
insulating layer
wiring board
wiring
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/006187
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
大地 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to US18/841,569 priority Critical patent/US20250168970A1/en
Priority to CN202380023743.8A priority patent/CN118765538A/zh
Priority to JP2024503165A priority patent/JP7778219B2/ja
Priority to EP23759966.7A priority patent/EP4489532A1/en
Priority to KR1020247028762A priority patent/KR20240141302A/ko
Publication of WO2023162965A1 publication Critical patent/WO2023162965A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0242—Structural details of individual signal conductors, e.g. related to the skin effect
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377—Protective layers

Definitions

  • the present invention relates to a wiring board and a mounting structure using the same.
  • Patent Document 1 describes that the surface of a resin substrate (insulating layer) is roughened to improve the adhesion between the wiring pattern and the insulating layer. ing.
  • a wiring board includes an insulating layer having a first surface and a second surface located opposite to the first surface, and a first wiring conductor located on the first surface.
  • the first surface of the insulating layer has a first region with a first arithmetic mean roughness and a second region with a second arithmetic mean roughness.
  • the second arithmetic mean roughness is greater than the first arithmetic mean roughness, and the first wiring conductor extends from the first region to the second region.
  • a mounting structure according to the present disclosure includes the wiring board described above and an element positioned on the surface of the wiring board.
  • FIG. 1 is an explanatory diagram for explaining a wiring board according to an embodiment of the present disclosure
  • FIG. FIG. 2 is an enlarged explanatory view for explaining one embodiment of a cross section of a region X shown in FIG. 1
  • 3 is an enlarged explanatory view for explaining another embodiment of the cross section of the region X shown in FIG. 1
  • FIG. 2 is an enlarged explanatory view for explaining a cross section of a region Y shown in FIG. 1
  • FIG. FIG. 4 is an explanatory diagram for explaining an embodiment of a method of forming first regions 2a and second regions 2b in an insulating layer (insulating layer for buildup)
  • FIG. 8 is an explanatory diagram for explaining another embodiment of a method of forming first regions 2a and second regions 2b in an insulating layer (insulating layer for buildup);
  • the wiring board according to the present disclosure has a configuration as described in the column of Means for Solving the Problems, thereby reducing the deterioration of electrical characteristics and making it difficult for the wiring conductor to peel off.
  • FIG. 1 is an explanatory diagram for explaining a wiring board 1 according to an embodiment of the present disclosure.
  • a wiring board 1 according to one embodiment includes an insulating layer 2, a conductor layer 3 and a solder resist 4. As shown in FIG. 1,
  • the insulating layer 2 includes a core insulating layer 21 and a build-up insulating layer 22 .
  • the core insulating layer 21 is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resins, bismaleimide-triazine resins, polyimide resins, and polyphenylene ether resins. These resins may be used in combination of two or more.
  • the thickness of the core insulating layer 21 is not particularly limited, and is, for example, 40 ⁇ m or more and 1800 ⁇ m or less.
  • the core insulating layer 21 may contain a reinforcing material.
  • reinforcing materials include insulating cloth materials such as glass fibers, glass nonwoven fabrics, aramid nonwoven fabrics, aramid fibers, and polyester fibers. Two or more reinforcing materials may be used in combination.
  • inorganic insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide may be dispersed in the core insulating layer 21 .
  • Through-hole conductors 21 a are located in the core insulating layer 21 to electrically connect the upper and lower surfaces of the core insulating layer 21 .
  • the through-hole conductor 21a is located in a through-hole penetrating from the upper surface to the lower surface of the core insulating layer 21 .
  • the through-hole conductors 21a are formed by, for example, metal plating such as copper plating.
  • Through-hole conductors 21 a are connected to conductor layers 3 formed on both surfaces of core insulating layer 21 .
  • the through-hole conductor 21a may be positioned only on the inner wall surface of the through-hole, or may be filled in the through-hole.
  • the conductor layer 3 is not limited as long as it is made of a conductor such as metal. Specifically, the conductor layer 3 is formed of metal foil such as copper foil, metal plating such as copper plating, or the like. The thickness of the conductor layer 3 is not particularly limited, and is, for example, 10 ⁇ m or more and 30 ⁇ m or less.
  • the build-up insulating layer 22 is not particularly limited as long as it is made of an insulating material, like the core insulating layer 21 .
  • insulating materials include resins such as epoxy resins, bismaleimide-triazine resins, polyimide resins, and polyphenylene ether resins. These resins may be used in combination of two or more.
  • the buildup insulating layers 22 may be made of the same resin, or may be made of different resins.
  • the buildup insulating layer 22 and the core insulating layer 21 may be made of the same resin or may be made of different resins.
  • inorganic insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide may be dispersed in the build-up insulating layer 22 .
  • the thickness of the buildup insulating layer 22 is not particularly limited, and is, for example, 25 ⁇ m or more and 40 ⁇ m or less.
  • the buildup insulating layers 22 may have the same thickness, or may have different thicknesses.
  • a via-hole conductor 22a for electrically connecting the layers is formed in the build-up insulating layer 22 .
  • the via-hole conductors 22a are located in via-holes penetrating the upper and lower surfaces of the buildup insulating layer 22 .
  • the via-hole conductors 22a are formed by, for example, metal plating such as copper plating.
  • the via-hole conductors 22 a are connected to the conductor layers 3 located on both sides of the build-up insulating layer 22 .
  • the via-hole conductor 22a may be filled in the via-hole, or may be located only on the inner wall surface of the via-hole.
  • a solder resist 4 may be located on the surface of the buildup layer.
  • the solder resist 4 is made of a resin such as an acrylic-modified epoxy resin.
  • the solder resist 4 is provided with openings for electrically connecting the conductor layer 3 and the electrodes of the device via the solder 5 .
  • Devices include, for example, semiconductor integrated circuit devices and optoelectronic devices.
  • the build-up insulating layer 22 has a first surface 221 and a second surface 222 located on the opposite side of the first surface 221, as shown in FIG.
  • FIG. 2 is an enlarged explanatory view for explaining one embodiment of the cross section of the region X shown in FIG.
  • the first surface 221 has a first region 2a having a first arithmetic mean roughness and a second region 2b having a second arithmetic mean roughness.
  • the second arithmetic mean roughness of the second region 2b is larger than the first arithmetic mean roughness of the first region 2a.
  • the first wiring conductor 31 is located from the first region 2a to the second region 2b. In this way, by locating in regions with different arithmetic mean roughnesses, the deterioration of electrical characteristics is reduced in the first region 2a with a small arithmetic mean roughness, and the first wiring is reduced in the second region 2b with a large arithmetic mean roughness. Adhesion of the conductor 31 can be improved. As a result, the wiring board 1 reduces the deterioration of the electrical characteristics and makes it difficult for the first wiring conductors 31 to peel off.
  • the conductor layer 3 generally includes power supply conductors, ground conductors and signal conductors.
  • the first wiring conductor 31 is, for example, a signal conductor.
  • the arithmetic average roughness (third arithmetic average roughness) of the side surface of the first wiring conductor 31 and the surface opposite to the surface in contact with the first surface 221 may be smaller than the first arithmetic average roughness.
  • the third arithmetic mean roughness is smaller than the first arithmetic mean roughness, the side surface and surface of the first wiring conductor 31 are relatively flat, which is advantageous in terms of improving transmission characteristics particularly when transmitting high-frequency signals. be.
  • the second arithmetic mean roughness may be 1.5 times or more the first arithmetic mean roughness.
  • the first arithmetic mean roughness may be, for example, 50 nm or more and 200 nm or less
  • the second arithmetic mean roughness may be, for example, 100 nm or more and 300 nm or less.
  • At least one first region 2 a and at least one second region 2 b need only exist for one first wiring conductor 31 .
  • the first regions 2 a and the second regions 2 b may be alternately positioned along the first wiring conductor 31 in consideration of reducing the deterioration of electrical characteristics and improving the adhesion of the first wiring conductor 31 .
  • the second region 2b may have a concave portion 2c recessed toward the second surface 222 side.
  • FIG. 3 is an enlarged explanatory view for explaining another embodiment of the cross section of the region X shown in FIG.
  • the arithmetic mean roughness of the concave portions 2c may be 100 nm or more and 300 nm or less, like the second arithmetic mean roughness of the second regions 2b.
  • the size of the concave portion 2c is not limited.
  • the depth (D in FIG. 3) is 5 ⁇ m or less at the deepest portion, and the opening width (W in FIG. 3) is 10 ⁇ m or more and 200 ⁇ m or less at the maximum portion. If the depth D and the opening width W of the recess 2c are within such ranges, the surface of the first wiring conductor 31 (the surface opposite to the recess 2c) can be kept flat. As a result, the adhesion of the first wiring conductors 31 can be further improved without affecting the electrical characteristics.
  • the wiring board 1 may include a second wiring conductor 32, as shown in FIG. FIG. 4 is an enlarged explanatory view for explaining a cross section of the region Y shown in FIG.
  • the second wiring conductor 32 is located on the second surface 222 of the insulating layer 22 for buildup, and is located so as to overlap the first region 2a of the insulating layer 22 for buildup when seen from above.
  • the second wiring conductor 32 is located between the buildup insulating layer 22 and the core insulating layer 21 with a part thereof embedded in the buildup insulating layer 22, and the cross section
  • the second wiring conductor 32 is located below the first region 2a. The thickness of the build-up insulating layer 22 located on the upper surface of the second wiring conductor 32 is reduced.
  • the thickness of the second wiring conductor 32 is, for example, 20 ⁇ m or more and 30 ⁇ m or less.
  • the distance between adjacent second wiring conductors 32 is, for example, 30 ⁇ m or more and 50 ⁇ m or less.
  • the first region 2a and the second region 2b of the insulating layer 2 are formed, for example, as follows. First, in order to laminate the insulating layer 2 (buildup insulating layer 22) having the first region 2a and the second region 2b, a base insulating layer 2 (for example, the core insulating layer 21) is prepared. A second wiring conductor 32 is formed on the surface of the core insulating layer 21 on which the build-up insulating layer 22 is to be formed.
  • a resin sheet 23 that will become the buildup insulating layer 22 is laminated on the surface of the core insulating layer 21 so as to cover the second wiring conductors 32 .
  • a resin sheet to which a protective film 23a having unevenness exists on the contact surface with the resin sheet 23 is adhered in a state where the protective film 23a is adhered to the surface opposite to the core insulating layer 21. 23 is used.
  • Lamination of the resin sheets 23 is performed at a relatively high temperature (120° C. or higher).
  • the resin sheet 23 is pressed from above the protective film 23a.
  • the portion where the second wiring conductor 32 exists is pressed more strongly than the other portion because the second wiring conductor 32 serves as a base.
  • the protective film 23a attached to the resin sheet 23 is peeled off to form the first region 2a and the second region 2b on the surface (first surface 221) of the buildup insulating layer 22.
  • FIG. The portion where the second wiring conductor 32 serves as a base and is strongly pressed has a small degree of roughness and becomes the first region 2a. The roughness of other portions is increased, and as shown in FIG. 5, it becomes a second region 2b.
  • a first wiring conductor 31 is formed on the upper surface of the build-up insulating layer 22 by a semi-additive method, spanning from the first region 2a to the second region 2b. Then, the metal oxide film such as the copper oxide film is removed by acid cleaning. After that, tin is deposited so as to have a thickness of about 100 nm. The excess deposited tin is then removed, for example by etching with nitric acid. Etching is performed in this manner to adjust the thickness of tin to approximately 2 nm or more and 5 nm or less.
  • a silane coupling agent is applied so as to cover the formed tin layer.
  • the silane coupling agent commercially available ones such as FC-9100Z (manufactured by MEC Co., Ltd.), KBM-303 (Shin-Etsu Chemical Co., Ltd., DOWSIL TM Z-6040 Silane (Dow Toray Industries, Inc.) can be used.
  • the surface is treated at a temperature of 70° C. or higher and 100° C. or lower for 1 minute or longer and 10 minutes or shorter to form a silane coupling agent layer on the surface of the tin layer.
  • a first wiring conductor 31 as shown in FIG. 1 is formed.
  • the resin sheet 23 forming the build-up insulating layer 22 is laminated on the surface of the core insulating layer 21 at a relatively low temperature (100° C. or lower), as shown in FIG. A recess is formed on the surface of the resin sheet 23 in the region between the conductors 32 .
  • a release film is interposed on the release surface of the resin sheet, and pressure is applied from above the release film.
  • the resin sheet 23 has a protective film 23a adhered to the surface opposite to the core insulating layer 21, and the resin sheet 23 adhered with the protective film 23a having irregularities on the contact surface with the resin sheet 23. to use.
  • the depressions on the surface of the resin sheet 23 are less likely to be pressurized, and the roughness tends to increase.
  • the portion where the second wiring conductor 32 exists is strongly pressed as described above, and the roughness is reduced.
  • a second region 2b having a first region 2a and recesses 2c is formed on the surface (first surface 221) of the insulating layer 22 for buildup. The existence of the second wiring conductors 32 facilitates the formation of the recesses 2c between the adjacent second wiring conductors 32 .
  • a mounting structure includes a wiring board 1 according to one embodiment and an element S positioned on the surface of the wiring board 1 .
  • the conductor layer 3 in the opening of the solder resist 4 and the electrode of the element S are connected via solder 5 .
  • the element S may be a semiconductor integrated circuit element, an optoelectronic element, or the like.
  • the elements S may be located on both sides of the wiring board 1, or the elements S may be located on one surface and a motherboard or the like may be located on the other surface.
  • the wiring board according to the present disclosure is not limited to the wiring board 1 according to the embodiment described above.
  • the buildup insulating layer 22 positioned directly above the core insulating layer 21 has the first region 2a and the second region 2b.
  • the insulating layers of the first region 2 a and the second region 2 b are not limited to the build-up insulating layer 22 located directly above the core insulating layer 21 .
  • the first region 2a and the second region 2b are formed on the first surface of the buildup insulating layer 22 other than the buildup insulating layer positioned directly above the core insulating layer. may exist, and the first surface of the core insulating layer 21 may have the first region 2a and the second region 2b.
  • the first region 2a and the second region 2b exist on the first surfaces of all the insulating layers, and the first regions 2a and 2b do not need to exist on the first surfaces of at least one insulating layer. It is sufficient if the region 2a and the second region 2b are present.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)
PCT/JP2023/006187 2022-02-28 2023-02-21 配線基板 Ceased WO2023162965A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US18/841,569 US20250168970A1 (en) 2022-02-28 2023-02-21 Wiring board
CN202380023743.8A CN118765538A (zh) 2022-02-28 2023-02-21 布线基板
JP2024503165A JP7778219B2 (ja) 2022-02-28 2023-02-21 配線基板及び実装構造体
EP23759966.7A EP4489532A1 (en) 2022-02-28 2023-02-21 Wiring board
KR1020247028762A KR20240141302A (ko) 2022-02-28 2023-02-21 배선 기판

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022-029334 2022-02-28
JP2022029334 2022-02-28

Publications (1)

Publication Number Publication Date
WO2023162965A1 true WO2023162965A1 (ja) 2023-08-31

Family

ID=87765907

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/006187 Ceased WO2023162965A1 (ja) 2022-02-28 2023-02-21 配線基板

Country Status (7)

Country Link
US (1) US20250168970A1 (https=)
EP (1) EP4489532A1 (https=)
JP (1) JP7778219B2 (https=)
KR (1) KR20240141302A (https=)
CN (1) CN118765538A (https=)
TW (1) TWI866088B (https=)
WO (1) WO2023162965A1 (https=)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1051113A (ja) * 1996-07-29 1998-02-20 Ibiden Co Ltd 多層プリント配線板の製造方法
JP2007095828A (ja) 2005-09-27 2007-04-12 Dainippon Printing Co Ltd パターン形成体
WO2019021895A1 (ja) * 2017-07-24 2019-01-31 古河電気工業株式会社 表面処理銅箔、並びにこれを用いた銅張積層板およびプリント配線板

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5855905B2 (ja) * 2010-12-16 2016-02-09 日本特殊陶業株式会社 多層配線基板及びその製造方法
JP6380626B1 (ja) * 2017-07-19 2018-08-29 オムロン株式会社 樹脂構造体の製造方法および樹脂構造体
JP6716781B2 (ja) 2017-12-15 2020-07-01 積水化学工業株式会社 積層フィルム及びプリント配線板用組み合わせ部材
JP2019127571A (ja) 2018-01-26 2019-08-01 日立化成株式会社 絶縁層用樹脂組成物、シート状積層材料、多層プリント配線板及び半導体装置
JP2022030289A (ja) 2020-08-06 2022-02-18 イビデン株式会社 配線基板及び配線基板の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1051113A (ja) * 1996-07-29 1998-02-20 Ibiden Co Ltd 多層プリント配線板の製造方法
JP2007095828A (ja) 2005-09-27 2007-04-12 Dainippon Printing Co Ltd パターン形成体
WO2019021895A1 (ja) * 2017-07-24 2019-01-31 古河電気工業株式会社 表面処理銅箔、並びにこれを用いた銅張積層板およびプリント配線板

Also Published As

Publication number Publication date
JPWO2023162965A1 (https=) 2023-08-31
KR20240141302A (ko) 2024-09-26
JP7778219B2 (ja) 2025-12-01
TW202344156A (zh) 2023-11-01
TWI866088B (zh) 2024-12-11
CN118765538A (zh) 2024-10-11
EP4489532A1 (en) 2025-01-08
US20250168970A1 (en) 2025-05-22

Similar Documents

Publication Publication Date Title
JP6885800B2 (ja) 配線基板およびその製造方法
CN103188866B (zh) 印刷线路板及其制造方法
JP2018504776A (ja) プリント回路基板のための高速インターコネクト
KR102117242B1 (ko) 배선 기판
WO2004091268A1 (ja) 多層プリント配線板
KR102078009B1 (ko) 인쇄회로기판 및 그 제조방법
TWI665772B (zh) 配線基板
JP5141084B2 (ja) 電子部品実装配線板、及び電子部品実装配線板における電子部品の剥離防止方法
KR101204083B1 (ko) 전기소자 내장 다층 연성 인쇄회로기판 및 그 제조 방법
US20240422900A1 (en) Wiring board and manufacturing method for the same
WO2023162965A1 (ja) 配線基板
JP7583680B2 (ja) 配線基板およびその製造方法
CN100583424C (zh) 封装基板
JP3049972B2 (ja) 多層配線板
US20230397335A1 (en) Wiring substrate
WO2026028759A1 (ja) 配線基板および実装構造体
KR100797669B1 (ko) 인쇄회로기판 및 그 제조방법
WO2024135456A1 (ja) 配線基板およびその製造方法
WO2025115582A1 (ja) 配線基板およびその製造方法
TW202425721A (zh) 配線基板及配線基板之製造方法
JP2022179156A (ja) 配線基板及び配線基板の製造方法
WO2026004500A1 (ja) 配線基板および実装構造体
JP2025068231A (ja) プリント配線板
JP2023039130A (ja) 配線基板及び配線基板の製造方法
JP2024032317A (ja) 配線基板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23759966

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 18841569

Country of ref document: US

Ref document number: 202380023743.8

Country of ref document: CN

ENP Entry into the national phase

Ref document number: 20247028762

Country of ref document: KR

Kind code of ref document: A

Ref document number: 2024503165

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2023759966

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2023759966

Country of ref document: EP

Effective date: 20240930

WWP Wipo information: published in national office

Ref document number: 18841569

Country of ref document: US

WWW Wipo information: withdrawn in national office

Ref document number: 1020247028762

Country of ref document: KR

WWW Wipo information: withdrawn in national office

Ref document number: 2023759966

Country of ref document: EP