WO2023123762A1 - 一种半导体结构及其形成方法 - Google Patents

一种半导体结构及其形成方法 Download PDF

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WO2023123762A1
WO2023123762A1 PCT/CN2022/088464 CN2022088464W WO2023123762A1 WO 2023123762 A1 WO2023123762 A1 WO 2023123762A1 CN 2022088464 W CN2022088464 W CN 2022088464W WO 2023123762 A1 WO2023123762 A1 WO 2023123762A1
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substrate
doped region
patterned
forming
gate oxide
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French (fr)
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李宗翰
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/8314—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having gate insulating layers with different properties
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure and method of forming the same.
  • embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.
  • an embodiment of the present disclosure provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first doped region and a second doped region, wherein the first doped region and the There is an isolation structure between the second doped regions; nitriding the first doped region and the second doped region; nitriding the first doped region and the second doped region after nitriding
  • the doped region is oxidized to form a first gate oxide layer and a second gate oxide layer respectively.
  • the providing the base includes: providing a substrate; forming an isolation structure on the substrate; doping the substrate on which the isolation structure is formed, and forming the first doped region and the second doped region.
  • the substrate corresponding to the first doped region is a first substrate
  • the substrate corresponding to the second doped region is a second substrate and formed on the second SiGe substrate on the substrate.
  • forming the silicon germanium substrate on the second substrate in the second doped region can increase the speed of the device formed on the second doped region and reduce the work function of the device, thereby changing the threshold voltage.
  • the step of forming a silicon germanium substrate on the second substrate includes: forming a patterned first mask layer on the first substrate and the second substrate, the The patterned first mask layer exposes the surface of the second substrate; the silicon germanium substrate is formed by epitaxial growth or deposition on the surface of the second substrate; all the silicon germanium substrates on the first substrate are removed The SiGe substrate and the patterned first mask layer.
  • the nitrogen ions doped on the germanium-silicon substrate during the nitriding process can prevent the formation of germanium-oxygen bonds (Ge-O), thereby reducing the thickness difference between the first gate oxide layer and the second gate oxide layer, and reducing the impact on The influence of electrical parameters of semiconductor devices such as threshold voltage and capacitance.
  • germanium-O germanium-oxygen bonds
  • the doping the substrate on which the isolation structure is formed, and forming a first doped region and a second doped region on both sides of the isolation structure includes: forming the isolation structure A patterned second mask layer is formed on the first substrate and the silicon germanium substrate, and the patterned second mask layer exposes the surface of the first substrate; with the patterned The second mask layer is a mask, performing first ion implantation on the first substrate to form the first doped region; removing the patterned second mask layer; forming the isolation structure and A patterned third mask layer is formed on the first substrate and the silicon germanium substrate of the first doped region, and the patterned third mask layer exposes the silicon germanium substrate.
  • the first doped region includes an N-type doped first substrate
  • the second doped region includes a P-type doped second substrate and a P-type doped germanium-silicon substrate. end.
  • the nitriding treatment of the first doped region and the second doped region includes: using plasma to treat the first doped region and the second doped region Nitriding treatment is carried out.
  • the reaction gas of the nitriding treatment includes nitrogen
  • the auxiliary gas includes helium
  • the flow rate ratio of the nitrogen to the helium is 1:5 to 1:2.
  • the second doped region and the first doped region can have sufficient volume concentration of nitrogen ions to reduce the growth rate of the second gate oxide layer, and at the same time reduce the electrical impact of excessive nitrogen ion volume concentration on subsequent devices. performance is adversely affected.
  • the reaction temperature of the nitriding treatment is 90°C to 100°C, and the reaction time is 90s to 110s.
  • the oxidation treatment is ozonation.
  • the oxidation rate can be better controlled, which is conducive to obtaining a consistent gate oxide thickness, and provides a better prerequisite for device performance adjustment.
  • the ozone oxidation adopts a wet oxidation process, and the oxidant of the wet oxidation process is ozone.
  • the ozone flow rate of the wet oxidation process is 8 to 12 L/min.
  • the temperature of the wet oxidation process is 20 to 30°C.
  • the thickness of the first gate oxide layer is 10.5 to The thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer, and the thickness difference is less than
  • an embodiment of the present disclosure provides a semiconductor structure formed by the above-mentioned method.
  • the nitrogen ions formed by the nitriding treatment will reduce the oxidation rate of the second doped region, thereby inhibiting the formation of the second gate oxide layer, thus reducing the thickness difference between the first gate oxide layer and the second gate oxide layer , reduce the impact on the electrical parameters of the semiconductor device such as threshold voltage and capacitance, and provide a good basis for adjusting the semiconductor device; on the other hand, the process flow of the method is simple and controllable.
  • FIG. 1a is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 1b is a schematic structural diagram of the process of forming a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2a is a schematic flow chart of a substrate forming method provided by an embodiment of the present disclosure
  • 2b to 2j are structural schematic diagrams of the process of forming a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 3a is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • 3b to 3e are structural schematic diagrams of the process of forming the semiconductor structure provided by the embodiments of the present disclosure.
  • An embodiment of the present disclosure provides a method for forming a semiconductor structure, as shown in FIG. 1a, including steps S101 to S103:
  • step S101 a substrate is provided, and the substrate includes a first doped region and a second doped region, wherein an isolation structure is provided between the first doped region and the second doped region.
  • the substrate 100 includes a first doped region 101 and a second doped region 102 with an isolation structure 104 between the first doped region 101 and the second doped region 102 .
  • a first doped region and a second doped region are respectively formed on both sides of the isolation structure to form
  • the substrate may include steps S201 to S210, as shown in FIG. 2a, and the steps of forming the substrate will be described below in conjunction with FIG. 2b to FIG. 2h.
  • a substrate 103 is provided, as shown in FIG. 2b; an isolation structure 104 is formed in the substrate 103, and the isolation structure 104 divides the substrate 103 into a first substrate 105 and a second substrate 106 arranged at intervals, that is, the first There is an isolation structure 104 between the substrate 105 and the second substrate 106, as shown in FIG. 2c.
  • the substrate may be a silicon substrate, a silicon-on-insulator substrate, etc.; the substrate may also include other semiconductor elements or include semiconductor compounds, such as: silicon carbide (SiC), gallium arsenide (GaAs), Gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or including other semiconductor alloys such as: gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs ), gallium aluminum arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide (GaInAsP) or combinations thereof.
  • SiC silicon carbide
  • GaAs gallium arsenide
  • GaP Gallium phosphide
  • InP indium
  • the isolation structure may include shallow trench isolation (Shallow Trench Isolation, STI) or local oxidation (Local Oxidation of Silicon, LOCOS) isolation, which is not limited herein.
  • the material of the isolation structure may include one or more of silicon oxides, such as silicon oxide or silicon oxynitride.
  • the isolation structure can be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD) or atomic layer deposition (Atomic Layer Deposition, ALD) process, etc.
  • Step S202 forming a patterned first mask layer on the first substrate and the second substrate, the patterned first mask layer exposing the surface of the second substrate.
  • a patterned first mask layer 107 is formed on the first substrate 105 and the second substrate 106 , wherein the patterned first mask layer 107 exposes the second substrate 106 .
  • the material of the patterned first mask layer 107 may include silicon oxide, oxynitride or carbide such as silicon oxide, silicon nitride, silicon carbide or silicon oxynitride. deposition, physical vapor deposition, atomic layer deposition and other processes to form a patterned first mask layer 107, and the patterned first mask layer can be formed by photolithography, dry or wet etching 107.
  • Step S203 forming a silicon germanium substrate on the surface of the second substrate by epitaxial growth or deposition.
  • a silicon-germanium substrate 108 is formed on the surface of the second substrate 106 by epitaxial growth or deposition.
  • the silicon-germanium substrate 108 may also be formed on the patterned first mask layer 107.
  • the process may be chemical vapor deposition; forming the silicon germanium substrate 108 on the second substrate 106 can effectively improve the mobility of holes, thereby increasing the turn-on speed of the device.
  • Step S204 removing the silicon germanium substrate on the patterned first mask layer.
  • the SiGe substrate 108 and the patterned first mask layer 107 on the first substrate 105 are removed to expose the surface of the first substrate 105 .
  • it can be removed by dry etching or wet etching, and the gas used in dry etching can be trifluoromethane (CHF 3 ), carbon tetrafluoride (CF 4 ), difluoromethane (CH 2 F 2 ), hydrobromic acid (HBr), chlorine (Cl 2 ) or sulfur hexafluoride (SF 6 ) or a combination thereof; wet etching can use hot phosphoric acid or hydrofluoric acid as etching solution.
  • Step S205 forming a patterned second mask layer on the first substrate forming the isolation structure and the silicon germanium substrate, the patterned second mask layer exposing the surface of the first substrate.
  • a patterned second mask layer 109 is formed on the first substrate 105 forming the isolation structure 104 and the silicon germanium substrate 108, and the patterned second mask layer 109 exposes the surface of the first substrate 105. surface.
  • the material of the second mask layer may include silicon nitride, silicon carbide or silicon oxynitride, and at the same time, it may be deposited by any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition and other processes.
  • a second mask layer, and a patterned second mask layer 109 can be formed by photolithography, dry or wet etching.
  • Step S206 using the patterned second mask layer as a mask to perform first ion implantation on the first substrate to form a first doped region.
  • the first ion implantation is performed on the first substrate 105 to form the first doped region 101, wherein the arrow A represents the first doped region 101.
  • the substrate 105 is subjected to first ion implantation.
  • the first doped region 101 may be an N-type doped first substrate, and the corresponding implanted first ions may be VA group ions such as phosphorus, arsenic, and antimony.
  • the ion implantation can also be realized through processes such as thermal diffusion and plasma doping; after the ion implantation, a high-temperature annealing process can also be included to repair the crystal lattice damage caused by the ion implantation.
  • Step S207 removing the patterned second mask layer.
  • the patterned second mask layer 109 is removed to expose the surface of the SiGe substrate 108 .
  • the patterned second mask layer 109 can be removed by a dry or wet etching process, and the etching solution or gas used can refer to the aforementioned patterned first mask layer 105, where No longer.
  • step S208 a patterned third mask layer is formed on the first substrate and the silicon-germanium substrate where the isolation structure and the first doped region are formed, and the third mask layer exposes the surface of the silicon-germanium substrate to be formed.
  • a patterned third mask layer 110 is formed on the first substrate 105 and the silicon-germanium substrate 108 forming the isolation structure 104 and the first doped region 101.
  • the patterned third mask layer 110 The surface of the SiGe substrate 108 is exposed.
  • the material of the third mask layer may include silicon oxide or oxynitride or carbide such as silicon oxide, silicon nitride, silicon carbide or silicon oxynitride.
  • the third mask layer is formed by any one of processes such as deposition and atomic layer deposition, and the patterned third mask layer 110 can be formed by photolithography, dry or wet etching.
  • Step S209 using the patterned third mask layer as a mask to perform second ion implantation on the SiGe substrate and the portion in contact with the lower surface of the SiGe substrate to form a second doped region.
  • the arrow B indicates that the second ion implantation is performed on the second substrate 106 and the silicon germanium substrate 108 .
  • a second ion implantation is performed on the SiGe substrate 108 and the second substrate 106 in contact with the lower surface of the SiGe substrate 108 to form the second doped region 102 . That is to say, the substrate corresponding to the first doped region is the first substrate, and the substrate corresponding to the second doped region is the second substrate and the silicon germanium substrate formed on the second substrate.
  • the second doped region can be a P-type doped second substrate and a P-type doped silicon germanium substrate, and the corresponding implanted second ions can be boron, indium and other group IIIA ions;
  • the second ion implantation process can refer to the first ion implantation process, which will not be repeated here.
  • Different doped regions in the embodiments of the present disclosure can use the same or different ion implantation processes.
  • the substrate includes When there are two different doped regions, the first doped region may adopt a thermal diffusion process, and the second doped region may adopt an ion implantation process, which is not limited herein.
  • Step S210 removing the patterned third mask layer.
  • the patterned third mask layer 110 is removed.
  • the patterned third mask layer 110 can be removed by dry or wet etching techniques, etc.
  • the etching solution or gas used can refer to the aforementioned patterned first mask layer, which is not described here. Let me repeat.
  • N-type ion implantation can also be performed on a P-type doped substrate, that is, to form a P well, to form the first doped region 101 to form a PN junction; , that is, perform P-type ion implantation in the formed N well to form the second doped region 102 to form a PN junction.
  • Step S102 performing nitriding treatment on the first doped region and the second doped region.
  • arrow C indicates that nitriding treatment is performed on the first doped region 101 and the second doped region 102, so that nitrogen ions enter the first doped region 101 and the second doped region 102 to form a nitriding treatment.
  • the first doped region 101 and the second doped region 102 can be nitrided by plasma nitriding process, rapid thermal nitriding or vertical furnace nitriding.
  • the first doped region and the second doped region can be nitrided by a decoupled plasma nitriding process
  • the reaction gas for nitriding treatment includes nitrogen
  • the auxiliary gas includes helium
  • nitrogen and helium The ratio of the flow rate is 1:5 to 1:2, wherein the flow rate of helium can be 300 to 500 standard milliliters per minute (sccm), and the flow rate of nitrogen can be 100 to 300 sccm; in the process of nitriding treatment, ensure that nitrogen
  • the concentration is greater than 5 ⁇ 10 15 /cubic centimeter (cm 3 ), and the pressure is 5 mTorr to 50 mTorr.
  • the power of the plasma device can be from 300 watts (W) to 1500W. In this way, ultra-low energy doping can be efficiently realized, which is more helpful to reduce the oxidation rate of the second doped region, and at the same time, the problem of interface defects can be reduced.
  • the reaction gas for nitriding treatment includes nitrogen
  • the auxiliary gas includes helium
  • the flow rate ratio of nitrogen and helium is 1:5 to 1:2.
  • the reaction temperature of the nitriding treatment is 90 degrees Celsius (° C.) to 100° C.
  • the reaction time is 90 seconds (s) to 110 s.
  • the gas flow rate of nitrogen as the reaction gas should be moderate. If the gas flow rate of nitrogen gas is too small, the volume concentration of nitrogen ions entering the second doped region is too low, so that the inhibition effect on the formation of the second gate oxide layer is not obvious enough, and it is difficult to reduce the growth rate of the second gate oxide layer; if If the gas flow rate of the nitrogen gas is too high, the volume concentration of nitrogen ions entering the surface of the second doping region is too high, which will easily cause adverse effects on the electrical properties of the subsequently formed devices. Therefore, in this embodiment, the gas flow rate of the nitrogen gas may be 30 milliliters per minute (ml/min) to 150 ml/min.
  • the second doped region and the first doped region can have sufficient volume concentration of nitrogen ions to reduce the growth rate of the second gate oxide layer, and at the same time reduce the electrical impact of excessive nitrogen ion volume concentration on subsequent devices. adverse effects on performance.
  • nitrogen ions enter the first doped region and the second doped region, and the nitrogen ions have an inhibitory effect on the formation of the second gate oxide layer, reducing the growth rate of the second gate oxide layer, thereby The thickness difference between the first gate oxide layer and the second gate oxide layer is reduced.
  • a high temperature annealing process may be included to stabilize the nitrogen doping and repair the plasma damage in the medium caused by the nitriding treatment.
  • nitriding treatment is performed on the first doped region and the second doped region; oxidation treatment is performed on the first doped region and the second doped region after nitriding treatment to form first gate oxide layer and the second gate oxide layer.
  • the nitrogen ions doped on the germanium-silicon substrate during the nitriding process can prevent the formation of Ge-O bonds, thereby reducing the thickness difference between the first gate oxide layer and the second gate oxide layer, and reducing the electrical impact on the semiconductor device. Influence of parameters such as threshold voltage and capacitance.
  • Step S103 performing oxidation treatment on the first doped region and the second doped region after the nitriding treatment to form a first gate oxide layer and a second gate oxide layer respectively.
  • the first doped region 101 a and the second doped region 102 a after the nitriding treatment are oxidized to form a first gate oxide layer 111 and a second gate oxide layer 112 .
  • the first gate oxide layer and the second gate oxide layer may be silicon oxide.
  • the oxidation treatment may be suitable oxidation processes such as ozone oxidation treatment, thermal oxidation treatment, in-situ water vapor generation (In-Situ Stream Generation, ISSG) oxidation treatment, wet oxygen oxidation treatment, and high-pressure oxidation treatment. limited.
  • the nitridated first doped region and the second doped region may be oxidized by ozone oxidation treatment to form the first gate oxide layer and the second gate oxide layer respectively.
  • the oxidation rate can be better controlled, which is conducive to obtaining a consistent gate oxide thickness, and provides a better prerequisite for device performance adjustment.
  • the ozone oxidation can adopt a wet oxidation process, the oxidant of the wet oxidation process is ozone; the ozone flow rate is 8 to 12 L/min; the temperature of the wet oxidation process is 20 to 30°C.
  • the first doped Taking the first substrate corresponding to the first doped region as a silicon substrate, the substrate corresponding to the second doped region as a silicon substrate, and the silicon germanium substrate formed on the silicon substrate as an example, the first doped
  • the reaction of formula (1) occurs when the region is subjected to nitriding treatment and ozone is used as the oxidant of the wet oxidation process to form the first gate oxide layer, and the second doped region is subjected to nitriding treatment and ozone is used as the oxidant of the wet oxidation process
  • the reaction of formula (2) occurs when the oxidant is used to form the second gate oxide layer.
  • the first arrow represents that silicon substrate is carried out the process of nitriding treatment, can generate SiNx ;
  • the second arrow represents that ozone oxidation treatment is carried out to the silicon substrate that generates SiNx , in An appropriate amount of deionized water (Deionized Water, DIW) is added during the ozone oxidation treatment, and SiN x reacts with ozone and DIW to form SiON x .
  • DIW deionized Water
  • the first arrow represents the process of nitriding the germanium-silicon substrate in the second doped region, which will generate SiGeN x ; the second arrow represents the process of generating SiGeN x
  • the silicon germanium substrate is subjected to ozone oxidation treatment, and an appropriate amount of deionized water is also added.
  • ozone oxidation treatment N ions will inhibit the formation of Ge-O bonds, and SiGeN x will react with ozone and DIW to form SiON x , thereby reducing the rate of forming the second gate oxide layer.
  • the first doped region and the second doped region are the same, for example, they can all be SiON x , thereby reducing the thickness difference between the first gate oxide layer and the second gate oxide layer, and increasing the gate oxide thickness of the first doped region and the second doped region. consistency.
  • passing the ozone into the deionized water can make the ozone concentration reach a saturated state, so as to ensure the stability of the concentration, which is beneficial to further improve the uniformity of the thickness of the formed gate oxide layer.
  • the thickness of the first gate oxide layer is 10.5 to The thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer, and the thickness difference is less than See Figure 2j, that is, d1 is 10.5 to The difference between d2 and d1 is less than
  • the nitridated first doped region and the second doped region may also be oxidized by an ISSG process to form a first gate oxide layer and a second gate oxide layer respectively.
  • the first gate oxide layer and the second gate oxide layer with good coverage, good uniformity, and high density can be formed, which helps to improve the performance of the device and improve the problem of device mismatch.
  • the reaction gases of the ISSG process can be oxygen and hydrogen
  • the reaction temperature can be 850°C to 950°C
  • the first doped region and the second doped region after the nitriding treatment are subjected to ISSG treatment for 15s to 20s to form the first gate oxide layer and the second gate oxide layer.
  • the reaction gas in the ISSG process further includes a mixed gas of N 2 O and H 2 or a mixed gas of N 2 O, O 2 and H 2 .
  • steps S104 to S106 may be further included after step S103 , referring to FIG. 3 a , step S104 to step S106 will be explained below in conjunction with FIGS. 3 b to 3 e. in:
  • Step S104 forming a first gate structure and a second gate structure on the first gate oxide layer and the second gate oxide layer respectively.
  • a first gate structure 113 and a second gate structure 114 are formed on the first gate oxide layer 111 and the second gate oxide layer 112, respectively.
  • the first gate structure includes a first gate oxide layer, a first high-k dielectric layer, a first work function layer, a first capping layer, and a polysilicon layer;
  • the second gate structure includes a second gate oxide layer , a second high-k dielectric layer, a second work function layer, a second covering layer and a polysilicon layer.
  • the step of forming the first gate and the second gate structure may include the following steps:
  • Step S1041 sequentially depositing and forming a first high-k dielectric layer, a first work function layer and a first capping layer on the first gate oxide layer to form a first stacked structure.
  • a first high-k dielectric layer 115 , a first work function layer 116 and a first capping layer 117 are sequentially deposited on the first gate oxide layer 111 to form a first stacked structure 118 .
  • the first high-k dielectric layer may be formed by CVD, PVD, or ALD processes.
  • the first high-k dielectric layer may include a hafnium silicon oxide (HfSiO) layer, a hafnium silicon oxynitride (HfSiON) layer, a hafnium tantalum oxide (HfTaO) layer, a hafnium titanium oxide (HfTiO) layer, a hafnium zirconium oxide (HfZrO) layer, At least one of a zirconium (ZrO 2 ) layer or an aluminum oxide (Al 2 O 3 ) layer.
  • the first work function layer may include a dilanthanum trioxide (La 2 O 3 ) layer, which may be used to adjust a threshold voltage.
  • the first covering layer can be a metal layer such as a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, etc., which can improve polysilicon depletion.
  • Step S1042 depositing and forming a second high-k dielectric layer, a second work function layer, and a second covering layer in sequence on the second gate oxide layer to form a second stacked structure.
  • a second high-k dielectric layer 119 , a second work function layer 120 , and a second capping layer 121 are sequentially deposited on the second gate oxide layer 112 to form a second stacked structure 122 .
  • the second high-k dielectric layer may be the same as or different from the first high-k dielectric layer.
  • the second work function layer may include an aluminum oxide (Al 2 O 3 ) layer, which may be used to adjust a threshold voltage.
  • the second covering layer can be the same as the first covering layer, or it can be different.
  • Step S1043 forming a polysilicon layer on the first stacked structure and the second stacked structure to form a first gate structure and a second gate structure.
  • a polysilicon layer 123 is formed on the first stacked structure 118 and the second stacked structure 122 to form the first gate structure 113 and the second gate structure 114 .
  • Step S105 forming a P-type extension region and an N-type extension region in the first doped region and the second doped region after the nitriding treatment, respectively.
  • a P-type extension region 124 and an N-type extension region 125 are respectively formed in the first doped region 101a and the second doped region 102a after the nitriding treatment.
  • the N-type extension region includes halo ion implantation and lightly doped drain (Lightly Doped Drain, LDD), and the P-type extension region also includes halo ion implantation and LDD, the difference is that the doped ions are different.
  • the ion implantation direction may not be perpendicular to the first doped region and the second doped region, and there is a certain angle to form a pocket-like doped region. In this way, the lateral expansion of the depletion region of the source and drain can be reduced, and the source-drain punchthrough phenomenon can be prevented.
  • the extension region forms an impurity concentration gradient between the source and drain and the channel, reduces the peak electric field near the drain, and improves the heat carrying current. Sub effect.
  • Step S106 forming spacer structures on both sides of the first gate structure and the second gate structure respectively.
  • spacer structures 126 are respectively formed on both sides of the first gate structure 113 and the second gate structure 114 .
  • the material used for the sidewall structure 126 may be nitride, such as silicon nitride or silicon oxynitride.
  • Embodiments of the present disclosure provide a semiconductor structure, which is formed by using the methods in the above embodiments.
  • a method for forming a semiconductor structure includes: providing a substrate, the substrate including a first doped region and a second doped region, wherein the first doped region and the second doped region There is an isolation structure between them; Nitriding treatment is performed on the first doped region and the second doped region; Oxidation treatment is performed on the first doped region and the second doped region after nitriding treatment , respectively forming a first gate oxide layer and a second gate oxide layer.
  • the nitrogen ions formed by the nitriding treatment will reduce the oxidation rate of the second doped region, thereby inhibiting the formation of the second gate oxide layer, thus reducing the thickness difference between the first gate oxide layer and the second gate oxide layer , reduce the impact on the electrical parameters of the semiconductor device such as threshold voltage and capacitance, and provide a good basis for adjusting the semiconductor device; on the other hand, the process flow of the method is simple and controllable.

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Abstract

本公开实施例提供一种半导体结构及其形成方法。其中，所述方法包括：提供基底，所述基底包括第一掺杂区和第二掺杂区，其中，所述第一掺杂区和所述第二掺杂区之间具有隔离结构；对所述第一掺杂区和所述第二掺杂区进行氮化处理；对氮化处理后的所述第一掺杂区和所述第二掺杂区进行氧化处理，分别形成第一栅氧化层和第二栅氧化层。

Description

一种半导体结构及其形成方法
相关申请的交叉引用
本公开基于申请号为202111625986.8、申请日为2021年12月28日、申请名称为“一种半导体结构及其形成方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以全文引入的方式引入本公开。
技术领域
本公开涉及但不限于一种半导体结构及其形成方法。
背景技术
相关技术中，在相同的栅氧工艺条件下，不同的掺杂区上形成的栅氧化层的厚度往往存在一些差异，栅氧化层的厚度差异会影响半导体器件的电学参数和/或电学性能。
发明内容
有鉴于此，本公开实施例提供一种半导体结构及其形成方法。
第一方面，本公开实施例提供一种半导体结构的形成方法，包括：提供基底，所述基底包括第一掺杂区和第二掺杂区，其中，所述第一掺杂区和所述第二掺杂区之间具有隔离结构；对所述第一掺杂区和所述第二掺杂区进行氮化处理；对氮化处理后的所述第一掺杂区和所述第二掺杂区进行氧化处理，分别形成第一栅氧化层和第二栅氧化层。
在一些实施例中，所述提供基底，包括：提供衬底；在所述衬底上形成隔离结构；对形成隔离结构的所述衬底进行掺杂，在所述隔离结构的两侧分别形成所述第一掺杂区和所述第二掺杂区。
在一些实施例中，所述第一掺杂区对应的所述衬底为第一衬底，所述第二掺杂区对应的所述衬底为第二衬底和形成于所述第二衬底上的锗硅衬底。
如此，在第二掺杂区的第二衬底上形成锗硅衬底，可以提高在第二掺杂区上形成的器件的速度并降低器件的功函数，从而改变阈值电压。
在一些实施例中，在所述第二衬底上形成锗硅衬底的步骤，包括：在所述第一衬底和所述第二衬底上形成图案化的第一掩膜层，所述图案化的第一掩膜层暴露出所述第二衬底的表面；通过外延生长或沉积在所述第二衬底的表面形成锗硅衬底；去除所述第一衬底上的所述锗硅衬底和所述图案化的第一掩膜层。
如此，氮化处理过程中在锗硅衬底掺杂的氮离子可以阻止形成锗氧键(Ge-O)，从 而减小第一栅氧化层与第二栅氧化层的厚度差异，减小对半导体器件的电学参数例如阈值电压和电容的影响。
在一些实施例中，所述对形成隔离结构的所述衬底进行掺杂，在所述隔离结构的两侧形成第一掺杂区和第二掺杂区，包括：在形成隔离结构的所述第一衬底和所述锗硅衬底上形成图案化的第二掩膜层，所述图案化的第二掩膜层暴露出所述第一衬底的表面；以所述图案化的第二掩膜层为掩膜，对所述第一衬底进行第一离子注入，形成所述第一掺杂区；去除所述图案化的第二掩膜层；在形成所述隔离结构和所述第一掺杂区的所述第一衬底和所述锗硅衬底上形成图案化的第三掩膜层，所述图案化的第三掩膜层暴露出形成所述锗硅衬底的表面；以所述图案化的第三掩膜层为掩膜，对所述锗硅衬底和与所述锗硅衬底下表面接触的所述第二衬底进行第二离子注入，形成所述第二掺杂区；去除所述图案化的第三掩膜层。
在一些实施例中，所述第一掺杂区包括N型掺杂的第一衬底，所述第二掺杂区包括P型掺杂的第二衬底和P型掺杂的锗硅衬底。
在一些实施例中，所述对所述第一掺杂区和所述第二掺杂区进行氮化处理，包括：采用等离子体对所述第一掺杂区和所述第二掺杂区进行氮化处理。
如此，可以高效地实现超低能量的掺杂，更有助于降低第二掺杂区的氧化速率，同时可以减小界面缺陷这一问题的产生。
在一些实施例中，所述氮化处理的反应气体包括氮气，辅助气体包括氦气，所述氮气和所述氦气的流量之比为1:5至1:2。
如此，可以使第二掺杂区和第一掺杂区有足够体积浓度的氮离子，减小第二栅氧化层的生长速度，同时减小氮离子体积浓度过大对后续形成的器件的电学性能造成不良影响。
在一些实施例中，所述氮化处理的反应温度为90℃至100℃，反应时间为90s至110s。
在一些实施例中，所述氧化处理为臭氧氧化。
如此，可以更好地控制氧化速率，有利于得到一致的栅氧厚度，为器件性能调整提供了较好的先决条件。
在一些实施例中，所述臭氧氧化采用湿法氧化工艺，所述湿法氧化工艺的氧化剂为臭氧。
在一些实施例中，所述湿法氧化工艺的臭氧流量为8至12L/min。
在一些实施例中，所述湿法氧化工艺的温度为20至30℃。
在一些实施例中，所述第一栅氧化层厚度为10.5至
Figure PCTCN2022088464-appb-000001
所述第二栅氧化层的厚度大于所述第一栅氧化层的厚度，且厚度差小于
Figure PCTCN2022088464-appb-000002
第二方面，本公开实施例提供一种半导体结构，采用如上述的方法形成。
本公开实施例中，通过对第一掺杂区和第二掺杂区进行氮化处理；对氮化处理后的第一掺杂区和第二掺杂区进行氧化处理，分别形成第一栅氧化层和第二栅氧化层。这样，一方面，氮化处理形成的氮离子会降低第二掺杂区的氧化速率，从而抑制形成第二栅氧化层，如此可以减小第一栅氧化层与第二栅氧化层的厚度差异，减小对半导体器件的电学参数例如阈值电压和电容的影响，并为调整半导体器件提供了良好的基础；另一方面，该方法的工艺流程简单可控。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1a为本公开实施例提供的一种半导体结构的形成方法的流程示意图；
图1b为本公开实施例提供的半导体结构形成过程的结构示意图；
图2a为本公开实施例提供的基底形成方法的流程示意图；
图2b至图2j为本公开实施例提供的半导体结构形成过程的结构示意图；
图3a为本公开实施例提供的一种半导体结构的形成方法的流程示意图；
图3b至图3e为本公开实施例提供的半导体结构形成过程的结构示意图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
本公开实施例提供一种半导体结构的形成方法，如图1a所示，包括步骤S101至步骤S103：
步骤S101，提供基底，基底包括第一掺杂区和第二掺杂区，其中，第一掺杂区和第二掺杂区之间具有隔离结构。
参见图1b，基底100包括第一掺杂区101和第二掺杂区102，第一掺杂区101和第二掺杂区102之间具有隔离结构104。
在一些实施例中，通过在衬底上形成隔离结构，并对已形成隔离结构的衬底进行掺杂，在隔离结构的两侧分别形成第一掺杂区和第二掺杂区，以形成基底，可以包括步骤S201至步骤S210，如图2a所示，下面结合图2b至图2h来说明基底的形成步骤。
步骤S201，提供衬底103，如图2b所示；在衬底103内形成隔离结构104，隔离结构104将衬底103分成间隔设置的第一衬底105和第二衬底106，即第一衬底105和第二衬底106之间具有隔离结构104，如图2c所示。在一些实施例中，衬底可以是硅衬底、绝缘体上硅衬底等等；衬底也可以包括其他半导体元素或包括半导体化合物，例如：碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)或锑 化铟(InSb)，或包括其他半导体合金，例如：磷化砷镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)、和/或磷砷化铟镓(GaInAsP)或其组合。
隔离结构可以包括浅槽隔离结构(Shallow Trench Isolation，STI)或局部氧化(Local Oxidation of Silicon，LOCOS)隔离，在此不作限定。隔离结构的材料可以包括硅氧化物中的一种或者多种，例如氧化硅或氮氧化硅。隔离结构可以通过化学气相沉积(Chemical Vapor Deposition，CVD)、物理气相沉积(Physical Vapor Deposition，PVD)或者原子层沉积(Atomic Layer Deposition，ALD)工艺等形成。
步骤S202，在第一衬底和第二衬底上形成图案化的第一掩膜层，图案化的第一掩膜层暴露出第二衬底的表面。
参见图2d，在第一衬底105和第二衬底106上形成图案化的第一掩膜层107，其中，图案化的第一掩膜层107暴露出第二衬底106。
在一些实施例中，图案化的第一掩膜层107的材料可以包括氧化硅、氮化硅、碳化硅或氮氧化硅等硅氧化物或氮氧化物或碳化物，同时，可以通过化学气相沉积、物理气相沉积、原子层沉积等工艺中的任意一种沉积形成图案化的第一掩膜层107，并可以通过光刻、干法或湿法刻蚀形成图案化的第一掩膜层107。
步骤S203，通过外延生长或沉积在第二衬底的表面形成锗硅衬底。
继续参见图2d，通过外延生长或沉积在第二衬底106的表面形成锗硅衬底108，在实施时，图案化的第一掩膜层107上也可能会形成锗硅衬底108，沉积工艺可以为化学气相沉积；在第二衬底106上形成锗硅衬底108，能有效提高空穴的迁移率，进而提高器件的开启速度。
步骤S204，去除图案化的第一掩膜层上的锗硅衬底。
参见图2e，去除第一衬底105上的锗硅衬底108和图案化的第一掩膜层107，以暴露出第一衬底105的表面。在一些实施例中，可以通过干法刻蚀或者湿法刻蚀等工艺去除，干法刻蚀采用的气体可以为三氟甲烷(CHF 3)、四氟化碳(CF 4)、二氟甲烷(CH 2F 2)、氢溴酸(HBr)、氯气(Cl 2)或六氟化硫(SF 6)中的一种或它们的组合；湿法刻蚀可以以热磷酸或氢氟酸作为刻蚀溶液。
步骤S205，在形成隔离结构的第一衬底和锗硅衬底上形成图案化的第二掩膜层，图案化的第二掩膜层暴露出第一衬底的表面。
参见图2f，在形成隔离结构104的第一衬底105和锗硅衬底108上形成图案化的第 二掩膜层109，图案化的第二掩膜层109暴露出第一衬底105的表面。在一些实施例中，第二掩膜层的材料可以包括氮化硅、碳化硅或氮氧化硅，同时，可以通过化学气相沉积、物理气相沉积、原子层沉积等工艺中的任意一种沉积形成第二掩膜层，并可以通过光刻、干法或湿法刻蚀形成图案化的第二掩膜层109。
步骤S206，以图案化的第二掩膜层为掩膜，对第一衬底进行第一离子注入，形成第一掺杂区。
同时参见图2f和图2g，以图案化的第二掩膜层109为掩膜，对第一衬底105进行第一离子注入，形成第一掺杂区101，其中，箭头A表示对第一衬底105进行第一离子注入。在一些实施例中，第一掺杂区101可以为N型掺杂的第一衬底，对应注入的第一离子可以是磷、砷、锑等VA族的离子。在一些实施例中，离子注入还可以通过热扩散和等离子体掺杂等工艺实现；离子注入后，还可以包括高温退火过程，用于修复离子注入导致的晶格损伤。
步骤S207，去除图案化的第二掩膜层。
继续参见图2g，去除图案化的第二掩膜层109，暴露出锗硅衬底108的表面。在一些实施例中，可以通过干法或者湿法刻蚀工艺等去除图案化的第二掩膜层109，采用的刻蚀溶液或气体可参考前述图案化的第一掩膜层105，此处不再赘述。
步骤S208，在形成隔离结构和第一掺杂区的第一衬底和锗硅衬底上形成图案化的第三掩膜层，第三掩膜层暴露出形成锗硅衬底的表面。
继续参见图2g，在形成隔离结构104和第一掺杂区101的第一衬底105和锗硅衬底108上形成图案化的第三掩膜层110，图案化的第三掩膜层110暴露出形成锗硅衬底108的表面。在一些实施例中，第三掩膜层的材料可以包括氧化硅、氮化硅、碳化硅或氮氧化硅等硅氧化物或氮氧化物或碳化物，同时，可以通过化学气相沉积、物理气相沉积、原子层沉积等工艺中的任意一种沉积形成第三掩膜层，并可以通过光刻、干法或湿法刻蚀形成图案化的第三掩膜层110。
步骤S209，以图案化的第三掩膜层为掩膜，对锗硅衬底和与锗硅衬底下表面接触的进行第二离子注入，形成第二掺杂区。
同时参见图2g和图2h，箭头B表示对第二衬底106和锗硅衬底108进行第二离子注入。以图案化的第三掩膜层110为掩膜，对锗硅衬底108和与锗硅衬底108下表面接触的第二衬底106进行第二离子注入，形成第二掺杂区102。也就是说，第一掺杂区对应的衬底为第一衬底，第二掺杂区的对应衬底为第二衬底和形成于第二衬底上的锗硅衬 底。
在一些实施例中，第二掺杂区可以为P型掺杂的第二衬底和P型掺杂的锗硅衬底，对应注入的第二离子可以是硼、铟等ⅢA族的离子；在一些实施例中，第二离子的注入工艺可以参考第一离子注入工艺，在此不再赘述，本公开实施例中不同的掺杂区可以采用相同或不同的离子注入工艺，例如基底中包括两个不同的掺杂区时，第一掺杂区可以采用热扩散工艺，第二掺杂区可以采用离子注入工艺，在此不作限定。
步骤S210，去除图案化的第三掩膜层。
参见图2h，去除图案化的第三掩膜层110。在一些实施例中，可以通过干法或者湿法刻蚀技术等去除图案化的第三掩膜层110，采用的刻蚀溶液或气体可参考前述图案化的第一掩膜层，此处不再赘述。
在一些实施例中，还可以在P型掺杂的基底，即形成P阱中进行N型离子注入，形成第一掺杂区101，以形成PN结；同时也可以在N型掺杂的基底，即形成的N阱中进行P型离子注入，形成第二掺杂区102，以形成PN结。
步骤S102，对第一掺杂区和第二掺杂区进行氮化处理。
参见图2i，箭头C表示对第一掺杂区101和第二掺杂区102进行氮化处理，使氮离子进入第一掺杂区101和第二掺杂区102，以形成氮化处理后的第一掺杂区101a和氮化处理后的第二掺杂区102a。
本公开实施例中可以采用等离子体氮化工艺、快速热氮化或垂直炉管氮化对第一掺杂区101和第二掺杂区102进行氮化处理。
在一些实施例中，可以采用去耦等离子氮化工艺对第一掺杂区和第二掺杂区进行氮化处理，氮化处理的反应气体包括氮气，辅助气体包括氦气；氮气和氦气的流量之比为1:5至1:2，其中，氦气的流量可以为300至500标准毫升/分钟(sccm)，氮气的流量可以为100至300sccm；在氮化处理的过程中确保氮气的浓度大于5×10 15/立方厘米(cm 3)，压强为5毫托至50毫托。等离子体设备的功率可以为300瓦(W)至1500W。如此，可以高效地实现超低能量的掺杂，更有助于降低第二掺杂区的氧化速率，同时可以减小界面缺陷这一问题的产生。
在一些实施例中，氮化处理的反应气体包括氮气，辅助气体包括氦气，氮气和氦气的流量之比为1:5至1:2，如此，可以使第二掺杂区和第一掺杂区有足够体积浓度的氮离子，减小第二栅氧化层的生长速度，同时减小氮离子体积浓度过大对后续形成的器件的电学性能造成不良影响。
在一些实施例中，氮化处理的反应温度为90摄氏度(℃)至100℃，反应时间为90秒(s)至110s。
作为反应气体的氮气的气体流量要适中。如果氮气的气体流量过少，进入第二掺杂区的氮离子体积浓度过低，从而对形成第二栅氧化层的抑制作用不够明显，进而难以减小第二栅氧化层的生长速度；如果氮气的气体流量过多，进入第二掺杂区表面的氮离子体积浓度过高，容易对后续形成的器件的电学性能造成不良影响。因此，本实施例中，氮气的气体流量可以为30毫升每分钟(ml/min)至150ml/min。
如此，可以使第二掺杂区和第一掺杂区有足够体积浓度的氮离子，减小第二栅氧化层的生长速度，同时减小氮离子体积浓度过大对后续形成的器件的电学性能造成的不良影响。如此一来，通过氮化处理，使氮离子进入到第一掺杂区和第二掺杂区，氮离子对形成第二栅氧化层具有抑制作用，降低第二栅氧化层的生长速率，从而使第一栅氧化层和第二栅氧化层的厚度差异减小。
在一些实施例中，氮化处理结束后还可以包括高温退火过程，用于稳定氮掺杂并修复氮化处理导致的介质中的等离子体损伤。
本公开实施例中，对第一掺杂区和第二掺杂区进行氮化处理；对氮化处理后的第一掺杂区和第二掺杂区进行氧化处理，分别形成第一栅氧化层和第二栅氧化层。如此，氮化处理过程中在锗硅衬底掺杂的氮离子可以阻止形成Ge-O键，从而减小第一栅氧化层与第二栅氧化层的厚度差异，减小对半导体器件的电学参数例如阈值电压和电容的影响。
步骤S103，对氮化处理后的第一掺杂区和第二掺杂区进行氧化处理，分别形成第一栅氧化层和第二栅氧化层。
参见图2j，对氮化处理后的第一掺杂区101a和第二掺杂区102a进行氧化处理，形成第一栅氧化层111和第二栅氧化层112。
本公开实施例中，第一栅氧化层和第二栅氧化层可以为氧化硅。氧化处理可以是臭氧氧化处理、热氧化处理、原位水汽生成(In-Situ Stream Generation，ISSG)氧化处理、湿氧氧化处理和高压氧化处理等合适的氧化工艺，本公开实施例对此并不限定。
在一些实施例中，可以通过臭氧氧化处理对氮化处理后的第一掺杂区和第二掺杂区进行氧化处理，分别形成第一栅氧化层和第二栅氧化层。如此，可以更好地控制氧化速率，有利于得到一致的栅氧厚度，为器件性能调整提供了较好的先决条件。在一些实施例中，臭氧氧化可以采用湿法氧化工艺，湿法氧化工艺的氧化剂为臭氧；臭氧流量为8至12L/min；湿法氧化工艺的温度为20至30℃。
以第一掺杂区对应的第一衬底为硅衬底、第二掺杂区对应的衬底为硅衬底和形成于硅衬底上的锗硅衬底为例，对第一掺杂区进行氮化处理和利用臭氧作为湿法氧化工艺的氧化剂来形成第一栅氧化层时发生式(1)的反应，对第二掺杂区进行氮化处理和利用臭氧作为湿法氧化工艺的氧化剂来形成第二栅氧化层时发生式(2)的反应。
Si→SiN x+O 3+DIW→SiON x       (1)
SiGe→SiGeN x+O 3+DIW→SiON x       (2)
公式(1)中包括两个箭头，第一个箭头表示对硅衬底进行氮化处理的过程，会生成SiN x；第二个箭头表示对生成SiN x的硅衬底进行臭氧氧化处理，在臭氧氧化处理过程中会加入适量去离子水(Deionized Water，DIW)，SiN x和臭氧以及DIW会反应生成SiON x。公式(2)中也包括两个箭头，第一个箭头表示对第二掺杂区中的锗硅衬底进行氮化处理的过程，会生成SiGeN x；第二个箭头表示对生成SiGeN x的锗硅衬底进行臭氧氧化处理，同样会加入适量去离子水。臭氧氧化处理过程中，N离子会抑制Ge-O键的形成，SiGeN x会和臭氧以及DIW反应生成SiON x，从而降低生成第二栅氧化层的速率。也就是说，在对第一掺杂区和第二掺杂区进行氮化处理和利用臭氧作为湿法氧化工艺的氧化剂来形成栅氧化层时，在第一掺杂区和第二掺杂区上形成的栅氧化层相同，例如可以都为SiON x，从而减小第一栅氧化层与第二栅氧化层的厚度差异，提高第一掺杂区和第二掺杂区的栅氧厚度的一致性。此外，通过将臭氧通入去离子水中能够使臭氧浓度达到饱和状态，从而确保浓度的稳定性，有利于进一步提高所形成的栅氧化层厚度的均匀性。
在一些实施例中，第一栅氧化层厚度为10.5至
Figure PCTCN2022088464-appb-000003
第二栅氧化层的厚度大于第一栅氧化层的厚度，且厚度差小于
Figure PCTCN2022088464-appb-000004
参见图2j，也就是说d1为10.5至
Figure PCTCN2022088464-appb-000005
d2与d1的差小于
Figure PCTCN2022088464-appb-000006
在一些实施例中，也可以通过ISSG工艺对氮化处理后的第一掺杂区和第二掺杂区进行氧化处理，分别形成第一栅氧化层和第二栅氧化层。如此，可以形成具有良好的覆盖能力、均匀性好、致密性好的优点的第一栅氧化层和第二栅氧化层，有助于提高器件的性能并改善器件失配的问题。在一写实施例中，ISSG工艺的反应气体可以为氧气和氢气，反应温度可以为850℃至950℃，对氮化处理后的第一掺杂区和第二掺杂区进行ISSG处理处理15s至20s，以形成第一栅氧化层和第二栅氧化层。
在一些实施例中，ISSG工艺中的反应气体还包括N 2O与H 2的混合气体或者N 2O、 O 2与H 2的混合气体的其中之一。
在一些实施例中，步骤S103之后还可以包括步骤S104至步骤S106，参见图3a，下面结合图3b至3e对步骤S104至步骤S106进行解释。其中：
步骤S104，在第一栅氧化层和第二栅氧化层上分别形成第一栅极结构和第二栅极结构。
参见图3b，在第一栅氧化层111和第二栅氧化层112上分别形成第一栅极结构113和第二栅极结构114。
在一些实施例中，第一栅极结构包括第一栅氧化层、第一高k介质层、第一功函数层、第一覆盖层和多晶硅层；第二栅极结构包括第二栅氧化层、第二高k介质层、第二功函数层、第二覆盖层和多晶硅层。对应地，形成第一栅极和第二栅极结构的步骤可以包括以下步骤：
步骤S1041，在第一栅氧化层上依次沉积形成第一高k介质层、第一功函数层和第一覆盖层，以形成第一叠层结构。
参见图3c，在第一栅氧化层111上依次沉积形成第一高k介质层115、第一功函数层116和第一覆盖层117，以形成第一叠层结构118。
在本公开实施例中，第一高k介质层可以通过CVD、PVD或者ALD工艺等形成。第一高k介质层可以包括氧化硅铪(HfSiO)层、氮氧化硅铪(HfSiON)层、氧化钽铪(HfTaO)层、氧化钛铪(HfTiO)层、氧化锆铪(HfZrO)层、氧化锆(ZrO 2)层或氧化铝(Al 2O 3)层中的至少一层。第一功函数层可以包括三氧化二镧(La 2O 3)层，可以用于调节阈值电压。第一覆盖层可以是氮化钛(TiN)层、氮化钽(TaN)层等金属层，可以改善多晶硅耗尽。
步骤S1042，在第二栅氧化层上依次沉积形成第二高k介质层、第二功函数层、第二覆盖层，以形成第二叠层结构。
继续参见图3c，在第二栅氧化层112上依次沉积形成第二高k介质层119、第二功函数层120、第二覆盖层121，以形成第二叠层结构122。
在实施时，第二高k介质层可以与第一高k介质层相同，也可以不同。第二功函数层可以包括三氧化二铝(Al 2O 3)层，可以用于调节阈值电压。第二覆盖层可以与第一覆盖层相同，也可以不同。
步骤S1043，在第一叠层结构和第二叠层结构上形成多晶硅层，形成第一栅极结构和第二栅极结构。
参见图3d，在第一叠层结构118和第二叠层结构122上形成多晶硅层123，形成第一栅极结构113和第二栅极结构114。
步骤S105，在氮化处理后的第一掺杂区和第二掺杂区分别形成P型扩展区和N型扩展区。
参见图3e，在氮化处理后的第一掺杂区101a和第二掺杂102a区分别形成P型扩展区124和N型扩展区125。
这里，N型扩展区包括晕环离子注入和轻掺杂漏(Lightly Doped Drain，LDD)，P型扩展区也包括晕环离子注入和LDD，区别在于两者掺杂的离子不同。在实施时，晕环离子注入时，离子注入方向可以与第一掺杂区和第二掺杂区不垂直，存在一定的角度，形成一个类似口袋的掺杂区。如此，可以降低源和漏极的耗尽区的横向扩展，防止源漏穿通现象，扩展区在源漏与沟道之间形成杂质浓度梯度，减小漏极附近的峰值电场，改善热载流子效应。
步骤S106，在第一栅极结构和第二栅极结构的两侧分别形成侧墙结构。
继续参见图3e，在第一栅极结构113和第二栅极结构114的两侧分别形成侧墙结构126。侧墙结构126所采用的材料可以是氮化物，例如氮化硅或者氮氧化硅等。
本公开实施例提供一种半导体结构，该半导体结构采用上述实施例中的方法形成。
本公开所提供的方法或半导体结构实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或半导体结构实施例。
以上半导体结构实施例的描述，与上述方法实施例的描述是类似的，具有同方法实施例相似的有益效果。对于本公开半导体实施例中未披露的技术细节，请参照本公开方法实施例的描述而理解。
以上所述，仅为本公开的示例性的实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。因此，本公开实施例的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例中，半导体结构的形成方法包括：提供基底，所述基底包括第一掺杂区和第二掺杂区，其中，所述第一掺杂区和所述第二掺杂区之间具有隔离结构；对所述第一掺杂区和所述第二掺杂区进行氮化处理；对氮化处理后的所述第一掺杂区和所述第二掺杂区进行氧化处理，分别形成第一栅氧化层和第二栅氧化层。这样，通过对第一掺杂区和第二掺杂区进行氮化处理；对氮化处理后的第一掺杂区和第二掺杂区进行氧化处 理，分别形成第一栅氧化层和第二栅氧化层。这样，一方面，氮化处理形成的氮离子会降低第二掺杂区的氧化速率，从而抑制形成第二栅氧化层，如此可以减小第一栅氧化层与第二栅氧化层的厚度差异，减小对半导体器件的电学参数例如阈值电压和电容的影响，并为调整半导体器件提供了良好的基础；另一方面，该方法的工艺流程简单可控。

Claims (15)

  1. 一种半导体结构形成方法，包括：
    提供基底，所述基底包括第一掺杂区和第二掺杂区，其中，所述第一掺杂区和所述第二掺杂区之间具有隔离结构；
    对所述第一掺杂区和所述第二掺杂区进行氮化处理；
    对氮化处理后的所述第一掺杂区和所述第二掺杂区进行氧化处理，分别形成第一栅氧化层和第二栅氧化层。
  2. 根据权利要求1所述的方法，其中，所述提供基底，包括：
    提供衬底；
    在所述衬底上形成隔离结构；
    对形成隔离结构的所述衬底进行掺杂，在所述隔离结构的两侧分别形成所述第一掺杂区和所述第二掺杂区。
  3. 根据权利要求2所述的方法，其中，所述第一掺杂区对应的所述衬底为第一衬底，所述第二掺杂区对应的所述衬底为第二衬底和形成于所述第二衬底上的锗硅衬底。
  4. 根据权利要求3所述的方法，其中，在所述第二衬底上形成锗硅衬底的步骤，包括：
    在所述第一衬底和所述第二衬底上形成图案化的第一掩膜层，所述图案化的第一掩膜层暴露出所述第二衬底的表面；
    通过外延生长或沉积在所述第二衬底的表面形成锗硅衬底；
    去除所述第一衬底上的所述锗硅衬底和所述图案化的第一掩膜层。
  5. 根据权利要求4所述的方法，其中，所述对形成隔离结构的所述衬底进行掺杂，在所述隔离结构的两侧形成第一掺杂区和第二掺杂区，包括：
    在形成隔离结构的所述第一衬底和所述锗硅衬底上形成图案化的第二掩膜层，所述图案化的第二掩膜层暴露出所述第一衬底的表面；
    以所述图案化的第二掩膜层为掩膜，对所述第一衬底进行第一离子注入，形成所述第一掺杂区；
    去除所述图案化的第二掩膜层；
    在形成所述隔离结构和所述第一掺杂区的所述第一衬底和所述锗硅衬底上形成图 案化的第三掩膜层，所述图案化的第三掩膜层暴露出形成所述锗硅衬底的表面；
    以所述图案化的第三掩膜层为掩膜，对所述锗硅衬底和与所述锗硅衬底下表面接触的所述第二衬底进行第二离子注入，形成所述第二掺杂区；
    去除所述图案化的第三掩膜层。
  6. 根据权利要求5所述的方法，其中，所述第一掺杂区包括N型掺杂的第一衬底，所述第二掺杂区包括P型掺杂的第二衬底和P型掺杂的锗硅衬底。
  7. 根据权利要求1至6任一项所述的方法，其中，所述对所述第一掺杂区和所述第二掺杂区进行氮化处理，包括：
    采用等离子体对所述第一掺杂区和所述第二掺杂区进行氮化处理。
  8. 根据权利要求7所述的方法，其中，所述氮化处理的反应气体包括氮气，辅助气体包括氦气，所述氮气和所述氦气的流量之比为1:5至1:2。
  9. 根据权利要求8所述的方法，其中，所述氮化处理的反应温度为90℃至100℃，反应时间为90s至110s。
  10. 根据权利要求1至6任一项所述的方法，其中，所述氧化处理为臭氧氧化。
  11. 根据权利要求10所述的方法，其中，所述臭氧氧化采用湿法氧化工艺，所述湿法氧化工艺的氧化剂为臭氧。
  12. 根据权利要求11所述的方法，其中，所述湿法氧化工艺的臭氧流量为8至12L/min。
  13. 根据权利要求11所述的方法，其中，所述湿法氧化工艺的温度为20至30℃。
  14. 根据权利要求1至6任一项所述的方法，其中，所述第一栅氧化层厚度为10.5至
    Figure PCTCN2022088464-appb-100001
    所述第二栅氧化层的厚度大于所述第一栅氧化层的厚度，且厚度差小于
    Figure PCTCN2022088464-appb-100002
  15. 一种半导体结构，采用如权利要求1至14任一项所述的方法形成。
PCT/CN2022/088464 2021-12-28 2022-04-22 一种半导体结构及其形成方法 Ceased WO2023123762A1 (zh)

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