WO2023098675A1 - 消除间隙型缺陷B-swirl的方法、硅片及电子器件 - Google Patents

消除间隙型缺陷B-swirl的方法、硅片及电子器件 Download PDF

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WO2023098675A1
WO2023098675A1 PCT/CN2022/135093 CN2022135093W WO2023098675A1 WO 2023098675 A1 WO2023098675 A1 WO 2023098675A1 CN 2022135093 W CN2022135093 W CN 2022135093W WO 2023098675 A1 WO2023098675 A1 WO 2023098675A1
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silicon wafer
preset temperature
temperature
swirl
silicon
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English (en)
French (fr)
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王振
李青海
许武警
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中环领先半导体材料有限公司
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • the disclosure belongs to the technical field of semiconductors, and in particular relates to a method for eliminating a gap defect B-swirl in a silicon wafer, a silicon wafer and an electronic device.
  • the development direction of the semiconductor industry is manifested in two aspects: on the one hand, the size of the characteristic line width is continuously reduced; on the other hand, the size of silicon wafers is constantly increasing.
  • the Czochralski (CZ) method is generally used to produce single crystal silicon. The increase in the size of the silicon wafer will cause the pulling speed of single crystal silicon to slow down during the crystal growth process, and the crystal growth time will be prolonged, and finally the size of the original defect in the single crystal silicon will become larger.
  • the present disclosure aims to solve one of the technical problems in the related art at least to a certain extent. Therefore, the purpose of the present disclosure is to provide a method for eliminating the gap-type defect B-swirl, a single crystal silicon wafer and an electronic device.
  • the disclosure eliminates the interstitial defect B-swirl in the single crystal silicon wafer through high-temperature rapid heat treatment without generating new defects, and improves the quality of the silicon wafer.
  • the present disclosure proposes a method for eliminating the interstitial defect B-swirl in a silicon wafer.
  • the method comprises:
  • the temperature of the single crystal silicon wafer having the interstitial defect B-swirl is raised to a first preset temperature, and the temperature is maintained, so as to eliminate the heat donor inside the silicon wafer;
  • step (2) under a nitrogen atmosphere, heating the silicon wafer obtained in step (1) to a second preset temperature and keeping it warm so as to form a vacancy region near the surface of the silicon wafer;
  • step (3) cooling the silicon wafer obtained in step (2) to a third preset temperature, and stopping the nitrogen atmosphere, so as to keep the vacancies in the vacancy region on the near surface of the silicon wafer;
  • step (3) Under an inert atmosphere, the silicon wafer obtained in step (3) is heated to a fourth preset temperature, and kept warm, so that silicon atoms in the silicon wafer can diffuse outward from interstitial silicon atoms and recombine with the vacancies near the surface annihilation.
  • the silicon wafer with the interstitial defect B-swirl is first raised to a first preset temperature, kept warm, and the heat donor inside the silicon wafer is eliminated, That is to eliminate the interstitial oxygen located at the gap position inside the silicon wafer; then raise the temperature to the second preset temperature under nitrogen atmosphere, keep warm, and form a vacancy area on the near surface of the silicon wafer; then cool down to the third preset temperature, stop In a nitrogen atmosphere, the vacancies are kept on the near surface of the silicon wafer to prevent the vacancies from continuing to diffuse outward during the continuous high temperature process, resulting in a decrease in the concentration of vacancies near the surface; finally, the temperature is raised to a fourth preset temperature and kept warm to make the silicon wafer Internal self-interstitial silicon atoms diffuse outward, recombining and annihilating with the vacancies formed near the surface.
  • the gap-type defect B-swirl in the silicon wafer is eliminated, and it is transformed into a perfect wafer without new defects, which improves the quality of the silicon wafer, thereby achieving the effect of not affecting the IC process. .
  • the method for eliminating the gap-type defect B-swirl in a silicon wafer may also have the following additional technical features:
  • the first preset temperature is 700-800°C
  • the holding time is 5-25s.
  • the second preset temperature is 1150°C-1200°C, and the holding time is 10-30s.
  • step (2) the flow rate of the nitrogen gas is 50-100 SLM.
  • the third preset temperature is 1000-1100°C.
  • the cooling rate is 50-100° C./s.
  • the vacancy concentration near the surface of the silicon wafer obtained in step (3) is 10 4 -10 8 cm -3 .
  • the near-surface vacancy concentration of the silicon wafer obtained in step (3) is A 1 ⁇ 10 4 cm -3 , wherein, 1 ⁇ A 1 ⁇ 10, and A 1 ⁇ real number,
  • the cooling rate of step (3) is 50-65°C/s
  • the second preset temperature in step (2) is 1150°C-1160°C
  • the flow rate of nitrogen in step (2) is 50-100SLM ;
  • the vacancy concentration near the surface of the silicon wafer obtained in step (3) is A 2 ⁇ 10 5 cm -3 , where 1 ⁇ A 2 ⁇ 10, and A 2 ⁇ real number, the cooling rate in step (3) is 65-75°C/s, the second preset temperature in step (2) is 1160°C-1190°C, and the flow rate of nitrogen in step (2) is 50-100SLM;
  • the vacancy concentration near the surface of the silicon wafer obtained in step (3) is A 3 ⁇ 10 6 cm -3 , where 1 ⁇ A 3 ⁇ 10, and A 3 ⁇ real number, the cooling rate of step (3) is 75-85°C/s, the second preset temperature in step (2) is 1160°C-1190°C, and the flow rate of nitrogen in step (2) is 50-100SLM;
  • the near-surface vacancy concentration of the silicon wafer obtained in step (3) is A 4 ⁇ 10 7 cm -3 , wherein, 1 ⁇ A 4 ⁇ 10, and A 4 ⁇ real number, the cooling rate of step (3) is 85-95°C/s, the second preset temperature in step (2) is 1160°C-1190°C, and the flow rate of nitrogen in step (2) is 50-100SLM;
  • the vacancy concentration near the surface of the silicon wafer obtained in step (3) is A 5 ⁇ 10 8 cm -3 , where 1 ⁇ A 5 ⁇ 10, and A 5 ⁇ real number, the cooling rate of step (3) is 95-100°C/s, the second preset temperature in step (2) is 1190°C-1200°C, and the flow rate of nitrogen in step (2) is 50-100SLM.
  • the fourth preset temperature is 1250-1300°C, and the holding time is 10-30s.
  • the inert atmospheres are each independently an argon atmosphere.
  • the present disclosure provides a silicon wafer.
  • the silicon wafer is obtained by processing the method described in the above embodiments. As a result, the quality of the silicon wafer is improved, thereby achieving the effect of not affecting the IC manufacturing process.
  • the present disclosure proposes an electronic device.
  • the electronic device has a silicon wafer processed by the method described in the above embodiment or the silicon wafer described in the above embodiment. Therefore, the electronic device has all the advantages of the above-mentioned silicon chip, which will not be repeated here.
  • FIG. 1 is a flowchart of a method for eliminating gap-type defects B-swirl in a silicon wafer according to an embodiment of the present disclosure
  • Fig. 2 is the B-swirl figure of the copper decoration method of the silicon chip that does not pass through annealing treatment of embodiment 1;
  • Fig. 3 is the B-swirl figure of the copper decoration method of the annealed silicon chip of embodiment 1;
  • Fig. 4 is the B-swirl figure of the copper decoration method of the silicon chip that does not pass through annealing treatment of embodiment 2;
  • Fig. 5 is the B-swirl figure of the copper decoration method of the annealed silicon chip of embodiment 2;
  • Fig. 6 is the B-swirl diagram of the copper decoration method of the silicon wafer without annealing treatment in Comparative Example 1;
  • FIG. 7 is a B-swirl diagram of the copper decoration method of the annealed silicon wafer of Comparative Example 1.
  • FIG. 7 is a B-swirl diagram of the copper decoration method of the annealed silicon wafer of Comparative Example 1.
  • a perfect crystal or a defect-free crystal does not mean an absolutely perfect crystal or a crystal free of any defects, but allows for the presence of one or more crystal defects in an insignificant amount that is not sufficient to degrade the crystal or the resulting wafer to a certain electrical degree. Or the mechanical characteristics produce large changes so that the performance of electronic devices made using them deteriorates.
  • the present disclosure proposes a method for eliminating the interstitial defect B-swirl. According to an embodiment of the present disclosure, with reference to accompanying drawing 1, described method comprises:
  • the temperature of the single crystal silicon wafer with the gap-type defect B-swirl is raised to the first preset temperature, and the heat preservation is carried out so as to eliminate the heat donor inside the silicon wafer, that is, to eliminate the gap position inside the silicon wafer.
  • the interstitial oxygen at the place so as to achieve the purpose of reducing the consumption of vacancies by interstitial oxygen.
  • the saturation of the interstitial oxygen of the silicon wafer increases, and the precipitated interstitial oxygen dissolves back into the silicon wafer, thereby achieving the purpose of eliminating the interstitial oxygen at the interstitial position.
  • B-swirl is a defect caused by silicon atoms at interstitial positions in a silicon wafer, specifically, B-swirl is a defect ring formed by agglomeration of silicon atoms at interstitial positions, and B-swirl is a small Three-dimensional interstitial aggregates, the concentration is about 10 4 -10 8 cm -3 .
  • the above-mentioned first preset temperature is 700-800°C
  • the holding time is 5-25s. Therefore, limiting the first preset temperature and holding time to the above-mentioned range is further conducive to eliminating The interstitial oxygen existing at the interstitial position, thereby achieving the purpose of reducing the consumption of interstitial oxygen on the vacancies.
  • the type of the inert gas used in this step is not particularly limited, and those skilled in the art can choose it at will according to actual needs, such as argon and the like.
  • step S200 Under a nitrogen atmosphere, heat up the silicon wafer obtained in step S100 to a second preset temperature, and keep it warm
  • the silicon wafer obtained in step S100 is heated up to a second preset temperature, and kept warm. Since heat treatment under the protection of N2 will cause the surface of the silicon wafer to be nitrided, thereby injecting a large number of vacancies, so that the above silicon A high-concentration vacancy region is formed near the surface of the sheet to provide sufficient vacancies for subsequent annihilation with interstitial silicon atoms.
  • the near surface refers to the range of 0-100 ⁇ m from the surface.
  • the above-mentioned second preset temperature is 1150°C-1200°C, and the holding time is 10-30s. Therefore, the second preset temperature and holding time are limited to the above-mentioned range, and further have It is beneficial to form a reasonable concentration of vacancy regions near the surface of the silicon wafer.
  • the flow rate of nitrogen gas is 50-100 SLM. Therefore, limiting the flow rate of nitrogen gas within the above range is further conducive to forming a reasonable concentration of vacancy regions near the surface of the silicon wafer.
  • SLM is a flow unit, meaning L/min.
  • step S300 cooling the silicon wafer obtained in step S200 to a third preset temperature, and stopping the nitrogen atmosphere
  • step S200 the temperature of the silicon wafer obtained in step S200 is lowered to a third preset temperature, and the nitrogen atmosphere is stopped, so as to keep the vacancies in the above-mentioned vacancy region near the surface of the silicon wafer, and prevent the outer diffusion of vacancies during the continuous high temperature process from causing near-surface
  • concentration of vacancies decreases. It should be noted that the higher the temperature, the faster the outward diffusion of vacancies, and the fewer vacancies remain near the surface of the silicon wafer.
  • the above-mentioned third preset temperature is 1000-1100°C, thus, the third preset temperature is limited within the above-mentioned range, and the temperature is further rapidly and slightly lowered so that vacancies remain on the near surface of the silicon wafer , to further prevent the out-diffusion of vacancies during the continuous high temperature process from reducing the concentration of near-surface vacancies.
  • the inventors found that if the third preset temperature is too low, the silicon wafer may have the risk of slip lines or fragments; if the third preset temperature is too high, it will cause out-diffusion of vacancies and reduce the concentration of vacancy near the surface.
  • the holding time in this step is not limited, as long as the temperature of the silicon wafer is lowered to the third preset temperature, the process of retaining the vacancies near the surface of the silicon wafer is completed.
  • the above-mentioned cooling rate is 50-100°C/s, thereby limiting the cooling rate within the above-mentioned range, further rapid and micro-cooling keeps vacancies near the surface of the silicon wafer, and further Preventing vacancy out-diffusion during sustained high temperature leads to a decrease in near-surface vacancy concentration.
  • the vacancy concentration near the surface of the silicon wafer obtained in step S300 is 10 4 -10 8 cm -3 , where the vacancy concentration refers to the concentration of vacancies in the whole silicon wafer, Therefore, it is further beneficial to keep the vacancy concentration in the vacancy region consistent with the B-swirl defect concentration, without introducing redundant defects, and sufficient to recombine with interstitial silicon atoms.
  • the concentration of interstitial defect B-swirl in the above-mentioned silicon wafer is about 10 4 -10 8 cm -3 , which can be directly detected by LSTD (laser scattering tomography defect, infrared scattering tomography defect).
  • LSTD laser scattering tomography defect, infrared scattering tomography defect
  • the vacancy concentration near the surface of the silicon wafer obtained in step S300 is related to the cooling rate in step S300, the second preset temperature in step S200, and the flow rate of the nitrogen gas in step S200, specifically :
  • the above-mentioned second preset temperature in step S200 is 1150°C-1160°C
  • the flow rate of the above-mentioned nitrogen in step S200 is 50-100SLM
  • the above-mentioned The vacancy concentration near the surface of the silicon wafer is A 1 ⁇ 10 4 cm -3 , where 1 ⁇ A 1 ⁇ 10, and A 1 ⁇ real number;
  • the above-mentioned second preset temperature in step S200 is 1160°C-1190°C
  • the flow rate of the above-mentioned nitrogen in step S200 is 50-100SLM
  • the above-mentioned The vacancy concentration near the surface of the silicon wafer is A 2 ⁇ 10 5 cm -3 , where 1 ⁇ A 2 ⁇ 10, and A 2 ⁇ real number;
  • step S300 When the cooling rate in step S300 is 75-85°C/s, the above-mentioned second preset temperature in step S200 is 1160°C-1190°C, and the flow rate of the above-mentioned nitrogen in step S200 is 50-100SLM, the above-mentioned temperature obtained in step S300
  • the vacancy concentration near the surface of the silicon wafer is A 3 ⁇ 10 6 cm -3 , where 1 ⁇ A 3 ⁇ 10, and A 3 ⁇ real number;
  • the above-mentioned second preset temperature in step S200 is 1160°C-1190°C
  • the flow rate of the above-mentioned nitrogen in step S200 is 50-100SLM
  • the above-mentioned The vacancy concentration near the surface of the silicon wafer is A 4 ⁇ 10 7 cm -3 , where 1 ⁇ A 4 ⁇ 10, and A 4 ⁇ real number;
  • the above-mentioned second preset temperature in step S200 is 1190°C-1200°C
  • the flow rate of the above-mentioned nitrogen in step S200 is 50-100SLM
  • the above-mentioned The vacancy concentration near the surface of the silicon wafer is A 5 ⁇ 10 8 cm -3 , where 1 ⁇ A 5 ⁇ 10, and A 5 ⁇ real number.
  • step S400 Under an inert atmosphere, the silicon wafer obtained in step S300 is heated to a fourth preset temperature, and kept warm
  • the above-mentioned silicon wafer obtained in step S300 is heated to a fourth preset temperature, and kept warm, so that the interstitial silicon atoms inside the silicon wafer can diffuse outwards and recombine and annihilate with the above-mentioned vacancies near the surface. It should be noted that the number of interstitial silicon atoms diffused outwards and the vacancies formed near the surface need to be equal, at least in an order of magnitude.
  • the cooling rate of S300 will be slowed down, thereby reducing the concentration of vacancies formed near the surface; If there are too many interstitial silicon atoms diffused outward, the cooling rate of S300 is accelerated or the second preset temperature is increased, so as to increase the concentration of vacancies formed near the surface.
  • the above-mentioned fourth preset temperature is 1250°C-1300°C, and the holding time is 10-30s. Therefore, the fourth preset temperature and holding time are limited to the above range, which is further sufficient Ensure that the silicon atoms in the silicon wafer diffuse outward from the interstitial space, and recombine and annihilate with the vacancies formed near the surface. The inventors found that if the temperature is too high or the holding time is too long, the silicon wafer will have the risk of slip lines or fragments; High concentration vacancy recombination annihilation.
  • the type of inert gas used in this step is not particularly limited, and those skilled in the art can choose at will according to actual needs, such as argon and the like.
  • the silicon wafer with the interstitial defect B-swirl is first raised to the first preset temperature, kept warm, and the heat donor inside the silicon wafer is eliminated; nitrogen atmosphere Then heat up to the second preset temperature, keep warm, and form a vacancy area on the near surface of the silicon wafer; then cool down to the third preset temperature, stop the nitrogen atmosphere, and keep the vacancies in the above-mentioned vacancy area on the near surface of the silicon wafer, Prevent the vacancies from continuing to diffuse outward during the continuous high temperature process, resulting in a decrease in the concentration of vacancies near the surface; finally raise the temperature to the fourth preset temperature and keep it warm, so that the interstitial silicon atoms in the above-mentioned silicon wafers diffuse outward and recombine with the vacancies formed near the surface to annihilate.
  • the gap-type defect B-swirl in the silicon wafer is eliminated through high-temperature rapid heat treatment, and it is transformed into a perfect wafer without new defects, which improves the quality of the silicon wafer, thereby realizing a process that does not affect the IC process. Effect.
  • the present disclosure provides a silicon wafer.
  • the silicon wafer is obtained by using the method of the above embodiment. As a result, the quality of the silicon wafer is improved, thereby achieving the effect of not affecting the IC manufacturing process.
  • the present disclosure proposes an electronic device.
  • the above-mentioned electronic device has a silicon wafer processed by the method of the above embodiment or the silicon wafer of the above embodiment. Therefore, the above-mentioned electronic device has all the advantages of the above-mentioned silicon chip, which will not be repeated here.
  • Two consecutive silicon wafers with interstitial defect B-swirl were produced from the same ingot, and the order of magnitude of interstitial defect B-Swirl concentration in the silicon wafer was detected by LSTD to be 10 4 cm -3 .
  • one silicon wafer does not undergo high-temperature rapid annealing, and the other silicon wafer undergoes high-temperature rapid annealing, and high-temperature rapid annealing includes the following steps:
  • the above-mentioned silicon wafers without annealing treatment and annealing treatment were tested by the copper decoration method respectively.
  • the copper decoration method detection steps (1) determine the thickness of the silicon wafer sample; (2) clean the test piece, first with tap water, and then Clean the surface of the test piece with a surfactant, KOH removes surface particles; (3) chemical polishing, polish and clean the surface of the test piece through MAE-A solution (mixture of nitric acid, acetic acid and hydrofluoric acid); (4) Copper nitrate coating; (5) heat treatment at 900°C for 4 hours; (6) chemical polishing, polishing and cleaning the surface of the test piece through MAE-B (a mixture of hydrofluoric acid, potassium dichromate and acetic acid); (7) Etching, Secco etching for 45 minutes to develop; (8) Photographing.
  • MAE-A solution mixture of nitric acid, acetic acid and hydrofluoric acid
  • MAE-B a mixture of hydrofluoric acid, potassium dichromat
  • the basic principle of the copper decoration method is that the copper precipitation will generate compressive stress in the surrounding area of the micro-defect, and these stresses will be relieved by the release of silicon atoms, which will form new dislocations around the copper. Copper precipitates subsequently form at these dislocations. Since many copper deposits and dislocations are formed around the micro-defects, forming a larger area, it is easy to observe under a microscope.
  • Figure 2 is the B-swirl diagram of the silicon wafer that has not been annealed
  • Figure 3 is the B-swirl diagram of the silicon wafer that has been annealed.
  • the area indicated by the arrow in Figure 2 is the B-swirl area, and there are white spots in this area, which means that there are B-swirl defects in the wafer.
  • the order of magnitude of interstitial defect B-Swirl concentration in the silicon wafer detected by LSTD is 10 5 cm -3 .
  • One of the silicon wafers does not undergo high-temperature rapid annealing, and the other silicon wafer undergoes high-temperature rapid annealing.
  • High-temperature rapid annealing includes the following steps:
  • Figure 4 is the B-swirl diagram of the silicon wafer without annealing treatment
  • Figure 4 5 is the B-swirl diagram of the annealed silicon wafer.
  • the area indicated by the arrow in Figure 4 is the B-swirl area, and there are white spots in this area, which means that there are B-swirl defects in the wafer.
  • the area indicated by the arrow in Figure 5 is the B-swirl area, and there are no white spots in this area, which means that no copper precipitation is formed in this area, that is, this area is a perfect area without defects. It can be seen that after the annealing treatment, the defects in the wafer are eliminated.
  • the above-mentioned silicon wafers without annealing treatment and annealing treatment were respectively tested by the copper decoration method.
  • the test results are: there are white spots in the B-swirl area of the B-swirl diagram of the silicon wafers without annealing treatment, representing the wafer There are B-swirl defects in it; there is no white spot in the B-swirl area in the B-swirl diagram of the annealed silicon wafer, which means that no copper precipitation is formed in this area, that is, this area is a perfect area without defects. It can be seen that after the annealing treatment, the defects in the wafer are eliminated.
  • the detection pictures of this embodiment are similar to those of Embodiments 1 and 2, and will not be repeated here.
  • the above-mentioned silicon wafers without annealing treatment and annealing treatment were respectively tested by the copper decoration method.
  • the test results are: there are white spots in the B-swirl area of the B-swirl diagram of the silicon wafers without annealing treatment, representing the wafer There are B-swirl defects in it; there is no white spot in the B-swirl area in the B-swirl diagram of the annealed silicon wafer, which means that no copper precipitation is formed in this area, that is, this area is a perfect area without defects. It can be seen that after the annealing treatment, the defects in the wafer are eliminated.
  • the detection pictures of this embodiment are similar to those of Embodiments 1 and 2, and will not be repeated here.
  • the order of magnitude of interstitial defect B-Swirl concentration in the silicon wafer detected by LSTD is 10 8 cm -3 .
  • One of the silicon wafers does not undergo high-temperature rapid annealing, and the other silicon wafer undergoes high-temperature rapid annealing.
  • High-temperature rapid annealing includes the following steps:
  • the above-mentioned silicon wafers without annealing treatment and annealing treatment were respectively tested by the copper decoration method.
  • the test results are: there are white spots in the B-swirl area of the B-swirl diagram of the silicon wafers without annealing treatment, representing the wafer There are B-swirl defects in it; there is no white spot in the B-swirl area in the B-swirl diagram of the annealed silicon wafer, which means that no copper precipitation is formed in this area, that is, this area is a perfect area without defects. It can be seen that after the annealing treatment, the defects in the wafer are eliminated.
  • the detection pictures of this embodiment are similar to those of Embodiments 1 and 2, and will not be repeated here.
  • the fourth preset temperature is 1230° C.
  • other contents are the same as those in Example 1.
  • the silicon wafer without annealing treatment and the silicon wafer with annealing treatment were tested by the copper decoration method, and the test results are shown in Figure 6 and Figure 7, where Figure 6 is the B-swirl diagram of the silicon wafer without annealing treatment , Figure 7 is a B-swirl diagram of annealed silicon wafer.
  • the area indicated by the arrow in Figure 6 is the B-swirl area, and there are white spots in this area, which means that there are B-swirl defects in the wafer.
  • the area indicated by the arrow in Figure 7 is the B-swirl area, and there are white spots in this area, which means that there are B-swirl defects in the wafer. It may be that the preset temperature in the fourth section is too low, which prevents interstitial silicon atoms from completing timely outdiffusion and recombination annihilation with high-concentration vacancies near the surface.

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Abstract

一种消除间隙型缺陷B-swirl的方法、硅片及电子器件，所述方法包括：(1)惰性氛围下，将具有间隙型缺陷B-swirl的单晶硅片升温至第一预设温度，保温；(2)氮气氛围下，将步骤(1)得到的所述硅片升温至第二预设温度，保温；(3)将步骤(2)得到的所述硅片降温至第三预设温度，停止氮气氛围；(4)惰性氛围下，步骤(3)得到的所述硅片升温至第四预设温度，保温。

Description

消除间隙型缺陷B-swirl的方法、硅片及电子器件
优先权信息
本申请请求2021年11月30日向中国国家知识产权局提交的、专利申请号为202111450289.3的专利申请的优先权和权益，并且通过参照将其全文并入此处。
技术领域
本公开属于半导体技术领域，具体涉及一种消除硅片中间隙型缺陷B-swirl的方法、硅片及电子器件。
背景技术
半导体行业发展方向表现为两个方面：一个方面，特征线宽的尺寸不断减小；另一方面，硅片尺寸不断增大。近年来随着集成电路产业的快速发展，进一步推动了集成电路产业的技术升级，随着线宽尺寸进一步缩小，对单晶硅片质量提出更高的要求。在实际生产中，生产单晶硅一般采用直拉法(Czochralski，CZ)。硅片尺寸的增大会引起晶体生长过程中单晶硅的提拉速度放缓，晶体生长时间延长，最终得到单晶硅中原生缺陷尺寸变大，而当单晶硅中原生缺陷尺寸达到器件特征线宽的1/3时就会直接导致器件的性能失效。故人们开始注重硅中缺陷的尺寸问题。根据Voronkov理论，直拉法硅晶体生长过程中严格控制晶体生长速度(V)和固液界面的温度梯度(G)比值为一特定值，即可得到无缺陷的完美晶体，但在实际操作过程中很难稳定V/G的值，晶体生长速度V过慢往往会产生间隙型缺陷，尤其是在晶棒头部拉速较慢，晶体往往出现间隙型缺陷，形成带有间隙型缺陷B-swirl的硅片，引起集成电路(Integrated Circuit，IC)IC制程漏电问题，该类硅片往往只能报废处理。
如何消除单晶硅片中的间隙型缺陷，是当前急需要解决的技术问题。
发明内容
本公开旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本公开的目的在于提出一种消除间隙型缺陷B-swirl的方法、单晶硅片及电子器件。本公开通过高温快速热处理消除了单晶硅片中的间隙型缺陷B-swirl，且不产生新的缺陷，提高了硅片的品质。
在本公开的一个方面，本公开提出了一种消除硅片中间隙型缺陷B-swirl的方法。根据本公开的实施方案，所述方法包括：
(1)惰性氛围下，将具有间隙型缺陷B-swirl的单晶硅片升温至第一预设温度，保温，以便消除所述硅片内部的热施主；
(2)氮气氛围下，将步骤(1)得到的所述硅片升温至第二预设温度，保温，以便在所述硅片的近表面形成空位区；
(3)将步骤(2)得到的所述硅片降温至第三预设温度，停止氮气氛围，以便将所述空位区的空位保留在所述硅片的近表面；
(4)惰性氛围下，步骤(3)得到的所述硅片升温至第四预设温度，保温，以便使所述硅片内部自间隙硅原子向外扩散，与近表面的所述空位复合湮灭。
根据本公开实施方案的消除硅片中间隙型缺陷B-swirl的方法，具有间隙型缺陷B-swirl的硅片首先升至第一预设温度，保温，消除所述硅片内部的热施主，即消除硅片内部的位于间隙位置处的间隙氧；氮气氛围下再升温至第二预设温度，保温，在所述硅片的近表面形成空位区；然后降温至第三预设温度，停止氮气氛围，将所述空位保留在所述硅片的近表面，防止持续高温过程空位继续向外扩散，导致近表面空位浓度降低；最后升温至第四预设温度，保温，使所述硅片内部自间隙硅原子向外扩散，与所述近表面形成的空位复合湮灭。由此，通过高温快速热处理消除了硅片中间隙型缺陷B-swirl，将其转变成完美型晶片，且不产生新的缺陷，提高了硅片的品质，从而实现了不影响IC制程的效果。
另外，根据本公开上述实施方案的消除硅片中间隙型缺陷B-swirl的方法还可以具有如下附加的技术特征：
在本公开的一些实施方案中，在步骤(1)中，所述第一预设温度为700-800℃，所述保温时间为5-25s。
在本公开的一些实施方案中，在步骤(2)中，所述第二预设温度为1150℃-1200℃，所述保温时间为10-30s。
在本公开的一些实施方案中，在步骤(2)中，所述氮气的流量为50-100SLM。
在本公开的一些实施方案中，在步骤(3)中，所述第三预设温度为1000-1100℃。
在本公开的一些实施方案中，在步骤(3)中，所述降温的速率为50-100℃/s。
在本公开的一些实施方案中，步骤(3)得到的所述硅片的近表面的空位浓度为10 4-10 8cm -3。
在本公开的一些实施方案中，步骤(3)得到的所述硅片的近表面的空位浓度为A 1×10 4cm -3，其中，1≤A 1<10，且A 1∈实数，步骤(3)的降温速率为50-65℃/s，步骤(2)中的所述第二预设温度为1150℃-1160℃，步骤(2)中的所述氮气的流量为50-100SLM；
或，步骤(3)得到的所述硅片的近表面的空位浓度为A 2×10 5cm -3，其中，1≤A 2<10，且A 2∈实数，步骤(3)的降温速率为65-75℃/s，步骤(2)中的所述第二预设温度为1160℃-1190℃，步骤(2)中的所述氮气的流量为50-100SLM；
或，步骤(3)得到的所述硅片的近表面的空位浓度为A 3×10 6cm -3，其中，1≤A 3<10，且A 3∈实数，步骤(3)的降温速率为75-85℃/s，步骤(2)中的所述第二预设温度为1160℃-1190℃，步骤(2)中的所述氮气的流量为50-100SLM；
或，步骤(3)得到的所述硅片的近表面的空位浓度为A 4×10 7cm -3，其中，1≤A 4<10，且A 4∈实数，步骤(3)的降温速率为85-95℃/s，步骤(2)中的所述第二预设温度为1160℃-1190℃，步骤(2)中的所述氮气的流量为50-100SLM；
或，步骤(3)得到的所述硅片的近表面的空位浓度为A 5×10 8cm -3，其中，1≤A 5<10，且A 5∈实数，步骤(3)的降温速率为95-100℃/s，步骤(2)中的所述第二预设温度为1190℃-1200℃，步骤(2)中的所述氮气的流量为50-100SLM。
在本公开的一些实施方案中，在步骤(4)中，所述第四预设温度为1250-1300℃，所述保温时间为10-30s。
在本公开的一些实施方案中，在步骤(1)和步骤(4)中，所述惰性氛围各自独立地为氩气氛围。
在本公开的再一个方面，本公开提出了一种硅片。根据本公开的实施方案，所述硅片是采用以上实施方案所述方法处理得到的。由此，提高了硅片的品质，从而实现了不影响IC制程的效果。
在本公开的第三个方面，本公开提出一种电子器件。根据本公开的实施方案，所述电子器件具有以上实施方案所述的方法处理得到的硅片或以上实施方案所述的硅片。由此，所述电子器件具有上述硅片的所有优点，在此不再赘述。
本公开的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本公开的实践了解到。
附图说明
本公开的上述和/或附加的方面和优点从结合下面附图对实施方案的描述中将变得明显和容易理解，其中：
图1为本公开实施方案的消除硅片中间隙型缺陷B-swirl的方法流程图；
图2为实施例1的不经过退火处理的硅片的铜饰法B-swirl图；
图3为实施例1的经过退火处理的硅片的铜饰法B-swirl图；
图4为实施例2的不经过退火处理的硅片的铜饰法B-swirl图；
图5为实施例2的经过退火处理的硅片的铜饰法B-swirl图；
图6为对比例1的不经过退火处理的硅片的铜饰法B-swirl图；
图7为对比例1的经过退火处理的硅片的铜饰法B-swirl图。
具体实施方式
下面详细描述本公开的实施方案，所述实施方案的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方案是示例性的，旨在用于解释本公开，而不能理解为对本公开的限制。
根据Voronkov的V/G理论，采用CZ法拉制单晶硅的过程中，在热场一定情况下，提拉速度V的快慢会引起单晶体内微缺陷的产生，当提拉速度V过快时，在单晶硅内会形成空位型缺陷，当提拉速度V过慢时，在单晶硅内会形成间隙型缺陷。其中，B-swirl是由于硅原子处于间隙位置，且该处的硅原子团聚而形成的缺陷环。
完美晶体或无缺陷晶体并不意指绝对完美的晶体或没有任何缺陷的晶体，而是容许存在极少量的一种或多种晶体缺陷，其不足以使晶体或结果得到的晶圆的某种电学或机械学特性产生大的变化以致使用其制成的电子器件的性能劣化。
在本公开的一个方面，本公开提出了一种消除间隙型缺陷B-swirl的方法。根据本公开的实施方案，参考附图1，所述方法包括：
S100：惰性氛围下，将具有间隙型缺陷B-swirl的单晶硅片升温至第一预设温度，保温
在该步骤中，惰性氛围下，将具有间隙型缺陷B-swirl的单晶硅片升温至第一预设温度，保温，以便消除上述硅片内部的热施主，即消除硅片内部位于间隙位置处的间隙氧，从而实现减少间隙氧对空位消耗的目的。具体来说，当硅片升温至第一预设温度时，硅片的间隙氧的饱和度增加，析出的间隙氧重新溶回硅片中去，从而达到消除间隙位置处间隙氧的目的。
在本公开的实施方案中，B-swirl是由硅片中间隙位置处硅原子引起的缺陷，具体来说，B-swirl是间隙位置处硅原子团聚并形成的缺陷环，B-swirl是小型三维间质团聚体，浓度约10 4-10 8cm -3。
根据本公开的一个具体实施方案，上述第一预设温度为700-800℃，保温时间为5-25s，由此，将第一预设温度和保温时间限定在上述范围内，进一步有利于消除间隙位置处存在的间隙氧，从而实现减少间隙氧对空位的消耗的目的。
在本公开的实施方案中，该步骤中采用的惰性气体的种类并不受特别限制，本领域人员可根据实际需要随意选择，例如氩气等。
S200：氮气氛围下，将步骤S100得到的硅片升温至第二预设温度，保温
在该步骤中，氮气氛围下，将步骤S100得到的硅片升温至第二预设温度，保温，由于N 2保护下进行热处理会使得硅片表面氮化，从而注入大量空位，以便在上述硅片的近表面形成高浓度的空位区，目的是为后续阶段与间隙硅原子复合湮灭提供足够的空位。其中， 近表面指的是距离表面0～100μm范围内。
根据本公开的再一个具体实施方案，上述第二预设温度为1150℃-1200℃，保温时间为10-30s，由此，将第二预设温度和保温时间限定在上述范围内，进一步有利于在上述硅片的近表面形成合理浓度的空位区。发明人发现，如果第二预设温度过高或者保温时间过长，会导致提供的空位浓度过高，从而导致出现新的空位型缺陷；如果第二预设温度过低或者保温时间过短，会导致提供的空位浓度过低，后续无法与间隙硅原子完全复合，硅片仍残留过多间隙硅原子。
根据本公开的又一个具体实施方案，氮气的流量为50-100SLM，由此，将氮气的流量限定在上述范围内，进一步有利于在硅片的近表面形成合理浓度的空位区。需要说明的是，SLM是流量单位，L/min的意思。
S300：将步骤S200得到的硅片降温至第三预设温度，停止氮气氛围
在该步骤中，将步骤S200得到的硅片降温至第三预设温度，停止氮气氛围，以便将上述空位区的空位保留在硅片的近表面，防止持续高温过程中空位外扩散导致近表面空位浓度降低。需要说明的是，温度越高，空位向外扩散的速度越快，保留在硅片近表面的空位就越少。
根据本公开的又一个具体实施方案，上述第三预设温度为1000-1100℃，由此，将第三预设温度限定在上述范围内，进一步快速微降温使空位保留在硅片的近表面，进一步防止持续高温过程中空位外扩散导致近表面空位浓度降低。发明人发现，如果第三预设温度过低，硅片可能会有产生滑移线或者破片的风险；如果第三预设温度过高，会造成空位外扩散导致近表面空位浓度降低。
需要说明的是，该步骤中的保温时间并不受限制，只要将硅片降温至第三预设温度就完成了空位在硅片近表面的保留过程。
根据本公开的又一个具体实施方案，上述降温的速率为50-100℃/s，由此，将降温的速率限定在上述范围内，进一步快速微降温使空位保留在硅片的近表面，进一步防止持续高温过程中空位外扩散导致近表面空位浓度降低。
根据本公开的又一个具体实施方案，步骤S300得到的上述硅片的近表面的空位浓度为10 4～10 8cm -3，此处的空位浓度指的是空位在整体硅片中的浓度，由此，进一步有利于使空位区的空位浓度与B-swirl缺陷浓度保持一致，不引入多余缺陷，足够与间隙硅原子复合。
如前所述，上述硅片中的间隙型缺陷B-swirl的浓度约为10 4-10 8cm -3，该浓度可通过LSTD(laser scattering tomography defect，红外散射断层缺陷)直接检测出来。为了消除B-swirl缺陷且不进入多余缺陷，需将上述硅片的近表面的空位浓度控制在与上述硅片中的间隙型缺陷B-swirl的浓度相当。需要说明的是，步骤S300得到的上述硅片的近表面的空位浓度 与步骤S300的降温速率、步骤S200中的上述第二预设温度以及步骤S200中的上述氮气的流量均相关，具体来说：
当步骤S300的降温速率为50-65℃/s，步骤S200中的上述第二预设温度为1150℃-1160℃，步骤S200中的上述氮气的流量为50-100SLM时，步骤S300得到的上述硅片的近表面的空位浓度为A 1×10 4cm -3，其中，1≤A 1<10，且A 1∈实数；
当步骤S300的降温速率为65-75℃/s，步骤S200中的上述第二预设温度为1160℃-1190℃，步骤S200中的上述氮气的流量为50-100SLM时，步骤S300得到的上述硅片的近表面的空位浓度为A 2×10 5cm -3，其中，1≤A 2<10，且A 2∈实数；
当步骤S300的降温速率为75-85℃/s，步骤S200中的上述第二预设温度为1160℃-1190℃，步骤S200中的上述氮气的流量为50-100SLM时，步骤S300得到的上述硅片的近表面的空位浓度为A 3×10 6cm -3，其中，1≤A 3<10，且A 3∈实数；
当步骤S300的降温速率为85-95℃/s，步骤S200中的上述第二预设温度为1160℃-1190℃，步骤S200中的上述氮气的流量为50-100SLM时，步骤S300得到的上述硅片的近表面的空位浓度为A 4×10 7cm -3，其中，1≤A 4<10，且A 4∈实数；
当步骤S300的降温速率为95-100℃/s，步骤S200中的上述第二预设温度为1190℃-1200℃，步骤S200中的上述氮气的流量为50-100SLM时，步骤S300得到的上述硅片的近表面的空位浓度为A 5×10 8cm -3，其中，1≤A 5<10，且A 5∈实数。
S400：惰性氛围下，步骤S300得到的硅片升温至第四预设温度，保温
在该步骤中，惰性氛围下，步骤S300得到的上述硅片升温至第四预设温度，保温，以便使硅片内部间隙硅原子向外扩散，与近表面的上述空位复合湮灭。需要说明的是，向外扩散的间隙硅原子与近表面形成的空位数量需要保持相当，至少在一个数量级，若空位过多，则减缓S300的降温速率，从而减小近表面形成的空位浓度；若向外扩散的间隙硅原子过多，加快S300的降温速率或者提高第二预设温度，从而增大近表面形成的空位浓度。
根据本公开的又一个具体实施方案，上述第四预设温度为1250℃-1300℃，保温时间为10-30s，由此，将第四预设温度和保温时间限定在上述范围内，进一步充分保证硅片内部自间隙硅原子向外扩散，与近表面形成的空位复合湮灭。发明人发现，如果温度过高或保温时间过长，硅片会有产生滑移线或破片的风险；如果温度过低或保温时间过短，导致无法有效完成间隙硅原子外扩散及与近表面高浓度空位复合湮灭。
在本公开的实施方案中，该步骤中采用惰性气体的种类并不受特别限制，本领域人员可根据实际需要随意选择，例如氩气等。
根据本公开实施方案的消除硅片中间隙型缺陷B-swirl的方法，具有间隙型缺陷B-swirl的硅片首先升至第一预设温度，保温，消除硅片内部的热施主；氮气氛围下再升温至第二 预设温度，保温，在硅片的近表面形成空位区；然后降温至第三预设温度，停止氮气氛围，将上述空位区的空位保留在上述硅片的近表面，防止持续高温过程空位继续向外扩散，导致近表面空位浓度降低；最后升温至第四预设温度，保温，使上述硅片内部间隙硅原子向外扩散，与近表面形成的空位复合湮灭。由此，通过高温快速热处理消除了硅片中的间隙型缺陷B-swirl，将其转变成完美型晶片，且不产生新的缺陷，提高了硅片的品质，从而实现了不影响IC制程的效果。
在本公开的再一个方面，本公开提出了一种硅片。根据本公开的实施方案，硅片是采用以上实施方案方法处理得到的。由此，提高了硅片的品质，从而实现了不影响IC制程的效果。
在本公开的第三个方面，本公开提出一种电子器件。根据本公开的实施方案，上述电子器件具有以上实施方案的方法处理得到的硅片或以上实施方案的硅片。由此，上述电子器件具有上述硅片的所有优点，在此不再赘述。
下面详细描述本公开的实施例，需要说明的是下面描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。另外，如果没有明确说明，在下面的实施例中所采用的所有试剂均为市场上可以购得的，或者可以按照本文或已知的方法合成的，对于没有列出的反应条件，也均为本领域技术人员容易获得的。
实施例1
同一根晶棒生产的连续两片带有间隙型缺陷B-swirl的硅片，通过LSTD检测出硅片中间隙型缺陷B-Swirl浓度的数量级为10 4㎝ -3。其中，一硅片不经过高温快速退火，另一硅片经过高温快速退火，高温快速退火包括如下步骤：
将带有间隙型缺陷B-swirl的硅片放入氩气氛围的快速退火炉中进行退火处理，快速升温至700℃，持温10s；
通入流速为50SLM的N 2，继续升温至1150℃，持温15s；
以50℃/s的速度降温至1050℃，停止供应N 2；
氩气氛围下继续升温至1250℃，持温10s，以50℃/s的速度降温至室温，由此消除了硅片中的B-swirl，得到完美晶体的硅片。
分别对上述不经过退火处理和经过退火处理的硅片经过铜饰法进行检测，铜饰法检测步骤：(1)确定硅片样片的厚度；(2)试片清洗，先用自来水清洗，再用表面活性剂清洗试片表面，KOH去除表面颗粒；(3)化学抛光，透过MAE-A液(硝酸、醋酸和氢氟酸的混合液)对试片表面进行抛光及清洁；(4)硝酸铜涂布；(5)热处理900℃保温4小时；(6)化学抛光，透过MAE-B(氢氟酸、重铬酸钾和醋酸的混合液)对试片表面进行抛光及 清洁；(7)刻蚀，Secco蚀刻45分钟显影；(8)拍照。
铜饰法的基本原理是铜沉淀会在微缺陷的周围区域产生压缩应力，这些应力会通过硅原子的释出而得以缓解，释出的硅原子会在铜周围形成新的位错。铜沉淀随后会在这些位错形成。由于微缺陷周围形成许多铜沉淀及位错，形成较大的区域，因此容易在显微镜下观察。
测试果如图2和图3所示，其中图2为不经过退火处理的硅片的B-swirl图，图3为经过退火处理的硅片的B-swirl图。图2中箭头所指区域为B-swirl区，该区域内有白点，代表晶片内有B-swirl缺陷。图3中箭头所指区域内没有白点，代表该处没有形成铜沉淀，即该处是无缺陷的完美区。可见，经过退火处理后，消除了晶片内的缺陷。
实施例2
同一根晶棒生产的连续两片带有间隙型缺陷B-swirl的硅片，通过LSTD检测出硅片中间隙型缺陷B-Swirl浓度的数量级为10 5㎝ -3。其中一硅片不经过高温快速退火，另一硅片经过高温快速退火，高温快速退火包括如下步骤：
将带有间隙型缺陷B-swirl的硅片放入氩气氛围的退火炉中进行退火处理，快速升温至750℃，持温12s；
通入流速为75SLM的N 2，继续升温至1165℃，持温20s；
以65℃/s的速度降温至1090℃，停止供应N 2；
氩气氛围下继续升温至1265℃，持温25s，以60℃/s的速度降温至室温，由此消除了硅片中的B-swirl，得到完美晶体的硅片。
分别对上述不经过退火处理和经过退火处理的硅片经过铜饰法进行检测，测试结果如图4和图5所示，其中图4为不经过退火处理的硅片的B-swirl图，图5为经过退火处理的硅片的B-swirl图。图4中箭头所指区域为B-swirl区，该区域内有白点，代表晶片内有B-swirl缺陷。图5中箭头所指区域为B-swirl区，该区域内没有白点，代表该处没有形成铜沉淀，即该处是无缺陷的完美区。可见，经过退火处理后，消除了晶片内的缺陷。
实施例3
同一根晶棒生产的连续两片带有间隙型缺陷B-swirl的硅片，通过LSTD检测出硅片中间隙型缺陷B-Swirl浓度的数量级为10 6㎝ -3。其中一硅片不经过高温快速退火，另一硅片经过高温快速退火，高温快速退火包括如下步骤：
将带有间隙型缺陷B-swirl的硅片放入氩气氛围的退火炉中进行退火处理，快速升温至760℃，持温15s；
通入流速为60SLM的N 2，继续升温至1175℃，持温20s；
以80℃/s的速度降温至1080℃，停止供应N 2；
氩气氛围下继续升温至1260℃，持温13s，以80℃/s的速度降温至室温，由此消除了硅片中的B-swirl，得到完美晶体的硅片。
分别对上述不经过退火处理和经过退火处理的硅片经过铜饰法进行检测，测试结果为：不经过退火处理的硅片的B-swirl图中的B-swirl区内有白点，代表晶片内有B-swirl缺陷；经过退火处理的硅片的B-swirl图中的B-swirl区内没有白点，代表该处没有形成铜沉淀，即该处是无缺陷的完美区。可见，经过退火处理后，消除了晶片内的缺陷。该实施例的检测图片与实施例1和2相似，在此不再重复放置。
实施例4
同一根晶棒生产的连续两片带有间隙型缺陷B-swirl的硅片，通过LSTD检测出硅片中间隙型缺陷B-Swirl浓度的数量级为10 7㎝ -3。其中一硅片不经过高温快速退火，另一硅片经过高温快速退火，高温快速退火包括如下步骤：
将带有间隙型缺陷B-swirl的硅片放入氩气氛围的退火炉中进行退火处理，快速升温至755℃，持温20s；
通入流速为75SLM的N 2，继续升温至1180℃，持温15s；
以85℃/s的速度降温至1070℃，停止供应N 2；
氩气氛围下继续升温至1290℃，持温15s，以85℃/s的速度降温至室温，由此消除了硅片中的B-swirl，得到完美晶体的硅片。
分别对上述不经过退火处理和经过退火处理的硅片经过铜饰法进行检测，测试结果为：不经过退火处理的硅片的B-swirl图中的B-swirl区内有白点，代表晶片内有B-swirl缺陷；经过退火处理的硅片的B-swirl图中的B-swirl区内没有白点，代表该处没有形成铜沉淀，即该处是无缺陷的完美区。可见，经过退火处理后，消除了晶片内的缺陷。该实施例的检测图片与实施例1和2相似，在此不再重复放置。
实施例5
同一根晶棒生产的连续两片带有间隙型缺陷B-swirl的硅片，通过LSTD检测出硅片中间隙型缺陷B-Swirl浓度的数量级为10 8㎝ -3。其中一硅片不经过高温快速退火，另一硅片经过高温快速退火，高温快速退火包括如下步骤：
将带有间隙型缺陷B-swirl的硅片放入氩气氛围的退火炉中进行退火处理，快速升温至750℃，持温15s；
通入流速为80SLM的N 2，继续升温至1200℃，持温15s；
以95℃/s的速度降温至1090℃，停止供应N 2；
氩气氛围下继续升温至1300℃，持温20s，以100℃/s的速度降温至室温，由此消除了硅片中的B-swirl，得到完美晶体的硅片。
分别对上述不经过退火处理和经过退火处理的硅片经过铜饰法进行检测，测试结果为：不经过退火处理的硅片的B-swirl图中的B-swirl区内有白点，代表晶片内有B-swirl缺陷；经过退火处理的硅片的B-swirl图中的B-swirl区内没有白点，代表该处没有形成铜沉淀，即该处是无缺陷的完美区。可见，经过退火处理后，消除了晶片内的缺陷。该实施例的检测图片与实施例1和2相似，在此不再重复放置。
对比例1
该对比例中，第四预设温度为1230℃，其他内容均与实施例1相同。分别对不经过退火处理和经过退火处理的硅片经过铜饰法进行检测，测试结果为测试结果如图6和图7所示，其中图6为不经过退火处理的硅片的B-swirl图，图7为经过退火处理的硅片的B-swirl图。图6中箭头所指区域为B-swirl区域，该区域内有白点，代表晶片内有B-swirl缺陷。图7中箭头所指区域为B-swirl区域，该区域内有白点，代表晶片内有B-swirl缺陷。可能是第四段预设温度过低导致间隙硅原子无法完成及时外扩散及与近表面高浓度空位复合湮灭。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (13)

  1. 一种消除间隙型缺陷B-swirl的方法，其中，包括：
    (1)惰性氛围下，将具有间隙型缺陷B-swirl的单晶硅片升温至第一预设温度，保温，以便消除所述硅片内部的热施主；
    (2)氮气氛围下，将步骤(1)得到的所述硅片升温至第二预设温度，保温，以便在所述硅片的近表面形成空位区；
    (3)将步骤(2)得到的所述硅片降温至第三预设温度，停止氮气氛围，以便将所述空位区的空位保留在所述硅片的近表面；
    (4)惰性氛围下，步骤(3)得到的所述硅片升温至第四预设温度，保温，以便使所述硅片内部自间隙硅原子向外扩散，与近表面的所述空位复合湮灭。
  2. 根据权利要求1所述的方法，其中，在步骤(1)中，所述第一预设温度为700-800℃，所述保温时间为5-25s。
  3. 根据权利要求1或2所述的方法，其中，在步骤(2)中，所述第二预设温度为1150℃-1200℃，所述保温时间为10-30s。
  4. 根据权利要求1-3中任一项所述的方法，其中，在步骤(2)中，所述氮气的流量为50-100SLM。
  5. 根据权利要求1-4中任一项所述的方法，其中，在步骤(2)中，所述近表面为距离所述硅片表面0-100μm的区域。
  6. 根据权利要求1-5中任一项所述的方法，其中，在步骤(3)中，所述第三预设温度为1000-1100℃。
  7. 根据权利要求1-6中任一项所述的方法，其中，在步骤(3)中，所述降温的速率为50-100℃/s。
  8. 根据权利要求1-7中任一项所述的方法，其中，步骤(3)得到的所述硅片的近表面的空位浓度为10 4-10 8cm -3。
  9. 根据权利要求1-8中任一项所述的方法，其中，步骤(3)得到的所述硅片的近表面的空位浓度为A 1×10 4cm -3，其中，1≤A 1<10，且A 1∈实数，步骤(3)的降温速率为50-65℃/s，步骤(2)中的所述第二预设温度为1150℃-1160℃，步骤(2)中的所述氮气的流量为50-100SLM；
    或，步骤(3)得到的所述硅片的近表面的空位浓度为A 2×10 5cm -3，其中，1≤A 2<10，且A 2∈实数，步骤(3)的降温速率为65-75℃/s，步骤(2)中的所述第二预设温度为1160℃-1190℃，步骤(2)中的所述氮气的流量为50-100SLM；
    或，步骤(3)得到的所述硅片的近表面的空位浓度为A 3×10 6cm -3，其中，1≤A 3<10，且A 3∈实数，步骤(3)的降温速率为75-85℃/s，步骤(2)中的所述第二预设温度为1160℃-1190℃，步骤(2)中的所述氮气的流量为50-100SLM；
    或，步骤(3)得到的所述硅片的近表面的空位浓度为A 4×10 7cm -3，其中，1≤A 4<10，且A 4∈实数，步骤(3)的降温速率为85-95℃/s，步骤(2)中的所述第二预设温度为1160℃-1190℃，步骤(2)中的所述氮气的流量为50-100SLM；
    或，步骤(3)得到的所述硅片的近表面的空位浓度为A 5×10 8cm -3，其中，1≤A 5<10，且A 5∈实数，步骤(3)的降温速率为95-100℃/s，步骤(2)中的所述第二预设温度为1190℃-1200℃，步骤(2)中的所述氮气的流量为50-100SLM。
  10. 根据权利要求1-9中任一项所述的方法，其中，在步骤(4)中，所述第四预设温度为1250-1300℃，所述保温时间为10-30s。
  11. 根据权利要求1-10中任一项所述的方法，其中，在步骤(1)和步骤(4)中，所述惰性氛围各自独立地为氩气氛围。
  12. 一种硅片，其中，所述硅片是采用权利要求1-11中任一项所述方法处理得到的。
  13. 一种电子器件，其中，所述电子器件具有权利要求1-11中任一项所述方法处理得到的硅片或权利要求12所述硅片。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01148800A (ja) * 1987-12-04 1989-06-12 Kyushu Electron Metal Co Ltd 半導体結晶基板の改善方法
US20030089967A1 (en) * 2001-11-12 2003-05-15 Young-Hee Mun Silicon wafer and fabricating method therefor
CN103820862A (zh) * 2012-11-16 2014-05-28 有研半导体材料股份有限公司 一种高温退火硅片的制备方法
CN104762656A (zh) * 2014-01-02 2015-07-08 浙江大学 大直径直拉硅片的一种内吸杂工艺
CN106917143A (zh) * 2015-12-25 2017-07-04 有研半导体材料有限公司 一种改善硅片内部氧沉淀及获得表面洁净区的方法
CN114182355A (zh) * 2021-11-30 2022-03-15 徐州鑫晶半导体科技有限公司 消除间隙型缺陷B-swirl的方法、硅片及电子器件

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006261632A (ja) * 2005-02-18 2006-09-28 Sumco Corp シリコンウェーハの熱処理方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01148800A (ja) * 1987-12-04 1989-06-12 Kyushu Electron Metal Co Ltd 半導体結晶基板の改善方法
US20030089967A1 (en) * 2001-11-12 2003-05-15 Young-Hee Mun Silicon wafer and fabricating method therefor
CN103820862A (zh) * 2012-11-16 2014-05-28 有研半导体材料股份有限公司 一种高温退火硅片的制备方法
CN104762656A (zh) * 2014-01-02 2015-07-08 浙江大学 大直径直拉硅片的一种内吸杂工艺
CN106917143A (zh) * 2015-12-25 2017-07-04 有研半导体材料有限公司 一种改善硅片内部氧沉淀及获得表面洁净区的方法
CN114182355A (zh) * 2021-11-30 2022-03-15 徐州鑫晶半导体科技有限公司 消除间隙型缺陷B-swirl的方法、硅片及电子器件

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