WO2023021589A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023021589A1
WO2023021589A1 PCT/JP2021/030097 JP2021030097W WO2023021589A1 WO 2023021589 A1 WO2023021589 A1 WO 2023021589A1 JP 2021030097 W JP2021030097 W JP 2021030097W WO 2023021589 A1 WO2023021589 A1 WO 2023021589A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
semiconductor element
semiconductor
lead electrode
sealing resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/030097
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English (en)
French (fr)
Japanese (ja)
Inventor
省二 斉藤
誠一郎 猪ノ口
太志 佐々木
宏哉 山内
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Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to PCT/JP2021/030097 priority Critical patent/WO2023021589A1/ja
Priority to DE112021008118.7T priority patent/DE112021008118T5/de
Priority to JP2023542072A priority patent/JP7604083B2/ja
Priority to US18/560,567 priority patent/US20240258188A1/en
Priority to CN202180101526.7A priority patent/CN117836928A/zh
Publication of WO2023021589A1 publication Critical patent/WO2023021589A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07354—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/327—Multiple die-attach connectors having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/347—Dispositions of multiple die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H10W74/476—Organic materials comprising silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/755—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a laterally-adjacent insulating package substrate, interpose or RDL

Definitions

  • the present disclosure relates to semiconductor devices.
  • a structure in which a semiconductor element and lead electrode terminals electrically connected to the semiconductor element are sealed with a sealing resin In such a semiconductor device, when a thermal cycle occurs due to repeated operation and non-operation of the semiconductor element, stress is generated in the sealing resin due to the difference in linear expansion coefficient between the lead electrode terminals and the sealing resin. Due to this stress, cracks extending from the ends of the lead electrode terminals and reaching the semiconductor element may occur in the sealing resin.
  • Patent Literature 1 proposes a technique of using a lead electrode terminal having a special shape in order to reduce the stress of a sealing resin that accompanies expansion and contraction of the lead electrode terminal.
  • the present disclosure has been made in view of the problems described above, and aims to provide a technique capable of suppressing cracks reaching a semiconductor element.
  • a semiconductor device includes a semiconductor element, an extended portion separated from an upper surface of the semiconductor element, a lead electrode terminal joined to the semiconductor element, and a first lead electrode terminal sealing the lead electrode terminal. a sealing member; and an intervening member provided between an end portion of the extending portion in the extending direction and the semiconductor element, and having an interface with the first sealing member under the end portion.
  • the intermediate member is provided between the end in the extending direction of the lead electrode terminal and the semiconductor element and has an interface with the first sealing member under the end. According to such a configuration, cracks reaching the semiconductor element can be suppressed.
  • FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to a first embodiment
  • FIG. 2 is a cross-sectional view showing the configuration of a related semiconductor device
  • FIG. 2 is a cross-sectional view showing a configuration of part of a related semiconductor device
  • FIG. 1 is a cross-sectional view showing a configuration of part of a semiconductor device according to a first embodiment
  • FIG. 10 is a cross-sectional view showing a configuration of part of a semiconductor device according to a second embodiment
  • FIG. 11 is a cross-sectional view showing a configuration of part of a semiconductor device according to a third embodiment
  • FIG. 11 is a top view showing a configuration of part of a semiconductor device according to a third embodiment
  • FIG. 11 is a cross-sectional view showing a configuration of part of a semiconductor device according to a fourth embodiment;
  • FIG. 11 is a cross-sectional view showing a configuration of part of a semiconductor device according to a fifth embodiment;
  • FIG. 21 is a cross-sectional view showing a configuration of part of a semiconductor device according to a sixth embodiment;
  • FIG. 21 is a cross-sectional view showing a configuration of part of a semiconductor device according to a seventh embodiment;
  • FIG. 21 is a cross-sectional view showing a configuration of part of a semiconductor device according to an eighth embodiment;
  • FIG. 21 is a cross-sectional view showing a configuration of part of a semiconductor device according to a ninth embodiment;
  • FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment.
  • the semiconductor device in FIG. 1 may be an inverter or converter that controls a motor of an electric vehicle or a train, or may be a device other than these.
  • the semiconductor device of FIG. 1 includes an insulating substrate 1, a fin 2, a semiconductor element 3, a lead electrode terminal 4, a signal terminal 5, a case 6, a sealing resin 7 as a first sealing member, a second 2 and a sealing resin 8a which is a sealing member.
  • a conductive pattern 1 a is provided on the lower surface of the insulating substrate 1
  • a conductive pattern 1 b is provided on the upper surface of the insulating substrate 1 .
  • the fin 2 is joined to the conductive pattern 1a by a joining member 11a such as solder or brazing material.
  • the semiconductor element 3 is joined to the conductive pattern 1b by a joining member 11b such as solder or brazing material.
  • the semiconductor element 3 includes, for example, semiconductor switching elements such as IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or diodes such as PND (PN junction Diode) and SBD (Schottky Barrier Diode).
  • semiconductor switching elements such as IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or diodes such as PND (PN junction Diode) and SBD (Schottky Barrier Diode).
  • the material of the semiconductor element 3 is general silicon (Si), but the material is not limited to this as will be described later.
  • the number of the semiconductor elements 3 is two in the first embodiment, the number may be one or more.
  • the lead electrode terminal 4 is a plate-shaped member made of a metal material such as copper, and is joined to the semiconductor element 3 .
  • the lead electrode terminal 4 has an extended portion extending along the upper surface of the semiconductor element 3 , and the extended portion is separated from the upper surface of the semiconductor element 3 .
  • the extending portion of the lead electrode terminal 4 is joined to the semiconductor element 3, but the present invention is not limited to this. In some cases, the projecting portion may be bonded to the semiconductor element 3 .
  • the lead electrode terminal 4 is joined to the semiconductor element 3 by the joining member 11c such as solder or brazing material, but may be directly joined to the semiconductor element 3, for example.
  • the signal terminals 5 are electrically connected to the semiconductor element 3 by wires 12 .
  • the case 6 is an insert case made of, for example, resin, and is provided on the fins 2 to surround the semiconductor element 3 and the like.
  • the case 6 fixes the lead electrode terminal 4 in a state in which an end portion 4a in the extending direction of the extending portion of the lead electrode terminal 4 and an electrode terminal 4b that is an end portion of the lead electrode terminal 4 are exposed. .
  • the case 6 fixes the signal terminal 5 while exposing the end of the signal terminal 5 connected to the wire 12 and the other end.
  • the sealing resin 7 is provided above the space surrounded by the case 6 and seals the lead electrode terminals 4 .
  • the sealing resin 8 a is provided under the space surrounded by the case 6 and seals the semiconductor element 3 .
  • the sealing resin 8a also seals the insulating substrate 1 and the like.
  • Each of the sealing resin 7 and the sealing resin 8a is made of, for example, an epoxy resin.
  • the sealing resin 8a is provided between the end portion 4a of the lead electrode terminal 4 and the semiconductor element 3, and functions as an intermediate member having an interface with the sealing resin 7 under the end portion 4a. .
  • Such an interface is formed, for example, by separately forming the sealing resin 7 and the sealing resin 8a with the same resin under the same manufacturing conditions.
  • the linear expansion coefficient of the sealing resin 8a becomes larger than the linear expansion coefficient of the sealing resin 7.
  • the coefficient of linear expansion of 7 and the coefficient of linear expansion of sealing resin 8a may be the same.
  • FIG. 2 is a cross-sectional view showing the configuration of a semiconductor device related to the semiconductor device according to the first embodiment (hereinafter referred to as "related semiconductor device").
  • the related semiconductor device includes a sealing resin 16 having no interface under the end portion 4a instead of the sealing resin 7 and the sealing resin 8a.
  • the sealing resin 8a is provided between the end portion 4a of the lead electrode terminal 4 and the semiconductor element 3, and functions as an intermediate member having an interface with the sealing resin 7 under the end portion 4a. .
  • the sealing resin 7 and the sealing resin 8a are cracked.
  • the direction of propagation of the crack 18 changes in the direction of the interface (that is, in the horizontal direction) due to the interface between the . Therefore, cracks 18 that reach the semiconductor element 3 can be suppressed, so reliability of the semiconductor device, such as thermal cycle resistance, can be improved.
  • the physical property values of the sealing resin 7 and the physical property values of the sealing resin 8a may be different from each other.
  • the physical property values are, for example, linear expansion coefficient and mechanical strength.
  • the difference between the linear expansion coefficient of the sealing resin 7 and the linear expansion coefficient of the lead electrode terminal 4 is the same as the linear expansion coefficient of the sealing resin 8a and the linear expansion coefficient of the lead electrode terminal 4. may be smaller than the difference between That is, the coefficient of linear expansion of the sealing resin 7 may be close to the coefficient of linear expansion of the lead electrode terminal 4 . With such a configuration, it is possible to suppress the occurrence of cracks 18 in the sealing resin 7 adjacent to the end portion 4 a of the lead electrode terminal 4 .
  • the difference between the coefficient of linear expansion of the sealing resin 8 a and the coefficient of linear expansion of the insulating substrate 1 may be smaller than the difference between the coefficient of linear expansion of the sealing resin 7 and the coefficient of linear expansion of the insulating substrate 1 . That is, the coefficient of linear expansion of the sealing resin 8a may be close to the coefficient of linear expansion of the insulating substrate 1 . According to such a configuration, it is possible to suppress the warping deformation of the semiconductor device due to thermal cycles over time and the occurrence of cracks 18 in the sealing resin 8 a adjacent to the insulating substrate 1 .
  • the mechanical strength of the sealing resin 8a may be greater than the mechanical strength of the sealing resin 7. According to such a configuration, it is possible to suppress the occurrence of cracks 18 reaching the semiconductor element 3 in the sealing resin 8a.
  • the material of the sealing resin 8a in Embodiment 1 may be silicone gel. According to such a configuration, even if a crack 18 extending from the end portion 4 a of the lead electrode terminal 4 occurs in the sealing resin 7 , the crack 18 reaching the semiconductor element 3 can be suppressed by the silicone gel. Therefore, reliability of the semiconductor device such as thermal cycle resistance can be improved.
  • FIG. 5 is a cross-sectional view showing the configuration of part of the semiconductor device according to the second embodiment.
  • the sealing resin 8a described in the first embodiment is replaced by molding resin 8b formed by molding.
  • FIG. 5 shows that the molding resin 8b is provided along the outer periphery of the semiconductor element 3 and the bonding member 11b without sealing the insulating substrate 1 as traces formed by molding.
  • a resin formed by molding, such as the molding resin 8b, is generally a high hardness resin.
  • the sealing resin 8a is the molding resin 8b. According to such a configuration, as in the first embodiment, cracks 18 propagate in the interface direction due to the interface between the sealing resin 7 and the molding resin 8b. Cracks 18 can be suppressed.
  • the molding resin 8b is a high-hardness resin, cracks 18 reaching the semiconductor element 3 can be further suppressed. In addition, since the molding resin 8b does not seal the insulating substrate 1, cracks 18 in the molding resin 8b due to thermal expansion of the insulating substrate 1 can be suppressed.
  • FIG. 6 is a cross-sectional view showing the configuration of part of the semiconductor device according to the third embodiment.
  • the configuration of the third embodiment is the same as that of the first embodiment, except that the sealing resin 8a is replaced with a stress buffering frame 8c.
  • the stress buffering frame 8c is a plate-like member made of resin or the like, which is provided apart from the lead electrode terminals 4 and the semiconductor element 3.
  • the stress buffering frame 8c is provided between the end portion 4a of the lead electrode terminal 4 and the semiconductor element 3, and functions as an intervening member having an interface with the sealing resin 7 under the end portion 4a. do.
  • the sealing resin 7 seals not only the lead electrode terminals 4 but also the semiconductor element 3 and the stress buffering frame 8c.
  • FIG. 7 is a top view showing the lead electrode terminal 4 and the stress buffering frame 8c.
  • the stress buffering frame 8c is preferably provided with a structure such as a lattice structure having holes 8c1 in FIG. 7, through which the sealing resin 7 liquefied during manufacturing can easily pass.
  • the sealing resin 7 liquefied during manufacturing can easily reach from the upper side to the lower side of the stress buffering frame 8c in FIG. The gap between can be reduced.
  • the end portion 4a of the lead electrode terminal 4 is positioned inside the contour line of the wire portion 8c2 of the stress buffering frame 8c in plan view. According to such a configuration, cracks 18 reaching the semiconductor element 3 can be suppressed.
  • the molding resin 8b functions as an intervening member like the sealing resin 8a described in the first embodiment. According to such a configuration, as in the first embodiment, the crack 18 propagates in the interface direction due to the interface between the sealing resin 7 and the stress buffering frame 8c. It is possible to suppress the cracks 18 that occur.
  • the stress buffering frame 8c may be integrated with the case 6. According to such a configuration, it is possible to suppress warping deformation of the semiconductor device due to thermal cycles over time. In such a configuration, it is preferable to use a resin having a coefficient of linear expansion close to that of the sealing resin 7 for the stress buffering frame 8c.
  • configuration of the third embodiment may be combined with at least one of the configurations of the first and second embodiments and modified examples 1 and 2 described above.
  • FIG. 8 is a cross-sectional view showing the configuration of part of the semiconductor device according to the fourth embodiment.
  • the semiconductor device according to the fourth embodiment does not include intervening members such as the sealing resin 8a described in the first embodiment.
  • the distance Wa between the semiconductor element 3 and the extended portion of the lead electrode terminal 4 is equal to or greater than the thickness Wb of the extended portion, and the sealing resin 7 is thicker than the semiconductor element. 3 and lead electrode terminals 4 are sealed.
  • FIG. 9 is a cross-sectional view showing the configuration of part of the semiconductor device according to the fifth embodiment.
  • the configuration of the fifth embodiment is similar to the configuration of the first embodiment in which projections 4c are provided on the upper surface side of the ends 4a of the lead electrode terminals 4 in the extending direction.
  • Such a lead electrode terminal 4 is formed, for example, by setting the punching when forming the lead electrode terminal 4 so as to have a sagging surface on the semiconductor element 3 side and a burr surface on the opposite side of the semiconductor element 3. can do.
  • configuration of the fifth embodiment may be combined with the configuration of at least one of the first to fourth embodiments and modified examples 1 and 2 described above.
  • FIG. 10 is a sectional view showing the configuration of part of the semiconductor device according to the sixth embodiment.
  • the configuration of the sixth embodiment is similar to the configuration of the first embodiment in which the extending direction of the extending portions of the lead electrode terminals 4 is inclined with respect to the upper surface of the semiconductor element 3 . That is, the angle between the extending direction of the extending portion of the lead electrode terminal 4 and the in-plane direction of the semiconductor element 3 is larger than 0 degrees.
  • FIG. 11 is a cross-sectional view showing the configuration of part of the semiconductor device according to the seventh embodiment.
  • the configuration of the seventh embodiment is the same as that of the first embodiment except that the sealing resin 8a is replaced with a buffer layer 8d.
  • the buffer layer 8 d is provided on the upper surface of the semiconductor element 3 .
  • the buffer layer 8d is provided between the end portion 4a of the lead electrode terminal 4 and the semiconductor element 3, and functions as an intervening member having an interface with the sealing resin 7 under the end portion 4a.
  • the sealing resin 7 seals not only the lead electrode terminals 4 but also the semiconductor element 3 and the buffer layer 8d.
  • the buffer layer 8d functions as an intervening member like the sealing resin 8a described in the first embodiment. According to such a configuration, as in the first embodiment, since the crack 18 propagates in the interface direction due to the interface between the sealing resin 7 and the buffer layer 8 d, the crack reaching the semiconductor element 3 is prevented from reaching the semiconductor element 3 . 18 can be suppressed.
  • the buffer layer 8d is preferably made of a material having a lower hardness (eg, Vickers hardness) than the sealing resin 7, such as a polyimide material. With such a configuration, the buffer layer 8d can absorb the stress from the sealing resin 7, so that the reliability of the semiconductor device, such as the thermal cycle resistance, can be improved.
  • a material having a lower hardness eg, Vickers hardness
  • the buffer layer 8d can absorb the stress from the sealing resin 7, so that the reliability of the semiconductor device, such as the thermal cycle resistance, can be improved.
  • configuration of the seventh embodiment may be combined with the configuration of at least one of the first to sixth embodiments and modified examples 1 and 2 described above.
  • FIG. 12 is a cross-sectional view showing the configuration of part of the semiconductor device according to the eighth embodiment.
  • the sealing resin 8a is removed from the configuration of the first embodiment.
  • the taper angle of the joining member 11c joining the semiconductor element 3 and the lead electrode terminal 4 is relatively large.
  • at least part of the bonding member 11c is provided between the end portion 4a of the lead electrode terminal 4 and the semiconductor element 3, and has an interface with the sealing resin 7 below the end portion 4a. It functions as an intervening member.
  • the sealing resin 7 seals not only the lead electrode terminals 4 but also the semiconductor element 3 and the bonding member 11c.
  • the joining member 11c functions as an intervening member like the sealing resin 8a described in the first embodiment.
  • the crack 18 progresses in the direction of the interface due to the interface between the sealing resin 7 and the bonding member 11c, and the distance until the crack 18 reaches the semiconductor element 3 becomes longer. , cracks 18 reaching the semiconductor element 3 can be suppressed.
  • the configuration of the eighth embodiment may be combined with at least one of the configurations of the first to seventh embodiments and modified examples 1 and 2 described above.
  • FIG. 13 is a cross-sectional view showing the configuration of part of the semiconductor device according to the ninth embodiment.
  • the configuration of the ninth embodiment is the same as that of the fourth embodiment (see FIG. 8) in which the region 3a of the semiconductor element 3 immediately below the end portion 4a is a non-conducting region.
  • the non-energized area is an area where the semiconductor element 3 can maintain normal operation even if the crack 18 reaches it, and includes, for example, an area where a temperature sensor is provided and an insulating area.
  • the semiconductor element 3 since the region 3a of the semiconductor element 3 immediately below the end portion 4a is a non-conducting region, even if the crack 18 reaches the semiconductor element 3, the semiconductor element 3 can operate normally. can.
  • the semiconductor element 3 may be configured to perform a retraction operation when a defect in the region 3a is detected due to the arrival of the crack 18 or the like. According to such a configuration, it is possible to suppress unintended sudden stoppage of the semiconductor element 3 due to a defect in the region 3a.
  • the material of the semiconductor element 3 may be a wide bandgap semiconductor.
  • Wide bandgap semiconductors are, for example, silicon carbide (SiC), gallium nitride (GaN), or diamond.
  • the semiconductor element 3 made of a wide bandgap semiconductor has higher hardness (eg, Vickers hardness) than the semiconductor element 3 made of silicon.
  • hardness eg, Vickers hardness
  • silicon carbide has a hardness of about 23 GPa
  • silicon has a hardness of about 10 GPa
  • the former is about 2.3 times as hard as the latter. Therefore, by using a wide bandgap semiconductor as the material of the semiconductor element 3, the stress resistance against the progress of the crack 18 can be enhanced.
  • 3 semiconductor element 3a region, 4 lead electrode terminal, 4a end, 4c projection, 7, 8a sealing resin, 8b molding resin, 8c stress buffering frame, 8d buffer layer, 11c joining member.

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Physics & Mathematics (AREA)
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PCT/JP2021/030097 2021-08-18 2021-08-18 半導体装置 Ceased WO2023021589A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/JP2021/030097 WO2023021589A1 (ja) 2021-08-18 2021-08-18 半導体装置
DE112021008118.7T DE112021008118T5 (de) 2021-08-18 2021-08-18 Halbleitervorrichtung
JP2023542072A JP7604083B2 (ja) 2021-08-18 2021-08-18 半導体装置
US18/560,567 US20240258188A1 (en) 2021-08-18 2021-08-18 Semiconductor device
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JP2010219420A (ja) * 2009-03-18 2010-09-30 Fuji Electric Systems Co Ltd 半導体装置
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