WO2022227334A1 - 半导体结构的制备方法、测量方法及半导体结构 - Google Patents

半导体结构的制备方法、测量方法及半导体结构 Download PDF

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WO2022227334A1
WO2022227334A1 PCT/CN2021/111569 CN2021111569W WO2022227334A1 WO 2022227334 A1 WO2022227334 A1 WO 2022227334A1 CN 2021111569 W CN2021111569 W CN 2021111569W WO 2022227334 A1 WO2022227334 A1 WO 2022227334A1
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conductive layer
gate
width
layer
semiconductor structure
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PCT/CN2021/111569
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English (en)
French (fr)
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王方方
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长鑫存储技术有限公司
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Priority to US17/647,654 priority Critical patent/US20220352040A1/en
Publication of WO2022227334A1 publication Critical patent/WO2022227334A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a preparation method, a measurement method and a semiconductor structure of a semiconductor structure.
  • DRAM dynamic random access memory
  • the dynamic random access memory usually includes a substrate and a trench arranged in the substrate, a barrier layer is arranged on the inner wall of the trench, the barrier layer surrounds a gate trench, a gate is arranged in the gate trench, and the top surface of the gate is low on the top surface of the base.
  • the size of the trench is also reduced, thereby reducing the width of the gate, which affects the storage performance of the dynamic random access memory.
  • a first aspect of the embodiments of the present application provides a method for fabricating a semiconductor structure, which includes:
  • a gate structure is formed in each of the gate trenches, and the gate structure includes a barrier layer and a conductive layer that are stacked in sequence, the barrier layer is in contact with the bottom wall of the gate trench, and the conductive layer
  • the material includes polysilicon.
  • a second aspect of the embodiments of the present application provides a semiconductor structure, comprising: a substrate and a plurality of gate trenches arranged in the substrate at intervals, each of the gate trenches is provided with a gate structure, the The gate structure includes a barrier layer and a conductive layer which are stacked in sequence, the barrier layer is in contact with the bottom wall of the gate trench, and the material of the conductive layer includes polysilicon.
  • a third aspect of the embodiments of the present application provides a method for measuring a semiconductor structure, the measuring method comprising:
  • a semiconductor structure to be tested includes a substrate and a plurality of gate trenches arranged at intervals in the substrate, each of the gate trenches is provided with a gate structure, the gate structure It includes stacking a barrier layer and a conductive layer in sequence, the barrier layer is in contact with the bottom wall of the gate trench, and the material of the conductive layer includes polysilicon;
  • the mask layer comprising a plurality of mask strips arranged at intervals, each of the mask strips is located between the adjacent gate trenches;
  • the semiconductor structure to be tested, with the mask strip formed thereon, is transferred into a photoelectron spectroscopy apparatus for measuring the concentration of dopant atoms in the conductive layer to obtain a measure of the dopant atom concentration.
  • the actual value of the dopant atom concentration in the conductive layer is determined according to the theoretical value and correction coefficient of the dopant atom concentration in the conductive layer.
  • the width of the conductive layer is the same as that of the gate electrode.
  • the widths of the trenches are equal.
  • the width of the conductive layer can be increased to ensure the conductivity of the conductive layer, and on the other hand, the width of the conductive layer can be increased.
  • the width of the gate trench can be reduced, so as to facilitate the development of the semiconductor structure in the direction of integration.
  • FIG. 1 is a schematic diagram of a semiconductor structure provided in the related art
  • FIG. 2 is a process flow diagram of a method for preparing a semiconductor structure provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of forming a gate trench in a method for fabricating a semiconductor structure provided by an embodiment of the present application;
  • FIG. 4 is a schematic structural diagram of forming an initial gate oxide layer in a method for fabricating a semiconductor structure provided by an embodiment of the present application;
  • FIG. 5 is a schematic structural diagram of forming a gate oxide layer in a method for fabricating a semiconductor structure provided by an embodiment of the present application
  • FIG. 6 is a schematic structural diagram of forming an initial barrier layer in a method for preparing a semiconductor structure provided by an embodiment of the present application
  • FIG. 7 is a schematic structural diagram of forming a barrier layer in a method for preparing a semiconductor structure provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of forming an initial conductive layer in a method for preparing a semiconductor structure provided by an embodiment of the present application;
  • FIG. 9 is a schematic structural diagram of forming a conductive layer in a method for preparing a semiconductor structure provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of forming a dielectric layer in a method for preparing a semiconductor structure provided by an embodiment of the present application;
  • FIG. 11 is a flowchart of a method for testing a semiconductor structure provided by an embodiment of the present application.
  • FIG. 13 is a diagram of a test light spot in a method for testing a semiconductor structure provided by an embodiment of the present application.
  • 311 Initial barrier layer
  • 32 Conductive layer
  • the dynamic random access memory usually includes a substrate and a trench arranged in the substrate, a barrier layer is arranged on the inner wall of the trench, the barrier layer surrounds a gate trench, a gate is arranged in the gate trench, and the top surface of the gate is low On the top surface of the substrate, as the width of the gate trench becomes smaller, the width of the gate also becomes smaller, which affects the storage performance of the dynamic random access memory.
  • the embodiments of the present application provide a method for preparing a semiconductor structure, a method for measuring and a semiconductor structure.
  • the width of the layer is equal to the width of the gate trench.
  • the width of the conductive layer can be increased to ensure electrical conductivity.
  • the width of the gate trench can be reduced, so as to facilitate the development of the semiconductor structure towards integration.
  • This embodiment does not limit the semiconductor structure.
  • the following will take the semiconductor structure as a dynamic random access memory (DRAM) as an example for introduction, but this embodiment is not limited to this, and the semiconductor structure in this embodiment may also be other structures .
  • DRAM dynamic random access memory
  • a method for preparing a semiconductor structure includes the following steps:
  • Step S100 Provide a substrate.
  • the substrate 10 is used as a supporting member of the memory to support other components disposed thereon, wherein the substrate 10 can be made of a semiconductor material, and the semiconductor material can be silicon, germanium, silicon germanium One or more of compounds and silicon carbon compounds.
  • Step S200 forming a plurality of gate trenches arranged at intervals on the substrate.
  • a photoresist layer can be formed on the substrate 10, and the photoresist layer can be patterned by exposing, developing or etching to form a plurality of openings in the photoresist layer, and then using an etching solution or etching The gas removes the substrate exposed in each opening to form a plurality of gate trenches 11 in the substrate, and the plurality of gate trenches 11 are spaced along a first direction, wherein the first direction may be a horizontal direction, that is, FIG. 3 in the X direction.
  • the widths of the gate trenches 11 along the first direction may be equal or unequal. When the widths of the gate trenches are not equal, the width of the gate trenches may be defined by controlling the size of each opening.
  • the widths of two adjacent gate trenches 11 may be unequal.
  • the plurality of gate trenches 11 are divided into several first gate trenches. Polar trenches 111 and several second gate trenches 112, along the first direction, several first gate trenches 111 and several second gate trenches 112 are alternately arranged, and the first gate trenches 111 and the width of the second gate trench 112 are not equal.
  • the width of the first gate trench 111 is smaller, and the width of the second gate trench 112 is larger, so that the gate trenches are arranged in a trend of small size and large size along the first direction.
  • the above arrangement can effectively utilize the area of the wafer and improve the storage performance of the semiconductor structure.
  • Step S300 forming a gate structure in each gate trench, the gate structure includes sequentially stacking a barrier layer and a conductive layer, the barrier layer is in contact with the bottom wall of the gate trench, and the material of the conductive layer includes polysilicon.
  • a gate oxide layer 20 needs to be formed on the inner wall of each gate trench, and the gate oxide layer 20 is used to realize the gate structure. Insulation arrangement between 30 and substrate 10 .
  • an atomic layer deposition process may be used to form an initial gate oxide layer 21 on the inner wall of each gate trench 11 , and the initial gate oxide layer 21 extends to the outside of the gate trench 11 , and Overlay on the top surface of the substrate 10 .
  • the initial gate oxide layer 21 located on the substrate 10 is removed by an etching solution or an etching gas, the initial gate oxide layer 21 located in the gate trench 11 is retained, and the remaining initial gate oxide layer 21 is retained.
  • the layer 21 constitutes the gate oxide layer 20, wherein the material of the gate oxide layer 20 may include silicon oxide or the like.
  • the gate structure 30 is formed in the area surrounded by the gate oxide layer 20, and the specific process steps are as follows:
  • an initial barrier layer 311 is formed in each gate trench 11 , and the initial barrier layer 311 fills the gate trench 11 , that is, a chemical vapor deposition process or a physical vapor deposition process can be used in the gate trenches
  • the trench is filled with the initial barrier layer 311 .
  • the initial barrier layer 311 in the portion located in the gate trench 11 is removed by an etching solution or an etching gas, and the remaining initial barrier layer 311 constitutes a barrier layer 31.
  • the material of the barrier layer 31 may include a conductive material such as titanium nitride. While preventing the penetration between the conductive material and the substrate in the gate structure, the titanium nitride also has conductivity and ensures the performance of the semiconductor structure.
  • an initial conductive layer 321 is formed on the barrier layer 31 by a chemical vapor deposition process or a physical vapor deposition process, and the initial conductive layer 321 fills the gate trench located above the barrier layer 31 . 11.
  • the initial conductive layer 321 in the portion located in the gate trench 11 is removed by an etching solution or an etching gas, and the remaining initial conductive layer 321 is formed into the conductive layer 32 , wherein the conductive layer 32 is
  • the material of the layer 32 may include polysilicon.
  • the sidewall of the conductive layer is in contact with the inner wall of the gate trench, that is, along the first direction, the width of the conductive layer is equal to the width of the gate trench, which is different from the gate oxide layer, the barrier layer and the gate oxide layer in the related art.
  • the width of the conductive layer can be increased to ensure the conductivity of the conductive layer;
  • the width of the pole trench is to facilitate the development of the semiconductor structure towards integration.
  • the thickness of the conductive layer 32 accounts for 1/4-1/2 of the depth of the gate trench 11. If the ratio of the thickness of the conductive layer 32 to the depth of the gate trench 11 is less than 1:4, then The thickness of the conductive layer will be reduced, thereby reducing the conductivity of the conductive layer. If the ratio of the thickness of the conductive layer 32 to the depth of the gate trench 11 is greater than 1:2, the height of the conductive layer will be increased, and it is easy to make the gate structure and the gate structure. Other devices disposed on the substrate are electrically connected, which increases the risk of leakage current of the gate structure and reduces the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the conductive layer and the depth of the gate trench are limited to ensure that both The conductivity of the conductive layer should also ensure the performance of the semiconductor structure.
  • the preparation method further includes: forming a dielectric layer 40 on the conductive layer 32, that is, using a chemical vapor deposition process or a physical vapor phase In the deposition process, a dielectric layer 40 is formed in the gate trench 11 above the conductive layer 32 , and the dielectric layer 40 fills the gate trench 11 above the conductive layer 32 , so that the top surface of the dielectric layer 40 is connected to the substrate 10 the top surface is flush.
  • the insulating arrangement between the gate structure and other devices arranged on the substrate is realized by the arrangement of the dielectric layer, wherein the material of the medium layer may include silicon nitride.
  • an embodiment of the present application further provides a semiconductor structure, including a substrate 10 and a plurality of gate trenches 11 arranged in the substrate 10 at intervals, and each gate trench 11 is provided with a gate electrode Structure 30, the gate structure 30 includes a barrier layer 31 and a conductive layer 32 stacked in sequence, the barrier layer 31 is in contact with the bottom wall of the gate trench 11, and the material of the conductive layer 32 includes polysilicon.
  • the barrier layer and the conductive layer in the semiconductor structure are usually stacked on the inner wall of the gate trench in sequence. If the size of the semiconductor structure is to be reduced, the width of the gate trench and the conductive layer will be reduced accordingly, affecting the performance of semiconductor structures.
  • the conductive layer is arranged on the barrier layer, and the outer wall of the conductive layer is arranged in close contact with the inner wall of the gate trench.
  • the widths of the gate trenches 11 along the first direction may be equal or unequal, for example, the plurality of gate trenches 11 includes several first gate trenches 111 and several second gate trenches pole trenches 112, and along the first direction, several first gate trenches 111 and several second gate trenches 112 are alternately arranged, and the width of the first gate trenches 111 and the second gate trenches 112 has different widths.
  • the width of the first gate trench is small, the width of the second gate trench is correspondingly large, so that the gate trenches are arranged in a trend of small size and large size along the first direction.
  • such an arrangement can effectively utilize the area of the wafer and improve the storage performance of the semiconductor structure.
  • the semiconductor structure further includes a gate oxide layer 20 , the gate oxide layer 20 is disposed on the inner wall of the gate trench 11 , and the gate oxide layer 20 is used to achieve insulation between the gate structure 30 and the substrate 10 . set up.
  • the semiconductor structure further includes a dielectric layer 40 .
  • the dielectric layer 40 is disposed on the conductive layer and fills the gate trench 11 located above the conductive layer 32 , so that the top surface of the dielectric layer 40 is connected to the bottom surface of the substrate 10 . The top surface is flush.
  • the insulating arrangement between the gate structure and other devices arranged on the substrate is realized by the arrangement of the dielectric layer, wherein the material of the medium layer may include silicon nitride.
  • the material of the conductive layer is usually metal tungsten.
  • the width and depth of the conductive layer need to be tested, and the width and depth of the conductive layer are used to measure the conductivity of the conductive layer.
  • the structure can not only develop towards small-scale integration, but also ensure the conductive performance of the conductive layer.
  • the traditional gate structure can no longer meet the requirements. Therefore, the structure and material of the conductive layer are limited in this embodiment.
  • the material of the conductive layer is improved from conventional metal tungsten to polysilicon, and the barrier layer and the conductive layer are designed to be stacked, so that the sidewall of the conductive layer is in direct contact with the sidewall of the gate trench, that is, the conductive layer.
  • Part of the gate trench is filled, so that the gate structure can not only ensure the conductivity of the conductive layer, but also meet the requirements of small-scale integration.
  • the embodiment of the present application provides a method for measuring a semiconductor structure, the measurement method uses It is used to detect the concentration of dopant atoms in the conductive layer of the semiconductor structure to prevent the concentration of dopant atoms from being too high or too low to affect the performance of the semiconductor structure.
  • polysilicon is a dopant of phosphorus atoms and silicon atoms.
  • concentration of phosphorus atoms the higher the conductivity of the conductive layer. Therefore, this embodiment needs to provide a brand new measurement method for detecting The concentration of phosphorus atoms in the conductive layer is used to measure the performance of the conductive layer by the concentration of phosphorus atoms in the conductive layer.
  • step S10 providing a semiconductor structure to be tested, the semiconductor structure to be tested includes a substrate and a plurality of gate trenches arranged at intervals in the substrate, each gate trench is provided with a gate
  • the gate structure includes a barrier layer and a conductive layer that are stacked in sequence, the barrier layer is in contact with the bottom wall of the gate trench, and the material of the conductive layer includes polysilicon.
  • the semiconductor structure to be tested may refer to FIG. 8 .
  • the conductive layer 32 In order to facilitate the measurement of the concentration of the conductive layer, the conductive layer 32 needs to be exposed in the gate trench 11 .
  • Step S20 forming a mask layer on the substrate, the mask layer includes a plurality of mask strips arranged at intervals, and each mask strip is located between adjacent gate trenches.
  • a photoresist layer with a certain thickness may be coated on the substrate between adjacent gate trenches, and the photoresist layer constitutes a mask strip 50 .
  • the area ratio occupied by the conductive layer can be calculated in the subsequent process, and then the concentration of the conductive layer can be calculated.
  • Step S30 Transfer the semiconductor structure to be tested with the mask strip formed to the measuring equipment, and the measuring equipment is used for measuring the width of the conductive layer and the width of the mask strip.
  • the semiconductor structure to be tested formed with the mask strip is transferred to a CD atomic force microscope or an OCD optical line width measuring device, and the above-mentioned device can measure the width W 1 of the conductive layer and the width W of the mask strip. 2
  • Step S40 transferring the semiconductor structure to be tested on which the mask strip is formed to a photoelectron spectroscopy analysis device, and the photoelectron spectroscopy analysis device is used to measure the concentration of dopant atoms in the conductive layer to obtain a measured value of the concentration of dopant atoms, That is, the semiconductor structure to be tested can be sent to an X-ray photoelectron spectroscopy (XPS for short), which has a test spot 60, and a photoelectron spectroscopy analysis device is used to measure the inside of the test spot.
  • XPS X-ray photoelectron spectroscopy
  • the concentration of dopant atoms, and the test spot can be adjusted according to the actual product to be tested.
  • the test light spot 60 is shown in FIG. 13 .
  • the working principle of the X-ray photoelectron spectrometer is to use X-rays to radiate the semiconductor structure, so that the inner electrons or valence electrons of atoms or molecules in the semiconductor structure are excited and emitted, and the electrons excited by photons are called electrons.
  • X-ray photoelectron spectroscopy can detect the energy and quantity of photoelectrons to obtain the composition of the semiconductor structure and the content of the composition.
  • Step S50 Determine the theoretical value of the dopant atom concentration in the conductive layer according to the width of the conductive layer, the width of the mask strip and the measured value of the dopant atom concentration.
  • W1 is the width of the conductive layer
  • W2 is the width of the mask strip.
  • the dimensions of adjacent gate trenches may be unequal, for example, the plurality of gate trenches include a plurality of first gate trenches and a plurality of second gate trenches, along the first direction , a number of first gate trenches and a number of second gate trenches are alternately arranged at intervals, and the width of the first gate trench and the width of the second gate trench are not equal, correspondingly, a plurality of masks
  • the strip includes several first mask strips and second mask strips, and the widths of the first mask strips and the second mask strips are not equal.
  • the width of the first gate trenches is smaller than the width of the second gate trenches, and the widths of the gate trenches are arranged in a small-sized and large-sized arrangement.
  • the width of the conductive layer in the groove is also smaller than the width of the second gate trench, that is, along the first direction, the width of the conductive layer is arranged in a small-sized and large-sized arrangement.
  • the width of the first mask strip is also smaller than the width of the second mask strip, and the width of the mask strips is arranged in a small-sized and large-sized arrangement.
  • the step of transferring the test semiconductor structure with the mask strips formed to the measuring equipment for measuring the width of the conductive layer and the width of the gate trench includes:
  • the average value of W 21 and W 22 is obtained as the width W 2 of the mask strip.
  • the conductive layer located in the first gate trench may be denoted as the first conductive layer
  • the conductive layer in the second gate trench may be denoted as the second conductive layer
  • Table 1 The specific values of the width of the conductive layer and the width of the mask strip
  • the average value of the width of the first conductive layer and the width of the second conductive layer is used as the width of the conductive layer, and the difference between the width of the first mask strip and the width of the second mask strip is taken as the width of the conductive layer.
  • the average value is used as the width of the mask strip, which can improve the accuracy of the phosphorus atomic concentration test.
  • Step S60 Determine the actual value of the dopant atom concentration in the conductive layer according to the theoretical value and correction coefficient of the dopant atom concentration in the conductive layer.
  • the polysilicon is formed by a chemical vapor deposition process or a physical vapor deposition process. During the deposition process, phosphorus atoms will diffuse to the gate oxide layer, so that the gate oxide layer will be doped with phosphorus atoms.
  • concentration of phosphorus atoms in the test spot as shown in Figure 13, there will be a gate oxide layer in the test spot. Therefore, the concentration of phosphorus atoms in the test spot is detected to be greater than that in the conductive layer, so it is necessary to provide A correction factor by which the actual value of the phosphorus atomic concentration is obtained.
  • the accuracy of the phosphorus atomic concentration obtained by the test method can be ensured, and an accurate theoretical basis can be provided for the design of the semiconductor structure.
  • the method for measuring the semiconductor structure further includes: obtaining the correction coefficient k.
  • a reference wafer is provided, the reference wafer only includes a substrate, a titanium nitride layer and a polysilicon layer stacked on the substrate in sequence, the thickness of the polysilicon layer is equal to the thickness of the conductive layer, and the polysilicon layer is doped Phosphorus atoms, which are doped in the same conditions as the semiconductor structure, are used to simulate the conductive layer.
  • the thickness of the polysilicon layer and the thickness of the conductive layer are between 10 nm and 15 nm.
  • the reference wafer is transported into a photoelectron spectroscopy apparatus for measuring the concentration of dopant atoms in the polysilicon layer in the reference wafer, i.e., the photoelectron spectroscopy is set up to measure the concentration of phosphorus atoms in the polysilicon layer. concentration.
  • the photoelectron spectroscopy analysis device can detect phosphorus atoms on the surface of polysilicon layer.
  • concentration is used as the concentration of phosphorus atoms in the reference wafer, and is referred to as ⁇ reference .
  • the correction coefficient k is determined according to the theoretical value of the concentration of dopant atoms in the conductive layer of the sample and the concentration of dopant atoms in the polysilicon in the reference wafer.
  • the reference wafer can be prepared, and the reference wafer can be placed in the photoelectron spectroscopy analysis equipment together with the semiconductor structure to be inspected.
  • the to-be-detected semiconductor structure is distinguished from other to-be-detected semiconductor structures.
  • the to-be-detected semiconductor structure placed into the photoelectron spectroscopy analysis device together with the reference wafer is called a sample.
  • the photoelectron spectroscopy analysis equipment measured the ⁇ reference of the reference wafer, and the measured value ⁇ sample of the dopant atom concentration in the conductive layer of the sample, and measured the width of the conductive layer in the sample by the method described in the above embodiment W Sample 1 and the width of the mask strip in the sample W sample 2 .
  • the correction coefficient k can be obtained, for example, by the following formula:
  • ⁇ reference represents the concentration of dopant atoms of the reference wafer
  • ⁇ sample represents the measured value of the dopant atom concentration of the sample used to determine the correction factor
  • W sample 1 represents the width of the conductive layer of the sample used to determine the correction factor
  • W Sample 2 represents the width of the mask strip of the sample used in determining the correction factor.
  • the number of samples may be one or multiple.
  • multiple correction coefficients are calculated by the above method, and the multiple The average value of the correction coefficient is used as the final correction coefficient k, which can ensure the accuracy of the correction coefficient k.
  • the concentration of phosphorus atoms in the reference wafer measured by the photoelectron spectrometer is 15.47%, that is, the value of the ⁇ reference is 15.47%.
  • the actual value of the concentration of phosphorus atoms in the conductive layer is determined, which is obtained by the following formula:

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本申请提供一种半导体结构的制备方法、测量方法及半导体结构，涉及半导体技术领域，该半导体结构的制备方法包括提供具有多个栅极沟槽的基底；在每个栅极沟槽内形成栅极结构，栅极结构包括依次层叠设置阻挡层和导电层，阻挡层与栅极沟槽的底壁接触，导电层的材质包括多晶硅。本申请通过使导电层的侧壁与栅极沟槽的内壁接触，即，沿第一方向，导电层的宽度与栅极沟槽的宽度相等，与相关技术中栅氧化层、阻挡层以及导电层依次层叠在栅极沟槽内的技术方案相比，一方面可以增加导电层的宽度，保证导电层的导电性能，另一方面，在保证导电层的导电性能的前提下，可以缩小栅极沟槽的宽度，以便于半导体结构向集成化方向发展。

Description

半导体结构的制备方法、测量方法及半导体结构
本申请要求于2021年04月30日提交中国专利局、申请号为202110484441.3、申请名称为“半导体结构的制备方法、测量方法及半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构的制备方法、测量方法及半导体结构。
背景技术
在半导体制造工艺中，通过需要利用光刻、刻蚀或者沉积等工艺在半导体基底上形成半导体结构，例如，动态随机存储器(Dynamic random access memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。
动态随机存储器通常包括基底以及设置在基底内的沟槽，沟槽的内壁上设置阻挡层，阻挡层围成栅极沟槽，栅极沟槽内设置有栅极，且栅极的顶面低于基底的顶面。
随着动态随机存储器向小型化、集成化的方向发展，使得沟槽的尺寸也随之减小，进而降低栅极的宽度尺寸，影响动态随机存储器的存储性能。
发明内容
本申请实施例的第一方面提供一种半导体结构的制备方法，其包括：
提供基底；
在所述基底上形成间隔设置的多个栅极沟槽；
在每个所述栅极沟槽内形成栅极结构，所述栅极结构包括依次层叠设置阻挡层和导电层，所述阻挡层与所述栅极沟槽的底壁接触，所述导电层的材质包括多晶硅。
本申请实施例的第二方面提供一种半导体结构，包括：基底以及间隔设置在所述基底内的多个栅极沟槽，每个所述栅极沟槽内设有栅极结构，所述栅极结构包括依次层叠设置的阻挡层和导电层，所述阻挡层与所述栅极沟槽的底壁接触，所述导电层的材质包括多晶硅。
本申请实施例的第三方面提供了一种半导体结构的测量方法，所述测量方法包括：
提供待测试半导体结构，所述待测试半导体结构包括基底以及间隔设置在所述基底内的多个栅极沟槽，每个所述栅极沟槽内设置有栅极结构，所述栅极结构包括依次层叠设置阻挡层和导电层，所述阻挡层与所述栅极沟槽的底壁接触，所述导电层的材质包括多晶硅；
在所述基底上形成掩膜层，所述掩膜层包括间隔设置的多个掩膜条，每个所述掩膜条位于相邻的所述栅极沟槽之间；
将形成有掩膜条的待测试的半导体结构传送至量测设备，所述量测设备用于测量所述导电层的宽度以及所述掩膜条的宽度；
将形成有掩膜条的待测试的半导体结构传送至光电子能谱分析设备内，所述光电子能谱分析设备用于测量导电层中掺杂原子的浓度，以获得掺杂原子浓度的测量值。
根据所述导电层的宽度、所述掩膜条的宽度以及所述掺杂原子浓度的测量值，确定所述导电层中所述掺杂原子浓度的理论值；
根据所述导电层中所述掺杂原子浓度的理论值以及修正系数，确定所述导电层中所述掺杂原子浓度的实际值。
本申请实施例所提供的半导体结构的制备方法、测量方法及半导体结构中，通过使导电层的侧壁与栅极沟槽的内壁接触，即，沿第一方向，导电层的宽度与栅极沟槽的宽度相等，与相关技术中栅氧化层、阻挡层以及导电层依次层叠在栅极沟槽内的技术方案相比，一方面可以增加导电层的宽度，保证导电层的导电性能，另一方面，在保证导电层的导电性能的前提下，可以缩小栅极沟槽的宽度，以便于半导体结构向集成化方向发展。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请实施例提供的半导体结构的制备方法、测量方法及半导体结构及所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有 益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
图1为相关技术中提供的半导体结构的示意图；
图2为本申请实施例提供的半导体结构的制备方法的工艺流程图；
图3为本申请实施例提供的半导体结构的制备方法中的形成栅极沟槽的结构示意图；
图4为本申请实施例提供的半导体结构的制备方法中形成初始栅氧化层的结构示意图；
图5为本申请实施例提供的半导体结构的制备方法中形成栅氧化层的结构示意图；
图6为本申请实施例提供的半导体结构的制备方法中形成初始阻挡层的结构示意图；
图7为本申请实施例提供的半导体结构的制备方法中形成阻挡层的结构示意图；
图8为本申请实施例提供的半导体结构的制备方法中形成初始导电层的结构示意图；
图9为本申请实施例提供的半导体结构的制备方法中形成导电层的结构示意图；
图10为本申请实施例提供的半导体结构的制备方法中形成介质层的结构示意图；
图11为本申请实施例提供的半导体结构的测试方法的流程图；
图12为本申请实施例提供的半导体结构的测试方法中的导电层和掩膜层的电镜图；
图13为本申请实施例提供的半导体结构的测试方法中的测试光斑的图。
附图标记：
10：基底；                  11：栅极沟槽；
111：第一栅极沟槽；         112：第二栅极沟槽；
20：栅氧化层；              21：初始栅氧化层；
30：栅极结构；               31：阻挡层；
311：初始阻挡层；            32：导电层；
321：初始导电层；            40：介质层；
50：掩膜条；                 60：测试光斑。
具体实施方式
动态随机存储器通常包括基底以及设置在基底内的沟槽，沟槽的内壁上设置阻挡层，阻挡层围成栅极沟槽，栅极沟槽内设置有栅极，且栅极的顶面低于基底的顶面，随着栅极沟槽的宽度变小，使得栅极的宽度也变小，影响动态随机存储器的存储性能。
基于上述的技术问题，本申请实施例提供了一种半导体结构的制备方法、测量方法及半导体结构，通过使导电层的侧壁与栅极沟槽的内壁接触，即，沿第一方向，导电层的宽度与栅极沟槽的宽度相等，与相关技术中栅氧化层、阻挡层以及导电层依次层叠在栅极沟槽内的技术方案相比，一方面可以增加导电层的宽度，保证导电层的导电性能，另一方面，在保证导电层的导电性能的前提下，可以缩小栅极沟槽的宽度，以便于半导体结构向集成化方向发展。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
实施例一
如图2所示，本申请实施例提供的一种半导体结构的制备方法，包括如下的步骤：
步骤S100：提供基底。
示例性地，如图3所示，基底10作为存储器的支撑部件，用于支撑设在其上的其他部件，其中，基底10可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。
步骤S200：在基底上形成间隔设置的多个栅极沟槽。
示例性地，可以在基底10上形成光刻胶层，并通过曝光、显影或者蚀刻的方式图形化光刻胶层，以在光刻胶层形成多个开口，然后利用刻蚀液或者刻蚀气体去除暴露在每个开口内的基底，以在基底内形成多个栅极沟槽11，多个栅极沟槽11沿第一方向间隔设置，其中，第一方向可以为水平方向，即图3中的X方向。
栅极沟槽11沿第一方向的宽度可以相等，也可以不等，当栅极沟槽的宽度不等时，可以通过控制各个开口的尺寸来限定栅极沟槽的宽度。
示例性地，相邻的两个栅极沟槽11的宽度可以不等，为了便于对栅极沟槽的尺寸进行限定，本实施例中将多个栅极沟槽11划分为数个第一栅极沟槽111和数个第二栅极沟槽112，沿第一方向，数个第一栅极沟槽111和数个第二栅极沟槽112交替设置，且第一栅极沟槽111的宽度和第二栅极沟槽112的宽度不等。
例如，如图3所示，第一栅极沟槽111的宽度较小，第二栅极沟槽112的宽度较大，使得栅极沟槽沿第一方向呈小大小大的趋势进行排布，本实施例通过上述的排布可以有效利用晶圆的面积，提高了半导体结构的存储性能。
步骤S300：在每个栅极沟槽内形成栅极结构，栅极结构包括依次层叠设置阻挡层和导电层，阻挡层与栅极沟槽的底壁接触，导电层的材质包括多晶硅。
示例性地，在每个栅极沟槽内形成栅极结构的步骤之前，还需要在每个栅极沟槽的内壁上形成栅氧化层20，利用栅氧化层20的设置来实现栅极结构30与基底10之间的绝缘设置。
具体地，如图4所示，可以采用原子层沉积工艺在每个栅极沟槽11的内壁上形成初始栅极氧化层21，初始栅氧化层21延伸至栅极沟槽11的外部，并覆盖在基底10的顶面上。
之后，如图5所示，采用刻蚀液或者刻蚀气体去除位于基底10上的初始栅氧化层21，保留位于栅极沟槽11内的初始栅氧化层21，被保留下来的初 始栅氧化层21构成栅氧化层20，其中，栅氧化层20的材质可以包括氧化硅等。
最后，再在栅氧化层20围成的区域内形成栅极结构30，具体的工艺步骤如下：
如图6所示，在每个栅极沟槽11内形成初始阻挡层311，初始阻挡层311填充满栅极沟槽11，即，可以采用化学气相沉积工艺或者物理气相沉积工艺在栅极沟槽内填充满初始阻挡层311。
如图7所示，待形成初始阻挡层311之后，利用刻蚀液或者刻蚀气体去除位于栅极沟槽11内的部分内的初始阻挡层311，被保留下来的初始阻挡层311构成阻挡层31。
阻挡层31的材质可以包括氮化钛等导电材质，氮化钛在阻止栅极结构中导电材料与基底之间发生渗透的同时，也同时具备导电性，保证了半导体结构的性能。
如图8所示，待形成阻挡层31之后，采用化学气相沉积工艺或者物理气相沉积工艺在阻挡层31上形成初始导电层321，初始导电层321填充满位于阻挡层31上方的栅极沟槽11。
如图9所示，之后，利用刻蚀液或者刻蚀气体去除位于栅极沟槽11内的部分内的初始导电层321，被保留下来的初始导电层321构成到导电层32，其中，导电层32的材质可以包括多晶硅。
本实施例通过使导电层的侧壁与栅极沟槽的内壁接触，即，沿第一方向，导电层的宽度与栅极沟槽的宽度相等，与相关技术中栅氧化层、阻挡层以及导电层依次层叠在栅极沟槽内的技术方案相比，一方面可以增加导电层的宽度，保证导电层的导电性能，另一方面，在保证导电层的导电性能的前提下，可以缩小栅极沟槽的宽度，以便于半导体结构向集成化方向发展。
在一些实施例中，导电层32的厚度占栅极沟槽11的深度的1/4-1/2，若导电层32的厚度与栅极沟槽11的深度之比小于1：4，则会降低导电层的厚度，进而降低导电层的导电性能，若导电层32的厚度与栅极沟槽11的深度之比大于1：2，则会增加导电层的高度，容易使栅极结构与设置在基底上的其他器件发生电连接，增加栅极结构的漏电流风险，降低半导体结构的性能，因此，本实施例对导电层的厚度与栅极沟槽的深度进行了限定，既要保证导电层的导电性能，也要保证半导体结构的性能。
如图10所示，在一些实施例中，在栅极沟槽内形成栅极结构的步骤之后，制备方法还包括：在导电层32上形成介质层40，即利用化学气相沉积工艺或者物理气相沉积工艺，在位于导电层32上方的栅极沟槽11内形成介质层40，该介质层40填充满位于导电层32上方的栅极沟槽11，以使介质层40的顶面与基底10的顶面平齐。
本实施例通过介质层的设置，实现对栅极结构与设置在基底上的其他器件之间的绝缘设置，其中，介质层的材质可以包括氮化硅。
实施例二
如图10所示，本申请实施例还提供了一种半导体结构，包括基底10以及间隔设置在基底10内的多个栅极沟槽11，每个栅极沟槽11内均设有栅极结构30，栅极结构30包括依次层叠设置的阻挡层31和导电层32，阻挡层31与栅极沟槽11的底壁接触，导电层32的材质包括多晶硅。
相关技术中，半导体结构中的阻挡层和导电层通常是依次层叠设置在栅极沟槽的内壁上，若是要缩小半导体结构的尺寸，相应地会减少栅极沟槽和导电层的宽度，影响半导体结构的性能。
本实施例所提供的半导体结构，导电层设置在阻挡层上，且导电层的外壁与栅极沟槽的内壁贴合设置，这样在缩小半导体结构的前提下，相对相关技术而言，可以避免过分的降低导电层的宽度，保证了半导体结构的性能，也便于半导体结构向集成化方向发展。
在一些实施例中，栅极沟槽11沿第一方向的宽度可以相等，也可以不等，比如，多个栅极沟槽11包括数个第一栅极沟槽111和数个第二栅极沟槽112，且沿第一方向，数个第一栅极沟槽111和数个第二栅极沟槽112交替设置，且第一栅极沟槽111的宽度和第二栅极沟槽112的宽度不等。
也就是说，若是第一栅极沟槽的宽度较小，相应地第二栅极沟槽的宽度较大，使得栅极沟槽沿第一方向呈小大小大的趋势进行排布，本实施例通过这样的排布可以有效利用晶圆的面积，提高了半导体结构的存储性能。
在一些实施例中，半导体结构还包括栅氧化层20，栅氧化层20设置在栅极沟槽11的内壁上，利用栅氧化层20的设置来实现栅极结构30与基底10之间的绝缘设置。
在一些实施例中，半导体结构还包括介质层40，介质层40设置在导电层上，并填充满位于导电层32上方的栅极沟槽11，以使介质层40的顶 面与基底10的顶面平齐。
本实施例通过介质层的设置，实现对栅极结构与设置在基底上的其他器件之间的绝缘设置，其中，介质层的材质可以包括氮化硅。
实施例三
相关技术中，导电层的材质通常为金属钨，在测试导电层的导电性能时，仅需要测试导电层的宽度和深度，用导电层的宽度和深度来衡量导电层的导电性能，若要半导体结构既能够向小尺寸集成化的发展，也能够保证导电层的导电性能，传统的栅极结构已不能满足要求，因此，本实施例对导电层的结构和材质进行了限定。
示例性地，将导电层的材质从常规的金属钨改进为多晶硅，并将阻挡层和导电层设计为层叠设置，使得导电层的侧壁直接与栅极沟槽的侧壁接触，即导电层填充满部分栅极沟槽，这样栅极结构既能保证导电层的导电性能，也能满足小尺寸集成化的要求。
鉴于本实施例中导电层的材质包括多晶硅，为了保证导电层的导电性能，需要对导电层中掺杂原子的浓度进行测量，本申请实施例提供一种半导体结构的测量方法，该测量方法用于检测半导体结构的导电层中掺杂原子的浓度，防止掺杂原子的浓度过高或者过低而影响半导体结构的性能。
具体地，多晶硅为磷原子和硅原子的掺杂物，磷原子的浓度越高，导电层的导电能力越高，因此，本实施例需要提供一种全新的测量方法，该测量方法用于检测导电层中磷原子的浓度，用导电层中磷原子的浓度来衡量导电层的性能。
示例性地，如图11所示，步骤S10：提供待测试半导体结构，待测试半导体结构包括基底以及间隔设置在基底内的多个栅极沟槽，每个栅极沟槽内设置有栅极结构，栅极结构包括依次层叠设置阻挡层和导电层，阻挡层与栅极沟槽的底壁接触，导电层的材质包括多晶硅。
待测试的半导体结构可以参考图8，为了便于对导电层的浓度进行测量，需要使导电层32暴露在栅极沟槽11内。
步骤S20：在基底上形成掩膜层，掩膜层包括间隔设置的多个掩膜条，每个掩膜条位于相邻的栅极沟槽之间。
示例性地，如图12所示，可以通过在位于相邻的栅极沟槽之间的基底上，涂覆一定厚度的光刻胶层，该光刻胶层构成一个掩膜条50，本实施例 通过掩膜条的设置，可以后续工艺中计算出导电层所占的面积比，进而对导电层的浓度进行计算。
步骤S30：将形成有掩膜条的待测试半导体结构传送至量测设备，量测设备用于测量导电层的宽度以及掩膜条的宽度。
示例性地，将形成有掩膜条的待测试半导体结构传送至CD原子力显微镜或者是OCD光学线宽量测设备中，上述的设备可以测量出导电层的宽度W 1以及掩膜条的宽度W 2
步骤S40：将形成有掩膜条的待测试半导体结构传送至光电子能谱分析设备内，光电子能谱分析设备用于测量导电层中掺杂原子的浓度，以获得掺杂原子浓度的测量值，即，可以将待测试半导体结构传送至X射线光电子能谱仪(X-ray photoelectron spectroscopy，简称XPS)中，该X射线光电子能谱仪具有测试光斑60，利用光电子能谱分析设备测量测试光斑内的掺杂原子的浓度，且该测试光斑可以根据实际需要测试的产品来调整。其中，测试光斑60如图13所示。
需要说明的是，X射线光电子能谱仪的工作原理是利用X射线去辐射半导体结构，使得半导体结构中的原子或者分子的内层电子或者价电子受激发射出来，被光子激发出来的电子称为光电子，X射线光电子能谱仪能够检测到光电子的能量和数量，以获得半导体结构的组成成分以组成成分的含量。
步骤S50：根据导电层的宽度、掩膜条的宽度以及掺杂原子浓度的测量值，确定导电层中掺杂原子浓度的理论值。
示例性地，导电层中掺杂的浓度的理论值ρ 理论通过如下公式得到：
Figure PCTCN2021111569-appb-000001
其中，ρ表示掺杂原子浓度的测量值，W 1表示导电层的宽度，W 2表示掩膜条的宽度。
在一些实施例中，相邻的栅极沟槽的尺寸可以不等，比如，多个栅极沟槽包括数个第一栅极沟槽和数个第二栅极沟槽，沿第一方向，数个第一栅极沟槽和数个第二栅极沟槽交替间隔设置，且第一栅极沟槽的宽度和第二栅极沟槽的宽度不等，相应地，多个掩膜条包括数个第一掩膜条和第二掩膜条，且第一掩膜条和第二掩膜条的宽度不等。
例如，沿第一方向，第一栅极沟槽的宽度小于第二栅极沟槽的宽度，栅极沟槽的宽度呈小大小大的排列方式进行排列，相应地，位于第一栅极沟槽内的导电层的宽度也会小于位于第二栅极沟槽的宽度，即，沿第一方向，导电层的宽度呈小大小大的排列方式进行排列。同时，第一掩膜条的宽度也会小于第二掩膜条的宽度，掩膜条的宽度呈小大小大的排列方式进行排列。
为了保证导电层中磷原子的浓度的理论值的准确性，需要对位于第一栅极沟槽内的导电层和位于第二栅极沟槽内的导电层的宽度求取平均值，相应地，对第一掩膜条的宽度和第二掩膜条的宽度求取平均值，具体地：
将形成有掩膜条的测试半导体结构传送至量测设备述量测设备用于测量导电层的宽度以及栅极沟槽的宽度的步骤中，包括：
测量位于第一栅极沟槽内的导电层的宽度W 11，测量位于第二栅极槽内的导电层的宽度W 12；
获取W 11和W 12的平均值，该平均值作为导电层的宽度W 1；
测量第一掩膜条的宽度W 21，测量第二掩膜条的宽度W 22；
获取W 21和W 22的平均值，该平均值作为掩膜条的宽度W 2。
为了便于对导电层的位置进行描述，可以将位于第一栅极沟槽内的导电层记为第一导电层，位于第二栅极沟槽内的导电层记为第二导电层，其中，导电层和掩膜条的宽度的具体数值如下表所示：
表一 导电层的宽度和掩膜条的宽度的具体数值
Figure PCTCN2021111569-appb-000002
Figure PCTCN2021111569-appb-000003
根据表一可以得知，本实施例将第一导电层的宽度和第二导电层的宽度的平均值作为导电层的宽度，将第一掩膜条的宽度和第二掩膜条的宽度的平均值作为掩膜条的宽度，可以提高磷原子浓度测试的精准度。
步骤S60：根据导电层中掺杂原子浓度的理论值以及修正系数，确定导电层中掺杂原子浓度的实际值。
当导电层的材质为多晶硅时，多晶硅是通过化学气相沉积工艺或者物理气相沉积工艺形成的，在沉积过程中，磷原子会向栅氧化层进行扩散，使得栅氧化层中会掺杂磷原子，在测量测试光斑内的磷原子浓度时，如图13所示，测试光斑内会存在栅氧化层，因此，检测到测试光斑内的磷原子的浓度会大于导电层中的磷原子，所以需要提供一个修正系数，利用该修正系数来得到磷原子浓度的实际值。
本实施例通过修正系数的设置，能够保证测试方法所得到的磷原子浓度的准确性，为半导体结构的设计提供准确的理论依据。
因此，半导体结构的测量方法还包括：获得修正系数k。
示例性地，提供基准晶圆，基准晶圆仅包括衬底以及依次层叠设置在衬底上的氮化钛层和多晶硅层，多晶硅层的厚度与导电层的厚度相等，在多晶硅层中掺杂磷原子，其掺杂条件和半导体结构一样，以此来实现对导电层的模拟。
需要说明的是，在本实施例中，多晶硅层的厚度和导电层的厚度位于10nm到15nm之间。
将基准晶圆传送至光电子能谱分析设备内，光电子能谱分析设备用于测量基准晶圆中多晶硅层中掺杂原子的浓度，即，光电子能谱分析设置用于测量多晶硅层中磷原子的浓度。
由于从厚度0nm-30nm之间，随着厚度的增加，光电子能谱分析设备检测的磷原子的浓度的变化呈类似于直线性，因此，可以将光电子能谱分析设备检测多晶硅层表面的磷原子浓度作为基准晶圆的磷原子的浓度，记为ρ 基准。
将至少一个待检测半导体结构作为样品，根据样品的导电层中掺杂原子浓度的理论值和基准晶圆中多晶硅中掺杂原子的浓度，确定修正系数k。
当需要获得修正系数时，就可以制备基准晶圆，并将该基准晶圆随待检测半导体结构一起放置到光电子能谱分析设备中，为了便于与基准晶圆一起放置到光电子能谱分析设备中的待检测半导体结构，与其他的待检测半导体结构进行区分，本实施例将与基准晶圆一起放置到光电子能谱分析设备中的待检测半导体结构称为样品。
光电子能谱分析设备测量出基准晶圆的ρ 基准，以及样品的导电层中掺杂原子浓度的测量值ρ 样品，并通过上述实施例中记载的方式测量出样品中导电层的宽度W 样品1和样品中掩膜条的宽度W 样品2。
根据上述的数值得到，修正系数k，示例性地，可以采用如下的公式得到：
Figure PCTCN2021111569-appb-000004
其中，ρ 基准表示基准晶圆的掺杂原子的浓度，ρ 样品表示确定修正系数时使用样品的掺杂原子浓度的测量值，W 样品1表示确定修正系数时使用样品的导电层的宽度，W 样品2表示确定修正系数时使用样品的掩膜条的宽度。
需要说明的是，在本实施例中，样品的个数可以为一个，也可以为多个，当样品的个数为多个时，通过上述的方式计算出多个修正系数，并将多个修正系数的平均值，作为最终的修正系数k，这样可以保证修正系数k的准确性。
在本实施例中，利用光电子能谱仪测量出来的基准晶圆的磷原子的浓度为15.47％，即，ρ 基准的数值为15.47％。
以表一中待检测产品的坐标点为(-4，-8)数值作为参考值，计算出W 1/W 1+W 2＝14.28/(14.28+26.59)＝34.9％，并根据ρ 样品的值，得到修正系数为0.88，在以后的测试中以该修正系数作为标准，每次测量产品中的磷 原子的浓度的实际浓度时，都需要与该修正系数进行相乘。
示例性地，根据导电层中磷原子浓度的理论值以及修正系数，确定导电层中磷原子浓度的实际值，通过如下的公式得到：
ρ 实际＝k*ρ 理论
本实施例通过修正系数的设置，可以保证利用上述的测量方法得到每个待测试半导体结构中掺杂原子的准确性，为保证半导体结构的性能提供理论基础。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种半导体结构的制备方法，包括如下步骤：
    提供基底；
    在所述基底上形成间隔设置的多个栅极沟槽；
    在每个所述栅极沟槽内形成栅极结构，所述栅极结构包括依次层叠设置阻挡层和导电层，所述阻挡层与所述栅极沟槽的底壁接触，所述导电层的材质包括多晶硅。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，所述导电层厚度占所述栅极沟槽深度的1/4-1/2。
  3. 根据权利要求2所述的半导体结构的制备方法，其中，在每个所述栅极沟槽内形成栅极结构的步骤包括：
    在每个所述栅极沟槽内形成初始阻挡层，所述初始阻挡层填充满所述栅极沟槽；
    去除位于所述栅极沟槽内的部分厚度的所述初始阻挡层，被保留下来所述初始阻挡层构成所述阻挡层；
    在所述阻挡层上形成初始导电层，所述初始导电层填充满位于所述阻挡层上方的所述栅极沟槽；
    去除部分厚度的所述初始导电层，被保留下来的所述初始导电层构成所述导电层。
  4. 根据权利要求3所述的半导体结构的制备方法，其中，在所述基底上形成间隔设置的多个栅极沟槽的步骤之后，在所述栅极沟槽形成栅极结构的步骤之前，所述制备方法还包括：
    在每个所述栅极沟槽的内壁上形成栅氧化层。
  5. 根据权利要求1-4任一项所述的半导体结构的制备方法，其中，在所述栅极沟槽内形成栅极结构的步骤之后，所述制备方法还包括：
    在所述导电层上形成介质层，所述介质层填充满位于所述导电层上方的所述栅极沟槽，所述介质层的顶面与所述基底的顶面平齐。
  6. 一种半导体结构，包括：基底以及间隔设置在所述基底内的多个栅极沟槽，每个所述栅极沟槽内设有栅极结构，所述栅极结构包括依次层叠设置的阻挡层和导电层，所述阻挡层与所述栅极沟槽的底壁接触，所述导 电层的材质包括多晶硅。
  7. 根据权利要求6所述的半导体结构，其中，多个所述栅极沟槽包括数个第一栅极沟槽和数个第二栅极沟槽，且沿第一方向，数个所述第一栅极沟槽和数个第二栅极沟槽交替间隔设置，所述第一栅极沟槽的宽度和所述第二栅极沟槽的宽度不等。
  8. 根据权利要求7所述的半导体结构，其中，所述半导体结构还包括栅氧化层，所述栅氧化层设置在所述栅极沟槽的内壁上。
  9. 根据权利要求8所述的半导体结构，其中，还包括介质层，所述介质层设置所述导电层上，并填充满位于所述导电层上方的所述栅极沟槽。
  10. 一种半导体结构的测量方法，所述测量方法包括：
    提供待测试半导体结构，所述待测试半导体结构包括基底以及间隔设置在所述基底内的多个栅极沟槽，每个所述栅极沟槽内设置有栅极结构，所述栅极结构包括依次层叠设置阻挡层和导电层，所述阻挡层与所述栅极沟槽的底壁接触，所述导电层的材质包括多晶硅；
    在所述基底上形成掩膜层，所述掩膜层包括间隔设置的多个掩膜条，每个所述掩膜条位于相邻的所述栅极沟槽之间；
    将形成有掩膜条的待测试的半导体结构传送至量测设备，所述量测设备用于测量所述导电层的宽度以及所述掩膜条的宽度；
    将形成有掩膜条的待测试的半导体结构传送至光电子能谱分析设备内，所述光电子能谱分析设备用于测量导电层中掺杂原子的浓度，以获得掺杂原子浓度的测量值；
    根据所述导电层的宽度、所述掩膜条的宽度以及所述掺杂原子浓度的测量值，确定所述导电层中所述掺杂原子浓度的理论值；
    根据所述导电层中所述掺杂原子浓度的理论值以及修正系数，确定所述导电层中所述掺杂原子浓度的实际值。
  11. 根据权利要求10所述的半导体结构的测量方法，其中，根据所述导电层的宽度、所述掩膜条的宽度以及所述掺杂原子浓度的测量值，确定所述导电层中掺杂原子的浓度的理论值ρ 理论通过如下公式得到：
    Figure PCTCN2021111569-appb-100001
    其中，ρ表示掺杂原子浓度的测量值，W 1表示导电层的宽度，W 2表示掩膜条的宽度。
  12. 根据权利要求11所述的半导体结构的测量方法，其中，多个所述栅极沟槽包括数个第一栅极沟槽和数个第二栅极沟槽，沿第一方向，数个第一栅极沟槽和数个第二栅极沟槽交替间隔设置，所述第一栅极沟槽的宽度和所述第二栅极沟槽的宽度不等，多个掩膜条包括数个第一掩膜条和第二掩膜条，所述第一掩膜条和所述第二掩膜条的宽度不等时，将形成有掩膜条的所述测试半导体结构传送至量测设备，所述量测设备用于测量所述导电层的宽度以及所述掩膜条的宽度的步骤中，包括：
    测量位于所述第一栅极沟槽内的导电层的宽度W 11，测量位于所述第二栅极槽内的导电层的宽度W 12；
    获取所述W 11和所述W 12的平均值，该平均值作为所述导电层的宽度W 1；
    测量所述第一掩膜条的宽度W 21，测量所述第二掩膜条的宽度W 22；
    获取所述W 21和所述W 22的平均值，该平均值作为所述掩膜条的宽度W 2。
  13. 根据权利要求10-12任一项所述的半导体结构的测量方法，其中，所述测量方法包括：
    提供基准晶圆，所述基准晶圆包括衬底以及依次层叠设置在所述衬底上的氮化钛层和多晶硅层，所述多晶硅层的厚度与所述导电层的厚度相等；
    将所述基准晶圆传送至光电子能谱分析设备内，所述光电子能谱分析设备用于测量所述基准晶圆中所述多晶硅层中掺杂原子的浓度；
    将至少一个所述待检测半导体结构作为样品，根据所述样品的导电层中的掺杂原子的浓度的理论值和所述基准晶圆中所述多晶硅层中掺杂原子的浓度，确定修正系数k。
  14. 根据权利要求13所述的半导体结构的测量方法，其中，将至少一个所述待检测半导体结构作为样品，根据所述样品的导电层中所述导电层中的掺杂原子的浓度的理论值和所述基准晶圆中所述多晶硅层中掺杂原子的浓度，确定修正系数k，通过如下的公式得到：
    Figure PCTCN2021111569-appb-100002
    其中，ρ 基准表示基准晶圆中多晶硅层中掺杂原子的浓度，ρ 样品表示确定修正系数时使用样品的掺杂原子浓度的测量值，W 样品1表示确定修正系 数时使用样品的导电层的宽度，W 样品2表示确定修正系数时使用样品的掩膜条的宽度。
  15. 根据权利要求14所述的半导体结构的测量方法，其中，根据所述导电层中掺杂原子浓度的理论值以及修正系数，确定所述导电层中掺杂原子浓度的实际值，通过如下的公式得到：
    ρ 实际＝k*ρ 理论。
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