WO2022156204A1 - 蚀刻机台的刻蚀缺陷的检测方法 - Google Patents

蚀刻机台的刻蚀缺陷的检测方法 Download PDF

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Publication number
WO2022156204A1
WO2022156204A1 PCT/CN2021/113357 CN2021113357W WO2022156204A1 WO 2022156204 A1 WO2022156204 A1 WO 2022156204A1 CN 2021113357 W CN2021113357 W CN 2021113357W WO 2022156204 A1 WO2022156204 A1 WO 2022156204A1
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etching
dielectric layer
layer
hole
etching machine
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PCT/CN2021/113357
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English (en)
French (fr)
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孙玉乐
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长鑫存储技术有限公司
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Priority to US17/647,634 priority Critical patent/US20220236051A1/en
Publication of WO2022156204A1 publication Critical patent/WO2022156204A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B11/00—Measuring arrangements characterised by the use of optical techniques
    • G01B11/24—Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

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  • the present disclosure relates to the technical field of semiconductor manufacturing, and in particular, to a method for detecting etching defects of an etching machine.
  • Dynamic random access memory is a semiconductor memory device commonly used in computers, and usually includes an array of multiple repetitive memory cells. Each memory cell includes a capacitor for storing data and a transistor that controls access to the data by the capacitor. Specifically, the gate of the transistor is electrically connected to the word line of the dynamic random access memory, one source/drain region of the transistor is electrically connected to the bit line of the dynamic random access memory, and the other source/drain region is connected to the capacitor through the capacitive contact structure, thereby To achieve the purpose of data storage and output.
  • the geometric size of the memory cell of the dynamic random access memory is continuously reduced, and the lateral area of the corresponding capacitor on the substrate is gradually reduced.
  • a stacked layer is usually formed on the substrate, and an etching machine is used to form a capacitor hole in the stacked layer that exposes the capacitor contact structure, so that the subsequently formed capacitor structure has a larger contact area, thereby obtaining Capacitive structure with high capacitance value.
  • the etching machine fails to etch through the stacked layer during etching, so that the capacitor contact structure cannot be exposed at the bottom of the corresponding capacitor hole, which reduces the device yield. .
  • the detection method of the etching machine in the prior art cannot detect the etching defect.
  • a method for detecting etching defects of an etching machine including:
  • test wafer includes a substrate, a first dielectric layer and a second dielectric layer, the first dielectric layer and the second dielectric layer are sequentially formed on the top surface of the substrate, the A capacitor contact structure is arranged in the substrate;
  • the shape of the capacitance hole of the measurement wafer it is determined whether there is an etching defect in the etching machine to be measured.
  • a test wafer is transferred into the etching machine to be tested, and part of the second dielectric layer and part of the first dielectric layer are etched to form capacitor holes.
  • the second dielectric layer is removed to form a measurement wafer. Then transfer the measurement wafer to the defect inspection machine to detect the shape of the capacitance hole in the measurement wafer, and determine the etching machine to be tested by comparing the image of the capacitance hole of the measurement wafer with the image of the normal capacitance hole Whether there are etching defects.
  • the second dielectric layer is removed after the capacitor hole is formed, the depth of the capacitor hole is reduced.
  • the defect inspection machine when used for inspection, the image of the capacitance hole of the measurement wafer can be clearly detected, and it can be determined whether there is a defect capacitance hole in the measurement wafer, and then it can be determined whether there is an etching defect in the etching machine to be measured. .
  • the method is simple and convenient, can accurately determine whether the etching machine to be tested has etching defects, greatly improves the detection efficiency of the etching machine, facilitates the timely maintenance of the defective etching machine by technicians, and further improves the yield of the product.
  • FIG. 1 is a schematic flowchart of a method for detecting etching defects of an etching machine according to an exemplary embodiment of the present disclosure
  • FIG. 2 is a schematic flowchart of a method for detecting etching defects of an etching machine according to another exemplary embodiment of the present disclosure
  • FIG. 3 is a schematic flowchart of a method for detecting etching defects of an etching machine according to another exemplary embodiment of the present disclosure
  • FIG. 4 is a schematic flowchart of a method for detecting etching defects of an etching machine according to still another exemplary embodiment of the present disclosure
  • FIG. 5 is a step-by-step flowchart of a method for detecting etching defects of an etching machine according to an exemplary embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a test wafer structure in an exemplary embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of forming a mask layer and a photoresist layer in an exemplary embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of a structure of forming a capacitor hole in an exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a structure of forming a support layer in an exemplary embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a measurement wafer structure in an exemplary embodiment of the present disclosure.
  • FIG. 11 is an image of a capacitive aperture of a metrology wafer in an exemplary embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • a certain structure When a certain structure is "on” other structures, it may mean that a certain structure is integrally formed on other structures, or that a certain structure is “directly” arranged on other structures, or that a certain structure is “indirectly” arranged on another structure through another structure. other structures.
  • a stacked layer is usually formed on a substrate, and an etching machine is used to form a capacitor hole in the stacked layer to expose the capacitor contact structure.
  • the etching machine may fail to etch through the stacked layer during etching, so that the bottom of the corresponding capacitor hole fails to expose the capacitor contact structure, that is, a defective capacitor hole is formed.
  • the bottom of the defective capacitor hole fails to expose the capacitor contact structure, so that the capacitor fabricated based on the defective capacitor hole cannot be in contact with the capacitor contact structure, resulting in reduced device yield.
  • the lower diameter of the defective capacitor hole is usually smaller than the upper diameter. Therefore, in the subsequent preparation process, it is easy to overturn, thereby causing a short circuit of the capacitor.
  • a high-height stacked layer structure formed with capacitive holes is usually scanned directly at the defect detection machine to obtain an image of the capacitive holes. Then, by analyzing the image of the capacitive hole obtained by scanning, it is detected whether the etching machine has etching defects.
  • the depth of the formed capacitive holes is relatively deep, and the difference between the images of the capacitive holes obtained by scanning is not large. Therefore, it is impossible to accurately identify the defective capacitive holes. Therefore, it is impossible to accurately judge whether the etching machine has etching defects.
  • an embodiment of the present disclosure provides a method for detecting etching defects of an etching machine, including the following steps:
  • Step S100 providing a test wafer, the test wafer includes a substrate, a first dielectric layer and a second dielectric layer, the first dielectric layer and the second dielectric layer are sequentially formed on the top surface of the substrate , the substrate is provided with a capacitive contact structure;
  • Step S200 transferring the test wafer into the etching machine to be tested, and etching part of the second dielectric layer and part of the first dielectric layer to form capacitor holes;
  • Step S300 removing the second dielectric layer to form a measurement wafer
  • Step S400 transferring the measurement wafer to a defect detection machine to detect the shape of the capacitance hole of the measurement wafer;
  • Step S500 according to the shape of the capacitance hole of the measurement wafer, determine whether there is an etching defect in the etching machine to be measured.
  • a test wafer is transferred into the etching machine to be tested, and part of the second dielectric layer and part of the first dielectric layer are etched to form capacitor holes.
  • the second dielectric layer is removed to form a measurement wafer. Then transfer the measurement wafer to the defect inspection machine to detect the shape of the capacitance hole in the measurement wafer, and determine the etching machine to be tested by comparing the image of the capacitance hole of the measurement wafer with the image of the normal capacitance hole Whether there are etching defects.
  • the second dielectric layer is removed after the capacitor hole is formed, the depth of the capacitor hole is reduced.
  • the defect inspection machine when used for inspection, the image of the capacitance hole of the measurement wafer can be clearly detected, and it can be determined whether there is a defect capacitance hole in the measurement wafer, and then it can be determined whether there is an etching defect in the etching machine to be measured. .
  • the method is simple and convenient, can accurately determine whether the etching machine to be tested has etching defects, greatly improves the detection efficiency of the etching machine, facilitates the timely maintenance of the defective etching machine by technicians, and further improves the yield of the product.
  • a test wafer is provided, and the test wafer includes a substrate, a first dielectric layer and a second dielectric layer, and the first dielectric layer and the second dielectric layer are sequentially formed on the substrate. a top surface, and the substrate is provided with a capacitive contact structure.
  • the test wafer includes a substrate 100 , a first dielectric layer 200 and a second dielectric layer 300 .
  • the substrate 100 may be a silicon substrate or other suitable substrate materials such as silicon, germanium, and silicon-germanium compounds.
  • the substrate 100 is a silicon substrate.
  • the substrate 100 can also be selected from other substrates known in the art.
  • a capacitor contact structure 400 is disposed in the substrate 100 , and the capacitor contact structure 400 is used to electrically connect with the capacitor structure formed subsequently, so as to control the charging and discharging of the capacitor structure.
  • the material of the capacitive contact structure 400 may be metal tungsten.
  • There are multiple capacitive contact structures 400 and two adjacent capacitive contact structures 400 are isolated from each other by the substrate 100 or the first dielectric layer 200 therebetween.
  • the formation process of the test wafer includes: providing a substrate 100 with a capacitive contact structure 400 disposed therein; depositing and forming a first dielectric layer 200 on the top surface of the substrate 100 , the first dielectric layer 200 covering the liner The surface of the bottom 100 ; the second dielectric layer 300 is formed by depositing the surface of the first dielectric layer 200 away from the substrate 100 , and the second dielectric layer 300 covers the surface of the first dielectric layer 200 .
  • the formation of the first dielectric layer 200 and the second dielectric layer 300 may be performed by chemical vapor deposition, atomic layer deposition, or physical vapor deposition.
  • the method for forming the first dielectric layer 200 and the second dielectric layer 300 is not limited, and the specific method may be selected by a skilled person according to actual needs.
  • the first dielectric layer 200 includes a first support layer 210 , a first insulating layer 220 and a second support layer 230 which are formed in sequence.
  • the first support layer 210 is formed on the top surface of the substrate 100
  • the first insulating layer 220 is formed on the surface of the first support layer 210 facing away from the substrate 100
  • the second support layer 230 is formed on the surface of the first insulating layer 220 facing away from the substrate 100 .
  • the second dielectric layer 300 includes a second insulating layer 310 and a third supporting layer 320 which are formed in sequence.
  • the second insulating layer 310 is formed on the surface of the second supporting layer 230 facing away from the substrate 100
  • the third supporting layer 320 is formed on the surface of the second insulating layer 310 facing away from the substrate 100 .
  • Materials of the first support layer 210, the first insulating layer 220 and the second support layer 230 may be selected from materials such as silicon dioxide, silicon boron nitride or silicon nitride.
  • the first support layer 210 is selected from silicon nitride or silicon boron nitride
  • the first insulating layer 220 is selected from silicon dioxide
  • the second support layer 230 is selected from silicon nitride.
  • the materials of the second insulating layer 310 and the third supporting layer 320 can also be selected from materials such as silicon dioxide, silicon boron nitride or silicon nitride.
  • the second insulating layer 310 is selected from silicon dioxide
  • the third support layer 320 is selected from silicon nitride.
  • the substrate 100 may include a plurality of active regions and an isolation structure (not shown in the figure) for defining the plurality of active regions, and each active region defines two source/ Drain area.
  • a plurality of word lines (not shown in the figure) and a plurality of bit lines (not shown in the figure) may be formed in the substrate 100, and each word line intersects an active region in the substrate 100 and separates two source/drain regions , for electrical connection with the gate of the transistor.
  • Each bit line intersects the corresponding active region and is in electrical contact with one of the source/drain regions, and the capacitive contact structure 400 is disposed on the substrate 100 and corresponds to the other source/drain region.
  • step S200 the test wafer is transferred into the etching machine to be tested, and part of the second dielectric layer and part of the first dielectric layer are etched to form capacitor holes.
  • the test wafer is etched by the etching machine to be tested to form capacitor holes.
  • each machine is regularly maintained.
  • the etching machine to be tested may be an etching machine that has been maintained, or an etching machine that has not been maintained and is in any period of time.
  • part of the second dielectric layer 300 and part of the first dielectric layer 200 are etched by the etching machine to be tested, and capacitor holes are formed in the first dielectric layer 200 and the second dielectric layer 300 .
  • the capacitor hole formed by etching may be a normal capacitor hole 700 or a defective capacitor hole 700a.
  • the number of capacitor holes is multiple.
  • the etching machine to be tested has an etching defect, the etching machine to be tested may fail to etch through the first dielectric layer 200 during etching, so that the bottom of the corresponding capacitor hole cannot be etched.
  • the capacitor contact structure 400 is exposed, ie, a defective capacitor hole 700a is formed.
  • the bottom of the defective capacitor hole 700 a fails to expose the capacitor contact structure 400 , so that the capacitor fabricated based on the defective capacitor hole 700 a cannot be in contact with the capacitor contact structure 400 , resulting in a decrease in device yield.
  • step S200 before step S200, it further includes:
  • Step S100-1 depositing a mask layer on the surface of the third support layer away from the substrate, the mask layer covering the third support layer;
  • Step S100-2 a photoresist layer having a pattern is formed on the surface of the mask layer away from the substrate, and the photoresist layer covers part of the mask layer.
  • a mask layer 500 is deposited on the surface of the third support layer 320 away from the substrate 100 , and the mask layer 500 covers the third support layer 320 .
  • the material of the mask layer 500 may be selected from other suitable materials such as polysilicon, carbon, silicon and compounds thereof, and specifically may be selected from silicon dioxide, silicon nitride, silicon oxynitride, carbon, and the like. One or more, which are not limited here.
  • the mask layer 500 may include a multi-layer structure. As shown in FIG.
  • the mask layer 500 includes a polysilicon layer 510 formed on the surface of the third support layer 320 , an oxide layer 520 formed on the surface of the polysilicon layer 510 and a carbon layer 530 formed on the surface of the oxide layer 520 .
  • the mask layer 500 may also include other material layers, which are not specifically limited in the present disclosure.
  • a patterned photoresist layer 600 is formed on the surface of the mask layer 500 away from the substrate 100 , and the photoresist layer 600 covers part of the top surface of the mask layer 500 .
  • the photoresist layer 600 has a plurality of openings 610 , and the orthographic projections of the openings 610 on the substrate 100 at least partially overlap the capacitive contact structure 400 .
  • the openings 610 are used for etching to form capacitor holes.
  • step S200 is performed, and the test wafer on which the mask layer 500 and the photoresist layer 600 are formed is etched to form capacitor holes. Specifically, using the photoresist layer 600 as a mask and the substrate 100 as a stop layer, part of the mask layer 500 , part of the second dielectric layer 300 and part of the first dielectric layer 200 are etched to form capacitor holes.
  • the method further includes:
  • Step S200-1 removing the photoresist layer and the mask layer.
  • the capacitor holes include normal capacitor holes 700 capable of exposing the capacitor contact structure 400 and defective capacitor holes 700 a that cannot expose the capacitor contact structure 400 due to etching defects.
  • step S200 after step S200, and before step S300, further includes:
  • Step S200-2 forming a support layer in the capacitor hole, the support layer covering at least the bottom and sidewalls of the capacitor hole.
  • a support layer 800 is formed in the capacitor hole, and the support layer 800 covers at least the bottom and sidewalls of the capacitor hole.
  • the thickness of the support layer 800 is 8-12 nm. It should be noted here that the thickness of the support layer 800 should be less than 1/2 of the width of the capacitor hole, so as to avoid the excessively thick support layer 800 filling the capacitor hole and affecting the subsequent detection of the shape of the capacitor hole.
  • the material of the support layer 800 is selected from titanium nitride.
  • the electrode plate material of the capacitor structure is generally selected from titanium nitride.
  • the support layer 800 is selected from titanium nitride, wherein, titanium nitride not only has strong hardness to prevent the capacitor hole structure from tipping after the second dielectric layer is removed by a grinding process, but also can simulate the subsequent formation of the upper electrode plate after the Capacitance hole structure, more accurate detection of etching defects in the etching machine to be tested.
  • step S200-2 is performed.
  • step S200-2 may also be performed before step S200-1 to deposit and form the support layer 800, and then the photoresist layer 600, the mask layer 500 and the layer above the second dielectric layer 300 are deposited.
  • the support layer 800 is removed, and the structure shown in FIG. 9 can also be formed.
  • step S300 the second dielectric layer is removed to form a measurement wafer.
  • the second dielectric layer 300 is removed to form a measurement wafer.
  • a measurement wafer with a lower height and a capacitor hole with a lower depth are obtained.
  • step S300 includes: removing the second dielectric layer and the support layer above the first dielectric layer by a grinding process to form the measurement wafer.
  • the formed support layer 800 covers the bottom and sidewalls of the capacitor hole.
  • the second dielectric layer 300 and the supporting layer 800 above the first dielectric layer 200 are removed by a grinding process, so as to obtain the measurement wafer as shown in FIG. 10 .
  • the measurement wafer includes a substrate 100 , a first dielectric layer 200 , and capacitor holes formed in the first dielectric layer 200 .
  • step S300 after step S300, and before step S400, further includes:
  • Step S300-1 cleaning the capacitance hole of the measurement wafer to remove impurities on the surface of the capacitance hole of the measurement wafer.
  • the capacitor holes are cleaned to remove impurities in the capacitor holes.
  • the support layer 800 formed in step S200-2 can protect the shape of the capacitor hole from being affected during the cleaning process, and ensure the accuracy of the subsequent shape detection of the capacitor hole.
  • the capacitive hole of the measurement wafer is cleaned with a diluted hydrofluoric acid solution to remove impurities on the surface of the capacitive hole.
  • the diluted hydrofluoric acid solution not only has a good cleaning effect, but also does not damage the support layer 800 , which provides a guarantee for the subsequent detection of the capacitive hole and the formation of the capacitive structure.
  • the dilution factor can be set according to the actual situation, which is not specifically limited in the present disclosure.
  • step S400 the measurement wafer is transferred to a defect inspection machine, and the shape of the capacitance hole of the measurement wafer is inspected.
  • a defect inspection machine is used to inspect the capacitance holes of the measurement wafer.
  • the defect detection machine can be a defect scanning machine, and the scanning machine scans the defects of the measurement wafer to obtain an image of the capacitance hole of the measurement wafer.
  • step S500 according to the shape of the capacitance hole of the measurement wafer, it is determined whether the etching machine to be tested has an etching defect.
  • this step it is determined whether the etching machine to be tested has etching defects according to the shape and structure of the capacitive hole obtained by the defect detection machine.
  • step S500 includes:
  • Step S510 using a defect detection machine to acquire an image of the capacitance hole of the measurement wafer
  • Step S520 compare the image of the capacitance hole of the measurement wafer with the image of the normal capacitance hole, and determine whether the etching machine to be tested has etching defects.
  • the depth of the defect capacitor hole formed by etching is shallower than that of the normal capacitor hole, and the corresponding image of the measured wafer capacitor hole is different from that of the normal capacitor hole.
  • the image brightness obtained by the detection of the defective capacitive hole 700 a is different from that of the normal capacitive hole 700 . Therefore, in the actual inspection, it can be determined whether the etching machine to be tested has etching defects by directly comparing the image brightness of the capacitance hole of the measurement wafer and the normal capacitance hole.
  • step S520 includes:
  • the etching machine to be tested has etching defects.
  • the image brightness of all the capacitive holes of the measurement wafer is the same as the image brightness of the normal capacitive holes, it is determined that the etching machine to be tested does not have etching defects.
  • the image brightness of each capacitive hole of the measurement wafer obtained by the defect inspection machine is different. It should be noted here that due to the different degrees of defects in different defective capacitor holes 700a, the corresponding image brightness will be different, but in general, the image brightness of each defective capacitor hole 700a is the same as that of the normal capacitor hole 700. Brightness is different. In some embodiments of the present disclosure, the image brightness of the defective capacitive hole 700 a is higher than that of the normal capacitive hole 700 . In other embodiments of the present disclosure, the image brightness of the defective capacitor hole 700a is lower than that of the normal capacitor hole 700, and the specific brightness is determined by the defect degree of the defective capacitor hole 700a, which is not limited in the present disclosure.

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Abstract

一种蚀刻机台的刻蚀缺陷的检测方法，属于半导体生产制造技术领域。蚀刻机台的刻蚀缺陷的检测方法包括提供测试晶圆，测试晶圆包括衬底（100）、第一介质层（200）和第二介质层（300），第一介质层（200）和第二介质层（300）依次形成于衬底（100）的顶表面，衬底（100）内设置有电容接触结构（400）（S100）；将测试晶圆传递至待测蚀刻机台内，刻蚀部分第二介质层（300）和部分第一介质层（200），以形成电容孔（S200）；去除第二介质层（300），以形成量测晶圆（S300）；将量测晶圆传递至缺陷检测机台，检测量测晶圆的电容孔的形状（S400）；根据量测晶圆的电容孔的形状，确定待测蚀刻机台是否存在刻蚀缺陷（S500）。蚀刻机台的刻蚀缺陷的检测方法简单便捷，可准确判断待测蚀刻机台是否存在刻蚀缺陷，提高对蚀刻机台的检测效率。

Description

蚀刻机台的刻蚀缺陷的检测方法
交叉引用
本公开要求于2020年01月25日提交的申请号为202110094612.1、名称为“蚀刻机台的刻蚀缺陷的检测方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体生产制造技术领域，尤其涉及一种蚀刻机台的刻蚀缺陷的检测方法。
背景技术
动态随机存储器是计算机中常用的半导体存储器件，通常包括多个重复的存储单元组成的阵列。每个存储单元包括电容器和晶体管，其中电容器用于存储数据，晶体管可控制电容器对于数据的存取。具体地，晶体管的栅极电连接至动态随机存储器的字线，晶体管的一个源/漏区电连接至动态随机存储器的位线，另一个源/漏区则通过电容接触结构连接至电容器，从而达到数据存储和输出的目的。
随着集成电路制程的发展，动态随机存储器的存储单元的几何尺寸不断减小，对应的电容器在基底上的横向面积逐渐减小。为了获得较大的电容，通常会在基底上形成堆叠层，并采用蚀刻机台在堆叠层中形成暴露电容接触结构的电容孔，从而使后续形成的电容结构具有较大的接触面积，进而获得具有高电容值的电容结构。然而，随着电容孔的深宽比的不断提高，蚀刻机台在刻蚀时存在未能刻穿堆叠层的情况，使得对应的电容孔底部未能暴露出电容接触结构，降低了器件良率。然而，现有技术中对蚀刻机台的检测方法无法检测出该刻蚀缺陷。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的第一个方面，提供一种蚀刻机台的刻蚀缺陷的检测方法，包括：
提供测试晶圆，所述测试晶圆包括衬底、第一介质层和第二介质层，所述第一介质层和所述第二介质层依次形成于所述衬底的顶表面，所述衬底内设置有电容接触结构；
将所述测试晶圆传递至待测蚀刻机台内，刻蚀部分所述第二介质层和部分所述第一介质层，以形成电容孔；
去除所述第二介质层，以形成量测晶圆；
将所述量测晶圆传递至缺陷检测机台，检测所述量测晶圆的电容孔的形状；
根据所述量测晶圆的电容孔的形状，确定所述待测蚀刻机台是否存在刻蚀缺陷。
本公开提供的蚀刻机台的刻蚀缺陷的检测方法，通过将测试晶圆传递至待测蚀刻机台内，刻蚀部分第二介质层和部分第一介质层，以形成电容孔。待形成电容孔后，去除第二介质层，以形成量测晶圆。随后将该量测晶圆传递至缺陷检测机台，检测该量测晶圆内电容孔的形状，通过比较量测晶圆的电容孔的图像与正常电容孔的图像，确定待测蚀刻机台是否存在刻蚀缺陷。该方法中，由于在形成电容孔后去除了第二介质层，使得电容孔的深度降低。因此，在使用缺陷检测机台进行检测时，能够清楚地检测到量测晶圆电容孔的图像，判断量测晶圆内是否存在缺陷电容孔，进而确定待测蚀刻机台是否存在刻蚀缺陷。该方法简单便捷，可准确判断待测蚀刻机台是否存在刻蚀缺陷，大大提高对蚀刻机台的检测效率，方便技术人员对有缺陷的蚀刻机台及时维护，进一步提高产品的良率。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合 本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开示例性实施例中蚀刻机台的刻蚀缺陷的检测方法流程示意图；
图2是本公开另一示例性实施例中蚀刻机台的刻蚀缺陷的检测方法流程示意图；
图3是本公开又一示例性实施例中蚀刻机台的刻蚀缺陷的检测方法流程示意图；
图4是本公开再一示例性实施例中蚀刻机台的刻蚀缺陷的检测方法流程示意图；
图5是本公开一示例性实施例中蚀刻机台的刻蚀缺陷的检测方法分步流程示意图；
图6是本公开示例性实施例中测试晶圆结构示意图；
图7是本公开示例性实施例中形成掩膜层和光刻胶层结构示意图；
图8是本公开示例性实施例中形成电容孔结构示意图；
图9是本公开示例性实施例中形成支撑层结构示意图；
图10是本公开示例性实施例中量测晶圆结构示意图；
图11是本公开示例性实施例中量测晶圆的电容孔的图像。
附图标记说明：
100-衬底；200-第一介质层；210-第一支撑层；220-第一绝缘层；230-第二支撑层；300-第二介质层；310-第二绝缘层；320-第三支撑层；400-电容接触结构；500-掩膜层；510-多晶硅层；520-氧化物层；530-碳层；600-光刻胶层；610-开口；700-正常电容孔；700a-缺陷电容孔；800-支撑层。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反， 提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的主要技术创意。
当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
相关技术中，在半导体制造工艺中，为了获得较大的电容，通常会在基底上形成堆叠层，并采用蚀刻机台在堆叠层中形成暴露电容接触结构的电容孔。蚀刻机台在刻蚀时存在未能刻穿堆叠层的情况，使得对应的电容孔底部未能暴露出电容接触结构，即形成缺陷电容孔。该缺陷电容孔的底部未能暴露电容接触结构，进而导致基于该缺陷电容孔制作的电容器无法与电容接触结构接触，导致器件良率降低。此外，该缺陷电容孔的下口径通常小于上口径。因此，在后续制备过程中，容易倾倒，进而造成电容器短路。
目前，对蚀刻机台进行刻蚀缺陷检测时，通常将形成有电容孔的高度较高的堆叠层结构直接于缺陷检测机台处进行扫描，获得电容孔图像。之后通过分析扫描获得的电容孔的图像，检测蚀刻机台是否存在刻蚀缺陷。然而，在实际应用中，由于目前的堆叠层结构具有较高的高度，形 成的电容孔的深度较深，扫描获得的电容孔的图像之间差异不大，因此，无法准确辨别缺陷电容孔，进而无法准确判断蚀刻机台是否存在刻蚀缺陷。
如图1所示，本公开实施方式中提供一种蚀刻机台的刻蚀缺陷的检测方法，包括以下步骤：
步骤S100，提供测试晶圆，所述测试晶圆包括衬底、第一介质层和第二介质层，所述第一介质层和所述第二介质层依次形成于所述衬底的顶表面，所述衬底内设置有电容接触结构；
步骤S200，将所述测试晶圆传递至待测蚀刻机台内，刻蚀部分所述第二介质层和部分所述第一介质层，以形成电容孔；
步骤S300，去除所述第二介质层，以形成量测晶圆；
步骤S400，将所述量测晶圆传递至缺陷检测机台，检测所述量测晶圆的电容孔的形状；
步骤S500，根据所述量测晶圆的电容孔的形状，确定所述待测蚀刻机台是否存在刻蚀缺陷。
本公开提供的蚀刻机台的刻蚀缺陷的检测方法，通过将测试晶圆传递至待测蚀刻机台内，刻蚀部分第二介质层和部分第一介质层，以形成电容孔。待形成电容孔后，去除第二介质层，以形成量测晶圆。随后将该量测晶圆传递至缺陷检测机台，检测该量测晶圆内电容孔的形状，通过比较量测晶圆的电容孔的图像与正常电容孔的图像，确定待测蚀刻机台是否存在刻蚀缺陷。该方法中，由于在形成电容孔后去除了第二介质层，使得电容孔的深度降低。因此，在使用缺陷检测机台进行检测时，能够清楚地检测到量测晶圆电容孔的图像，判断量测晶圆内是否存在缺陷电容孔，进而确定待测蚀刻机台是否存在刻蚀缺陷。该方法简单便捷，可准确判断待测蚀刻机台是否存在刻蚀缺陷，大大提高对蚀刻机台的检测效率，方便技术人员对有缺陷的蚀刻机台及时维护，进一步提高产品的良率。
下面结合附图对本公开实施方式提供的蚀刻机台的刻蚀缺陷的检测方法的各步骤进行详细说明：
在步骤S100中，提供测试晶圆，所述测试晶圆包括衬底、第一介质 层和第二介质层，所述第一介质层和所述第二介质层依次形成于所述衬底的顶表面，所述衬底内设置有电容接触结构。
如图6所示，测试晶圆包括衬底100、第一介质层200和第二介质层300。其中，衬底100可以为硅衬底或硅、锗、硅锗化合物等其他合适的衬底材料。在本公开一些实施例中，衬底100选用硅衬底。当然不限于此，在其他一些实施例中，衬底100也可以选用本领域公知的其他衬底。
衬底100内设置有电容接触结构400，电容接触结构400用于与后续形成的电容结构电连接，从而控制电容结构的充电与放电。电容接触结构400的材料可以是金属钨。电容接触结构400的数量为多个，相邻两个电容接触结构400通过其间的衬底100或第一介质层200相互隔绝。本公开中，测试晶圆的形成过程包括：提供衬底100，该衬底100内设置有电容接触结构400；于衬底100顶表面沉积形成第一介质层200，第一介质层200覆盖衬底100的表面；于第一介质层200背离衬底100的表面沉积形成第二介质层300，第二介质层300覆盖第一介质层200的表面。第一介质层200和第二介质层300的形成具体可采用过化学气相沉积法、原子层沉积法或物理气相沉积法等。本公开中，形成第一介质层200和第二介质层300的方法不做限定，具体可有技术人员根据实际需求进行选择。
在本公开一些实施例中，第一介质层200包括依次形成的第一支撑层210、第一绝缘层220和第二支撑层230。第一支撑层210形成于衬底100的顶表面，第一绝缘层220形成于第一支撑层210背离衬底100的表面，第二支撑层230形成于第一绝缘层220背离衬底100的表面。第二介质层300包括依次形成的第二绝缘层310和第三支撑层320。第二绝缘层310形成于第二支撑层230背离衬底100的表面，第三支撑层320形成于第二绝缘层310背离衬底100的表面。第一支撑层210、第一绝缘层220和第二支撑层230的材料可以选自二氧化硅、氮硼化硅或氮化硅等材料。在具体一实施例中，第一支撑层210选自氮化硅或氮硼化硅，第一绝缘层220选自二氧化硅，第二支撑层230选自氮化硅。第二绝缘层310和第三支撑层320的材料也可以选自二氧化硅、氮硼化硅或氮化 硅等材料，在具体一实施例中，第二绝缘层310选自二氧化硅，第三支撑层320选自氮化硅。
在本公开另一些实施例中，衬底100可以包括多个有源区和用于限定多个有源区的隔离结构(图中未显示)，每个有源区中界定有两个源/漏区。衬底100内可形成多条字线(图中未显示)和多条位线(图中未显示)，每条字线与衬底100中的有源区相交并分隔两个源/漏区，用于与晶体管的栅极电连接。每条位线与相应的有源区相交并与其中一个源/漏区电接触，电容接触结构400设置于衬底100并对应于另一个源/漏区。
在步骤S200中，将所述测试晶圆传递至待测蚀刻机台内，刻蚀部分所述第二介质层和部分所述第一介质层，以形成电容孔。
在该步骤中，利用待测蚀刻机台对测试晶圆进行刻蚀，形成电容孔。在半导体生产制造中，定期会对各个机台进行保养维护。在本公开中，待测蚀刻机台可以是保养维护后的蚀刻机台，也可以是未进行保养维护，处于任何时段的蚀刻机台。
如图8所示，在该步骤中，利用待测蚀刻机台刻蚀部分第二介质层300和部分第一介质层200，在第一介质层200和第二介质层300中形成电容孔。刻蚀形成的电容孔可能为正常电容孔700，也可能为缺陷电容孔700a。电容孔的数量为多个，当待测蚀刻机台存在刻蚀缺陷时，待测蚀刻机台在刻蚀时存在未能刻穿第一介质层200的情况，使得对应的电容孔底部未能暴露出电容接触结构400，即形成缺陷电容孔700a。该缺陷电容孔700a的底部未能暴露电容接触结构400，进而导致基于该缺陷电容孔700a制作的电容器无法与电容接触结构400接触，导致器件良率降低。
如图2所示，在本公开一些实施例中，在步骤S200之前还包括：
步骤S100-1，于所述第三支撑层背离所述衬底的表面沉积掩膜层，所述掩膜层覆盖所述第三支撑层；
步骤S100-2，于所述掩膜层背离所述衬底的表面形成具有图形的光刻胶层，所述光刻胶层覆盖部分所述掩膜层。
如图7所示，在步骤S100-1中，于第三支撑层320的背离衬底100 的表面沉积掩膜层500，掩膜层500覆盖第三支撑层320。在本公开一些实施例中，掩膜层500的材料可以选自多晶硅、碳、硅及其化合物等其他合适材料，具体可以选自二氧化硅、氮化硅、氮氧化硅、碳等中的一种或多种，在此不做限定。本公开中，掩膜层500可以包含多层结构。如图7所示，掩膜层500包括形成于第三支撑层320表面的多晶硅层510、形成于多晶硅层510表面氧化物层520和形成于氧化物层520表面的碳层530。当然，在其他实施例中，掩膜层500也可以包括其他材料层，具体本公开不做限定。
继续如图7所示，在步骤S100-2中，于掩膜层500背离衬底100的表面形成具有图形的光刻胶层600，光刻胶层600覆盖部分掩膜层500的顶表面。光刻胶层600具有多个开口610，开口610在衬底100上的正投影与电容接触结构400至少部分重叠。开口610用于刻蚀形成电容孔。
待形成光刻胶层600后，进行步骤S200，将形成有掩膜层500和光刻胶层600的测试晶圆进行刻蚀，以形成电容孔。具体地，以光刻胶层600作为掩膜，以衬底100作为停止层，刻蚀部分掩膜层500、部分第二介质层300和部分第一介质层200，以形成电容孔。
如图2所示，在本公开一些实施例中，在步骤S200之后，在步骤S300之前还包括：
步骤S200-1，去除所述光刻胶层和所述掩膜层。
如图7、图8所示，在该步骤中，去除光刻胶层600和剩余掩膜层500后，形成如图8所示的结构体。该结构体中，电容孔包括能够暴露电容接触结构400的正常电容孔700和存在刻蚀缺陷未能暴露电容接触结构400的缺陷电容孔700a。
如图3所示，在本公开一些实施例中，在步骤S200之后，步骤S300之前还包括：
步骤S200-2，于所述电容孔内形成支撑层，所述支撑层至少覆盖所述电容孔的底部及侧壁。
如图9所示，在该步骤中，在电容孔孔内形成支撑层800，支撑层800至少覆盖电容孔的底部和侧壁。支撑层800的厚度为8-12nm。在此 需说明的是，支撑层800的厚度应小于电容孔宽度的1/2，以避免过厚的支撑层800将电容孔填充，影响后续对电容孔形状的检测。在具体一实施例中，支撑层800的材料选自氮化钛。在半导体制造工艺中，电容结构的电极板材料一般选用氮化钛。本公开中支撑层800选用氮化钛，其中，氮化钛不仅具有较强的硬度，防止利用研磨工艺去除所述第二介质层后电容孔结构倾倒，而且可以模拟后续形成上电极板后的电容孔结构，更加精确的检测待测蚀刻机台是否存在刻蚀缺陷。
在一些实施例中，当步骤S200-1完成后，即待光刻胶层600和掩膜层500去除后，再进行步骤S200-2。当然，在另一些实施例中，也可在步骤S200-1之前进行步骤S200-2，沉积形成支撑层800，之后再将光刻胶层600、掩膜层500以及第二介质层300上方的支撑层800去除，同样可形成如图9所示的结构。
在步骤S300中，去除所述第二介质层，以形成量测晶圆。
如图9、图10所示，在该步骤中，去除第二介质层300，形成量测晶圆。该步骤中，去除第二介质层300后，获得了较低高度的量测晶圆，以及较低深度的电容孔。
在本公开一些实施例中，步骤S300包括：利用研磨工艺去除所述第二介质层，以及所述第一介质层上方的所述支撑层，以形成所述量测晶圆。
如图9所示，形成的支撑层800覆盖电容孔的底部和侧壁。该步骤中，利用研磨工艺将第二介质层300，以及第一介质层200上方的支撑层800去除，以获得如图10所示的量测晶圆。该量测晶圆包括衬底100和第一介质层200，以及形成于第一介质层200内的电容孔。
如图4所示，在本公开一些实施例中，在步骤S300之后，步骤S400之前还包括：
步骤S300-1，将所述量测晶圆的电容孔进行清洗，以去除所述量测晶圆的电容孔表面的杂质。
该步骤中，对电容孔进行清洗，以去除电容孔内的杂质。此时，在步骤S200-2中形成的支撑层800，能够保护电容孔的形状在清洗过程中不受影响，保证后续对电容孔形状检测的准确性。在本公开一些实施例 中，采用稀释的氢氟酸溶液将量测晶圆的电容孔进行清洗，以去除电容孔表面的杂质。稀释的氢氟酸溶液不仅清洗效果好，且不会损伤支撑层800，为后续电容孔的检测以及电容结构的形成提供保障。该步骤中，稀释倍数可根据实际情况进行设定，具体本公开不做限定。
在步骤S400中，将所述量测晶圆传递至缺陷检测机台，检测所述量测晶圆的电容孔的形状。
在该步骤中，利用缺陷检测机台对量测晶圆的电容孔进行检测。缺陷检测机台可以为缺陷扫描机台，扫描机台对量测晶圆进行缺陷扫描，可以获得量测晶圆电容孔的图像。
在步骤S500中，根据所述量测晶圆的电容孔的形状，确定所述待测蚀刻机台是否存在刻蚀缺陷。
该步骤中，根据缺陷检测机台检测获得的电容孔的形状结构，确定待测蚀刻机台是否存在刻蚀缺陷。
如图5所示，在本公开一些实施例中，步骤S500包括：
步骤S510，利用缺陷检测机台获取所述量测晶圆的电容孔的图像；
步骤S520，比较所述量测晶圆的电容孔的图像与正常电容孔的图像，判断所述待测蚀刻机台是否存在刻蚀缺陷。
当待测蚀刻机台存在刻蚀缺陷时，刻蚀形成的缺陷电容孔的深度相较正常电容孔的深度较浅，相对应的量测晶圆电容孔的图像与正常电容孔的图像不同。在本公开一些实施例中，缺陷电容孔700a检测获得的图像亮度与正常电容孔700的图像亮度不同。因此，在实际检测中，直接通过比较量测晶圆的电容孔和正常电容孔的图像亮度，即可判断出待测蚀刻机台是否存在刻蚀缺陷。
在本公开一些实施例中，步骤S520包括：
当量测晶圆部分或全部电容孔的图像亮度与正常电容孔的亮度不同时，则判断待测蚀刻机台存在刻蚀缺陷。当量测晶圆全部电容孔的图像与正常电容孔的图像亮度相同时，判断待测蚀刻机台不存在刻蚀缺陷。
如图11所示，采用缺陷检测机台获得的量测晶圆的各个电容孔的图像亮度不同。在此需说明的是，不同缺陷电容孔700a由于缺陷程度不同，因此，其对应的图像亮度会有差异，但总体而言，每个缺陷电容孔700a 的图像亮度均与正常电容孔700的图像亮度不同。在本公开一些实施例中，缺陷电容孔700a的图像亮度高于正常电容孔700的图像亮度。在本公开另一些实施例中，缺陷电容孔700a的图像亮度低于正常电容孔700的图像亮度，具体亮度由缺陷电容孔700a的自身缺陷程度决定，本公开对此不做限定。
需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等，均应视为本公开的一部分。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (15)

  1. 一种蚀刻机台的刻蚀缺陷的检测方法，包括：
    提供测试晶圆，所述测试晶圆包括衬底、第一介质层和第二介质层，所述第一介质层和所述第二介质层依次形成于所述衬底的顶表面，所述衬底内设置有电容接触结构；
    将所述测试晶圆传递至待测蚀刻机台内，刻蚀部分所述第二介质层和部分所述第一介质层，以形成电容孔；
    去除所述第二介质层，以形成量测晶圆；
    将所述量测晶圆传递至缺陷检测机台，检测所述量测晶圆的电容孔的形状；
    根据所述量测晶圆的电容孔的形状，确定所述待测蚀刻机台是否存在刻蚀缺陷。
  2. 根据权利要求1所述的蚀刻机台的刻蚀缺陷的检测方法，其中，在形成所述电容孔的步骤之后，在去除所述第二介质层的步骤之前还包括：
    于所述电容孔内形成支撑层，所述支撑层至少覆盖所述电容孔的底部及侧壁。
  3. 根据权利要求2所述的蚀刻机台的刻蚀缺陷的检测方法，其中，所述支撑层的厚度为8-12nm。
  4. 根据权利要求2所述的蚀刻机台的刻蚀缺陷的检测方法，其中，所述支撑层的材料包含氮化钛。
  5. 根据权利要求2所述的蚀刻机台的刻蚀缺陷的检测方法，其中，所述去除所述第二介质层，以形成量测晶圆包括：
    利用研磨工艺去除所述第二介质层，以及所述第一介质层上方的所述支撑层，以形成所述量测晶圆。
  6. 根据权利要求1所述的蚀刻机台的刻蚀缺陷的检测方法，其中，在形成所述量测晶圆的步骤之后，在将所述量测晶圆传递至缺陷检测机台，检测所述量测晶圆的电容孔的形状的步骤之前，还包括：
    将所述量测晶圆的电容孔进行清洗，以去除所述量测晶圆的电容孔表面的杂质。
  7. 根据权利要求6所述的蚀刻机台的刻蚀缺陷的检测方法，其中，采用稀释的氢氟酸溶液将所述量测晶圆的电容孔进行清洗。
  8. 根据权利要求1所述的蚀刻机台的刻蚀缺陷的检测方法，其中，所述根据所述量测晶圆的电容孔的形状，确定所述待测蚀刻机台是否存在刻蚀缺陷包括：
    利用缺陷检测机台获取所述量测晶圆的电容孔的图像；
    比较所述量测晶圆的电容孔的图像与正常电容孔的图像，判断所述待测蚀刻机台是否存在刻蚀缺陷。
  9. 根据权利要求8所述的蚀刻机台的刻蚀缺陷的检测方法，其中，所述比较所述量测晶圆的电容孔的图像与正常电容孔的图像，判断所述待测蚀刻机台是否存在刻蚀缺陷包括：
    当所述量测晶圆的全部或部分电容孔的图像亮度与所述正常电容孔的图像亮度不同时，判断所述待测蚀刻机台存在刻蚀缺陷；当所述量测晶圆的全部电容孔的图像亮度与所述正常电容孔的图像亮度相同时，判断所述待测蚀刻机台不存在刻蚀缺陷。
  10. 根据权利要求1所述的蚀刻机台的刻蚀缺陷的检测方法，其中，所述第一介质层包括依次形成的第一支撑层、第一绝缘层和第二支撑层，所述第二介质层包括依次形成的第二绝缘层和第三支撑层。
  11. 根据权利要求10所述的蚀刻机台的刻蚀缺陷的检测方法，其中，在将所述测试晶圆传递至待测蚀刻机台内，刻蚀部分所述第二介质层和部分所述第一介质层，以形成电容孔的步骤之前，还包括；
    于所述第三支撑层背离所述衬底的表面沉积掩膜层，所述掩膜层覆盖所述第三支撑层；
    于所述掩膜层背离所述衬底的表面形成具有图形的光刻胶层，所述光刻胶层覆盖部分所述掩膜层。
  12. 根据权利要求11所述的蚀刻机台的刻蚀缺陷的检测方法，其中，所述掩膜层包括依次形成的多晶硅层、氧化物层和碳层。
  13. 根据权利要求11所述的蚀刻机台的刻蚀缺陷的检测方法，其中，所述光刻胶层具有多个开口，所述开口在所述衬底上的正投影与所述电容接触结构至少部分重叠。
  14. 根据权利要求11所述的蚀刻机台的刻蚀缺陷的检测方法，其中，将所述测试晶圆传递至待测蚀刻机台内，刻蚀部分所述第二介质层和部分所述第一介质层，以形成电容孔包括：
    以所述光刻胶层作为掩膜，以所述衬底作为停止层，刻蚀部分所述掩膜层、部分所述第二介质层和部分所述第一介质层，以形成所述电容孔。
  15. 根据权利要求14所述的蚀刻机台的刻蚀缺陷的检测方法，其中，在将所述测试晶圆传递至待测蚀刻机台内，刻蚀部分所述第二介质层和部分所述第一介质层，以形成电容孔的步骤之后，在去除所述第二介质层，以形成量测晶圆步骤之前还包括：
    去除所述光刻胶层和所述掩膜层。
PCT/CN2021/113357 2021-01-25 2021-08-18 蚀刻机台的刻蚀缺陷的检测方法 WO2022156204A1 (zh)

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