WO2022205726A1 - 对准误差的测试方法、调整方法、测试系统和存储介质 - Google Patents

对准误差的测试方法、调整方法、测试系统和存储介质 Download PDF

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WO2022205726A1
WO2022205726A1 PCT/CN2021/111778 CN2021111778W WO2022205726A1 WO 2022205726 A1 WO2022205726 A1 WO 2022205726A1 CN 2021111778 W CN2021111778 W CN 2021111778W WO 2022205726 A1 WO2022205726 A1 WO 2022205726A1
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conductive layer
resistance
distance
width
alignment
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PCT/CN2021/111778
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English (en)
French (fr)
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骆晓东
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长鑫存储技术有限公司
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Priority to US17/452,570 priority Critical patent/US11935797B2/en
Publication of WO2022205726A1 publication Critical patent/WO2022205726A1/zh

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography

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  • the yellow light process is a commonly used process in the semiconductor field.
  • the yellow light process is also known as the photolithography process.
  • the semiconductor structure plays a protective role. After photolithography, the semiconductor structure is etched using the patterned photoresist layer as a mask to obtain a permanent pattern. An alignment operation is also performed before exposure, using alignment marks on the scribe lines for alignment, so that the semiconductor structure can be aligned with the lithographic reticle, so that the pattern on the reticle can be accurately transferred to the photosensitivity materially.
  • Embodiments of the present application provide an alignment error testing method, an adjustment method, a testing system and a storage medium, so as to improve the accuracy of testing alignment errors.
  • An embodiment of the present application provides a method for testing alignment errors, including: providing a substrate with a first conductive layer and a second conductive layer spaced thereon, the first conductive layer and the second conductive layer
  • the arrangement direction is the first direction; obtain the first distance, the first distance is the center axis of the first conductive layer perpendicular to the first direction and the second conductive layer perpendicular to the first distance from the central axis in one direction; obtain the first resistance of the first conductive layer and the second resistance of the second conductive layer; according to the first distance, the first resistance and the second resistance , obtain the actual distance between the first conductive layer and the second conductive layer; obtain the first conductive layer through the actual distance and the standard distance between the first conductive layer and the second conductive layer Alignment error value between a conductive layer and the second conductive layer.
  • the embodiment of the present application further provides an alignment error testing system, the alignment error testing system is suitable for executing the aforementioned alignment error testing method; comprising: a first acquisition module, a second acquisition module, a a third acquisition module and a calculation module; the first acquisition module is adapted to acquire the first distance; the second acquisition module is adapted to acquire the first resistance and the second resistance; the third acquisition module is adapted to obtain the actual distance between the first conductive layer and the second conductive layer through the first distance, the first resistance and the second resistance; the calculation module is adapted to obtain the actual distance between the first conductive layer and the second conductive layer through the actual distance The spacing and the standard spacing between the first conductive layer and the second conductive layer are used to obtain an alignment error value between the first conductive layer and the second conductive layer.
  • An embodiment of the present application further provides an alignment error adjustment method, including: adjusting the process parameters of the yellow light process according to the alignment error value obtained by the alignment error test method as described above, so as to change the The actual spacing between the first conductive layer and the second conductive layer on the substrate of a later batch.
  • Embodiments of the present application further provide a computer-readable storage medium for storing a computer program, wherein, when the computer program program is executed by a processor, the test of the alignment error described in any one of the foregoing is implemented. method.
  • the first distance is obtained, and the first distance is the distance between the central axis of the first conductive layer and the central axis of the second conductive layer; the first resistance of the first conductive layer and the second resistance of the second conductive layer are obtained; Through the first resistance, the second resistance and the first distance, the actual distance between the first conductive layer and the second conductive layer can be obtained, and the alignment error can be obtained according to the actual distance and the standard distance. Therefore, the embodiment of the present application can test the alignment error between different conductive layers on the semiconductor structure, thereby expanding the testing range of the alignment error, and also improving the measurement accuracy of the alignment error.
  • 1 is a schematic diagram of a semiconductor structure
  • FIG. 2 is a schematic diagram of another semiconductor structure
  • FIG. 3 is a schematic diagram of a test of alignment error provided by an embodiment of the present application.
  • FIG. 4 is a top view of a substrate provided by an embodiment of the present application.
  • FIG. 5 is a test flow chart of an alignment error provided by an embodiment of the present application.
  • FIG. 6 is a functional block diagram of an alignment error testing system provided by an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a semiconductor structure including a substrate 23 and a first conductive layer 21 and a second conductive layer 22 disposed on the substrate 23 at intervals.
  • a large alignment error occurs, if the distance between the first conductive layer 21 and the second conductive layer 22 is too close, the first conductive layer 21 and the second conductive layer 22 are easily short-circuited, thereby causing the transistor to fail.
  • FIG. 2 is a schematic diagram of a semiconductor structure including a substrate 43 , a first conductive layer 41 and a second conductive layer 42 spaced on the substrate 43 , and source/drain electrodes 44 in the substrate 43 .
  • a large alignment error if the distance between the first conductive layer 41 and the second conductive layer 42 is too far, it is easy to cause the second conductive layer 42 to not be completely located on the source/drain 44, resulting in voltage transmission problems, thus Decreases the yield of semiconductor structures.
  • alignment marks are usually formed on the surface of semiconductor structures, such as dicing lines, by measuring the offset value between the alignment marks of the previous layer and the alignment marks of the latter layer on the surface of the semiconductor structure. Get the alignment error. Due to the limited number of alignment marks, each alignment mark can only be used as an alignment reference within a certain range of the semiconductor structure, but cannot be used as an alignment reference for some specific local structures in the semiconductor structure. Therefore, it is difficult to measure the alignment errors of all regions of the semiconductor structure by measuring the offset values of a few alignment marks, and it is also difficult to measure the alignment errors of some specific local structures. That is to say, with the current method of measuring the alignment marks, the number of regions on the semiconductor structure to be detected is limited, and the measurement accuracy of the alignment error of the local structure is poor.
  • An embodiment of the present application provides a method for testing alignment errors, including: obtaining a first resistance of the first conductive layer, a second resistance of the second conductive layer, and the difference between the center axis of the first conductive layer and the second conductive layer.
  • the first distance between the central axes can obtain the actual distance between the first conductive layer and the second conductive layer, and the alignment error can be obtained according to the actual distance and the standard distance. Therefore, the embodiment of the present application can test the alignment error between different conductive layers on the semiconductor structure, thereby expanding the test range of the alignment error; in addition, the alignment error of the adjacent conductive layers in the local structure can also be tested, In turn, the accuracy of the measurement of the local structure alignment error is improved.
  • FIG. 3 is a schematic diagram of the method for testing alignment errors
  • FIG. 4 is a top view of a substrate
  • FIG. 5 is a flowchart for testing alignment errors.
  • a substrate 10 is provided, and the substrate 10 has a first conductive layer 14 and a second conductive layer 13 spaced thereon, and the arrangement direction of the first conductive layer 14 and the second conductive layer 13 is the first direction Y.
  • the material of the substrate 10 may be a semiconductor such as silicon or germanium.
  • the substrate 10 further includes a source/drain 12 .
  • the source/drain 12 can be made of semiconductors such as silicon or germanium, and the semiconductor material also includes dopant ions such as boron or phosphorus.
  • the substrate 10 further includes a shallow trench isolation structure 11 .
  • the first conductive layer 14 is a gate structure, and the material of the gate structure may be a conductive material such as polysilicon or tungsten.
  • the second conductive layer 13 is a conductive contact structure, and the second conductive layer 13 is a single-layer structure.
  • the material of the second conductive layer 13 can be a conductive material such as polysilicon, copper, or silver. It should be noted that this embodiment only takes the gate structure and the conductive contact structure as examples, and does not limit the specific types of the first conductive layer 14 and the second conductive layer 13 . In other embodiments, the first conductive layer and the second conductive layer may be any two conductive structures.
  • the dielectric layer is used to isolate the first conductive layer 14 and the second conductive layer 13 to avoid electrical connection between the first conductive layer 14 and the second conductive layer 13, thereby causing problems such as leakage or short circuit.
  • the contact surface between the second conductive layer 13 and the source/drain electrode 12 may be offset, thereby reducing the size of the second conductive layer 13 Contact effect with the source/drain 12; if the actual distance between the first conductive layer 14 and the second conductive layer 13 is small, that is, the dielectric layer between the first conductive layer 14 and the second conductive layer 13 is thin, the The first conductive layer 14 and the second conductive layer 13 have the risk of short circuit and leakage, which may cause the transistor to fail.
  • the alignment error test method provided in this embodiment can more accurately measure the actual distance between the first conductive layer 14 and the second conductive layer 13.
  • the alignment error can be fed back into the fabrication process of the semiconductor structure of the subsequent batch, so that the process parameters can be adjusted so that the first conductive layer 14 and the second conductive layer 13 of the subsequent batch can have a more suitable actual spacing.
  • S1 obtain the first distance d, the first distance d is the center axis of the first conductive layer 14 perpendicular to the first direction Y and the second conductive layer 13 perpendicular to the first direction Y distance from the center axis.
  • the positioning accuracy of the central axis is higher and the positioning difficulty is lower.
  • the first distance d can be obtained by scanning electron microscopy. For example, first pre-process the semiconductor structure, make it into a size suitable for fitting into the sample holder of the instrument, and clean the surface of the semiconductor structure; after placing the semiconductor structure in the instrument, select an appropriate magnification, and Adjust the part to be measured of the semiconductor structure to the center of the field of view, and select the best conditions for shooting; select the scale indexing that is close to the length to be measured, move it to the center of the field of view, and make the scale indexing direction parallel to the direction to be measured, After focusing, shoot again; obtain the first distance d according to the magnification, the scale division, and the distance between the two central axes in the captured image.
  • S2 Obtain the first resistance of the first conductive layer 14 and the second resistance of the second conductive layer 13. For example, a certain voltage is applied to the first conductive layer 14, and the current flowing through the first conductive layer 14 under the voltage is tested. According to the voltage and current, the first resistance of the first conductive layer 14 is obtained. A certain voltage is applied to the second conductive layer 13, and the current flowing through the second conductive layer 13 at the voltage is tested. According to the voltage and current, the second resistance of the second conductive layer 13 is obtained.
  • S3 Obtain the first width a of the first conductive layer 14 and the second width r of the second conductive layer 13 .
  • the first width a of the first conductive layer 14 in the first direction Y is obtained through the first resistance
  • the second width r of the second conductive layer 13 in the first direction Y is obtained through the second resistance.
  • the resistance of the conductive structure is related to the size of the conductive structure. For example, the larger the resistance of the conductive structure is, the smaller the size of the conductive structure is; the smaller the resistance of the conductive structure is, the larger the size of the conductive structure is. Therefore, after obtaining the magnitudes of the first resistance and the second resistance, the first width a of the first conductive layer 14 and the second width r of the second conductive layer 13 can be obtained.
  • the method for obtaining the first width a includes: the first resistance and the first width a have a first correspondence, and the first width is calculated by the first resistance and the first correspondence.
  • the first resistance is related to the height of the first conductive layer 14 perpendicular to the first direction Y, the cross-sectional area of the first direction Y and the resistivity of the material.
  • R 1 ⁇ 1 L 1 /S 1 , where R 1 is the first resistance, ⁇ 1 is the resistivity of the first conductive layer 14 , and L 1 is the first conductive layer 14 in the Perpendicular to the height in the first direction Y, S 1 is the cross-sectional area in the first direction Y.
  • the cross section of the first conductive layer 14 is square or circular.
  • the first width a can be obtained.
  • L 1 can be obtained by scanning electron microscope, and ⁇ 1 needs to be determined according to the specific material of the first conductive layer 14 .
  • first width of the first conductive layer in the first direction is relatively large, a relatively accurate first width can also be measured by a scanning electron microscope at this time.
  • the method for obtaining the second width r includes: the second resistance and the second width r have a second corresponding relationship, and the second width r is calculated according to the second resistance and the second corresponding relationship. It can be understood that the second resistance is related to the height of the second conductive layer 13 perpendicular to the first direction Y, the cross-sectional area in the first direction Y, and the resistivity of the material.
  • R 2 ⁇ 2 L 2 /S 2 , where R 2 is the second resistance, ⁇ 2 is the resistivity of the second conductive layer 13 , and L 2 is the second conductive layer 13 in the Perpendicular to the height in the first direction Y, S 2 is the cross-sectional area in the first direction Y.
  • the sidewall of the second conductive layer 13 may have a certain slope, so that the area of the top surface of the second conductive layer 13 is larger than the area of the bottom surface of the second conductive layer 13 . Therefore, the cross-sectional area S 2 calculated using the above formula is not the area of the top or bottom surface of the second conductive layer 13 , but the cross-sectional area of the middle region of the second conductive layer 13 perpendicular to the first direction Y. Compared with the top surface or the bottom surface, the distance between the cross section of the middle region of the second conductive layer 13 and the first conductive layer 14 can more accurately reflect the actual distance therebetween.
  • the cross section of the second conductive layer 13 is square or circular.
  • the second width r can be obtained. It can be understood that the obtained second width r is not the width of the top surface or the bottom surface of the second conductive layer 13 , but the width of the cross section of the middle region of the second conductive layer 13 .
  • the width of the second conductive layer 13 is directly measured from above the semiconductor structure by a scanning electron microscope, a larger width value may be obtained; A pitch of the conductive layer 14 may obtain a small pitch value.
  • the width of the cross-section of the middle region of the second conductive layer 13 is used to obtain the distance between the cross-section of the middle region of the first conductive layer 14 and the second conductive layer 13, and a more accurate actual distance can be obtained.
  • S5 Obtain the alignment error value between the first conductive layer 14 and the second conductive layer 13.
  • the alignment error value between the first conductive layer 14 and the second conductive layer 13 is obtained through the actual distance x and the standard distance between the first conductive layer 14 and the second conductive layer 13.
  • the actual distance x is subtracted from the standard distance, and the obtained difference is the alignment error value.
  • FIG. 4 is a top view of the substrate, and the scribe line 16 on the substrate 10 has alignment marks 15 ; the alignment error value between the first conductive layer 14 and the second conductive layer 13 is obtained when obtaining Before, it also includes: obtaining the offset values of the alignment marks 15 in different processes.
  • the alignment mark 15 is used as an alignment reference for a certain region or some structures on the semiconductor structure.
  • the alignment mark 15 is used as an alignment reference for a transistor including the first conductive layer. 14 and the second conductive layer 13. Since the alignment mark 15 has a corresponding relationship with the transistor, so.
  • the alignment marks 15 also have a corresponding relationship with the first conductive layer 14 and the second conductive layer 13 .
  • the first conductive layer 14 and the second conductive layer 13 corresponding to the alignment mark 15 are determined by the alignment mark 15 .
  • the offset value between the first conductive layer 14 and the second conductive layer 13 measured by the alignment mark 15 can be compared with the first conductive layer 14 and the second conductive layer 13 measured by the method in this embodiment.
  • the alignment error is used as a cross-reference to improve the accuracy of the test.
  • the alignment mark 15 is first positioned to a certain area on the semiconductor structure, and then the corresponding first conductive layer 14 and the second conductive layer 13 are positioned to the corresponding first conductive layer 14 and the second conductive layer 13 through the positioned area, which can improve the test efficiency.
  • the actual distance between the first conductive layer and the second conductive layer can be obtained by obtaining the first resistance, the second resistance and the first distance, and can be obtained according to the actual distance and the standard distance. alignment error. Therefore, the present embodiment can expand the test range of the alignment error; in addition, it can also improve the measurement accuracy of the alignment error of the local area and the local structure.
  • FIG. 6 is a functional block diagram of an alignment error testing system provided in this embodiment.
  • the test system includes: a first acquisition module 31 , a second acquisition module 32 , a third acquisition module 33 and a calculation module 34 .
  • the first obtaining module 31 is adapted to obtain a first distance, which is the distance between the central axis of the first conductive layer perpendicular to the first direction and the central axis of the second conductive layer perpendicular to the first direction.
  • the first acquisition module 31 includes a scanning electron microscope through which the first distance can be acquired.
  • the second acquisition module 32 is adapted to acquire the first resistance and the second resistance.
  • the second obtaining module 32 includes an ammeter and a voltmeter, and obtains the first resistance and the second resistance through the current value obtained by the ammeter and the voltage value obtained by the voltmeter.
  • the third obtaining module 33 is adapted to obtain the actual distance between the first conductive layer and the second conductive layer through the first distance, the first resistance and the second resistance. For example, the third obtaining module 33 obtains the first width of the first conductive layer according to the first resistance, obtains the second width of the second conductive layer according to the second resistance, and obtains the actual width according to the first width, the second width and the first distance. spacing.
  • the calculation module 34 is adapted to obtain the alignment error value between the first conductive layer and the second conductive layer through the actual distance and the standard distance between the first conductive layer and the second conductive layer. For example, the calculation module 34 subtracts the actual distance from the standard distance, and the difference obtained by the subtraction is the alignment error value.
  • Yet another embodiment of the present application provides a method for adjusting an alignment error, including:
  • the process parameters of the yellow light process are adjusted to change the actual value between the first conductive layer and the second conductive layer on the substrate of the subsequent batch. spacing.
  • the subsequent production process can be optimized, thereby reducing the degree of alignment error of the first conductive layer and the second conductive layer , thereby improving the yield of subsequent semiconductor structures.
  • Still another embodiment of the present application provides a computer-readable storage medium for storing a computer program.
  • the computer program program is executed by a processor, the method for testing alignment errors in the foregoing embodiments is implemented.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes .

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Abstract

一种对准误差的测试方法、测试系统、调整方法以及计算机可读存储介质，测试方法包括：提供基底（10），基底（10）上具有间隔设置的第一导电层（14）和第二导电层（13），第一导电层（14）和第二导电层（13）的排列方向为第一方向；获取第一距离，第一距离为第一导电层（14）在垂直于第一方向上的中心轴线与第二导电层（13）在垂直于第一方向上的中心轴线的距离；获取第一导电层（14）的第一电阻和第二导电层（13）的第二电阻；根据第一距离、第一电阻和第二电阻，获取第一导电层（14）和第二导电层（13）之间的实际间距；通过实际间距以及第一导电层（14）与第二导电层（13）之间的标准间距，获取第一导电层（14）与第二导电层（13）之间的对准误差值。这种方法能够提高对准误差的测试精度。

Description

对准误差的测试方法、调整方法、测试系统和存储介质
交叉引用
本申请基于申请号为202110336244.7、申请日为2021年3月29日、申请名称为“对准误差的测试方法、调整方法、测试系统和存储介质”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及半导体领域，特别涉及一种对准误差的测试方法、调整方法、测试系统和存储介质。
背景技术
黄光制程是半导体领域中常用的制程工艺。黄光制程又称为光刻工艺，其原理为：对涂敷在玻璃表面的光敏性物质进行曝光、显影，从而形成图形化的光刻胶层，图形化的光刻胶层能够对底层的半导体结构起到保护作用。光刻后，以图形化的光刻胶层为掩膜刻蚀半导体结构，从而获得永久性的图形。在曝光之前还会进行对准操作，利用切割道上的对准标记进行对准，以使半导体结构能够与光刻的掩膜版对准，从而使得掩膜版上的图形能够精确转移到光敏性物质上。
在实际生产过程中，经常会出现低良率的半导体结构。对其进行切片和物理失效分析后发现：对准误差会影响图形的精确度，最终会影响半导体结构的性能。因此，亟需获得一种能够精确测试对准误差 的方法。
发明内容
本申请实施例提供一种对准误差的测试方法、调整方法、测试系统和存储介质，以提高测试对准误差的精确度。
本申请实施例提供一种对准误差的测试方法，包括：提供基底，所述基底上具有间隔设置的第一导电层和第二导电层，所述第一导电层和所述第二导电层的排列方向为第一方向；获取第一距离，所述第一距离为所述第一导电层在垂直于所述第一方向上的中心轴线与所述第二导电层在垂直于所述第一方向上的中心轴线的距离；获取所述第一导电层的第一电阻和所述第二导电层的第二电阻；根据所述第一距离、所述第一电阻和所述第二电阻，获取所述第一导电层和所述第二导电层之间的实际间距；通过所述实际间距以及所述第一导电层与所述第二导电层之间的标准间距，获取所述第一导电层与所述第二导电层之间的对准误差值。
本申请实施例还提供一种对准误差的测试系统，所述对准误差的测试系统适于执行如前所述的对准误差的测试方法；包括：第一获取模块、第二获取模块、第三获取模块和计算模块；所述第一获取模块适于获取所述第一距离；所述第二获取模块适于获取所述第一电阻和所述第二电阻；所述第三获取模块适于通过所述第一距离、所述第一电阻和所述第二电阻获取所述第一导电层与所述第二导电层之间的实际间距；所述计算模块适于通过所述实际间距以及所述第一导电层与所述第二导电层之间的标准间距，获取所述第一导电层与所述第二导电层之间的对准误差值。
本申请实施例还提供一种对准误差的调整方法，包括：根据如前所述的对准误差的测试方法获取的所述对准误差值，对黄光制程的工艺参数进行调整，以改变在后批次的所述基底上的所述第一导电层和所述第二导电层之间的所述实际间距。
本申请实施例还提供一种计算机可读存储介质，用于存储计算机程序，其中，所述计算机程序程序被处理器执行时，实现如前所述的任一项所述的对准误差的测试方法。
本申请实施例提供的技术方案至少具有以下优点：
本申请实施例获取第一距离，第一距离为第一导电层的中心轴线与第二导电层的中心轴线的距离；获取第一导电层的第一电阻和第二导电层的第二电阻；通过第一电阻、第二电阻和第一距离，即可获取第一导电层和第二导电层之间的实际间距，并根据实际间距和标准间距就能够获得对准误差。因此，本申请实施例能够测试半导体结构上不同导电层之间对准误差，从而扩大对准误差的测试范围，还能够提高对准误差的测量的精确度。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。
图1为一种半导体结构的示意图；
图2为另一种半导体结构的示意图；
图3为本申请实施例提供的对准误差的测试原理图；
图4为本申请实施例提供的基底的俯视图；
图5为本申请实施例提供的对准误差的测试流程图；
图6为本申请实施例提供的对准误差的测试系统的功能框图。
具体实施方式
由背景技术可知，亟需获得一种能够精确测试对准误差的方法。
参考图1，图1为一种半导体结构的示意图，包括基底23以及位于基底23上间隔设置的第一导电层21和第二导电层22。当出现较大的对准误差时，如果第一导电层21和第二导电层22距离太近，容易使得第一导电层21和第二导电层22发生短路，从而造成晶体管失效。
参考图2，图2为一种半导体结构的示意图，包括基底43、位于基底43上间隔设置的第一导电层41和第二导电层42，以及位于基底43内的源/漏极44。当出现较大的对准误差时，如果第一导电层41和第二导电层42距离太远，容易导致第二导电层42不能完全位于源/漏极44上，导致电压传输出现问题，从而降低半导体结构的良率。
经分析发现，主要原因在于：目前通常在半导体结构表面，例如切割道上，形成对准标记，通过测量半导体结构表面的前一层对准标记与后一层对准标记之间的偏移值来获取对准误差。由于设置的对准标记的数量有限，且每一对准标记只能作为半导体结构内部的一定范围内的对准参照，而无法作为半导体结构中某些特定的局部结构的对准参照。因此，通过测量少数的对准标记的偏移值很难量测到半导体结构的所有区域的对准误差，也很难量测到某些特定的局部结构的对准误差。也就是说，通过目前量测对准标记的手段，检测到半导体结构上的区域数量有限，且对局部结构的对准误差的测量精度较差。
本申请实施例提供一种对准误差的测试方法，包括：通过获取第一导电层的第一电阻、第二导电层的第二电阻，以及第一导电层的中心轴线与第二导电层的中心轴线之间的第一距离，即可获取第一导电层和第二导电层之间的实际间距，并根据实际间距和标准间距就能够获得对准误差。因此，本申请实施例能够测试半导体结构上不同导电层之间的对准误差，从而扩大对准误差的测试范围；另外，还能对局部结构内的相邻导电层的对准误差进行测试，进而提高局部结构对准 误差的测量的精确度。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
本申请一实施例提供一种对准误差的测试方法，图3为对准误差的测试方法的原理图，图4为基底的俯视图，图5为对准误差的测试流程图。以下将结合附图进行具体说明。
参考图3，提供基底10，基底10上具有间隔设置的第一导电层14和第二导电层13，第一导电层14和第二导电层13的排列方向为第一方向Y。
基底10的材料可以为硅或锗等半导体。基底10还包括源/漏极12，源/漏极12的材料可以为硅或锗等半导体，且半导体材料中还具有硼或磷等掺杂离子，基底10还包括浅沟槽隔离结构11。
一些实施例中，第一导电层14为栅极结构，栅极结构的材料可以为多晶硅或钨等导电材料。第二导电层13为导电接触结构，且第二导电层13为单层结构，第二导电层13的材料可以为多晶硅、铜或银等导电材料。值得注意的是，本实施例仅以栅极结构和导电接触结构作为示例，并不对第一导电层14和第二导电层13的具体类型进行限制。在其他实施例中，第一导电层和第二导电层可以为任意的两个导电结构。
第一导电层14和第二导电层13之间还具有介质层。介质层用于将第一导电层14和第二导电层13隔离开，以避免第一导电层14和第二导电层13电连接，从而发生漏电或短路等问题。
可以理解的是，若第一导电层14与第二导电层13的实际间距较 大，则第二导电层13与源/漏极12的接触面可能发生偏移，从而降低第二导电层13与源/漏极12的接触效果；若第一导电层14与第二导电层13的实际间距较小，即第一导电层14与第二导电层13之间的介质层较薄，则第一导电层14与第二导电层13具有短路和漏电的风险，进而可能造成晶体管失效。而本实施例提供的对准误差的测试方法能够较为准确地测量出第一导电层14和第二导电层13之间的实际间距，通过实际间距与标准间距的对照，可以获得较为精确的对准误差。可以将对准误差反馈到在后批次的半导体结构的制造工艺中，从而调整工艺参数，以使在后批次的第一导电层14和第二导电层13能够具有较为合适的实际间距。
以下将对测试方法进行具体说明。
结合参考图3和图5，S1:获取第一距离d，第一距离d为第一导电层14在垂直于第一方向Y上的中心轴线与第二导电层13在垂直于第一方向Y上的中心轴线的距离。
相比于第一导电层14和第二导电层13在垂直于第一方向Y上的其他轴线，中心轴线的定位精度更高，且定位难度更低。
一些实施例中，可以通过扫描电子显微镜来获取第一距离d。例如，首先对半导体结构进行预处理，将其制成适于装入仪器样品座内的尺寸，并对半导体结构的表面进行清洗；将半导体结构放入仪器内后，选择合适的放大倍数，并将半导体结构的待测部位调整到视场中心，选择最佳条件拍摄；选取与待测长度接近的标尺分度，将其移到视场中心，并使得标尺分度方向与待测方向平行，聚焦后再次拍摄；根据放大倍数、标尺分度以及拍摄图像中的两个中心轴线的距离来获取第一距离d。
S2:获取第一导电层14的第一电阻和第二导电层13的第二电阻。例如，对第一导电层14施加一定的电压，并测试在该电压下流经第一导电层14的电流。根据电压与电流，进而获取第一导电层14的第一电阻。对第二导电层13施加一定的电压，并测试在该电压下流经 第二导电层13的电流。根据电压与电流，进而获取第二导电层13的第二电阻。
S3:获取第一导电层14的第一宽度a和第二导电层13的第二宽度r。例如，通过第一电阻获取第一导电层14在第一方向Y上的第一宽度a；通过第二电阻获取第二导电层13在第一方向Y上的第二宽度r。
导电结构的电阻大小与导电结构的尺寸相关，例如，导电结构的电阻越大，导电结构的尺寸越小；导电结构的电阻越小，导电结构的尺寸越大。因此，在获取到第一电阻和第二电阻的大小后，可以获取到第一导电层14的第一宽度a和第二导电层13的第二宽度r。
其中，获取第一宽度a的方法包括：第一电阻与第一宽度a具有第一对应关系，通过第一电阻和第一对应关系，计算第一宽度。可以理解的是，第一电阻与第一导电层14在垂直于第一方向Y上的高度、在第一方向Y上的横截面积以及材料的电阻率有关。例如，可通过如下公式来表示：R 1＝ρ 1L 1/S 1，其中，R 1为第一电阻，ρ 1为第一导电层14的电阻率，L 1为第一导电层14在垂直于第一方向Y上的高度，S 1为在第一方向Y上的横截面积。
例如，第一导电层14的横截面为正方形或圆形。当第一导电层14的横截面为正方形时，R 1＝ρ 1L 1/a 2；当第一导电层14的横截面为圆形时，R 1＝4ρ 1L 1/(πa 2)。此时，通过R 1、ρ 1和L 1，即可获得第一宽度a。另外，L 1可以通过扫描电子显微镜来获取，ρ 1则需根据第一导电层14的具体材料来确定。
可以理解的是，在其他实施例中，若第一导电层在第一方向上的第一宽度较大时，此时通过扫描电子显微镜也可以量测出较为准确的第一宽度。
其中，获取第二宽度r的方法包括：第二电阻与第二宽度r具有第二对应关系，通过第二电阻和第二对应关系，计算第二宽度r。可以理解的是，第二电阻与第二导电层13在垂直于第一方向Y上的高 度、在第一方向Y上的横截面积以及材料的电阻率有关。例如，可通过如下公式来表示：R 2＝ρ 2L 2/S 2，其中，R 2为第二电阻，ρ 2为第二导电层13的电阻率，L 2为第二导电层13在垂直于第一方向Y上的高度，S 2为在第一方向Y上的横截面积。
在实际工艺中，第二导电层13的侧壁可能具有一定的倾斜度，从而使得第二导电层13顶面的面积大于第二导电层13的底面的面积。因此，利用上述公式计算出的横截面积S 2不是第二导电层13顶面或底面的面积，而是第二导电层13在垂直于第一方向Y上的中间区域的横截面积。相比于顶面或底面，第二导电层13中间区域的横截面与第一导电层14的间距能够更为准确地反映二者之间的实际间距。
例如，第二导电层13的横截面为正方形或圆形。当第二导电层13的横截面为正方形时，R 2＝ρ 2L 2/r 2；当第二导电层13的横截面为圆形时，R 2＝4ρ 2L 2/(πr 2)。此时，通过R 2、ρ 2和L 2，即可获得第二宽度r。可以理解的是，获得的第二宽度r不是第二导电层13顶面或底面的宽度，而是第二导电层13中间区域的横截面的宽度。
S4:获取第一导电层14和第二导电层13之间的实际距离x。例如，通过第一距离d、第一宽度a和第二宽度r，获取实际间距x，且实际间距x，第一距离d、第一宽度a和第二宽度r满足：x＝d-1/2(a+r)。图3所示的a/2为第一宽度a的1/2，r/2为第二宽度r的1/2。
值得注意的是，若直接通过扫描电子显微镜从半导体结构的上方测试第二导电层13的宽度，则可能会获取到偏大的宽度值；若直接通过扫描电子显微镜获取第二导电层13和第一导电层14的间距，则可能会获取到偏小的间距值。而本实施例通过第二导电层13中间区域的横截面的宽度，进而获取第一导电层14与第二导电层13中间区域的横截面的间距，能够获得较为精确的实际间距。
S5:获取第一导电层14和第二导电层13之间的对准误差值。例 如，通过实际间距x以及第一导电层14与第二导电层13之间的标准间距，获取第一导电层14与第二导电层13之间的对准误差值。例如，将实际间距x与标准间距相减，所获取的差值为对准误差值。
一些实施例中，参考图4，图4为基底的俯视图，基底10上的切割道16上具有对准标记15；在获取第一导电层14与第二导电层13之间的对准误差值之前，还包括：获取对准标记15在不同制程中的偏移值。
例如，通过扫描电子显微镜测量基底10上的对准标记15在第一导电层14制程中与第二导电层13中的位置偏差，获取对准标记15的偏移值，即可获得半导体结构中第一导电层14与第二导电层13之间的偏移值。
值得注意的是，对准标记15作为半导体结构上某一区域或某些结构的对准参照，一些实施例中，对准标记15作为晶体管的对准参照，且该晶体管包括了第一导电层14和第二导电层13。由于对准标记15与晶体管具有对应关系，因此。对准标记15与第一导电层14和第二导电层13也具有对应关系。
在获取了对准标记15的偏移值后，则通过对准标记15确定与对准标记15对应的第一导电层14和第二导电层13。可以将通过对准标记15的测得的第一导电层14和第二导电层13之间的偏移值与通过本实施例中的方法测得的第一导电层14和第二导电层13的对准误差作为相互参照，以提高测试的准确性。另外，先通过对准标记15定位到半导体结构上的某一区域，再通过定位的区域，定位到相应的第一导电层14和第二导电层13，可以提高测试的效率。
综上所述，本实施例通过获取第一电阻、第二电阻和第一距离，即可获取第一导电层和第二导电层之间的实际间距，并根据实际间距和标准间距就能够获得对准误差。因此，本实施例能够扩大对准误差的测试范围；另外，还能提高局部区域和局部结构的对准误差的测量精确度。
本申请另一实施例提供一种对准误差的测试系统，对准误差的测试系统适于执行如前述实施例中的对准误差的测试方法。图6为本实施例提供的对准误差的测试系统的功能框图。参考图6，测试系统包括：第一获取模块31、第二获取模块32、第三获取模块33和计算模块34。
其中，第一获取模块31适于获取第一距离，第一距离为第一导电层在垂直于第一方向上的中心轴线与第二导电层在垂直于第一方向上的中心轴线的距离。第一获取模块31包括扫描电子显微镜，通过扫描电子显微镜可获取第一距离。
第二获取模块32适于获取第一电阻和第二电阻。第二获取模块32包括电流表和电压表，通过电流表所获取到的电流值和电压表所获取到的电压值，获取第一电阻和第二电阻。
第三获取模块33适于通过第一距离、第一电阻和第二电阻获取第一导电层与第二导电层之间的实际间距。例如，第三获取模块33根据第一电阻获取第一导电层的第一宽度，根据第二电阻获取第二导电层的第二宽度，并根据第一宽度、第二宽度和第一距离获取实际间距。
计算模块34适于通过实际间距以及第一导电层与第二导电层之间的标准间距，获取第一导电层与第二导电层之间的对准误差值。例如，计算模块34将实际间距与标准间距相减，相减所得到的差值为对准误差值。
本申请又一实施例提供一种对准误差的调整方法，包括：
根据如前述的对准误差的测试方法获取的对准误差值，对黄光制程的工艺参数进行调整，以改变在后批次的基底上的第一导电层和第二导电层之间的实际间距。
换句话说，通过在前批次的第一导电层和第二导电层的对准误差值，可以对后续的生产工艺进行优化，从而降低第一导电层和第二导 电层的对准误差程度，从而提高后续半导体结构的良率。
本申请再一实施例提供一种计算机可读存储介质，用于存储计算机程序，计算机程序程序被处理器执行时，实现前述实施例中的对准误差的测试方法。
可以理解的是，实现上述实施例方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序存储在一个存储介质中，包括若干指令用以使得一个设备或处理器执行测试方法中的各个步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-0nly Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (15)

  1. 一种对准误差的测试方法，包括：
    提供基底，所述基底上具有间隔设置的第一导电层和第二导电层，所述第一导电层和所述第二导电层的排列方向为第一方向；
    获取第一距离，所述第一距离为所述第一导电层在垂直于所述第一方向上的中心轴线与所述第二导电层在垂直于所述第一方向上的中心轴线的距离；
    获取所述第一导电层的第一电阻和所述第二导电层的第二电阻；
    根据所述第一距离、所述第一电阻和所述第二电阻，获取所述第一导电层和所述第二导电层之间的实际间距；
    通过所述实际间距以及所述第一导电层与所述第二导电层之间的标准间距，获取所述第一导电层与所述第二导电层之间的对准误差值。
  2. 根据权利要求1所述的对准误差的测试方法，其中，获取所述第一电阻和所述第二电阻后，还包括：通过所述第一电阻获取所述第一导电层在所述第一方向上的第一宽度；通过所述第二电阻获取所述第二导电层在所述第一方向上的第二宽度。
  3. 根据权利要求2所述的对准误差的测试方法，其中，所述第一导电层和所述第二导电层之间的所述实际间距的获取方法包括：通过所述第一距离、所述第一宽度和所述第二宽度，获取所述实际间距，且所述实际间距、所述第一距离、所述第一宽度和所述第二宽度满足：
    x＝d-1/2(a+r)，其中，x为所述实际间距，a为所述第一宽度，r 为所述第二宽度，d为所述第一距离。
  4. 根据权利要求2所述的对准误差的测试方法，其中，获取所述第一宽度的方法包括：所述第一电阻与所述第一宽度具有第一对应关系，通过所述第一电阻和所述第一对应关系，计算所述第一宽度。
  5. 根据权利要求4所述的对准误差的测试方法，其中，所述第一导电层为栅极结构。
  6. 根据权利要求2所述的对准误差的测试方法，其中，获取所述第二宽度的方法包括：所述第二电阻与所述第二宽度具有第二对应关系，通过所述第二电阻和所述第二对应关系，计算所述第二宽度。
  7. 根据权利要求6所述的对准误差的测试方法，其中，所述第二导电层为导电接触结构。
  8. 根据权利要求6所述的对准误差的测试方法，其中，所述第二导电层在所述第一方向上的剖面形状为圆形，且所述第二对应关系为：R 2＝4ρ 2L 2/(πr 2)，其中，R 2为所述第二电阻，ρ 2为所述第二导电层的电阻率，L 2为所述第二导电层在垂直于所述第一方向上的高度，r为所述第二宽度。
  9. 根据权利要求6所述的对准误差的测试方法，其中，所述第二导电层在所述第一方向的剖面形状为正方形，且所述第二对应关系为：R 2＝ρ 2L 2/r 2，其中，R 2为所述第二电阻，ρ 2为所述第二导电层的电阻率，L 2为所述第二导电层在垂直于所述第一方向上的高度，r为所述第二宽度。
  10. 根据权利要求1所述的对准误差的测试方法，其中，通过扫 描电子显微镜获取所述第一距离。
  11. 根据权利要求1所述的对准误差的测试方法，其中，所述基底上具有对准标记；在获取所述第一导电层与所述第二导电层之间的所述对准误差值之前，还包括：
    获取所述对准标记在不同制程中的偏移值。
  12. 根据权利要求11所述的对准误差的测试方法，其中，所述对准标记与所述第一导电层和所述第二导电层具有对应关系，通过所述对准标记确定与所述对准标记对应的所述第一导电层和所述第二导电层。
  13. 一种对准误差的测试系统，所述对准误差的测试系统适于执行如权利要求1-12所述的对准误差的测试方法；包括：
    第一获取模块、第二获取模块、第三获取模块和计算模块；
    所述第一获取模块适于获取所述第一距离；
    所述第二获取模块适于获取所述第一电阻和所述第二电阻；
    所述第三获取模块适于通过所述第一距离、所述第一电阻和所述第二电阻获取所述第一导电层与所述第二导电层之间的所述实际间距；
    所述计算模块适于通过所述实际间距以及所述第一导电层与所述第二导电层之间的所述标准间距，获取所述第一导电层与所述第二导电层之间的所述对准误差值。
  14. 一种对准误差的调整方法，包括：
    根据如权利要求1-12所述的对准误差的测试方法获取的所述对 准误差值，对黄光制程的工艺参数进行调整，以改变在后批次的所述基底上的所述第一导电层和所述第二导电层之间的所述实际间距。
  15. 一种计算机可读存储介质，用于存储计算机程序，所述计算机程序程序被处理器执行时，实现权利要求1-12任一项所述的对准误差的测试方法。
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