WO2022227167A1 - 显示面板及其制备方法 - Google Patents

显示面板及其制备方法 Download PDF

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Publication number
WO2022227167A1
WO2022227167A1 PCT/CN2021/096445 CN2021096445W WO2022227167A1 WO 2022227167 A1 WO2022227167 A1 WO 2022227167A1 CN 2021096445 W CN2021096445 W CN 2021096445W WO 2022227167 A1 WO2022227167 A1 WO 2022227167A1
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Prior art keywords
layer
electrode
gate
display panel
source
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English (en)
French (fr)
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卢马才
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US17/419,729 priority Critical patent/US12289957B2/en
Publication of WO2022227167A1 publication Critical patent/WO2022227167A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/425—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer having different crystal properties in different TFTs or within an individual TFT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a manufacturing method thereof.
  • OLED Organic Light-Emitting Diode, Organic Light Emitting Diode
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light Emitting Diode
  • display panels are widely used because they can realize flexible display by self-emission.
  • at least two thin film transistors are used to control the pixels for display, and in order to reduce the power consumption of the display panel, low temperature polysilicon thin film transistors are used as driving transistors, and oxide thin film transistors are used as transistors for controlling capacitance potential.
  • the display panel has many process steps, which affects the stability of the oxide thin film transistors and causes the display panel. Poor display occurs.
  • the existing display panel manufacturing method has a technical problem of many process steps.
  • Embodiments of the present application provide a display panel and a manufacturing method thereof, so as to alleviate the technical problem of many process steps in the existing display panel manufacturing method.
  • An embodiment of the present application provides a display panel, the display panel includes:
  • a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines are cross-insulated and arranged to form a plurality of sub-pixels arranged in an array, and each of the sub-pixels is provided with at least a first a thin film transistor, a second thin film transistor, a pixel capacitor, a power supply terminal and a light-emitting unit;
  • the first thin film transistor includes a low temperature polysilicon thin film transistor, the low temperature polysilicon thin film transistor includes a first gate electrode, a first source electrode and a first drain electrode, the first gate electrode is connected to the pixel capacitor, and the first gate electrode is connected to the pixel capacitor. a source is connected to the power terminal, and the first drain is connected to the light-emitting unit;
  • the second thin film transistor includes an oxide thin film transistor, the oxide thin film transistor includes a second gate electrode, a second source electrode and a second drain electrode, the second gate electrode is connected to the gate line, and the A second source electrode is connected to the data line, and the second drain electrode is connected to the first gate electrode;
  • first source electrode, the first drain electrode, the second source electrode and the second drain electrode are arranged in the same layer, and the first source electrode and the first drain electrode and the second source electrode and the second drain electrode are arranged in the same layer. poles are insulated from each other.
  • the display panel further includes a substrate
  • the low temperature polysilicon thin film transistor includes a first active layer on the substrate
  • the first gate electrode is disposed on the first active layer one side
  • the first source electrode and the first drain electrode are disposed on the side of the first active layer away from the substrate
  • the first source electrode and the first drain electrode are connected to the first source electrode and the first drain electrode. source layer connection.
  • the oxide thin film transistor includes a second active layer on the substrate, the second gate is disposed on a side of the second active layer away from the substrate, The second source electrode and the second drain electrode are disposed under the second active layer, and the second gate electrode is disposed on a side of the second active layer away from the second source electrode.
  • the display panel includes:
  • a first insulating layer disposed on the first source electrode and the first drain electrode
  • a second insulating layer disposed on the second source electrode and the second drain electrode
  • first insulating layer and the second insulating layer are provided separately.
  • the display panel further includes:
  • a first gate insulating layer disposed on the side of the first active layer away from the substrate;
  • a first gate layer disposed on a side of the first gate insulating layer away from the first active layer, and the first gate layer includes a first gate;
  • an interlayer insulating layer disposed on the side of the first gate layer away from the first gate insulating layer;
  • a source and drain layer disposed on a side of the interlayer insulating layer away from the first gate layer
  • a first passivation layer disposed on the side of the source and drain layers away from the interlayer insulating layer
  • a second active layer disposed on the side of the first passivation layer away from the source and drain layers;
  • a second gate insulating layer disposed on the side of the second active layer away from the first passivation layer
  • a second gate layer disposed on a side of the second gate insulating layer away from the second active layer, the second gate layer includes a second gate and a gate line;
  • a second passivation layer disposed on the side of the second gate layer away from the second gate insulating layer
  • the source-drain layer includes a first source electrode, a first drain electrode, a second source electrode, a second drain electrode and a data line.
  • the first passivation layer is disposed on the first source electrode and the first drain electrode, and the first passivation layer extends to the second source electrode and the second drain electrode .
  • the second gate and the projections of the second source and the second drain on the substrate have an overlapping portion, and an area of the overlapping portion is greater than or equal to a threshold.
  • the threshold is 2 microns.
  • the display panel further includes a buffer layer disposed between the substrate and the first active layer.
  • the material of the buffer layer includes silicon oxide, silicon nitride, silicon oxynitride, a stack of silicon oxide and silicon nitride, or a mixed material.
  • the material of the first active layer includes polysilicon.
  • the material of the first gate layer includes molybdenum, molybdenum aluminum laminate, molybdenum copper laminate, molybdenum titanium alloy and copper laminate, titanium aluminum titanium laminate, titanium copper titanium laminate, molybdenum / Copper/Indium Zinc Oxide Laminate, Indium Zinc Oxide/Copper/Indium Zinc Oxide Laminate, Molybdenum/Cu/Indium Tin Oxide Laminate, Nickel/Cu/Nickel Laminate, Molybdenum-Nitinol/Cu/Molybdenum-Nitinol Laminates, NiCr/Cu/NiCr, TiNi/Cu/TiNi, TiCr/Cu/TiCr, Niobium Cu.
  • the low temperature polysilicon thin film transistor includes an N-type transistor and a P-type transistor.
  • the material of the interlayer insulating layer includes silicon oxide, silicon nitride, and silicon oxynitride.
  • the material of the source and drain layers includes molybdenum, molybdenum-aluminum stack, molybdenum-copper stack, molybdenum-titanium alloy/copper stack, molybdenum-titanium alloy/copper/molybdenum-titanium alloy, titanium-aluminum-titanium Laminates, Titanium Copper Titanium Laminates, Molybdenum/Copper/Indium Zinc Oxide Laminates, Indium Zinc Oxide/Cu/Indium Zinc Oxide Laminates, Molybdenum/Cu/Indium Tin Oxide Laminates, Nickel/Cu/Nickel Laminates, Molybdenum Nitinol/Copper/Molybdenum Nitinol Laminate, NiCr/Cu/NiCr, TiNi/Cu/TiNi, TiCr/Cu/TiCr, Niobium Cu.
  • the material of the first passivation layer includes silicon oxide, silicon oxide/silicon nitride stack, and aluminum oxide/silicon oxide stack.
  • the material of the second active layer includes indium gallium zinc oxide, indium gallium tin oxide, indium gallium oxide, indium zinc oxide, zinc aluminum oxide, and zinc aluminum tin oxide.
  • the pixel capacitor includes a first electrode plate and a second electrode plate, the first electrode plate and the first grid electrode are arranged in the same layer, and the second electrode plate and the second grid electrode are arranged in the same layer. Very homogenous settings.
  • the pixel capacitor includes a first electrode plate and a second electrode plate, the first electrode plate and the second source electrode are disposed in the same layer, and the second electrode plate and the second gate electrode are arranged in the same layer. Very homogenous settings.
  • an embodiment of the present application provides a method for manufacturing a display panel.
  • the method for manufacturing a display panel includes:
  • a first gate layer is formed on the first gate insulating layer; the first gate layer includes a first gate;
  • a source and drain layer is formed on the interlayer insulating layer, and the source and drain layers are patterned to form a first source electrode, a first drain electrode, a second source electrode, a second drain electrode and a data line; A source electrode and a second drain electrode are connected to the first active layer through a first via hole;
  • a pixel electrode layer is formed on the second passivation layer, and the pixel electrode layer is patterned to form a pixel electrode; the pixel electrode is connected to the first electrode through the second via hole.
  • the present application provides a display panel and a manufacturing method thereof.
  • the display panel includes a plurality of gate lines and a plurality of data lines, and the plurality of gate lines and the plurality of data lines are cross-insulated and arranged to form a plurality of sub-pixels arranged in an array.
  • Each sub-pixel is provided with at least a first thin film transistor, a second thin film transistor, a pixel capacitor, a power supply terminal and a light-emitting unit; wherein, the first thin film transistor includes a low temperature polysilicon thin film transistor, and the low temperature polysilicon thin film transistor includes a first gate, a first A source electrode and a first drain electrode, the first gate electrode is connected to the pixel capacitor, the first source electrode is connected to the power supply terminal, the first drain electrode is connected to the light emitting unit, the second thin film transistor includes an oxide thin film transistor, an oxide thin film transistor It includes a second gate, a second source and a second drain, the second gate is connected to the gate line, the second source is connected to the data line, and the second drain is connected to the first gate, wherein the first The source electrode, the first drain electrode, the second source electrode and the second drain electrode are arranged in the same layer, and the first source electrode and the first drain electrode and the second source electrode and the second drain electrode are insulated from each other.
  • the first source electrode and the first drain electrode of the low temperature polysilicon thin film transistor are arranged in the same layer as the second source electrode and the second drain electrode of the oxide thin film transistor, so that when the low temperature polysilicon thin film transistor and the oxide thin film transistor are formed, , the process steps of the display panel can be reduced, so that the stability of the oxide thin film transistor can be improved, the channel length of the oxide thin film transistor can be shortened accordingly, the resolution of the display panel can be improved, and the display failure of the display panel can be avoided.
  • the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are arranged in the same layer, which can reduce the thickness of the display panel.
  • FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present application.
  • FIG. 2 is a first schematic circuit diagram of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a second circuit of the display panel provided by the embodiment of the present application.
  • FIG. 4 is a flowchart of a method for fabricating a display panel provided by an embodiment of the present application.
  • FIG. 5 is a first schematic diagram of a display panel corresponding to each step of the method for manufacturing a display panel provided by an embodiment of the present application.
  • FIG. 6 is a second schematic diagram of a display panel corresponding to each step of the method for manufacturing a display panel provided by an embodiment of the present application.
  • FIG. 7 is a third schematic diagram of a display panel corresponding to each step of the method for manufacturing a display panel provided by an embodiment of the present application.
  • FIG. 8 is a fourth schematic diagram of a display panel corresponding to each step of the method for manufacturing a display panel provided by an embodiment of the present application.
  • the embodiments of the present application provide a display panel and a manufacturing method thereof for alleviating the above-mentioned technical problems in view of the technical problem of the existing display panel manufacturing method that the existing display panel manufacturing method has many process steps.
  • an embodiment of the present application provides a display panel, the display panel includes a plurality of gate lines Vscan and a plurality of data lines Vdata, the plurality of gate lines Vscan and the plurality of data lines
  • the lines Vdata are arranged in a cross and form a plurality of sub-pixels 10 arranged in an array, and each of the sub-pixels 10 is provided with at least a first thin film transistor T1, a second thin film transistor T2, a pixel capacitor C, a power supply terminal VDD and a light emitting unit LED; in,
  • the first thin film transistor T1 includes a low temperature polysilicon thin film transistor 31, the low temperature polysilicon thin film transistor 31 includes a first gate 15, a first source 231 and a first drain 232, and the first gate is connected to the pixel.
  • the capacitor C is connected, the first source is connected to the power supply terminal VDD, and the first drain is connected to the light-emitting unit LED;
  • the second thin film transistor T2 includes an oxide thin film transistor 32, the oxide thin film transistor 32 includes a second gate electrode 20, a second source electrode 233 and a second drain electrode 234, the second gate electrode is connected to the gate the pole line Vscan is connected, the second source is connected to the data line Vdata, and the second drain is connected to the first gate;
  • first source electrode 231, the first drain electrode 232, the second source electrode 233 and the second drain electrode 234 are arranged in the same layer, and the first source electrode 231 and the first drain electrode 232 and the second drain electrode 231 are arranged in the same layer.
  • the source electrode 233 and the second drain electrode 234 are insulated from each other.
  • An embodiment of the present application provides a display panel, in which the first source electrode and the first drain electrode of the low temperature polysilicon thin film transistor are arranged in the same layer as the second source electrode and the second drain electrode of the oxide thin film transistor, so that the process steps of the display panel can be reduced, so that the stability of the oxide thin film transistor can be improved, the channel length of the oxide thin film transistor can be correspondingly shortened, and the resolution of the display panel can be improved. , and avoid poor display on the display panel.
  • the mutual isolation between the first source electrode and the first drain electrode and the second source electrode and the second drain electrode means that the first source electrode is insulated from the second source electrode and the second drain electrode, and the first drain electrode is insulated from the second source electrode and the second drain electrode.
  • the second source electrode and the second drain electrode are insulated, while the first source electrode and the first drain electrode of the low temperature polysilicon thin film transistor and the second source electrode and the second drain electrode of the oxide thin film transistor are turned on when realizing the function of the transistor.
  • the signal terminal VSS may be the negative pole of the power supply, or may be the ground terminal.
  • the low temperature polysilicon thin film transistor is used to drive the light-emitting unit to emit light
  • the oxide thin film transistor is used to control the capacitance potential
  • each sub-pixel includes a first thin film transistor, a second thin film transistor, a pixel capacitor, a power supply terminal and a light-emitting unit, and when the scan line and the data line provide a high level, the second gate of the second thin film transistor It is turned on, and the data voltage provided by the data line passes through the second thin film transistor to charge the pixel capacitor, and the first gate of the first thin film transistor is turned on.
  • the light-emitting unit emits light, and when the scan line is at a low level, the pixel capacitor continues to provide a voltage to the first gate of the first thin film transistor, so that the light-emitting unit continues to emit light.
  • each sub-pixel includes a 3T1C circuit.
  • the drive circuit can also be a 3T1C circuit or a 7T1C circuit, for example, as shown in FIG. 3 , each sub-pixel includes a 3T1C circuit.
  • a third thin film transistor T3 is added, and the second thin film transistor T2 and the third thin film transistor T3 are respectively controlled by the first gate line Vscan1 and the second gate line Vscan2
  • the 3T1C circuit By setting the 3T1C circuit, the threshold voltage of the first thin film transistor T1 is compensated, and the brightness uniformity of the display panel is improved.
  • the display panel further includes a substrate 11
  • the low temperature polysilicon thin film transistor 31 includes a first active layer 13 located on the substrate 11 , the first active layer 13 .
  • the gate electrode 15 is disposed on the side of the first active layer 13 away from the substrate 11
  • the first source electrode 231 and the first drain electrode 232 are disposed on the first active layer 13 away from the substrate one side of the bottom 11
  • the first source electrode 231 and the first drain electrode 232 are connected to the first active layer 13 .
  • the low temperature polysilicon thin film transistor includes a first active layer on the substrate, and the first gate is disposed on a side of the first active layer close to the substrate , the first source electrode and the first drain electrode are arranged on the side of the first active layer away from the substrate, and the first source electrode and the first drain electrode are connected to the first source electrode and the first drain electrode. source layer connection.
  • the gate and source and drain of the low temperature polysilicon thin film transistor can also be arranged on both sides, and the embodiment of the present application is not limited to this. Requirement settings.
  • the oxide thin film transistor 32 includes a second active layer 18 on the substrate 11 , and the second gate 20 is disposed on the second active layer 18 .
  • the side of the source layer 18 away from the substrate 11, the second source electrode 233 and the second drain electrode 234 are arranged under the second active layer 18, and the second gate electrode 20 is arranged at the bottom of the second active layer 18.
  • a side of the second active layer 18 away from the second source electrode 233 is provided.
  • the process steps are reduced, thereby reducing the possibility of being affected in the preparation process of the oxide thin film transistor, and improving the device stability. Therefore, the channel of the oxide thin film transistor is shortened, and by arranging the second gate, the second source and the second drain on both sides of the second active layer, the second source and the second drain are The area of the overlapping portion with the second gate can be increased, so that the size of the oxide thin film transistor can be reduced, the frame can be reduced, and the resolution of the display panel can be improved.
  • the display panel includes:
  • a first insulating layer disposed on the first source electrode and the first drain electrode
  • a second insulating layer disposed on the second source electrode and the second drain electrode
  • the first insulating layer and the second insulating layer are provided separately.
  • the first insulating layer and the second insulating layer can be provided separately, so as to avoid the short circuit of the metal layer in the display panel.
  • the display panel further includes:
  • the first gate insulating layer 14 is disposed on the side of the first active layer 13 away from the substrate 11;
  • the first gate layer 15 is disposed on the side of the first gate insulating layer 14 away from the first active layer 13 , and the first gate layer 15 includes a first gate 15 (the first gate The layer and the first gate use the same reference numeral 15);
  • the interlayer insulating layer 16 is disposed on the side of the first gate layer 15 away from the first gate insulating layer 14;
  • the source and drain layers 23 are disposed on the side of the interlayer insulating layer 16 away from the first gate layer 15;
  • the first passivation layer 17 is disposed on the side of the source-drain layer 23 away from the interlayer insulating layer 16;
  • the second active layer 18 is disposed on the side of the first passivation layer 17 away from the source and drain layers 23;
  • the second gate insulating layer 19 is disposed on the side of the second active layer 18 away from the first passivation layer 17;
  • the second gate layer 20 is disposed on the side of the second gate insulating layer 19 away from the second active layer 18 , and the second gate layer 20 includes a second gate 20 and a gate line ( The second gate layer and the second gate use the same reference numeral 20);
  • the second passivation layer 21 is disposed on the side of the second gate layer 20 away from the second gate insulating layer 19;
  • the source-drain layer 23 includes a first source electrode 231 , a first drain electrode 232 , a second source electrode 233 , a second drain electrode 234 and a data line.
  • the source and drain layers are patterned to obtain a first source electrode, a first drain electrode, a second source electrode and a second drain electrode, so that the source and drain electrodes of the low temperature polysilicon thin film transistor and the source and drain electrodes of the oxide thin film transistor are Both are arranged on the source and drain layers, thereby reducing the process steps of the display panel. Only one process is required for the source and drain layers to form the source and drain of the low-temperature polysilicon thin film transistor and the source and drain of the oxide thin film transistor, which improves the oxidation rate. stability of thin-film transistors.
  • the first passivation layer 17 is disposed on the first source electrode 231 and the first drain electrode 232 , and the first passivation layer 17 extends to the On the second source electrode 233 and the second drain electrode 234, that is, by changing the passivation layer on the low temperature polysilicon thin film transistor and the interlayer insulating layer of the oxide thin film transistor into a first passivation layer, the display panel
  • the process steps can be further reduced, the stability of the oxide thin film transistor can be further improved, and since the first passivation layer is used as the passivation layer on the low temperature polysilicon thin film transistor and the interlayer insulation of the oxide thin film transistor respectively layer, which can reduce the thickness of the display panel.
  • the second gate and the projections of the second source and the second drain on the substrate have an overlapping portion, and an area of the overlapping portion is greater than or equal to a threshold. Since the second gate, the second source and the second drain are respectively disposed on both sides of the second active layer, and the source and drain layers are disposed at the bottom of the second active layer, the second gate and the second source can be The overlapping portion of the electrode and the second drain increases, correspondingly reducing the size of the oxide thin film transistor, thereby improving the resolution of the display panel and the resolution of the display panel.
  • the threshold is 2 microns, but the embodiments of the present application are not limited to this, and the threshold is set according to requirements when the stability of the oxide thin film transistor is not affected.
  • the pixel capacitor includes a first electrode plate and a second electrode plate, the first electrode plate and the first gate electrode are arranged in the same layer, and the second electrode plate and the second electrode plate are arranged in the same layer.
  • the gate is set on the same layer.
  • the pixel capacitor includes a first electrode plate and a second electrode plate, the first electrode plate and the second source electrode are arranged in the same layer, and the second electrode plate and the second electrode plate are arranged in the same layer.
  • the gate is set on the same layer.
  • the display panel further includes a buffer layer 12 disposed between the substrate 11 and the first active layer 13 .
  • the material of the buffer layer includes silicon oxide, silicon nitride, silicon oxynitride, a stack or a mixed material of silicon oxide and silicon nitride.
  • the material of the first active layer includes polysilicon, and the polysilicon is prepared by laser annealing crystallization of amorphous silicon or other crystallization methods.
  • the material of the first gate insulating layer includes silicon oxide, silicon nitride, aluminum oxide, a stack of silicon oxide and silicon nitride or a mixed material, a stack of silicon oxide and silicon nitride or mixed materials.
  • the material of the first gate layer includes molybdenum, molybdenum-aluminum laminate, molybdenum-copper laminate, molybdenum-titanium alloy and copper laminate, titanium-aluminum-titanium laminate, titanium-copper-titanium laminate, Molybdenum/Copper/Indium Zinc Oxide Laminate, Indium Zinc Oxide/Cu/Indium Zinc Oxide Laminate, Molybdenum/Cu/Indium Tin Oxide Laminate, Nickel/Cu/Nickel Laminate, Molybdenum-Nitinol/Cu/Molybdenum-Nitinol Alloy Lamination, Nichrome/Cu/NiCr, TiNi/Cu/TiNi, TiCr/Cu/TiCr, Niobium Cu.
  • the low temperature polysilicon thin film transistor includes an N-type transistor and a P-type transistor.
  • the material of the interlayer insulating layer includes silicon oxide, silicon nitride, and silicon oxynitride.
  • the material of the source and drain layers includes molybdenum, molybdenum-aluminum laminate, molybdenum-copper laminate, molybdenum-titanium alloy/copper laminate, molybdenum-titanium alloy/copper/molybdenum-titanium alloy Dezen, titanium-aluminum-titanium laminate layer, titanium copper titanium laminate, molybdenum/copper/indium zinc oxide laminate, indium zinc oxide/copper/indium zinc oxide laminate, molybdenum/copper/indium tin oxide laminate, nickel/copper/nickel laminate, molybdenum nickel Titanium/Copper/Molybdenum-Nitinol Laminate, Nichrome/Cu/NiCr, Titanium/Cu/TiNi, Titanium/Copper/Ti-Cr laminate, Niobium-Cu alloy.
  • the material of the first passivation layer includes silicon oxide, silicon oxide/silicon nitride stack, and aluminum oxide/silicon oxide stack.
  • the material of the second active layer includes indium gallium zinc oxide, indium gallium tin oxide, indium gallium oxide, indium zinc oxide, zinc aluminum oxide, and zinc aluminum tin oxide.
  • the material of the second gate insulating layer includes silicon oxide, silicon nitride, aluminum oxide, a stack of silicon oxide and silicon nitride or a mixed material, a stack of silicon oxide and silicon nitride or mixed materials.
  • the material of the second gate layer includes molybdenum, molybdenum-aluminum laminate, molybdenum-copper laminate, molybdenum-titanium alloy and copper laminate, titanium-aluminum-titanium laminate, titanium-copper-titanium laminate, Molybdenum/Copper/Indium Zinc Oxide Laminate, Indium Zinc Oxide/Cu/Indium Zinc Oxide Laminate, Molybdenum/Cu/Indium Tin Oxide Laminate, Nickel/Cu/Nickel Laminate, Molybdenum-Nitinol/Cu/Molybdenum-Nitinol Alloy Laminate, Nichrome/Cu/NiCr, TiNi/Cu/TiNi, TiCr/Cu/TiCr, Niobium Cu.
  • the material of the second passivation layer includes silicon oxide, silicon oxide/silicon nitride stack, and aluminum oxide/silicon oxide stack.
  • the display panel further includes pixel electrodes 22 .
  • the material of the pixel electrode includes indium tin oxide, indium zinc oxide, indium tin oxide/silver/indium tin oxide stack, indium zinc oxide/silver/indium tin oxide stack, molybdenum copper stack , Molybdenum-titanium alloy/copper/molybdenum-titanium alloy stack.
  • an embodiment of the present application provides a method for fabricating a display panel, and the method for fabricating a display panel includes:
  • a first active layer is formed on the substrate; the structure of the display panel is shown in (a) of FIG. 5 ;
  • a first gate layer is formed on the first gate insulating layer; the first gate layer includes a first gate; the structure of the display panel is shown in (c) of FIG. 5 ;
  • An embodiment of the present application provides a method for fabricating a display panel.
  • the source and drain layers are patterned to form a first source electrode, a first drain electrode, a second source electrode and a second drain electrode, so that the source and drain electrodes of the low temperature polysilicon thin film transistor are formed.
  • the source and drain electrodes of the oxide thin film transistor are arranged in the same layer, which reduces the process steps of the source and drain layers.
  • the first passivation layer is used as the passivation layer of the low temperature polysilicon thin film transistor and the interlayer insulation of the oxide thin film transistor.
  • the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are arranged in the same layer, and the first passivation layer serves as the passivation layer of the low temperature polysilicon thin film transistor and the interlayer insulating layer of the oxide thin film transistor, which can reduce the Displays the thickness of the panel.
  • Embodiments of the present application provide a display panel and a method for fabricating the same.
  • the display panel includes a plurality of gate lines and a plurality of data lines, and the plurality of gate lines and the plurality of data lines are cross-insulated and arranged to form a plurality of arrays.
  • each sub-pixel is provided with at least a first thin film transistor, a second thin film transistor, a pixel capacitor, a power supply terminal and a light-emitting unit;
  • the first thin film transistor includes a low temperature polysilicon thin film transistor
  • the low temperature polysilicon thin film transistor includes a first gate , a first source and a first drain
  • the first gate is connected to the pixel capacitor
  • the first source is connected to the power supply terminal
  • the first drain is connected to the light-emitting unit
  • the second thin film transistor includes an oxide thin film transistor
  • the oxide The thin film transistor includes a second gate electrode, a second source electrode and a second drain electrode, the second gate electrode is connected to the gate line
  • the second source electrode is connected to the data line
  • the second drain electrode is connected to the first gate electrode
  • the first source electrode and the first drain electrode of the low temperature polysilicon thin film transistor are arranged in the same layer as the second source electrode and the second drain electrode of the oxide thin film transistor, so that when the low temperature polysilicon thin film transistor and the oxide thin film transistor are formed, , the process steps of the display panel can be reduced, so that the stability of the oxide thin film transistor can be improved, the channel length of the oxide thin film transistor can be shortened accordingly, the resolution of the display panel can be improved, and the display failure of the display panel can be avoided.
  • the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are arranged in the same layer, which can reduce the thickness of the display panel.
  • a display panel and a manufacturing method thereof provided by the embodiments of the present application have been described in detail above, and the principles and implementations of the present application are described with specific examples.
  • the technical solution of the application and its core idea; those of ordinary skill in the art should understand that: it can still make modifications to the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements to some of the technical features; and these modifications or replacements,
  • the essence of the corresponding technical solutions does not deviate from the scope of the technical solutions of the embodiments of the present application.

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Abstract

一种显示面板及其制备方法，显示面板通过将低温多晶硅薄膜晶体管（31）的第一源极（231）和第一漏极（232）与氧化物薄膜晶体管（32）的第二源极（233）和第二漏极（234）同层设置，能够减少显示面板的工艺步骤，从而可以提高氧化物薄膜晶体管（32）的稳定性，相应可以减短氧化物薄膜晶体管（32）的沟道长度，提高显示面板的解析度，降低显示面板的厚度。

Description

显示面板及其制备方法 技术领域
本申请涉及显示技术领域，尤其是涉及一种显示面板及其制备方法。
 背景技术
OLED（Organic Light-Emitting Diode，有机发光二极管）显示面板由于自发光可以实现柔性显示被广泛应用。在显示面板的驱动过程中，会采用至少两个薄膜晶体管控制像素进行显示，且为了降低显示面板的功耗，会采用低温多晶硅薄膜晶体管作为驱动晶体管，采用氧化物薄膜晶体管作为控制电容电位的晶体管。但在现有采用低温多晶硅和氧化物薄膜晶体管的显示面板中，由于低温多晶硅和氧化物薄膜晶体管需要分开制备，导致显示面板的工艺步骤较多，影响氧化物薄膜晶体管的稳定性，导致显示面板出现显示不良。
所以，现有显示面板制备方法存在工艺步骤较多的技术问题。
 技术问题
本申请实施例提供一种显示面板及其制备方法，用以缓解现有显示面板制备方法存在工艺步骤较多的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，该显示面板包括：
多条栅极线和多条数据线，所述多条栅极线与所述多条数据线交叉绝缘排布并形成阵列排布的多个子像素，各所述子像素中至少设有第一薄膜晶体管、第二薄膜晶体管、像素电容、电源端和发光单元；其中，
所述第一薄膜晶体管包括低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管包括第一栅极、第一源极和第一漏极，所述第一栅极与所述像素电容连接，所述第一源极与所述电源端连接，所述第一漏极与所述发光单元连接；
所述第二薄膜晶体管包括氧化物薄膜晶体管，所述氧化物薄膜晶体管包括第二栅极、第二源极和第二漏极，所述第二栅极与所述栅极线连接，所述第二源极与所述数据线连接，所述第二漏极与所述第一栅极连接；
其中，所述第一源极、第一漏极、第二源极和第二漏极同层设置，且所述第一源极和第一漏极与所述第二源极和第二漏极相互绝缘。
在一些实施例中，所述显示面板还包括衬底，所述低温多晶硅薄膜晶体管包括位于所述衬底上的第一有源层，所述第一栅极设置于所述第一有源层一侧，所述第一源极和第一漏极设置于所述第一有源层远离所述衬底的一侧，且所述第一源极和第一漏极与所述第一有源层连接。
在一些实施例中，所述氧化物薄膜晶体管包括位于所述衬底上的第二有源层，所述第二栅极设置于所述第二有源层远离所述衬底的一侧，所述第二源极和所述第二漏极设置于所述第二有源层下，所述第二栅极设置于所述第二有源层远离所述第二源极的一侧。
在一些实施例中，所述显示面板包括：
第一绝缘层，设置于所述第一源极和第一漏极上；
第二绝缘层，设置于所述第二源极和第二漏极上；
其中，所述第一绝缘层与所述第二绝缘层分离设置。
在一些实施例中，所述显示面板还包括：
第一栅极绝缘层，设置于所述第一有源层远离所述衬底的一侧；
第一栅极层，设置于所述第一栅极绝缘层远离所述第一有源层的一侧，所述第一栅极层包括第一栅极；
层间绝缘层，设置于所述第一栅极层远离所述第一栅极绝缘层的一侧；
源漏极层，设置于所述层间绝缘层远离所述第一栅极层的一侧；
第一钝化层，设置于所述源漏极层远离所述层间绝缘层的一侧；
第二有源层，设置于所述第一钝化层远离所述源漏极层的一侧；
第二栅极绝缘层，设置于所述第二有源层远离所述第一钝化层的一侧；
第二栅极层，设置于所述第二栅极绝缘层远离所述第二有源层的一侧，所述第二栅极层包括第二栅极和栅极线；
第二钝化层，设置于所述第二栅极层远离所述第二栅极绝缘层的一侧；
其中，所述源漏极层包括第一源极、第一漏极、第二源极、第二漏极和数据线。
在一些实施例中，所述第一钝化层设置于所述第一源极和第一漏极上，且所述第一钝化层延伸至所述第二源极与第二漏极上。
在一些实施例中，所述第二栅极与所述第二源极和第二漏极在所述衬底上的投影存在重叠部分，所述重叠部分的面积大于或者等于阈值。
在一些实施例中，所述阈值为2微米。
在一些实施例中，所述显示面板还包括缓冲层，所述缓冲层设置于所述衬底与所述第一有源层之间。
在一些实施例中，所述缓冲层的材料包括氧化硅、氮化硅、氮氧化硅、氧化硅和氮化硅的叠层或者混合材料。
在一些实施例中，所述第一有源层的材料包括多晶硅。
在一些实施例中，所述第一栅极层的材料包括钼、钼铝叠层、钼铜叠层、钼钛合金和铜的叠层、钛铝钛叠层、钛铜钛叠层、钼/铜/氧化铟锌叠层、氧化铟锌/铜/氧化铟锌叠层、钼/铜/氧化铟锡叠层、镍/铜/镍叠层、钼镍钛合金/铜/钼镍钛合金叠层，镍铬合金/铜/镍铬合金、钛镍合金/铜/钛镍合金、钛铬合金/铜/钛铬合金叠层、铌铜合金。
在一些实施例中，所述低温多晶硅薄膜晶体管包括N型晶体管和P型晶体管。
在一些实施例中，所述层间绝缘层的材料包括氧化硅、氮化硅、氮氧化硅。
在一些实施例中，所述源漏极层的材料包括钼、钼铝叠层、钼铜叠层、钼钛合金/铜叠层、钼钛合金/铜/钼钛合金得曾、钛铝钛叠层、钛铜钛叠层、钼/铜/氧化铟锌叠层、氧化铟锌/铜/氧化铟锌叠层、钼/铜/氧化铟锡叠层、镍/铜/镍叠层、钼镍钛合金/铜/钼镍钛合金叠层，镍铬合金/铜/镍铬合金、钛镍合金/铜/钛镍合金、钛铬合金/铜/钛铬合金叠层、铌铜合金。
在一些实施例中，所述第一钝化层的材料包括氧化硅、氧化硅/氮化硅叠层，氧化铝/氧化硅叠层。
在一些实施例中，所述第二有源层的材料包括铟镓锌氧化物、铟镓锡氧化物、铟镓氧化物、铟锌氧化物、氧化锌铝、氧化锌铝锡。
在一些实施例中，所述像素电容包括第一极板和第二极板，所述第一极板与所述第一栅极同层设置，所述第二极板与所述第二栅极同层设置。
在一些实施例中，所述像素电容包括第一极板和第二极板，所述第一极板与所述第二源极同层设置，所述第二极板与所述第二栅极同层设置。
同时，本申请实施例提供一种显示面板制备方法，该显示面板制备方法包括：
在衬底上形成第一有源层；
在所述第一有源层上形成第一栅极绝缘层；
在所述第一栅极绝缘层上形成第一栅极层；所述第一栅极层包括第一栅极；
在所述第一栅极层上形成层间绝缘层，并刻蚀所述层间绝缘层形成第一过孔；
在所述层间绝缘层上形成源漏极层，并图案化所述源漏极层形成第一源极，第一漏极、第二源极、第二漏极和数据线；所述第一源极和第二漏极通过第一过孔与所述第一有源层连接；
在所述源极层上形成第一钝化层，并刻蚀所述第一钝化层形成第二过孔；
在所述第一钝化层上形成第二有源层；所述第二源极和第二漏极通过所述第二过孔与所述第二有源层连接；
在所述第二有源层上形成第二栅极绝缘层、第二栅极和第二栅极线；
在所述第二栅极上形成第二钝化层，并刻蚀所述第二钝化层形成第三过孔；
在所述第二钝化层上形成像素电极层，并图案化所述像素电极层形成像素电极；所述像素电极通过所述第二过孔与所述第一电极连接。
 有益效果
本申请提供一种显示面板及其制备方法，该显示面板包括多条栅极线和多条数据线，多条栅极线与多条数据线交叉绝缘排布并形成阵列排布的多个子像素，各子像素中至少设有第一薄膜晶体管、第二薄膜晶体管、像素电容、电源端和发光单元；其中，第一薄膜晶体管包括低温多晶硅薄膜晶体管，低温多晶硅薄膜晶体管包括第一栅极、第一源极和第一漏极，第一栅极与像素电容连接，第一源极与电源端连接，第一漏极与发光单元连接，第二薄膜晶体管包括氧化物薄膜晶体管，氧化物薄膜晶体管包括第二栅极、第二源极和第二漏极，第二栅极与栅极线连接，第二源极与数据线连接，第二漏极与第一栅极连接，其中，第一源极、第一漏极、第二源极和第二漏极同层设置，且第一源极和第一漏极与第二源极和第二漏极相互绝缘。本申请通过将低温多晶硅薄膜晶体管的第一源极和第一漏极与氧化物薄膜晶体管的第二源极和第二漏极同层设置，使得在形成低温多晶硅薄膜晶体管和氧化物薄膜晶体管时，能够减少显示面板的工艺步骤，从而可以提高氧化物薄膜晶体管的稳定性，相应可以减短氧化物薄膜晶体管的沟道长度，提高显示面板的解析度，且避免显示面板出现显示不良，且由于第一源极、第一漏极、第二源极和第二漏极同层设置，可以降低显示面板的厚度。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的显示面板的示意图。
图2为本申请实施例提供的显示面板的第一种电路示意图。
图3为本申请实施例提供的显示面板的第二种电路示意图。
图4为本申请实施例提供的显示面板制备方法的流程图。
图5为本申请实施例提供的显示面板制备方法的各步骤对应的显示面板的第一示意图。
图6为本申请实施例提供的显示面板制备方法的各步骤对应的显示面板的第二示意图。
图7为本申请实施例提供的显示面板制备方法的各步骤对应的显示面板的第三示意图。
图8为本申请实施例提供的显示面板制备方法的各步骤对应的显示面板的第四示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例针对现有显示面板存在现有显示面板制备方法存在工艺步骤较多的技术问题，提供一种显示面板及其制备方法，用于缓解上述技术问题。
如图1、图2所示，本申请实施例提供一种显示面板，该显示面板包括多条栅极线Vscan和多条数据线Vdata，所述多条栅极线Vscan和所述多条数据线Vdata交叉排布并形成阵列排布的多个子像素10，各所述子像素10中至少设有第一薄膜晶体管T1、第二薄膜晶体管T2、像素电容C、电源端VDD和发光单元LED；其中，
所述第一薄膜晶体管T1包括低温多晶硅薄膜晶体管31，所述低温多晶硅薄膜晶体管31包括第一栅极15、第一源极231和第一漏极232，所述第一栅极与所述像素电容C连接，所述第一源极与所述电源端VDD连接，所述第一漏极与所述发光单元LED连接；
所述第二薄膜晶体管T2包括氧化物薄膜晶体管32，所述氧化物薄膜晶体管32包括第二栅极20、第二源极233和第二漏极234，所述第二栅极与所述栅极线Vscan连接，所述第二源极与所述数据线Vdata连接，所述第二漏极与所述第一栅极连接；
其中，所述第一源极231、第一漏极232、第二源极233和第二漏极234同层设置，且所述第一源极231和第一漏极232与所述第二源极233和第二漏极234相互绝缘。
本申请实施例提供一种显示面板，该显示面板通过将低温多晶硅薄膜晶体管的第一源极和第一漏极与氧化物薄膜晶体管的第二源极和第二漏极同层设置，使得在形成低温多晶硅薄膜晶体管和氧化物薄膜晶体管时，能够减少显示面板的工艺步骤，从而可以提高氧化物薄膜晶体管的稳定性，相应可以减短氧化物薄膜晶体管的沟道长度，提高显示面板的解析度，且避免显示面板出现显示不良。
需要说明的是，第一源极和第一漏极与第二源极和第二漏极相互绝缘是指第一源极与第二源极和第二漏极绝缘，第一漏极与第二源极和第二漏极绝缘，而低温多晶硅薄膜晶体管的第一源极和第一漏极、氧化物薄膜晶体管的第二源极和第二漏极在实现晶体管的功能时导通。
需要说明的是，信号端VSS可以为电源负极，也可以是接地端。
在一种实施例中，低温多晶硅薄膜晶体管用于驱动发光单元发光，氧化物薄膜晶体管用于控制电容电位。
在一种实施例中，每个子像素包括第一薄膜晶体管、第二薄膜晶体管、像素电容、电源端和发光单元，在扫描线和数据线提供高电平时，第二薄膜晶体管的第二栅极开启，且数据线提供的数据电压通过第二薄膜晶体管、使像素电容充电，并使得第一薄膜晶体管的第一栅极开启，第一薄膜晶体根据电源电压和数据电压输出电流至发光单元，使发光单元发光，在扫描线为低电平时，像素电容持续向第一薄膜晶体管的第一栅极提供电压，使发光单元持续发光。
上述实施例对2T1C（两个薄膜晶体管和1个存储电容）驱动电路进行了详细说明，但本申请实施例不限于此，驱动电路还可以为3T1C电路、7T1C电路，例如，如图3所示，每个子像素中包括3T1C电路，相较于2T1C电路，增加第三薄膜晶体管T3，且通过第一栅极线Vscan1和第二栅极线Vscan2分别控制第二薄膜晶体管T2和第三薄膜晶体管T3的开启和关闭，通过设置3T1C电路，对第一薄膜晶体管T1的阈值电压进行补偿，提高显示面板的亮度均一性。
在一种实施例中，如图1所示，所述显示面板还包括衬底11，所述低温多晶硅薄膜晶体管31包括位于所述衬底11上的第一有源层13，所述第一栅极15设置于所述第一有源层13远离所述衬底11的一侧，所述第一源极231和第一漏极232设置于所述第一有源层13远离所述衬底11的一侧，且所述第一源极231和第一漏极232与所述第一有源层13连接。在设置低温多晶硅薄膜晶体管时，可以使低温多晶硅薄膜晶体管的栅极与源漏极设置在一侧，通过将氧化物薄膜晶体管的源漏极与低温多晶硅薄膜晶体管的源漏极设置在同一层，从而提高氧化物薄膜晶体管的稳定性。
在一种实施例中，所述低温多晶硅薄膜晶体管包括位于所述衬底上的第一有源层，所述第一栅极设置于所述第一有源层靠近所述衬底的一侧，所述第一源极和第一漏极设置于所述第一有源层远离所述衬底的一侧，且所述第一源极和所述第一漏极与所述第一有源层连接。在设置低温多晶硅薄膜晶体管时，还可以将低温多晶硅薄膜晶体管的栅极与源漏极设置在两侧，本申请实施例不限于此，低温多晶硅薄膜晶体管的栅极和源漏极的设置位置根据需求设置。
在采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管的显示面板中，针对栅极和源漏极设置在有源层一侧的氧化物薄膜晶体管、背沟道刻蚀型的氧化物晶体管，会存在氧化物的性能不稳定的问题。在一种实施例中，如图1所示，所述氧化物薄膜晶体管32包括位于所述衬底11上的第二有源层18，所述第二栅极20设置于所述第二有源层18远离所述衬底11的一侧，所述第二源极233和所述第二漏极234设置于所述第二有源层18下，所述第二栅极20设置于所述第二有源层18远离所述第二源极233的一侧。
本申请实施例通过将低温多晶硅薄膜晶体管和氧化物薄膜晶体管的源漏极设置在同一层，降低了工艺步骤，从而降低了氧化物薄膜晶体管制备过程中受到影响的可能性，提高器件稳定性，从而使氧化物薄膜晶体管的沟道变短，且通过将第二栅极与第二源极和第二漏极分别设置在第二有源层两侧，则第二源极和第二漏极与第二栅极的重叠部分的面积可以提高，从而可以减小氧化物薄膜晶体管的尺寸，减小边框，提高显示面板的分辨率。
在一种实施例中，所述显示面板包括：
第一绝缘层，设置于所述第一源极和第一漏极上；
第二绝缘层，设置于所述第二源极和第二漏极上；
其中，所述第一绝缘层与所述第二绝缘层分离设置。在形成低温多晶硅薄膜晶体管和氧化物薄膜晶体管时，需要在第一源极和第一漏极上形成第一绝缘层，在第二源极和第二漏极形成第二绝缘层，以避免出现短路问题，在设置第一绝缘层和第二绝缘层时，可以分开设置第一绝缘层和第二绝缘层，从而避免显示面板中的金属层出现短路。
在一种实施例中，如图1所示，所述显示面板还包括：
第一栅极绝缘层14，设置于所述第一有源层13远离所述衬底11的一侧；
第一栅极层15，设置于所述第一栅极绝缘层14远离所述第一有源层13的一侧，所述第一栅极层15包括第一栅极15（第一栅极层和第一栅极采用同一标号15）；
层间绝缘层16，设置于所述第一栅极层15远离所述第一栅极绝缘层14的一侧；
源漏极层23，设置于所述层间绝缘层16远离所述第一栅极层15的一侧；
第一钝化层17，设置于所述源漏极层23远离所述层间绝缘层16的一侧；
第二有源层18，设置于所述第一钝化层17远离所述源漏极层23的一侧；
第二栅极绝缘层19，设置于所述第二有源层18远离所述第一钝化层17的一侧；
第二栅极层20，设置于所述第二栅极绝缘层19远离所述第二有源层18的一侧，所述第二栅极层20包括第二栅极20和栅极线（第二栅极层和第二栅极采用同一标号20）；
第二钝化层21，设置于所述第二栅极层20远离所述第二栅极绝缘层19的一侧；
其中，所述源漏极层23包括第一源极231、第一漏极232、第二源极233、第二漏极234和数据线。具体的，对源漏极层进行图案化得到第一源极、第一漏极、第二源极和第二漏极，使得低温多晶硅薄膜晶体管的源漏极和氧化物薄膜晶体管的源漏极均设置在源漏极层，从而降低显示面板的工艺步骤，仅需要对源漏极层进行一道工艺即可形成低温多晶硅薄膜晶体管的源漏极和氧化物薄膜晶体管的源漏极，提高了氧化物薄膜晶体管的稳定性。
针对低温多晶硅薄膜晶体管和氧化物薄膜晶体管需要分开设置绝缘层会导致显示面板的工艺较多，影响氧化物薄膜晶体管的稳定性。在一种实施例中，如图1所示，所述第一钝化层17设置于所述第一源极231和第一漏极232上，且所述第一钝化层17延伸至所述第二源极233和第二漏极234上，即通过将低温多晶硅薄膜晶体管上的钝化层与氧化物薄膜晶体管的层间绝缘层变为一层第一钝化层，则在显示面板的制备过程中，可以进一步减少工艺步骤，则进一步提高了氧化物薄膜晶体管的稳定性，且由于第一钝化层分别作为低温多晶硅薄膜晶体管上的钝化层和氧化物薄膜晶体管的层间绝缘层，可以降低显示面板的厚度。
针对氧化物薄膜晶体管的尺寸较大，导致显示面板的分辨率无法提高，无法提高显示面板的解析度。在一种实施例中，所述第二栅极与所述第二源极和第二漏极在所述衬底上的投影存在重叠部分，所述重叠部分的面积大于或者等于阈值。由于第二栅极与第二源极和第二漏极分别设置于第二有源层两侧，源漏极层设置在第二有源层底部，则可以使得第二栅极与第二源极和第二漏极的重叠部分增大，相应的降低氧化物薄膜晶体管的尺寸，从而提高显示面板的分辨率，提高显示面板的解析度。
具体的，所述阈值为2微米，但本申请实施例不限于此，在不影响氧化物薄膜晶体管的稳定性时，所述阈值根据需求设定。
在一种实施例中，所述像素电容包括第一极板和第二极板，所述第一极板与所述第一栅极同层设置，所述第二极板与所述第二栅极同层设置。在形成电容时，可以使得电容的极板分别通过第一栅极层和第二栅极层形成，从而使得在形成电容的同时，无需增加其他膜层，降低显示面板的厚度。
在一种实施例中，所述像素电容包括第一极板和第二极板，所述第一极板与所述第二源极同层设置，所述第二极板与所述第二栅极同层设置。通过将电容的第一极板和第二极板分别设置在源漏极层和第二栅极层，使得在形成电容的同时，无需增加其他膜层，降低显示面板的厚度。
在一种实施例中，如图1所示，所述显示面板还包括缓冲层12，所述缓冲层12设置于所述衬底11与所述第一有源层13之间。
在一种实施例中，所述缓冲层的材料包括氧化硅、氮化硅、氮氧化硅、氧化硅和氮化硅的叠层或者混合材料。
在一种实施例中，所述第一有源层的材料包括多晶硅，所述多晶硅通过非晶硅激光退火晶化或者其他晶化方法制备得到。
在一种实施例中，所述第一栅极绝缘层的材料包括氧化硅、氮化硅、氧化铝、氧化硅和氮化硅的叠层或者混合材料，氧化硅和氮化硅的叠层或者混合材料。
在一种实施例中，所述第一栅极层的材料包括钼、钼铝叠层、钼铜叠层、钼钛合金和铜的叠层、钛铝钛叠层、钛铜钛叠层、钼/铜/氧化铟锌叠层、氧化铟锌/铜/氧化铟锌叠层、钼/铜/氧化铟锡叠层、镍/铜/镍叠层、钼镍钛合金/铜/钼镍钛合金叠层，镍铬合金/铜/镍铬合金、钛镍合金/铜/钛镍合金、钛铬合金/铜/钛铬合金叠层、铌铜合金。
在一种实施例中，所述低温多晶硅薄膜晶体管包括N型晶体管和P型晶体管。
在一种实施例中，所述层间绝缘层的材料包括氧化硅、氮化硅、氮氧化硅。
在一种实施例中，源漏极层的材料包括钼、钼铝叠层、钼铜叠层、钼钛合金/铜叠层、钼钛合金/铜/钼钛合金得曾、钛铝钛叠层、钛铜钛叠层、钼/铜/氧化铟锌叠层、氧化铟锌/铜/氧化铟锌叠层、钼/铜/氧化铟锡叠层、镍/铜/镍叠层、钼镍钛合金/铜/钼镍钛合金叠层，镍铬合金/铜/镍铬合金、钛镍合金/铜/钛镍合金、钛铬合金/铜/钛铬合金叠层、铌铜合金。
在一种实施例中，所述第一钝化层的材料包括氧化硅、氧化硅/氮化硅叠层，氧化铝/氧化硅叠层。
在一种实施例中，第二有源层的材料包括铟镓锌氧化物、铟镓锡氧化物、铟镓氧化物、铟锌氧化物、氧化锌铝、氧化锌铝锡。
在一种实施例中，所述第二栅极绝缘层的材料包括氧化硅、氮化硅、氧化铝、氧化硅和氮化硅的叠层或者混合材料，氧化硅和氮化硅的叠层或者混合材料。
在一种实施例中，所述第二栅极层的材料包括钼、钼铝叠层、钼铜叠层、钼钛合金和铜的叠层、钛铝钛叠层、钛铜钛叠层、钼/铜/氧化铟锌叠层、氧化铟锌/铜/氧化铟锌叠层、钼/铜/氧化铟锡叠层、镍/铜/镍叠层、钼镍钛合金/铜/钼镍钛合金叠层，镍铬合金/铜/镍铬合金、钛镍合金/铜/钛镍合金、钛铬合金/铜/钛铬合金叠层、铌铜合金。
在一种实施例中，所述第二钝化层的材料包括氧化硅、氧化硅/氮化硅叠层，氧化铝/氧化硅叠层。
在一种实施例中，如图1所示，所述显示面板还包括像素电极22。
在一种实施例中，所述像素电极的材料包括氧化铟锡、氧化铟锌、氧化铟锡/银/氧化铟锡叠层、氧化铟锌/银/氧化铟锡叠层、钼铜叠层、钼钛合金/铜/钼钛合金叠层。
如图4所示，本申请实施例提供一种显示面板制备方法，该显示面板制备方法包括：
S1，在衬底上形成第一有源层；显示面板的结构如图5中的（a）所示；
S2，在所述第一有源层上形成第一栅极绝缘层；显示面板的结构如图5中的（b）所示；
S3，在所述第一栅极绝缘层上形成第一栅极层；所述第一栅极层包括第一栅极；显示面板的结构如图5中的（c）所示；
S4，在所述第一栅极层上形成层间绝缘层，并刻蚀所述层间绝缘层形成第一过孔；显示面板的结构如图6中的（a）所示；
S5，在所述层间绝缘层上形成源漏极层，并图案化所述源漏极层形成第一源极，第一漏极、第二源极、第二漏极和数据线；所述第一源极和第二漏极通过第一过孔与所述第一有源层连接；显示面板的结构如图6中的（b）所示；
S6，在所述源极层上形成第一钝化层，并刻蚀所述第一钝化层形成第二过孔；显示面板的结构如图7中的（a）所示；
S7，在所述第一钝化层上形成第二有源层；所述第二源极和第二漏极通过所述第二过孔与所述第二有源层连接；显示面板的结构如图7中的（b）所示；
S8，在所述第二有源层上形成第二栅极绝缘层、第二栅极和第二栅极线；显示面板的结构如图8中的（a）所示；
S9，在所述第二栅极上形成第二钝化层，并刻蚀所述第二钝化层形成第三过孔；显示面板的结构如图8中的（b）所示；
S10，在所述第二钝化层上形成像素电极层，并图案化所述像素电极层形成像素电极；所述像素电极通过所述第二过孔与所述第一电极连接；显示面板的结构如图1所示。
本申请实施例提供一种显示面板制备方法，通过对源漏极层图案化形成第一源极、第一漏极、第二源极和第二漏极，使得低温多晶硅薄膜晶体管的源漏极与氧化物薄膜晶体管的源漏极设置在同一层，减少了源漏极层的工艺步骤，同时通过将第一钝化层作为低温多晶硅薄膜晶体管的钝化层和氧化物薄膜晶体管的层间绝缘层，减少了绝缘层的工艺，从而减少了对氧化物薄膜晶体管的影响，相应可以减短氧化物薄膜晶体管的沟道长度，提高显示面板的解析度，且避免显示面板出现显示不良，且由于第一源极、第一漏极、第二源极和第二漏极同层设置，第一钝化层作为低温多晶硅薄膜晶体管的钝化层和氧化物薄膜晶体管的层间绝缘层，可以降低显示面板的厚度。
根据以上实施例可知：
本申请实施例提供一种显示面板及其制备方法，该显示面板包括多条栅极线和多条数据线，多条栅极线与多条数据线交叉绝缘排布并形成阵列排布的多个子像素，各子像素中至少设有第一薄膜晶体管、第二薄膜晶体管、像素电容、电源端和发光单元；其中，第一薄膜晶体管包括低温多晶硅薄膜晶体管，低温多晶硅薄膜晶体管包括第一栅极、第一源极和第一漏极，第一栅极与像素电容连接，第一源极与电源端连接，第一漏极与发光单元连接，第二薄膜晶体管包括氧化物薄膜晶体管，氧化物薄膜晶体管包括第二栅极、第二源极和第二漏极，第二栅极与栅极线连接，第二源极与数据线连接，第二漏极与第一栅极连接，其中，第一源极、第一漏极、第二源极和第二漏极同层设置，且第一源极和第一漏极与第二源极和第二漏极相互绝缘。本申请通过将低温多晶硅薄膜晶体管的第一源极和第一漏极与氧化物薄膜晶体管的第二源极和第二漏极同层设置，使得在形成低温多晶硅薄膜晶体管和氧化物薄膜晶体管时，能够减少显示面板的工艺步骤，从而可以提高氧化物薄膜晶体管的稳定性，相应可以减短氧化物薄膜晶体管的沟道长度，提高显示面板的解析度，且避免显示面板出现显示不良，且由于第一源极、第一漏极、第二源极和第二漏极同层设置，可以降低显示面板的厚度。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板及其制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其包括多条栅极线和多条数据线，所述多条栅极线与所述多条数据线交叉绝缘排布并形成阵列排布的多个子像素，各所述子像素中至少设有第一薄膜晶体管、第二薄膜晶体管、像素电容、电源端和发光单元；其中，
    所述第一薄膜晶体管包括低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管包括第一栅极、第一源极和第一漏极，所述第一栅极与所述像素电容连接，所述第一源极与所述电源端连接，所述第一漏极与所述发光单元连接；
    所述第二薄膜晶体管包括氧化物薄膜晶体管，所述氧化物薄膜晶体管包括第二栅极、第二源极和第二漏极，所述第二栅极与所述栅极线连接，所述第二源极与所述数据线连接，所述第二漏极与所述第一栅极连接；
    其中，所述第一源极、第一漏极、第二源极和第二漏极同层设置，且所述第一源极和第一漏极与所述第二源极和第二漏极相互绝缘。
  2. 如权利要求1所述的显示面板，其中，所述显示面板还包括衬底，所述低温多晶硅薄膜晶体管包括位于所述衬底上的第一有源层，所述第一栅极设置于所述第一有源层一侧，所述第一源极和第一漏极设置于所述第一有源层远离所述衬底的一侧，且所述第一源极和第一漏极与所述第一有源层连接。
  3. 如权利要求2所述的显示面板，其中，所述氧化物薄膜晶体管包括位于所述衬底上的第二有源层，所述第二栅极设置于所述第二有源层远离所述衬底的一侧，所述第二源极和所述第二漏极设置于所述第二有源层下，所述第二栅极设置于所述第二有源层远离所述第二源极的一侧。
  4. 如权利要求3所述的显示面板，其中，所述显示面板包括：
    第一绝缘层，设置于所述第一源极和第一漏极上；
    第二绝缘层，设置于所述第二源极和第二漏极上；
    其中，所述第一绝缘层与所述第二绝缘层分离设置。
  5. 如权利要求3所述的显示面板，其中，所述显示面板还包括：
    第一栅极绝缘层，设置于所述第一有源层远离所述衬底的一侧；
    第一栅极层，设置于所述第一栅极绝缘层远离所述第一有源层的一侧，所述第一栅极层包括第一栅极；
    层间绝缘层，设置于所述第一栅极层远离所述第一栅极绝缘层的一侧；
    源漏极层，设置于所述层间绝缘层远离所述第一栅极层的一侧；
    第一钝化层，设置于所述源漏极层远离所述层间绝缘层的一侧；
    第二有源层，设置于所述第一钝化层远离所述源漏极层的一侧；
    第二栅极绝缘层，设置于所述第二有源层远离所述第一钝化层的一侧；
    第二栅极层，设置于所述第二栅极绝缘层远离所述第二有源层的一侧，所述第二栅极层包括第二栅极和栅极线；
    第二钝化层，设置于所述第二栅极层远离所述第二栅极绝缘层的一侧；
    其中，所述源漏极层包括第一源极、第一漏极、第二源极、第二漏极和数据线。
  6. 如权利要求5所述的显示面板，其中，所述第一钝化层设置于所述第一源极和第一漏极上，且所述第一钝化层延伸至所述第二源极与第二漏极上。
  7. 如权利要求5所述的显示面板，其中，所述第二栅极与所述第二源极和第二漏极在所述衬底上的投影存在重叠部分，所述重叠部分的面积大于或者等于阈值。
  8. 如权利要求7所述的显示面板，其中，所述阈值为2微米。
  9. 如权利要求5所述的显示面板，其中，所述显示面板还包括缓冲层，所述缓冲层设置于所述衬底与所述第一有源层之间。
  10. 如权利要求9所述的显示面板，其中，所述缓冲层的材料包括氧化硅、氮化硅、氮氧化硅、氧化硅和氮化硅的叠层或者混合材料。
  11. 如权利要求5所述的显示面板，其中，所述第一有源层的材料包括多晶硅。
  12. 如权利要求5所述的显示面板，其中，所述第一栅极层的材料包括钼、钼铝叠层、钼铜叠层、钼钛合金和铜的叠层、钛铝钛叠层、钛铜钛叠层、钼/铜/氧化铟锌叠层、氧化铟锌/铜/氧化铟锌叠层、钼/铜/氧化铟锡叠层、镍/铜/镍叠层、钼镍钛合金/铜/钼镍钛合金叠层，镍铬合金/铜/镍铬合金、钛镍合金/铜/钛镍合金、钛铬合金/铜/钛铬合金叠层、铌铜合金。
  13. 如权利要求5所述的显示面板，其中，所述低温多晶硅薄膜晶体管包括N型晶体管和P型晶体管。
  14. 如权利要求5所述的显示面板，其中，所述层间绝缘层的材料包括氧化硅、氮化硅、氮氧化硅。
  15. 如权利要求5所述的显示面板，其中，所述源漏极层的材料包括钼、钼铝叠层、钼铜叠层、钼钛合金/铜叠层、钼钛合金/铜/钼钛合金得曾、钛铝钛叠层、钛铜钛叠层、钼/铜/氧化铟锌叠层、氧化铟锌/铜/氧化铟锌叠层、钼/铜/氧化铟锡叠层、镍/铜/镍叠层、钼镍钛合金/铜/钼镍钛合金叠层，镍铬合金/铜/镍铬合金、钛镍合金/铜/钛镍合金、钛铬合金/铜/钛铬合金叠层、铌铜合金。
  16. 如权利要求5所述的显示面板，其中，所述第一钝化层的材料包括氧化硅、氧化硅/氮化硅叠层，氧化铝/氧化硅叠层。
  17. 如权利要求5所述的显示面板，其中，所述第二有源层的材料包括铟镓锌氧化物、铟镓锡氧化物、铟镓氧化物、铟锌氧化物、氧化锌铝、氧化锌铝锡。
  18. 如权利要求1所述的显示面板，其中，所述像素电容包括第一极板和第二极板，所述第一极板与所述第一栅极同层设置，所述第二极板与所述第二栅极同层设置。
  19. 如权利要求1所述的显示面板，其中，所述像素电容包括第一极板和第二极板，所述第一极板与所述第二源极同层设置，所述第二极板与所述第二栅极同层设置。
  20. 一种显示面板制备方法，其包括：
    在衬底上形成第一有源层；
    在所述第一有源层上形成第一栅极绝缘层；
    在所述第一栅极绝缘层上形成第一栅极层；所述第一栅极层包括第一栅极；
    在所述第一栅极层上形成层间绝缘层，并刻蚀所述层间绝缘层形成第一过孔；
    在所述层间绝缘层上形成源漏极层，并图案化所述源漏极层形成第一源极，第一漏极、第二源极、第二漏极和数据线；所述第一源极和第二漏极通过第一过孔与所述第一有源层连接；
    在所述源极层上形成第一钝化层，并刻蚀所述第一钝化层形成第二过孔；
    在所述第一钝化层上形成第二有源层；所述第二源极和第二漏极通过所述第二过孔与所述第二有源层连接；
    在所述第二有源层上形成第二栅极绝缘层、第二栅极和第二栅极线；
    在所述第二栅极上形成第二钝化层，并刻蚀所述第二钝化层形成第三过孔；
    在所述第二钝化层上形成像素电极层，并图案化所述像素电极层形成像素电极；所述像素电极通过所述第二过孔与所述第一电极连接。
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