WO2022099786A1 - 半导体功率器件的制造方法 - Google Patents

半导体功率器件的制造方法 Download PDF

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WO2022099786A1
WO2022099786A1 PCT/CN2020/131291 CN2020131291W WO2022099786A1 WO 2022099786 A1 WO2022099786 A1 WO 2022099786A1 CN 2020131291 W CN2020131291 W CN 2020131291W WO 2022099786 A1 WO2022099786 A1 WO 2022099786A1
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dielectric layer
trench
insulating dielectric
type substrate
gate
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PCT/CN2020/131291
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English (en)
French (fr)
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毛振东
徐真逸
刘伟
刘磊
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苏州东微半导体有限公司
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Priority to JP2022550817A priority Critical patent/JP2023515135A/ja
Priority to KR1020227030936A priority patent/KR20220137965A/ko
Priority to US18/016,200 priority patent/US20230274941A1/en
Publication of WO2022099786A1 publication Critical patent/WO2022099786A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

Definitions

  • the embodiments of the present application relate to the technical field of semiconductor power devices, for example, to a method for manufacturing a semiconductor power device.
  • a method for manufacturing a semiconductor power device in the related art includes: first, as shown in FIG. 1 , forming a hard mask layer 11 on a silicon substrate 10 , using a photolithography process to define trench positions, and then applying a photolithography process to the hard mask layer 11 . Etch and continue to etch the silicon substrate 10 to form a trench 12; next, as shown in FIG. 2, a first insulating dielectric layer 13 is formed in the trench, and then a first polysilicon layer is deposited and The first polysilicon layer is etched back to remove the first polysilicon layer located outside the trench, the remaining first polysilicon layer after etching forms the shield gate 14, and then the silicon lining on the side of the trench 12 is used.
  • the bottom portion and the shielding gate 14 are self-aligned to etch the first insulating dielectric layer 13 for the self-aligned boundary, and the first insulating dielectric layer located at the upper part of the trench is removed and the first insulating dielectric layer 13 at the lower part of the trench is retained;
  • a second insulating dielectric layer 15 is formed, and then a second polysilicon layer is deposited and etched back to the second polysilicon layer outside the trench.
  • the polysilicon gate 16 is formed by removing and etching the remaining second polysilicon layer.
  • the polysilicon gate 16 and the shielding gate 14 are isolated by the second insulating dielectric layer 15 , because the second insulating dielectric layer 15 also serves as a connection between the polysilicon gate 16 and the silicon substrate 10 .
  • the gate dielectric layer is used, so the thickness of the second insulating dielectric layer 15 is relatively thin, which makes the gate-source capacitance of the semiconductor power device smaller and the gate-source leakage larger.
  • the present application provides a method for manufacturing a semiconductor power device, so as to reduce the gate-source capacitance of the semiconductor power device and reduce the gate-source leakage of the semiconductor power device.
  • the present application provides a method for manufacturing a semiconductor power device, including:
  • Self-aligned etching is performed on the field oxide layer with the n-type substrate and the shielding gate as the self-aligned boundary, and the field oxide layer in the upper part of the first trench is etched away.
  • a second trench formed on the upper portion of the first trench and between the shield gate and the n-type substrate;
  • first insulating dielectric layer forming a first insulating dielectric layer, the first insulating dielectric layer covering the sidewalls and the bottom of the second trench;
  • the photoresist is removed, and a gate dielectric layer and a gate electrode are formed in the second trench.
  • the method for manufacturing a semiconductor power device of the present application further includes:
  • An n-type source region is formed within the p-type body region.
  • the first insulating medium layer is a silicon oxide layer.
  • the method for manufacturing a semiconductor power device of the present application, forming a first insulating dielectric layer includes:
  • the first insulating dielectric layer is formed by a sub-atmospheric pressure chemical vapor deposition process.
  • etching away the first insulating dielectric layer located in the second trench and close to the side of the n-type substrate comprising:
  • the first insulating dielectric layer located in the second trench and close to the side of the n-type substrate is etched away by a wet etching process.
  • the n-type substrate is a silicon substrate.
  • the thickness of the first insulating dielectric layer is greater than the thickness of the gate dielectric layer.
  • a photoresist is formed on a first insulating dielectric layer, and the first insulating dielectric layer located in the second trench and close to the side of the shielding gate is reserved by using the photoresist as a mask.
  • the thickness of the first insulating dielectric layer can be made thicker, and when the gate and the shielding gate are isolated by the first insulating dielectric layer, the gate-source capacitance can be reduced, and the gate-source leakage can be reduced, and the reliability of the semiconductor power device can be improved. sex.
  • 1 to 3 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of a method for manufacturing a semiconductor power device of the related art
  • 4 to 7 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of an embodiment of the manufacturing method of a semiconductor power device provided by the present application.
  • 4 to 7 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of an embodiment of the manufacturing method of a semiconductor power device provided by the present application.
  • first trenches 31 are formed in the provided n-type substrate 20 .
  • the n-type substrate 20 is usually a silicon substrate, and the number of the first trenches 31 is determined by the designed semiconductor power device. For specification determination, only two first grooves 31 are exemplarily shown in the embodiments of the present application.
  • a field oxide layer 21 and a shielding gate 22 are formed in the first trench 31 according to a conventional process, and the field oxide layer 21 is self-aligned by using the n-type substrate 20 and the shielding gate 22 as self-aligned boundaries,
  • the field oxide layer 21 in the upper part of the first trench 31 is etched away, and a second trench 32 is formed in the upper part of the first trench 31 and between the shielding gate 22 and the n-type substrate 20 .
  • a first insulating dielectric layer 23 is formed.
  • the first insulating dielectric layer 23 should cover the sidewall and bottom of the second trench, and the first insulating dielectric layer 23 cannot fill the second trench.
  • the first insulating dielectric layer 23 is usually a silicon oxide layer, which can be formed by a sub-atmospheric pressure chemical vapor deposition process.
  • a layer of photoresist 24 is formed, the photoresist 24 should fill the second trench, and then photolithography is performed to expose the first insulating dielectric layer 23 located in the second trench and close to the side of the n-type substrate 20 come out.
  • the first insulating dielectric layer located in the second trench and close to the side of the n-type substrate 20 is etched away, while the first insulating dielectric layer located in the second trench and close to the side of the shielding gate 22 remains.
  • the first insulating dielectric layer 23 is etched in this step, a wet etching process may be used, so that the etching selectivity ratio of silicon oxide and silicon may not be limited when the first insulating dielectric layer 23 is etched.
  • a gate dielectric layer and a gate electrode are formed in the second trench, a p-type body region is formed in the n-type substrate, an n-type source region is formed in the p-type body region, and then an isolation dielectric layer is formed and metal layers, etc., to obtain semiconductor power devices.
  • the first insulating dielectric layer and the gate dielectric layer are formed through a two-step process, so that the thickness of the first insulating dielectric layer is greater than that of the gate dielectric layer, and the thickness of the first insulating dielectric layer is greater than that of the gate dielectric layer, and the gap between the gate and the shielding gate is It is isolated by the first insulating medium layer, and by increasing the thickness of the first insulating medium layer, the gate-source capacitance can be reduced, the gate-source leakage can be reduced, and the reliability of the semiconductor power device can be improved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Chemical Kinetics & Catalysis (AREA)
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  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本申请属于半导体功率器件技术领域，具体公开了一种半导体功率器件的制造方法，包括：形成第一绝缘介质层，所述第一绝缘介质层覆盖所述第二沟槽的侧壁和底部；形成一层光刻胶，所述光刻胶填满所述第二沟槽；进行光刻，将位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层暴露出来，并刻蚀掉位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层。本申请的半导体功率器件的制造方法，栅极通过第一绝缘介质层与屏蔽栅隔离，通过增加第一绝缘介质层的厚度可以降低栅源电容，并降低栅源漏电，提高半导体功率器件的可靠性。

Description

半导体功率器件的制造方法
本申请要求在2020年11月12日提交中国专利局、申请号为202011263819.9的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体功率器件技术领域，例如涉及一种半导体功率器件的制造方法。
背景技术
相关技术的一种半导体功率器件的制造方法包括：首先，如图1所示，在硅衬底10上形成硬掩膜层11，采用光刻工艺定义沟槽位置，然后对硬掩膜层11进行刻蚀并继续对硅衬底10进行刻蚀以形成沟槽12；接下来，如图2所示，在沟槽内形成第一绝缘介质层13，然后淀积第一多晶硅层并对该第一多晶硅层进行回刻将位于沟槽外部的第一多晶硅层去除，刻蚀后剩余的第一多晶硅层形成屏蔽栅14，然后以沟槽12侧面的硅衬底部分和屏蔽栅14为自对准边界对第一绝缘介质层13进行自对准刻蚀，将位于沟槽上部的第一绝缘介质层去除而保留沟槽下部的第一绝缘介质层13；接下来，如图3所示，形成第二绝缘介质层15，然后淀积第二多晶硅层并对该第二多晶硅层进行回刻将位于沟槽外部的第二多晶硅层去除，刻蚀后剩余的第二多晶硅层形成多晶硅栅极16。相关技术的半导体功率器件的制造方法，多晶硅栅极16与屏蔽栅14之间由第二绝缘介质层15隔离，由于第二绝缘介质层15还作为多晶硅栅极16与硅衬底10之间的栅介质层使用，因此第二绝缘介质层15的厚度较薄，这使得半导体功率器件的栅源电容较小，且栅源漏电较大。
发明内容
本申请提供一种半导体功率器件的制造方法，以降低半导体功率器件的栅 源电容，并降低半导体功率器件的栅源漏电。
本申请提供了一种半导体功率器件的制造方法，包括：
在n型衬底内形成第一沟槽，在所述第一沟槽内形成场氧化层和屏蔽栅；
以所述n型衬底和所述屏蔽栅为自对准边界对所述场氧化层进行自对准刻蚀，将所述第一沟槽上部内的所述场氧化层刻蚀掉，在所述第一沟槽的上部形成且介于所述屏蔽栅与所述n型衬底之间的第二沟槽；
形成第一绝缘介质层，所述第一绝缘介质层覆盖所述第二沟槽的侧壁和底部；
形成一层光刻胶，所述光刻胶填满所述第二沟槽；
进行光刻，将位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层暴露出来，然后刻蚀掉位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层，保留位于所述第二沟槽内且靠近所述屏蔽栅一侧的所述第一绝缘介质层；
去除掉所述光刻胶，在所述第二沟槽内形成栅介质层和栅极。
可选的，本申请的半导体功率器件的制造方法，还包括：
在所述n型衬底内形成p型体区；
在所述p型体区内形成n型源区。
可选的，本申请的半导体功率器件的制造方法，所述第一绝缘介质层为氧化硅层。
可选的，本申请的半导体功率器件的制造方法，形成第一绝缘介质层，包括：
采用次常压化学气相沉积工艺形成第一绝缘介质层。
可选的，本申请的半导体功率器件的制造方法，刻蚀掉位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层，包括：
采用湿法刻蚀工艺刻蚀掉位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层。
可选的，本申请的半导体功率器件的制造方法，所述n型衬底为硅衬底。
可选的，本申请的半导体功率器件的制造方法，所述第一绝缘介质层的厚度大于所述栅介质层的厚度。
本申请提供的半导体功率器件的制造方法，通过在第一绝缘介质层上形成光刻胶，以光刻胶为掩膜保留位于第二沟槽内且靠近屏蔽栅一侧的第一绝缘介质层，如此，可以使得第一绝缘介质层的厚度较厚，当通过此第一绝缘介质层对栅极与屏蔽栅隔离时，可以降低栅源电容，并降低栅源漏电，提高半导体功率器件的可靠性。
附图说明
图1至图3是相关技术的一种半导体功率器件的制造方法的制造工艺中的主要结构的剖面结构示意图；
图4至图7是本申请提供的半导体功率器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。
具体实施方式
以下将结合本申请实施例中的附图，完整地描述本申请的技术方案。显然，所描述的实施例是本申请的一部分实施例，而不是全部的实施例。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列示意图，放大了本申请所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。
图4至图7是本申请提供的半导体功率器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。
首先，如图4所示，在提供的n型衬底20内形成第一沟槽31，n型衬底20通常为硅衬底，第一沟槽31的数量由所设计的半导体功率器件的规格确定，本申请实施例中仅示例性的示出了两个第一沟槽31。然后，按照常规工艺在第一沟槽31内形成场氧化层21和屏蔽栅22，并以n型衬底20和屏蔽栅22为自对 准边界对场氧化层21进行自对准刻蚀，将第一沟槽31上部内的场氧化层21刻蚀掉，在第一沟槽31的上部形成且介于屏蔽栅22与n型衬底20之间的第二沟槽32。
接下来，如图5所示，形成第一绝缘介质层23，第一绝缘介质层23应覆盖第二沟槽的侧壁和底部，第一绝缘介质层23不能填满第二沟槽。第一绝缘介质层23通常为氧化硅层，可以采用次常压化学气相沉积工艺形成。然后形成一层光刻胶24，光刻胶24应填满第二沟槽，之后进行光刻，将位于第二沟槽内且靠近n型衬底20一侧的第一绝缘介质层23暴露出来。
接下来，如图6所示，刻蚀掉位于第二沟槽内且靠近n型衬底20一侧的第一绝缘介质层，而保留位于第二沟槽内且靠近屏蔽栅22一侧的第一绝缘介质层23。在该步刻蚀第一绝缘介质层23时，可以采用湿法刻蚀工艺，这样对第一绝缘介质层23进行刻蚀时可以不受氧化硅、硅的刻蚀选择比限制。
接下来，如图7所示，去除掉光刻胶。
最后，按照常规工艺，在第二沟槽内形成栅介质层和栅极，并在n型衬底内形成p型体区，在p型体区内形成n型源区，之后形成隔离介质层和金属层等即可得到半导体功率器件。
本申请提供的半导体功率器件的制造方法，第一绝缘介质层和栅介质层通过两步工艺形成，可以使得第一绝缘介质层的厚度大于栅介质层的厚度，而栅极与屏蔽栅之间由第一绝缘介质层隔离，通过增加第一绝缘介质层的厚度可以降低栅源电容，并降低栅源漏电，提高半导体功率器件的可靠性。

Claims (7)

  1. 半导体功率器件的制造方法，包括：
    在n型衬底内形成第一沟槽，在所述第一沟槽内形成场氧化层和屏蔽栅；
    以所述n型衬底和所述屏蔽栅为自对准边界对所述场氧化层进行自对准刻蚀，将所述第一沟槽上部内的所述场氧化层刻蚀掉，在所述第一沟槽的上部形成且介于所述屏蔽栅与所述n型衬底之间的第二沟槽；
    形成第一绝缘介质层，所述第一绝缘介质层覆盖所述第二沟槽的侧壁和底部；
    形成一层光刻胶，所述光刻胶填满所述第二沟槽；
    进行光刻，将位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层暴露出来，然后刻蚀掉位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层，保留位于所述第二沟槽内且靠近所述屏蔽栅一侧的所述第一绝缘介质层；
    去除掉所述光刻胶，在所述第二沟槽内形成栅介质层和栅极。
  2. 如权利要求1所述的方法，还包括：
    在所述n型衬底内形成p型体区；
    在所述p型体区内形成n型源区。
  3. 如权利要求1所述的方法，其中，所述第一绝缘介质层为氧化硅层。
  4. 如权利要求1所述的方法，其中，形成第一绝缘介质层，包括：
    采用次常压化学气相沉积工艺形成第一绝缘介质层。
  5. 如权利要求1所述的方法，其中，刻蚀掉位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层，包括：
    采用湿法刻蚀工艺刻蚀掉位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层。
  6. 如权利要求1所述的方法，其中，所述n型衬底为硅衬底。
  7. 如权利要求1所述的方法，其中，所述第一绝缘介质层的厚度大于所述栅介质层的厚度。
PCT/CN2020/131291 2020-11-12 2020-11-25 半导体功率器件的制造方法 WO2022099786A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109830526A (zh) * 2019-02-27 2019-05-31 中山汉臣电子科技有限公司 一种功率半导体器件及其制备方法
CN109979823A (zh) * 2017-12-28 2019-07-05 深圳尚阳通科技有限公司 一种屏蔽栅功率器件及制造方法
US20200044078A1 (en) * 2018-03-01 2020-02-06 Ipower Semiconductor Shielded gate trench mosfet devices
CN111785642A (zh) * 2020-08-26 2020-10-16 上海华虹宏力半导体制造有限公司 一种半导体器件的制造方法
US10811502B1 (en) * 2019-05-30 2020-10-20 Nxp Usa, Inc. Method of manufacture of super-junction power semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016063004A (ja) * 2014-09-16 2016-04-25 株式会社東芝 半導体装置及びその製造方法
JP2020150185A (ja) * 2019-03-14 2020-09-17 株式会社東芝 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109979823A (zh) * 2017-12-28 2019-07-05 深圳尚阳通科技有限公司 一种屏蔽栅功率器件及制造方法
US20200044078A1 (en) * 2018-03-01 2020-02-06 Ipower Semiconductor Shielded gate trench mosfet devices
CN109830526A (zh) * 2019-02-27 2019-05-31 中山汉臣电子科技有限公司 一种功率半导体器件及其制备方法
US10811502B1 (en) * 2019-05-30 2020-10-20 Nxp Usa, Inc. Method of manufacture of super-junction power semiconductor device
CN111785642A (zh) * 2020-08-26 2020-10-16 上海华虹宏力半导体制造有限公司 一种半导体器件的制造方法

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