WO2022082902A1 - 半导体功率器件的制造方法 - Google Patents

半导体功率器件的制造方法 Download PDF

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WO2022082902A1
WO2022082902A1 PCT/CN2020/128371 CN2020128371W WO2022082902A1 WO 2022082902 A1 WO2022082902 A1 WO 2022082902A1 CN 2020128371 W CN2020128371 W CN 2020128371W WO 2022082902 A1 WO2022082902 A1 WO 2022082902A1
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Prior art keywords
insulating layer
trench
layer
etching
gate
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PCT/CN2020/128371
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English (en)
French (fr)
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刘伟
徐真逸
毛振东
王鑫
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苏州东微半导体股份有限公司
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Priority to KR1020237017512A priority Critical patent/KR102600345B1/ko
Priority to JP2021576567A priority patent/JP7313082B2/ja
Priority to US17/622,021 priority patent/US12015078B2/en
Priority to KR1020217043143A priority patent/KR102578494B1/ko
Priority to DE112020002907.7T priority patent/DE112020002907T5/de
Publication of WO2022082902A1 publication Critical patent/WO2022082902A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

  • the present application belongs to the technical field of semiconductor power devices, for example, a manufacturing method of a semiconductor power device.
  • a method for manufacturing a semiconductor power device in the related art includes: forming a hard mask layer on a provided silicon substrate, using a photolithography process to define a trench position, and then etching away the hard mask layer at the trench position ; use the etched hard mask layer as a mask to etch the silicon substrate to form a trench; cover the bottom surface and side of the trench to form a first dielectric layer; deposit a first polysilicon layer, the first multi-layer
  • the crystalline silicon layer completely fills the trench formed with the first dielectric layer and extends to the outside of the trench; perform polysilicon etchback to remove the first polysilicon layer located outside the trench, and the remaining first polysilicon after etching
  • the first dielectric layer is self-aligned and etched with the silicon and the first polysilicon layer on the side of the trench as the self-aligned boundary, and the self-aligned etching will be located on the top of the trench.
  • the first dielectric layer that is removed and located at the bottom of the trench remains, and the remaining first dielectric layer is located at the bottom of the subsequently formed body region; a fourth insulating layer is formed on the inner surface of the top region of the trench after the first dielectric layer is removed , the thickness of the fourth insulating layer is less than the thickness of the first dielectric layer; a second polysilicon layer is deposited, and the second polysilicon layer removes the first dielectric layer and forms the top area of the trench with the fourth insulating layer Complete filling; perform polysilicon etchback to remove the second polysilicon layer outside the trench, and the remaining second polysilicon layer after etching forms a polysilicon gate.
  • the manufacturing method of the semiconductor power device in the related art in order to ensure the quality of the polysilicon gate, it is necessary to form a first dielectric layer of sufficient thickness, but the thickness of the first dielectric layer will affect the charge depletion at the bottom of the trench, thereby affecting the semiconductor power withstand voltage of the device.
  • the present application provides a method for manufacturing a semiconductor power device, which can keep the withstand voltage of the semiconductor power device unaffected under the condition of ensuring gate quality.
  • the present application provides a method for manufacturing a semiconductor power device, including:
  • the method for manufacturing a semiconductor power device of the present application further includes:
  • An n-type source region is formed within the p-type body region.
  • the method for manufacturing a semiconductor power device of the present application further includes:
  • a fourth insulating layer and a gate are formed in the second trench, and the gate is isolated from the shielding gate by the fourth insulating layer;
  • An n-type source region is formed within the p-type body region.
  • the first insulating layer includes a silicon oxide layer.
  • the second insulating layer is a silicon oxide layer.
  • the third insulating layer is a silicon oxide layer.
  • the insulating spacer is a silicon nitride layer.
  • an etching method combining anisotropic etching and isotropic etching is used.
  • the depth of the second trench is smaller than the depth of the first trench.
  • a first trench is formed by a photolithography process, and an n-type substrate is self-aligned by using the first insulating layer, the second insulating layer and the third insulating layer as masks. , forming a second trench in the n-type substrate, and forming a fourth insulating layer and a gate in the second trench.
  • the formation quality of the gate is not limited by the thickness of the second insulating layer. Under the condition of ensuring the quality of the gate, the thickness of the second insulating layer can be reduced, so that the resistance of the semiconductor power device can be improved. pressure is not affected.
  • 1 to 6 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of an embodiment of a method for manufacturing a semiconductor power device provided by the present application.
  • 1 to 6 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of an embodiment of a method for manufacturing a semiconductor power device provided by the present application.
  • an insulating spacer 32 is formed in the opening of the first insulating layer 31 , and the insulating spacer 32 is optionally a silicon nitride layer.
  • the process includes: depositing a layer first The silicon nitride layer is then etched back to form the deposited silicon nitride layer to form insulating spacers 32 in self-aligned positions at the sidewalls of the openings 40 .
  • the n-type substrate 20 is etched by using the first insulating layer 31 and the insulating spacers 32 as masks to form the first trenches 41 in the n-type substrate 20 .
  • a second insulating layer 21 and a shielding gate 22 are formed in the first trench.
  • the second insulating layer 21 is optionally a silicon oxide layer, which is formed by a thermal oxidation process; the shielding gate 22 is usually
  • the polysilicon gate formation process includes: after the second insulating layer 21 is formed, a layer of polysilicon is first deposited, and then the deposited polysilicon layer is etched back, and the remaining polysilicon layer after etching forms the shield gate 22 .
  • a third insulating layer 33 is formed on the surface of the shielding gate 22.
  • the third insulating layer 33 is optionally a silicon oxide layer and is formed by a thermal oxidation process. At this time, the third insulating layer 33 and the second insulating layer 21 will be connected so that the shielding grid 22 will be wrapped by the second insulating layer 21 and the third insulating layer 33 .
  • the oxidized thickness of the n-type substrate 20 at the position of the sidewall of the first trench should be smaller than the thickness of the insulating spacer to ensure that the insulating side After the wall is etched away, the n-type substrate 20 is exposed, so that the n-type substrate 20 can be etched to form the second trench 42 .
  • a fourth insulating layer 23 is formed in the second trench.
  • the fourth insulating layer 23 is usually a silicon oxide layer and is formed by a thermal oxidation process.
  • a gate 24 is formed in the second trench.
  • the formation process includes: firstly depositing a layer of polysilicon, then etching back the deposited polysilicon layer, and forming the gate 24 with the remaining polysilicon layer after etching, and the gate 24
  • the shield gate 22 is isolated by the second insulating layer 21 . Afterwards, the first insulating layer and the third insulating layer are etched away.
  • the first insulating layer, the third insulating layer and the second insulating layer 21 at the sidewalls of the second trench may be etched away first, and then a fourth insulating layer is formed by a thermal oxidation process.
  • the gate 24 is isolated from the shielding gate 22 through the fourth insulating layer 23, as shown in FIG. 6 . . At this time, the gate 24 has a larger width, so that it can be drawn out by the external electrodes more easily.
  • a p-type body region is formed in the n-type substrate, an n-type source region is formed in the p-type body region, and then an isolation dielectric layer and a metal layer are formed to obtain a semiconductor power device.
  • a first trench is formed by a photolithography process, a shielding gate structure is formed in the first trench, and then a first insulating layer, a second insulating layer and a third insulating layer are used as The mask is self-aligned to etch the n-type substrate, a second trench is formed in the n-type substrate, and a fourth insulating layer and a gate electrode are formed in the second trench. Therefore, in the manufacturing method of the semiconductor power device of the present application, the gate is formed in the second trench on both sides of the first trench, and the formation quality of the gate is not limited by the thickness of the second insulating layer. Under certain conditions, the thickness of the second insulating layer can be reduced, so that the withstand voltage of the semiconductor power device is not affected.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种半导体功率器件的制造方法，包括：以第一绝缘层（31）、第二绝缘层（21）和第三绝缘层（33）为掩膜自对准的刻蚀n型衬底（20），在n型衬底（20）内形成第二沟槽（42），在第二沟槽（42）内形成第四绝缘层（23）和栅极（24）。

Description

半导体功率器件的制造方法
本申请要求在2020年10月20日提交中国专利局、申请号为202011127631.1的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请属于半导体功率器件技术领域，例如一种半导体功率器件的制造方法。
背景技术
相关技术中的一种半导体功率器件的制造方法包括：在提供的硅衬底上形成硬掩膜层，采用光刻工艺定义出沟槽位置，然后刻蚀掉沟槽位置处的硬掩膜层；以刻蚀后的硬掩膜层为掩膜对硅衬底进行刻蚀形成沟槽；覆盖沟槽的底部表面和侧面形成第一介质层；淀积第一多晶硅层，第一多晶硅层将形成有第一介质层的沟槽完全填充并延伸到沟槽外部；进行多晶硅回刻将位于沟槽外部的第一多晶硅层去除，刻蚀后剩余的第一多晶硅层形成屏蔽栅；以沟槽侧面的硅和第一多晶硅层为自对准边界对第一介质层进行自对准刻蚀，自对准刻蚀将位于沟槽顶部的第一介质层去除、位于沟槽底部的第一介质层保留，且所保留的第一介质层位于后续形成的体区的底部；在第一介质层去除后的沟槽的顶部区域内部表面形成第四绝缘层，第四绝缘层的厚度小于第一介质层的厚度；淀积第二多晶硅层，第二多晶硅层将第一介质层去除后且形成有第四绝缘层的沟槽的顶部区域完全填充；进行多晶硅回刻将位于沟槽外部的第二多晶硅层去除，刻蚀后剩余的第二多晶硅层形成多晶硅栅极。相关技术中的半导体功率器件的制造方法，为了保证多晶硅栅极的质量，需要形成足够厚度的第一介质层，但是第一介质层的厚度会影响沟槽底部的电荷耗尽，从而影响半导体功率器件的耐压。
发明内容
本申请提供了一种半导体功率器件的制造方法，在保证栅极质量的条件下，可以使半导体功率器件的耐压不受影响。
第一方面，本申请提供了一种半导体功率器件的制造方法，包括：
在n型衬底上形成第一绝缘层，刻蚀所述第一绝缘层形成开口；
在所述开口内形成绝缘侧墙；
以所述第一绝缘层和所述绝缘侧墙为掩膜对所述n型衬底进行刻蚀，在所述n型衬底内形成第一沟槽；
在所述第一沟槽内形成第二绝缘层和屏蔽栅；
在所述屏蔽栅的表面形成第三绝缘层；
刻蚀掉所述绝缘侧墙，以所述第一绝缘层、所述第二绝缘层和所述第三绝缘层为掩膜刻蚀所述n型衬底，在所述n型衬底内形成第二沟槽。
可选的，本申请的半导体功率器件的制造方法，还包括：
在所述第二沟槽内形成第四绝缘层和栅极，所述栅极通过所述第二绝缘层与所述屏蔽栅隔离；
刻蚀掉所述第一绝缘层和所述第三绝缘层；
在所述n型衬底内形成p型体区；
在所述p型体区内形成n型源区。
可选的，本申请的半导体功率器件的制造方法，还包括：
刻蚀掉所述第一绝缘层、所述第三绝缘层和所述第二沟槽的侧壁位置处的所述第二绝缘层；
在所述第二沟槽内形成第四绝缘层和栅极，所述栅极通过所述第四绝缘层与所述屏蔽栅隔离；
在所述n型衬底内形成p型体区；
在所述p型体区内形成n型源区。
可选的，本申请的半导体功率器件的制造方法，所述第一绝缘层包括氧化 硅层。
可选的，本申请的半导体功率器件的制造方法，所述第二绝缘层为氧化硅层。
可选的，本申请的半导体功率器件的制造方法，所述第三绝缘层为氧化硅层。
可选的，本申请的半导体功率器件的制造方法，所述绝缘侧墙为氮化硅层。
可选的，本申请的半导体功率器件的制造方法，在刻蚀形成所述第二沟槽时，采用各向异性刻蚀和各向同性刻蚀相结合的刻蚀方法。
可选的，本申请的半导体功率器件的制造方法，所述第二沟槽的深度小于所述第一沟槽的深。
本申请提供的半导体功率器件的制造方法，通过一次光刻工艺形成第一沟槽，以第一绝缘层、第二绝缘层和第三绝缘层为掩膜自对准的刻蚀n型衬底，在n型衬底内形成第二沟槽，在第二沟槽内形成第四绝缘层和栅极。本申请的半导体功率器件的制造方法，栅极的形成质量不受第二绝缘层的厚度限制，在保证栅极质量的条件下，可以减小第二绝缘层的厚度，使得半导体功率器件的耐压不受影响。
附图说明
图1至图6是本申请提供的半导体功率器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。
具体实施方式
以下将结合本申请实施例中的附图，完整地描述本申请的技术方案。显然，所描述的实施例是本申请的一部分实施例，而不是全部的实施例。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列示意图，放大了本 申请所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。
图1至图6是本申请提供的半导体功率器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。
首先，如图1所示，在提供的n型衬底20之上形成第一绝缘层31，n型衬底20通常为n型硅衬底，第一绝缘层31包括氧化硅层，例如可以为氧化硅层或者为氧化硅层-氮化硅层-氧化硅层的叠层。通过光刻工艺定义开口的位置，然后对第一绝缘层31进行刻蚀，在第一绝缘层31中形成至少一个开口40，开口40的数量由所设计的半导体功率器件的规格确定，本申请实施例中仅示例性的示出了两个开口40。
接下来，如图2所示，在第一绝缘层31的开口内形成绝缘侧墙32，绝缘侧墙32可选的为氮化硅层，示例性的，该工艺包括：先淀积一层氮化硅层，然后对所淀积形成的氮化硅层进行回刻，从而自对准的在开口40内的侧壁位置处形成绝缘侧墙32。形成绝缘侧墙32后，以第一绝缘层31和绝缘侧墙32为掩膜对n型衬底20进行刻蚀，在n型衬底20内形成第一沟槽41。
接下来，如图3所示，在第一沟槽内形成第二绝缘层21和屏蔽栅22，第二绝缘层21可选的为氧化硅层，通过热氧化工艺形成；屏蔽栅22通常为多晶硅栅，形成工艺包括：在形成第二绝缘层21后，先淀积一层多晶硅，然后对所淀积的多晶硅层进行回刻，刻蚀后剩余的多晶硅层形成屏蔽栅22。形成屏蔽栅22后，在屏蔽栅22的表面形成第三绝缘层33，第三绝缘层33可选的为氧化硅层，通过热氧化工艺形成，此时第三绝缘层33和第二绝缘层21会连接起来，从而屏蔽栅22会被第二绝缘层21和第三绝缘层33包裹起来。
接下来，如图4所示，刻蚀掉绝缘侧墙，以第一绝缘层31、第二绝缘层 21和第三绝缘层33为掩膜自对准的刻蚀n型衬底20，在n型衬底20内形成第二沟槽42，第二沟槽42的深度小于第一沟槽的深度。在刻蚀形成第二沟槽42时，可以采用各向异性刻蚀和各向同性刻蚀相结合的刻蚀方法，这样可以增加第二沟槽42的宽度，使得第二沟槽42的宽度大于前面形成的绝缘侧墙的宽度，以增加后面形成的栅极的宽度，从而使栅极可以更容易被引出。
需要注意的是，通过热氧化工艺形成第二绝缘层21时，要使得第一沟槽侧壁位置处的n型衬底20被氧化的厚度要小于绝缘侧墙的厚度，以保证将绝缘侧墙刻蚀掉后将n型衬底20暴露出来，从而可以对n型衬底20进行刻蚀以形成第二沟槽42。
接下来，如图5所示，在第二沟槽内形成第四绝缘层23，第四绝缘层23通常为氧化硅层，通过热氧化工艺形成。然后在第二沟槽内形成栅极24，形成工艺包括：先淀积一层多晶硅，然后对所淀积的多晶硅层进行回刻，刻蚀后剩余的多晶硅层形成栅极24，栅极24通过第二绝缘层21与屏蔽栅22隔离。之后刻蚀掉第一绝缘层和第三绝缘层。
可选的，在形成第二沟槽后，可以先刻蚀掉第一绝缘层、第三绝缘层和第二沟槽的侧壁位置处的第二绝缘层21，然后通过热氧化工艺形成第四绝缘层23，此时屏蔽栅22的暴露侧壁上也会形成第四绝缘层23，形成栅极24后，栅极通24过第四绝缘层23与屏蔽栅22隔离，如图6所示。此时栅极24具有更大的宽度，从而可以更加容易的被外部电极引出。
接下来，按照常规工艺，在n型衬底内形成p型体区，在p型体区内形成n型源区，之后形成隔离介质层和金属层等即可得到半导体功率器件。
本申请提供的半导体功率器件的制造方法，通过一次光刻工艺形成第一沟槽，在第一沟槽内形成屏蔽栅结构，然后以第一绝缘层、第二绝缘层和第 三绝缘层为掩膜自对准的刻蚀n型衬底，在n型衬底内形成第二沟槽，在第二沟槽内形成第四绝缘层和栅极。从而，本申请的半导体功率器件的制造方法，栅极形成在第一沟槽两侧的第二沟槽内，栅极的形成质量不受第二绝缘层的厚度限制，在保证栅极质量的条件下，可以减小第二绝缘层的厚度，使得半导体功率器件的耐压不受影响。

Claims (9)

  1. 半导体功率器件的制造方法，包括：
    在n型衬底上形成第一绝缘层，刻蚀所述第一绝缘层形成开口；
    在所述开口内形成绝缘侧墙；
    以所述第一绝缘层和所述绝缘侧墙为掩膜对所述n型衬底进行刻蚀，在所述n型衬底内形成第一沟槽；
    在所述第一沟槽内形成第二绝缘层和屏蔽栅；
    在所述屏蔽栅的表面形成第三绝缘层；
    刻蚀掉所述绝缘侧墙，以所述第一绝缘层、所述第二绝缘层和所述第三绝缘层为掩膜刻蚀所述n型衬底，在所述n型衬底内形成第二沟槽。
  2. 如权利要求1所述的方法，还包括：
    在所述第二沟槽内形成第四绝缘层和栅极，所述栅极通过所述第二绝缘层与所述屏蔽栅隔离；
    刻蚀掉所述第一绝缘层和所述第三绝缘层；
    在所述n型衬底内形成p型体区；
    在所述p型体区内形成n型源区。
  3. 如权利要求1所述的方法，还包括：
    刻蚀掉所述第一绝缘层、所述第三绝缘层和所述第二沟槽的侧壁位置处的所述第二绝缘层；
    在所述第二沟槽内形成第四绝缘层和栅极，所述栅极通过所述第四绝缘层与所述屏蔽栅隔离；
    在所述n型衬底内形成p型体区；
    在所述p型体区内形成n型源区。
  4. 如权利要求1所述的方法，其中，所述第一绝缘层包括氧化硅层。
  5. 如权利要求1所述的方法，其中，所述第二绝缘层为氧化硅层。
  6. 如权利要求1所述的方法，其中，所述第三绝缘层为氧化硅层。
  7. 如权利要求1所述的方法，其中，所述绝缘侧墙为氮化硅层。
  8. 如权利要求1所述的方法，其中，在刻蚀形成所述第二沟槽时，采用各向异性刻蚀和各向同性刻蚀相结合的刻蚀方法。
  9. 如权利要求1所述的方法，其中，所述第二沟槽的深度小于所述第一沟槽的深度。
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