CN111725293A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN111725293A
CN111725293A CN201910648589.9A CN201910648589A CN111725293A CN 111725293 A CN111725293 A CN 111725293A CN 201910648589 A CN201910648589 A CN 201910648589A CN 111725293 A CN111725293 A CN 111725293A
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contact
forming
gate
layer
dielectric layer
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黄圣富
黄崇勋
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本发明提供一种半导体结构及其形成方法。在半导体结构中，至少在基底中接触沟渠的侧壁上形成接触窗间隙壁，因此金属硅化物层只会位于接触沟渠底面上，而不会位于接触沟渠的侧壁上。使得栅极与金属硅化物层之间的距离可以增加，而能减少因栅极诱导而生的漏电流。

Description

半导体结构及其形成方法
技术领域
本发明涉及一种半导体结构及其形成方法，尤其涉及一种可防止由栅极引起漏电流的半导体结构及其形成方法。
背景技术
在MOSFET的源极和漏极上形成接触开口之后，通常会在源极和漏极的表面上形成金属硅化物层以降低接触电阻。然而，随着集积度的增加，临界尺寸跟着减小，漏极漏电流也跟着增加，从而对MOSFET的性能产生不利影响。
发明内容
本发明提供一种半导体结构以减小由栅极引起的漏电流。
上述半导体结构包括设置在基底上的栅极结构；设置在栅极结构两侧的基底中的源极和漏极；设置在基底和栅极结构上的介电层；设置在介电层中的两个接触开口，以分别露出源极和漏极；分别设置在源极和漏极之中以及两个接触开口之下的两个接触沟渠；分别覆盖接触沟渠侧壁的接触窗间隙壁，以避免栅极引起的漏电流；设置在接触沟渠的底面之下的两个金属硅化物层；以及填充在接触沟渠和接触开口中的接触插塞。
在本发明的一些实施例中，所述接触窗间隙壁还覆盖所述接触开口的侧壁。
在本发明的另一些实施例中，所述接触窗间隙壁的材料包括氧化硅或氮化硅。
在本发明的又一些实施例中，所述金属硅化物层的材料包括TiSi2、NiSi2或CoSi2。
本发明还提供一种半导体的形成方法。首先，在基底上形成栅极结构，再于所述栅极结构两侧的所述基底中形成源极和漏极。接着，在所述基底和所述栅极结构上形成介电层。然后，在所述介电层中形成两个接触开口，以分别暴露所述源极和所述漏极。并接着在所述源极和漏极之中并在所述两个接触开口之下形成两个接触沟渠。形成两个接触窗间隙壁分别覆盖所述两个接触沟渠的侧壁，以避免产生栅极诱发的漏电流。在所述接触沟渠的底面上形成两个金属硅化物层，然后在所述两个接触沟渠和所述两个接触开口中形成两个接触插塞。
在一些实施例中，所述接触窗间隙壁的形成方法包括以热氧化法或热氮化法分别在所述两个接触沟渠的表面上形成接触介电层，再等向性地蚀刻所述接触介电层，以在所述接触沟渠的所述侧壁上形成所述接触窗间隙壁并暴露所述基底。
在另一些实施例中，所述接触窗间隙壁的形成方法包括形成接触介电层，以共形地覆盖所述介电层、所述接触开口和所述接触沟渠的暴露表面。然后，非等向性地蚀刻所述接触介电层以在所述接触开口和所述接触沟渠的侧壁上形成所述接触窗间隙壁并暴露所述基底。
在又一些实施例中，在形成所述介电层和形成所述接触开口的步骤之间，还包括形成硬罩幕层在所述介电层之上。当蚀刻介电层以形成接触开口时，所述硬罩幕层用作蚀刻罩幕。然后在形成所述接触窗间隙壁和形成所述金属硅化物层的步骤之间，移除所述硬罩幕层。
基于上述，由于接触窗间隙壁只形成在基底中接触沟渠的侧壁上，因此金属硅化物层只会在接触沟渠的底面上生成，而不会在于接触沟渠的侧壁上生成。所以，可增加栅极与金属硅化物层之间的距离，并因而能减少因栅极诱导而产生的漏电流。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A-图1B和图2A-图2B是依据本发明一实施例的半导体结构的制造流程剖面结构示意图；
图1A-图1B和图3A-图3B是依据本发明另一实施例的半导体结构的制造流程剖面结构示意图。
附图标号说明：
100：基底
102：栅极介电层
104：栅极层
106：栅极罩幕层
108：栅极间隙壁
110：源极、漏极
112：介电层
114：硬罩幕层
116a：接触开口
116b：接触沟渠
118a：栅极开口
118b：栅极沟渠
120a、120b：接触窗介电层
122a、122b：接触窗间隙壁
124a：栅极接触窗间隙壁
126：金属硅化物层
128：接触插塞
130：栅极插塞
具体实施方式
图1A-图1B和图2A-图2B是依据本发明一实施例的半导体结构的制造流程剖面结构示意图。图1A-图1B和图3A-图3B是依据本发明另一实施例的半导体结构的制造流程剖面结构示意图。
在图1A中，在基底100上依次形成栅极介电层102，栅极层104和栅极罩幕层106。接下来，通过诸如微影蚀刻法来图案化栅极介电层102、栅极层104和栅极罩幕层106，以形成具有栅极介电层102、栅极层104和栅极罩幕层106的栅极结构。在此步骤中，当蚀刻栅极层104和栅极介电层102时，可使用栅极罩幕层106为蚀刻罩幕。栅极介电层102例如可为氧化硅层，或具有高介电常数的介电层，例如氧化铪层或氧化锆层。栅极层104是导电层，例可为掺杂多晶硅层或金属层(例如可为钨层)。栅极罩幕层106可以是氧化硅层。
接下来，在基底100和栅极结构上形成共形的绝缘层(例如可为氧化硅层)。然后，非等向性地蚀刻绝缘层，以在栅极结构的侧壁上形成栅极间隙壁108。随后，以离子植入法在栅极结构的两侧的基底100中形成源极/漏极110。在基底100上依次形成介电层112和硬罩幕层114。介电层112可以是氧化硅层或具有低介电常数的介电层，例如掺氟氧化硅层、碳掺杂氧化物层(carbon-doped oxide layer；CDO)、多孔氧化硅层或旋涂玻璃层。硬罩幕层114可以是氮化硅层。
在图1B中，图案化硬罩幕层114和介电层112，图案化的方法例如可为微影蚀刻法，以在介电层112中形成接触开口116a和栅极开口118a，以分别暴露出源极/漏极110和栅极罩幕层106。然后，过蚀刻被接触开口116a暴露的基底100和被栅极开口118a暴露的栅极罩幕层106，在基底100的源极/漏极110中和栅极罩幕层106中分别形成接触沟渠116b和栅极沟渠118b。
接下来，有两种方法可以用来完成半导体结构制程的剩下步骤。第一种方法显示在图2A和图2B中，第二种方法显示在图3A和图3B中。
在第一种方法的图2A中，在基底100、介电层112和硬罩幕层114的暴露表面上共形地形成接触介电层120a。接触介电层120a例如可为氧化硅层或氮化硅层，接触介电层120a的形成方法例如可为化学气相沉积法(chemical vapor deposition；CVD)。
在第一种方法的图2B中，对接触介电层120a进行非等向性蚀刻，以在接触开口116a和接触沟渠116b的侧壁上形成接触窗间隙壁122a并暴露出基底100，并在栅极开口118a和栅极沟渠118b的侧壁上形成栅极接触窗间隙壁124a并暴露出硬罩幕层114。请注意，接触沟渠116b的外露侧壁被接触窗间隙壁122a覆盖，只有接触沟渠116b的底面未被接触窗间隙壁122a覆盖而暴露出基底100。
然后，使用自对准硅化物制程(salicidation process)，在暴露的基底100上形成金属硅化物层126。自对准硅化物制程包括沉积金属层，然后进行热处理以允许金属层与暴露基底100中的硅反应以形成金属硅化物层126。金属硅化物层126的材料例如可为TiSi2、NiSi2或CoSi2。
在此步骤中，由于接触窗间隙壁122a覆盖着接触沟渠116b的侧壁，因此只能在接触沟渠116b的底面上形成金属硅化物层126，并无法在接触沟渠116b的侧壁上形成金属硅化物。因此，金属硅化物层126和栅极层104之间可以保持足够远的距离，以避免产生由栅极层104所引起的漏电流。
接下来，去除硬罩幕层114后，沉积金属层以填充接触开口116a、接触沟渠116b、栅极开口118a和栅极沟渠118b，再进行回蚀。因此，在接触开口116a和接触沟渠116b中形成接触插塞128，并且在栅极开口118a和栅极沟渠118b中形成栅极插塞130。金属层可以是钨层。
在第二种方法的图3A中，则只在基底100中的接触沟渠116b的暴露表面上形成接触介电层120b。接触介电层120b例如可为氧化硅层或氮化硅层，并且可以通过热氧化法或热氮化法而形成。
在第二种方法的图3B中，对接触介电层120b进行非等向性地蚀刻，以在接触沟渠116b的侧壁上形成接触窗间隙壁122b，并暴露出基底100。请注意，接触沟渠116b的外露侧壁被接触窗间隙壁122b所覆盖着，只有接触沟渠116b的底面未被接触窗间隙壁122b覆盖并暴露基底100。
然后，使用自对准硅化物制程在暴露的基底100上形成金属硅化物层126，其包括沉积金属层，然后进行热处理以允许金属层与暴露基底100中的硅反应以形成金属硅化物层126。金属硅化物层126的材料例如可为TiSi2、NiSi2或CoSi2。
在此步骤中，由于接触窗间隙壁122b覆盖接触沟渠116b的侧壁，因此只能在接触沟渠116b的底面上形成金属硅化物层126，并且不能在接触沟渠116b的侧壁上形成金属硅化物。因此，金属硅化物层126和栅极层104之间可以保持足够远的距离，以避免产生由栅极层104所引起的漏电流。
基于上述，由于接触窗间隙壁只形成在基底中接触沟渠的侧壁上，因此金属硅化物层只能在接触沟渠的底面上生成，而不能于接触沟渠的侧壁上生成。所以，可增加栅极与金属硅化物层之间的距离，并因而能减少因栅极诱导而产生的漏电流。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视权利要求所界定的为准。

Claims (16)

1.一种半导体结构，用于避免漏电流，其特征在于，包括：
栅极结构，位于基底上；
源极和漏极，位于所述栅极结构两侧的所述基底中；
介电层，位于所述基底和所述栅极结构上；
两个接触开口，位于所述介电层之中，以分别暴露所述源极和所述漏极；
两个接触沟渠，分别位于所述源极和漏极之中并位于所述两个接触开口之下；
两个接触窗间隙壁，分别覆盖所述接触沟渠的侧壁，以避免栅极引起的漏电流；
两个金属硅化物层，分别设置在所述接触沟渠的底面下；以及
两个接触插塞，分别填充于所述接触沟渠和所述接触开口之中。
2.根据权利要求1所述的半导体结构，其中所述接触窗间隙壁还覆盖所述接触开口的侧壁。
3.根据权利要求1所述的半导体结构，其中所述接触窗间隙壁的材料包括氧化硅或氮化硅。
4.根据权利要求1所述的半导体结构，其中所述金属硅化物层的材料包括TiSi2、NiSi2或CoSi2。
5.根据权利要求1所述的半导体结构，其中所述栅极结构包括：
栅极介电层，位于所述基底上；
栅极层，位于所述栅极介电层上；以及
栅极罩幕层，位于所述栅极层上。
6.根据权利要求5所述的半导体结构，还包括位于所述栅极结构的侧壁上的栅极间隙壁。
7.一种半导体结构的形成方法，其特征在于，所述方法包括：
形成栅极结构在基底上；
形成源极和漏极在所述栅极结构两侧的所述基底中；
形成介电层在所述基底和所述栅极结构上；
形成两个接触开口在所述介电层中，以分别暴露所述源极和所述漏极；
形成两个接触沟渠分别在所述源极和漏极之中并位于所述两个接触开口之下；
形成两个接触窗间隙壁分别覆盖所述两个接触沟渠的侧壁，以避免栅极引起的漏电流；
形成两个金属硅化物层在所述接触沟渠的底面上；以及
形成两个接触插塞以填满所述两个接触沟渠和所述两个接触开口。
8.根据权利要求7所述半导体结构的形成方法，其中所述接触窗间隙壁的形成方法包括：
以热氧化法或热氮化法分别在所述两个接触沟渠的表面上形成接触介电层；以及
非等向性地蚀刻所述接触介电层，以在所述接触沟渠的所述侧壁上形成所述接触窗间隙壁并暴露所述基底。
9.根据权利要求7所述半导体结构的形成方法，其中所述接触窗间隙壁的形成方法包括：
形成接触介电层，以共形地覆盖所述介电层、所述接触开口和所述接触沟渠的暴露表面；以及
非等向性地蚀刻所述接触介电层以在所述接触开口和所述接触沟渠的所述侧壁上形成所述接触窗间隙壁并暴露所述基底。
10.根据权利要求9所述半导体结构的形成方法，其中所述接触介电层的形成方法包括化学气相沉积法。
11.根据权利要求9所述半导体结构的形成方法，其中所述接触介电层是氧化硅层或氮化硅层。
12.根据权利要求7所述半导体结构的形成方法，在形成所述介电层和形成所述接触开口的步骤之间，还包括形成硬罩幕层在所述介电层之上，其中所述硬罩幕层用作蚀刻罩幕。
13.根据权利要求12所述半导体结构的形成方法，在形成所述两个接触窗间隙壁和形成所述金属硅化物层的步骤之间，还包括移除所述硬罩幕层。
14.根据权利要求7所述半导体结构的形成方法，其中所述金属硅化物层的材料包括TiSi2、NiSi2或CoSi2。
15.根据权利要求7所述半导体结构的形成方法，其中形成所述栅极结构的步骤包括：
在所述基底上形成栅极介电层；
在所述基底上形成栅极介电层；
在所述栅极层上形成栅极罩幕层；以及
顺序地图案化所述栅极罩幕层，所述栅极层和所述栅极介电层以形成所述栅极结构。
16.根据权利要求15所述半导体结构的形成方法，在形成所述栅极结构和形成所述源极和所述漏极的步骤之间，还包括在所述栅极结构的侧壁上形成两个栅极间隙壁。
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Application publication date: 20200929