TWI708390B - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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TWI708390B
TWI708390B TW108116145A TW108116145A TWI708390B TW I708390 B TWI708390 B TW I708390B TW 108116145 A TW108116145 A TW 108116145A TW 108116145 A TW108116145 A TW 108116145A TW I708390 B TWI708390 B TW I708390B
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forming
gate
layer
dielectric layer
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TW202036909A (zh
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黃聖富
黃崇勳
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南亞科技股份有限公司
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Abstract

提供一種半導體結構及其形成方法。在半導體結構中，至少在基底中接觸溝渠的側壁上形成接觸窗間隙壁，因此金屬矽化物層只會位於接觸溝渠底面上，而不會位於接觸溝渠的側壁上。使得閘極與金屬矽化物層之間的距離可以增加，而能減少因閘極誘導而生的漏電流。

Description

半導體結構及其形成方法
本發明是有關於一種半導體結構及其形成方法，且特別是有關於一種可防止由閘極引起漏電流的半導體結構及其形成方法。
在MOSFET的源極和汲極上形成接觸開口之後，通常會在源極和汲極的表面上形成金屬矽化物層以降低接觸電阻。然而，隨著集積度的增加，臨界尺寸跟著減小，汲極漏電流也跟著增加，從而對MOSFET的性能產生不利影響。
本發明提供一種半導體結構以減小由閘極引起的漏電流。
上述半導體結構包括設置在基底上的閘極結構；設置在閘極結構兩側的基底中的源極和汲極；設置在基底和閘極結構上的介電層；設置在介電層中的兩個接觸開口，以分別露出源極和汲極；分別設置在源極和汲極之中以及兩個接觸開口之下的兩個接觸溝渠；分別覆蓋接觸溝渠側壁的接觸窗間隙壁，以避免閘極引起的漏電流；設置在接觸溝渠的底面之下的兩個金屬矽化物層；以及填充在接觸溝渠和接觸開口中的接觸插塞。
在本發明的一些實施例中，所述接觸窗間隙壁還覆蓋所述接觸開口的側壁。
在本發明的另一些實施例中，所述接觸窗間隙壁的材料包括氧化矽或氮化矽。
在本發明的又一些實施例中，所述金屬矽化物層的材料包括TiSi 2、NiSi 2或CoSi 2。
本發明還提供一種半導體的形成方法。首先，在基底上形成閘極結構，再於所述閘極結構兩側的所述基底中形成源極和汲極。接著，在所述基底和所述閘極結構上形成介電層。然後，在所述介電層中形成兩個接觸開口，以分別暴露所述源極和所述汲極。並接著在所述源極和汲極之中並在所述兩個接觸開口之下形成兩個接觸溝渠。形成兩個接觸窗間隙壁分別覆蓋所述兩個接觸溝渠的側壁，以避免產生閘極誘發的漏電流。在所述接觸溝渠的底面上形成兩個金屬矽化物層，然後在所述兩個接觸溝渠和所述兩個接觸開口中形成兩個接觸插塞。
在一些實施例中，所述接觸窗間隙壁的形成方法包括以熱氧化法或熱氮化法分別在所述兩個接觸溝渠的表面上形成接觸介電層，再等向性地蝕刻所述接觸介電層，以在所述接觸溝渠的所述側壁上形成所述接觸窗間隙壁並暴露所述基底。
在另一些實施例中，所述接觸窗間隙壁的形成方法包括形成接觸介電層，以共形地覆蓋所述介電層、所述接觸開口和所述接觸溝渠的暴露表面。然後，非等向性地蝕刻所述接觸介電層以在所述接觸開口和所述接觸溝渠的側壁上形成所述接觸窗間隙壁並暴露所述基底。
在又一些實施例中，在形成所述介電層和形成所述接觸開口的步驟之間，還包括形成硬罩幕層在所述介電層之上。當蝕刻介電層以形成接觸開口時，所述硬罩幕層用作蝕刻罩幕。然後在形成所述接觸窗間隙壁和形成所述金屬矽化物層的步驟之間，移除所述硬罩幕層。
基於上述，由於接觸窗間隙壁只形成在基底中接觸溝渠的側壁上，因此金屬矽化物層只會在接觸溝渠的底面上生成，而不會在於接觸溝渠的側壁上生成。所以，可增加閘極與金屬矽化物層之間的距離，並因而能減少因閘極誘導而產生的漏電流。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A-1B和2A-2B是依據本發明一實施例之半導體結構的製造流程剖面結構示意圖。圖1A-1B和3A-3B是依據本發明另一實施例之半導體結構的製造流程剖面結構示意圖。
在圖1A中，在基底100上依次形成閘極介電層102，閘極層104和閘極罩幕層106。接下來，通過諸如微影蝕刻法來圖案化閘極介電層102、閘極層104和閘極罩幕層106，以形成具有閘極介電層102、閘極層104和閘極罩幕層106的閘極結構。在此步驟中，當蝕刻閘極層104和閘極介電層102時，可使用閘極罩幕層106為蝕刻罩幕。閘極介電層102例如可為氧化矽層，或具有高介電常數的介電層，例如氧化鉿層或氧化鋯層。閘極層104是導電層，例可為摻雜多晶矽層或金屬層（例如可為鎢層）。閘極罩幕層106可以是氧化矽層。
接下來，在基底100和閘極結構上形成共形的絕緣層(例如可為氧化矽層)。然後，非等向性地蝕刻絕緣層，以在閘極結構的側壁上形成閘極間隙壁108。隨後，以離子植入法在閘極結構的兩側的基底100中形成源極/汲極110。在基底100上依次形成介電層112和硬罩幕層114。介電層112可以是氧化矽層或具有低介電常數的介電層，例如摻氟氧化矽層、碳摻雜氧化物層（carbon-doped oxide layer; CDO）、多孔氧化矽層或旋塗玻璃層。硬罩幕層114可以是氮化矽層。
在圖1B中，圖案化硬罩幕層114和介電層112，圖案化的方法例如可為微影蝕刻法，以在介電層112中形成接觸開口116a和閘極開口118a，以分別暴露出源極/汲極110和閘極罩幕層106。然後，過蝕刻被接觸開口116a暴露的基底100和被閘極開口118a暴露的閘極罩幕層106，在基底100的源極/汲極110中和閘極罩幕層106中分別形成接觸溝渠116b和閘極溝渠118b。
接下來，有兩種方法可以用來完成半導體結構製程的剩下步驟。第一種方法顯示在圖2A和2B中，第二種方法顯示在圖3A和3B中。
在第一種方法的圖2A中，在基底100、介電層112和硬罩幕層114的暴露表面上共形地形成接觸介電層120a。接觸介電層120a例如可為氧化矽層或氮化矽層，接觸介電層120a的形成方法例如可為化學氣相沉積法（chemical vapor deposition; CVD）。
在第一種方法的圖2B中，對接觸介電層120a進行非等向性蝕刻，以在接觸開口116a和接觸溝渠116b的側壁上形成接觸窗間隙壁122a並暴露出基底100，並在閘極開口118a和閘極溝渠118b的側壁上形成閘極接觸窗間隙壁124a並暴露出硬罩幕層114。請注意，接觸溝渠116b的外露側壁被接觸窗間隙壁122a覆蓋，只有接觸溝渠116b的底面未被接觸窗間隙壁122a覆蓋而暴露出基底100。
然後，使用自對準矽化物製程(salicidation process)，在暴露的基底100上形成金屬矽化物層126。自對準矽化物製程包括沉積金屬層，然後進行熱處理以允許金屬層與暴露基底100中的矽反應以形成金屬矽化物層126。金屬矽化物層126的材料例如可為TiSi 2、NiSi 2或CoSi 2。
在此步驟中，由於接觸窗間隙壁122a覆蓋著接觸溝渠116b的側壁，因此只能在接觸溝渠116b的底面上形成金屬矽化物層126，並無法在接觸溝渠116b的側壁上形成金屬矽化物。因此，金屬矽化物層126和閘極層104之間可以保持足夠遠的距離，以避免產生由閘極層104所引起的漏電流。
接下來，去除硬罩幕層114後，沉積金屬層以填充接觸開口116a、接觸溝渠116b、閘極開口118a和閘極溝渠118b，再進行回蝕。因此，在接觸開口116a和接觸溝渠116b中形成接觸插塞128，並且在閘極開口118a和閘極溝渠118b中形成閘極插塞130。金屬層可以是鎢層。
在第二種方法的圖3A中，則只在基底100中的接觸溝渠116b的暴露表面上形成接觸介電層120b。接觸介電層120b例如可為氧化矽層或氮化矽層，並且可以通過熱氧化法或熱氮化法而形成。
在第二種方法的圖3B中，對接觸介電層120b進行非等向性地蝕刻，以在接觸溝渠116b的側壁上形成接觸窗間隙壁122b，並暴露出基底100。請注意，接觸溝渠116b的外露側壁被接觸窗間隙壁122b所覆蓋著，只有接觸溝渠116b的底面未被接觸窗間隙壁122b覆蓋並暴露基底100。
然後，使用自對準矽化物製程在暴露的基底100上形成金屬矽化物層126，其包括沉積金屬層，然後進行熱處理以允許金屬層與暴露基底100中的矽反應以形成金屬矽化物層126。金屬矽化物層126的材料例如可為TiSi 2、NiSi 2或CoSi 2。
在此步驟中，由於接觸窗間隙壁122b覆蓋接觸溝渠116b的側壁，因此只能在接觸溝渠116b的底面上形成金屬矽化物層126，並且不能在接觸溝渠116b的側壁上形成金屬矽化物。因此，金屬矽化物層126和閘極層104之間可以保持足夠遠的距離，以避免產生由閘極層104所引起的漏電流。
基於上述，由於接觸窗間隙壁只形成在基底中接觸溝渠的側壁上，因此金屬矽化物層只能在接觸溝渠的底面上生成，而不能於接觸溝渠的側壁上生成。所以，可增加閘極與金屬矽化物層之間的距離，並因而能減少因閘極誘導而產生的漏電流。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100：基底 102：閘極介電層 104：閘極層 106：閘極罩幕層 108：閘極間隙壁 110：源極、汲極 112：介電層 114：硬罩幕層 116a：接觸開口 116b：接觸溝渠 118a：閘極開口 118b：閘極溝渠 120a、120b：接觸窗介電層 122a、122b：接觸窗間隙壁 124a：閘極接觸窗間隙壁 126：金屬矽化物層 128：接觸插塞 130：閘極插塞
圖1A-1B和2A-2B是依據本發明一實施例之半導體結構的製造流程剖面結構示意圖。 圖1A-1B和3A-3B是依據本發明另一實施例之半導體結構的製造流程剖面結構示意圖。
100：基底 102：閘極介電層 104：閘極層 106：閘極罩幕層 108：閘極間隙壁 110：源極、汲極 112：介電層 122a：接觸窗間隙壁 124a：閘極接觸窗間隙壁 126：金屬矽化物層 128：接觸插塞 130：閘極插塞

Claims (16)

  1. 一種半導體結構，用於避免漏電流，包括：閘極結構，位在基底上；源極和汲極，位在所述閘極結構兩側的所述基底中；介電層，位在所述基底和所述閘極結構上；兩個接觸開口，位在所述介電層之中，以分別暴露所述源極和所述汲極；兩個接觸溝渠，分別位在所述源極和汲極之中並位在所述兩個接觸開口之下；兩個接觸窗間隙壁，分別覆蓋所述接觸溝渠的側壁，以避免閘極引起的漏電流；兩個金屬矽化物層，分別設置在所述接觸溝渠的底面下，其中所述兩個金屬矽化物層的頂面低於所述閘極結構與所述基底的接觸面；以及兩個接觸插塞，分別填充於所述接觸溝渠和所述接觸開口之中。
  2. 如請求項1所述的半導體結構，其中所述接觸窗間隙壁還覆蓋所述接觸開口的側壁。
  3. 如請求項1所述的半導體結構，其中所述接觸窗間隙壁的材料包括氧化矽或氮化矽。
  4. 如請求項1所述的半導體結構，其中所述金屬矽化物層的材料包括TiSi2、NiSi2或CoSi2。
  5. 如請求項1所述的半導體結構，其中所述閘極結構包括：閘極介電層，位於所述基底上；閘極層，位於所述閘極介電層上；以及閘極罩幕層，位於所述閘極層上。
  6. 如請求項5所述的半導體結構，還包括位在所述閘極結構的側壁上的閘極間隙壁。
  7. 一種半導體結構的形成方法，所述方法包括：形成閘極結構在基底上；形成源極和汲極在所述閘極結構兩側的所述基底中；形成介電層在所述基底和所述閘極結構上；形成兩個接觸開口在所述介電層中，以分別暴露所述源極和所述汲極；形成兩個接觸溝渠分別在所述源極和汲極之中並位在所述兩個接觸開口之下；形成兩個接觸窗間隙壁分別覆蓋所述兩個接觸溝渠的側壁，以避免閘極引起的漏電流；形成兩個金屬矽化物層在所述接觸溝渠的底面上，其中所述兩個金屬矽化物層的頂面低於所述閘極結構與所述基底的接觸面；以及形成兩個接觸插塞以填滿所述兩個接觸溝渠和所述兩個接觸開口。
  8. 如請求項7所述半導體結構的形成方法，其中所述接觸窗間隙壁的形成方法包括：以熱氧化法或熱氮化法分別在所述兩個接觸溝渠的表面上形成接觸介電層；以及非等向性地蝕刻所述接觸介電層，以在所述接觸溝渠的所述側壁上形成所述接觸窗間隙壁並暴露所述基底。
  9. 如請求項7所述半導體結構的形成方法，其中所述接觸窗間隙壁的形成方法包括：形成接觸介電層，以共形地覆蓋所述介電層、所述接觸開口和所述接觸溝渠的暴露表面；以及非等向性地蝕刻所述接觸介電層以在所述接觸開口和所述接觸溝渠的所述側壁上形成所述接觸窗間隙壁並暴露所述基底。
  10. 如請求項9所述半導體結構的形成方法，其中所述接觸介電層的形成方法包括化學氣相沉積法。
  11. 如請求項9所述半導體結構的形成方法，其中所述接觸介電層是氧化矽層或氮化矽層。
  12. 如請求項7所述半導體結構的形成方法，在形成所述介電層和形成所述接觸開口的步驟之間，還包括形成硬罩幕層在所述介電層之上，其中所述硬罩幕層用作蝕刻罩幕。
  13. 如請求項12所述半導體結構的形成方法，在形成所述兩個接觸窗間隙壁和形成所述金屬矽化物層的步驟之間，還包括移除所述硬罩幕層。
  14. 如請求項7所述半導體結構的形成方法，其中所述金屬矽化物層的材料包括TiSi2、NiSi2或CoSi2。
  15. 如請求項7所述半導體結構的形成方法，其中形成所述閘極結構的所述步驟包括：在所述基底上形成閘極介電層；在所述閘極介電層上形成閘極層；在所述閘極層上形成閘極罩幕層；以及順序地圖案化所述閘極罩幕層，所述閘極層和所述閘極介電層以形成所述閘極結構。
  16. 如請求項15所述半導體結構的形成方法，在形成所述閘極結構和形成所述源極和所述汲極的步驟之間，還包括在所述閘極結構的側壁上形成兩個閘極間隙壁。
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