CN114496917A - 半导体功率器件的制造方法 - Google Patents

半导体功率器件的制造方法 Download PDF

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CN114496917A
CN114496917A CN202011263819.9A CN202011263819A CN114496917A CN 114496917 A CN114496917 A CN 114496917A CN 202011263819 A CN202011263819 A CN 202011263819A CN 114496917 A CN114496917 A CN 114496917A
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groove
semiconductor power
power device
layer
forming
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毛振东
徐真逸
刘伟
刘磊
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Suzhou Dongwei Semiconductor Co ltd
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Suzhou Dongwei Semiconductor Co ltd
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Priority to CN202011263819.9A priority Critical patent/CN114496917A/zh
Priority to KR1020227030936A priority patent/KR20220137965A/ko
Priority to US18/016,200 priority patent/US20230274941A1/en
Priority to PCT/CN2020/131291 priority patent/WO2022099786A1/zh
Priority to JP2022550817A priority patent/JP2023515135A/ja
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Abstract

本发明属于半导体功率器件技术领域，具体公开了一种半导体功率器件的制造方法，包括：形成第一绝缘介质层，所述第一绝缘介质层覆盖所述第二沟槽的侧壁和底部；形成一层光刻胶，所述光刻胶填满所述第二沟槽；进行光刻，将位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层暴露出来，并刻蚀掉位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层。本发明的半导体功率器件的制造方法，栅极通过第一绝缘介质层与屏蔽栅隔离层，通过增加第一绝缘介质层的厚度可以降低栅源电容，并降低栅源漏电，提高半导体功率器件的可靠性。

Description

半导体功率器件的制造方法
技术领域
本发明实施例涉及半导体功率器件技术领域，尤其涉及一种半导体功率器件的制造方法。
背景技术
现有技术的一种半导体功率器件的制造方法包括：首先，如图1所示，在硅衬底10上形成硬掩膜层11，采用光刻工艺定义沟槽位置，然后对硬掩膜层11进行刻蚀并继续对硅衬底10进行刻蚀以形成沟槽12；接下来，如图2所示，在沟槽内形成第一绝缘介质层13，然后淀积第一多晶硅层并对该第一多晶硅层进行回刻将位于沟槽外部的第一多晶硅层去除，刻蚀后剩余的第一多晶硅层形成屏蔽栅14，然后以沟槽12侧面的硅衬底部分和屏蔽栅14为自对准边界对第一绝缘介质层13进行自对准刻蚀，将位于沟槽上部的第一绝缘介质层去除而保留沟槽下部的第一绝缘介质层13；接下来，如图3所示，形成第二绝缘介质层15，然后淀积第二多晶硅层并对该第二多晶硅层进行回刻将位于沟槽外部的第二多晶硅层去除，刻蚀后剩余的第二多晶硅层形成多晶硅栅极16。现有技术的半导体功率器件的制造方法，多晶硅栅极16与屏蔽栅14之间由第二绝缘介质层15隔离，由于第二绝缘介质层15还作为多晶硅栅极16与硅衬底10之间的栅介质层使用，因此第二绝缘介质层15的厚度较薄，这使得半导体功率器件的栅源电容较小，且栅源漏电较大。
发明内容
有鉴于此，本发明的目的是提供一种半导体功率器件的制造方法，以降低半导体功率器件的栅源电容，并降低半导体功率器件的栅源漏电。
为达到本发明的上述目的，本发明提供了一种半导体功率器件的制造方法，包括：
在n型衬底内形成第一沟槽，在所述第一沟槽内形成场氧化层和屏蔽栅；
以所述n型衬底和所述屏蔽栅为自对准边界对所述场氧化层进行自对准刻蚀，将所述第一沟槽上部内的所述场氧化层刻蚀掉，在所述第一沟槽的上部形成且介于所述屏蔽栅与所述n型衬底之间的第二沟槽；
形成第一绝缘介质层，所述第一绝缘介质层覆盖所述第二沟槽的侧壁和底部；
形成一层光刻胶，所述光刻胶填满所述第二沟槽；
进行光刻，将位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层暴露出来，然后刻蚀掉位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层，保留位于所述第二沟槽内且靠近所述屏蔽栅一侧的所述第一绝缘介质层；
去除掉所述光刻胶，在所述第二沟槽内形成栅介质层和栅极。
可选的，本发明的半导体功率器件的制造方法，还包括：
在所述n型衬底内形成p型体区；
在所述p型体区内形成n型源区。
可选的，本发明的半导体功率器件的制造方法，所述第一绝缘介质层为氧化硅层。
可选的，本发明的半导体功率器件的制造方法，形成第一绝缘介质层，包括：
采用次常压化学汽相沉积工艺形成第一绝缘介质层。
可选的，本发明的半导体功率器件的制造方法，刻蚀掉位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层，包括：
采用湿法刻蚀工艺刻蚀掉位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层。
可选的，本发明的半导体功率器件的制造方法，所述n型衬底为硅衬底。
可选的，本发明的半导体功率器件的制造方法，所述第一绝缘介质层的厚度大于所述栅介质层的厚度。
本发明提供的半导体功率器件的制造方法，通过在第一绝缘介质层上形成光刻胶，以光刻胶为掩膜保留位于第二沟槽内且靠近屏蔽栅一侧的第一绝缘介质层，如此，可以使得第一绝缘介质层的厚度较厚，当通过此第一绝缘介质层对栅极与屏蔽栅隔离时，可以降低栅源电容，并降低栅源漏电，提高半导体功率器件的可靠性。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。
图1至图3是现有技术的一种半导体功率器件的制造方法的制造工艺中的主要结构的剖面结构示意图；
图4至图7是本发明提供的半导体功率器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。
具体实施方式
以下将结合本发明实施例中的附图，完整地描述本发明的技术方案。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。同时，为清楚地说明本发明的具体实施方式，说明书附图中所列示意图，放大了本发明所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。
图4至图7是本发明提供的半导体功率器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。
首先，如图4所示，在提供的n型衬底20内形成第一沟槽31，n型衬底20通常为硅衬底，第一沟槽31的数量由所设计的半导体功率器件的规格确定，本发明实施例中仅示例性的示出了两个第一沟槽31。然后，按照常规工艺在第一沟槽31内形成场氧化层21和屏蔽栅22，并以n型衬底20和屏蔽栅22为自对准边界对场氧化层21进行自对准刻蚀，将第一沟槽31上部内的场氧化层21刻蚀掉，在第一沟槽31的上部形成且介于屏蔽栅22与n型衬底20之间的第二沟槽32。
接下来，如图5所示，形成第一绝缘介质层23，第一绝缘介质层23应覆盖第二沟槽的侧壁和底部，第一绝缘介质层23不能填满第二沟槽。第一绝缘介质层23通常为氧化硅层，可以采用次常压化学汽相沉积工艺形成。然后形成一层光刻胶24，光刻胶24应填满第二沟槽，之后进行光刻，将位于第二沟槽内且靠近n型衬底20一侧的第一绝缘介质层23暴露出来。
接下来，如图6所示，刻蚀掉位于第二沟槽内且靠近n型衬底20一侧的第一绝缘介质层，而保留位于第二沟槽内且靠近屏蔽栅22一侧的第一绝缘介质层23。在该步刻蚀第一绝缘介质层23时，可以采用湿法刻蚀工艺，这样对第一绝缘介质层23进行刻蚀时可以不受氧化硅、硅的刻蚀选择比限制。
接下来，如图7所示，去除掉光刻胶。
最后，按照常规工艺，在第二沟槽内形成栅介质层和栅极，并在n型衬底内形成p型体区，在p型体区内形成n型源区，之后形成隔离介质层和金属层等即可得到半导体功率器件。
本发明提供的半导体功率器件的制造方法，第一绝缘介质层和栅介质层通过两步工艺形成，可以使得第一绝缘介质层的厚度大于栅介质层的厚度，而栅极与屏蔽栅之间由第一绝缘介质层隔离，通过增加第一绝缘介质层的厚度可以降低栅源电容，并降低栅源漏电，提高半导体功率器件的可靠性。
以上具体实施方式及实施例是对本发明技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。

Claims (7)

1.半导体功率器件的制造方法，其特征在于，包括：
在n型衬底内形成第一沟槽，在所述第一沟槽内形成场氧化层和屏蔽栅；
以所述n型衬底和所述屏蔽栅为自对准边界对所述场氧化层进行自对准刻蚀，将所述第一沟槽上部内的所述场氧化层刻蚀掉，在所述第一沟槽的上部形成且介于所述屏蔽栅与所述n型衬底之间的第二沟槽；
形成第一绝缘介质层，所述第一绝缘介质层覆盖所述第二沟槽的侧壁和底部；
形成一层光刻胶，所述光刻胶填满所述第二沟槽；
进行光刻，将位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层暴露出来，然后刻蚀掉位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层，保留位于所述第二沟槽内且靠近所述屏蔽栅一侧的所述第一绝缘介质层；
去除掉所述光刻胶，在所述第二沟槽内形成栅介质层和栅极。
2.如权利要求1所述的半导体功率器件的制造方法，其特征在于，还包括：
在所述n型衬底内形成p型体区；
在所述p型体区内形成n型源区。
3.如权利要求1所述的半导体功率器件的制造方法，其特征在于，所述第一绝缘介质层为氧化硅层。
4.如权利要求1所述的半导体功率器件的制造方法，其特征在于，形成第一绝缘介质层，包括：
采用次常压化学汽相沉积工艺形成第一绝缘介质层。
5.如权利要求1所述的半导体功率器件的制造方法，其特征在于，刻蚀掉位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层，包括：
采用湿法刻蚀工艺刻蚀掉位于所述第二沟槽内且靠近所述n型衬底一侧的所述第一绝缘介质层。
6.如权利要求1所述的半导体功率器件的制造方法，其特征在于，所述n型衬底为硅衬底。
7.如权利要求1所述的半导体功率器件的制造方法，其特征在于，所述第一绝缘介质层的厚度大于所述栅介质层的厚度。
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