CN117116748A - 半导体功率器件的制造方法及器件 - Google Patents

半导体功率器件的制造方法及器件 Download PDF

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CN117116748A
CN117116748A CN202210539330.2A CN202210539330A CN117116748A CN 117116748 A CN117116748 A CN 117116748A CN 202210539330 A CN202210539330 A CN 202210539330A CN 117116748 A CN117116748 A CN 117116748A
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王鹏飞
毛振东
范让萱
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Suzhou Dongwei Semiconductor Co ltd
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Abstract

本发明实施例提供的一种半导体功率器件的制造方法,包括:对提供的n型半导体层进行刻蚀,在所述n型半导体层内形成若干个栅沟槽;在所述栅沟槽的下部内形成场氧化层和屏蔽栅;在所述屏蔽栅上方形成隔离介质层和栅介质层;淀积多晶硅层并回刻,在所述栅沟槽的上部内形成多晶硅牺牲层;进行p型离子注入并退火,在所述n型半导体层内形成介于相邻的所述栅沟槽之间的p型体区;去除所述栅沟槽的上部内的所述多晶硅牺牲层;淀积金属材料层并回刻,在所述栅沟槽的上部内形成金属材料控制栅。

Description

半导体功率器件的制造方法及器件
技术领域
本发明属于半导体功率器件技术领域,特别是涉及一种采用屏蔽栅结构的半导体功率器件的制造方法及器件。
背景技术
为了提高半导体功率器件的开关速度,需要降低功率MOSFET的寄生电容和栅极电阻。现有技术的采用屏蔽栅结构的功率MOSFET通常使用重掺杂的多晶硅做为栅极材料,这使得采用屏蔽栅结构的功率MOSFET的栅极电阻较大,难以应用到1MHz以上的高速开关中。
发明内容
有鉴于此,本发明的目的是提供一种半导体功率器件的制造方法及器件,以降低采用屏蔽栅结构的功率MOSFET的栅极电阻,提高采用屏蔽栅结构的功率MOSFET的开关速度。
本发明实施例提供的一种半导体功率器件的制造方法,包括:
对提供的n型半导体层进行刻蚀,在所述n型半导体层内形成若干个栅沟槽;
在所述栅沟槽的下部内形成场氧化层和屏蔽栅;
在所述屏蔽栅上方形成隔离介质层和栅介质层;
淀积多晶硅层并回刻,在所述栅沟槽的上部内形成多晶硅牺牲层;
进行p型离子注入并退火,在所述n型半导体层内形成介于相邻的两个所述栅沟槽之间的p型体区;
去除所述栅沟槽的上部内的所述多晶硅牺牲层;
淀积金属材料层并回刻,在所述栅沟槽的上部内形成金属材料控制栅。
可选的,本发明的半导体功率器件的制造方法,在所述栅沟槽的下部内形成场氧化层和屏蔽栅,包括:
覆盖所述栅沟槽的侧壁和底部形成场氧化层;
淀积多晶硅层并回刻,在所述栅沟槽的下部内形成屏蔽栅;
刻蚀掉所述栅沟槽的上部内的所述场氧化层。
可选的,本发明的半导体功率器件的制造方法,在所述屏蔽栅上方形成隔离介质层和栅介质层,包括:
淀积一层氧化硅并回刻,在所述屏蔽栅上方形成隔离介质层;
沿所述栅沟槽的上部的侧壁对所述n型半导体层进行热氧化,在所述栅沟槽的上部的侧壁处形成栅介质层。
可选的,本发明的半导体功率器件的制造方法,还包括:在所述p型体区内形成n型源区。
可选的,本发明的半导体功率器件的制造方法,所述金属材料控制栅的材料为金属、合金或者金属硅化物。
通过本发明的一种半导体功率器件的制造方法制备得到的半导体功率器件,包括:
n型半导体层;
位于所述n型半导体层内的若干个栅沟槽;
位于相邻的两个所述栅沟槽之间的p型体区,所述p型体区内设有n型源区;
位于所述栅沟槽的下部内的屏蔽栅,所述屏蔽栅通过场氧化层与所述n型半导体层隔离;
位于所述栅沟槽的上部内的金属材料控制栅,所述金属材料控制栅通过栅介质层与所述n型半导体层隔离,所述金属材料控制栅通过隔离介质层与所述屏蔽栅绝缘隔离。
可选,本发明的半导体功率器件,所述金属材料控制栅的材料为金属、合金或者金属硅化物。
本发明的半导体功率器件,位于栅沟槽的上部内的控制栅采用金属、合金或者金属硅化物等金属材料,可以有效降低栅极电阻,提高半导体功率器件的开关速度。本发明的半导体功率器件的制造方法,首先,形成p型体区的离子注入和高温退火工艺是在形成屏蔽栅之后,这能够避免p型体区经历对场氧化层的退火工艺,进而能够精确控制p型体区的深度,有效控制电流沟道的长度并降低寄生电容,提高半导体功率器件的开关速度;其次,金属材料控制栅在p型体区形成之后形成,避免p型体区的高温退火工艺对金属材料控制栅造成损伤。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案,下面对描述实施例中所需要用到的附图做一简单介绍。
图1是本发明的半导体功率器件的一个实施例的剖面结构示意图;
图2至图8是本发明的半导体功率器件的制造方法的一个实施例的主要工艺节点的剖面结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚,以下将结合本发明实施例中的附图,通过具体方式,完整地描述本发明的技术方案。
图2至图8是本发明的半导体功率器件的制造方法的一个实施例的主要工艺节点的剖面结构示意图。如图2至图8所示,本发明的一种半导体功率器件的制造方法,包括:
首先,如图2所示,提供一n型半导体层21,n型半导体层21形成于衬底20之上。当衬底20为n型掺杂时,用于形成功率MOSFET器件;当衬底20为p型掺杂时,用于形成IGBT器件。在n型半导体层21内形成若干个栅沟槽30,具体的,包括:在n型半导体层21上形成硬掩膜层,硬掩膜层通常包括一层薄的氧化硅层31和位于氧化硅31之上的氮化硅层32。通过光刻工艺定义栅沟槽的位置,然后对硬掩膜层和n型半导体层21进行刻蚀,在n型半导体层21内形成栅沟槽30,图2中仅示例性的示出了两个栅沟槽30结构。
接下来,如图3所示,在栅沟槽30的下部内形成场氧化层22和屏蔽栅23,具体的,包括:覆盖栅沟槽30的侧壁和底部形成场氧化层22,此时,场氧化层22通常采用湿氧氧化工艺形成,这需要进行退火工艺以增加场氧化层22的致密性并修复场氧化层22的表面的缺陷,提高半导体功率器件的抗击穿能力。然后淀积多晶硅层并回刻,刻蚀后剩余的多晶硅层在栅沟槽30的下部内形成屏蔽栅23,之后刻蚀掉栅沟槽30的上部内的场氧化层。
接下来,如图4所示,在屏蔽栅23的上方形成隔离介质层24和栅介质层25,具体的,包括:淀积氧化硅层并回刻,刻蚀后剩余的氧化硅层在屏蔽栅23上方形成隔离介质层24,优选的,淀积氧化硅层时采用高密度等离子体化学气相淀积(HDP)的方法;之后沿栅沟槽30的上部的侧壁对n型半导体层21进行热氧化,在栅沟槽30的上部的侧壁处形成栅介质层25。
接下来,如图5所示,淀积多晶硅层并回刻,刻蚀后剩余的多晶硅层在栅沟槽30的上部内形成多晶硅牺牲层26a。
接下来,如图6所示,刻蚀掉氮化硅层32,之后进行p型离子注入并进行高温退火,在n型半导体层21内形成介于相邻的两个栅沟槽30之间的p型体区27。
接下来,如图7所示,去除掉栅沟槽30的上部内的多晶硅牺牲层26a,然后淀积金属材料层并回刻,刻蚀后的金属材料层在栅沟槽30的上部内形成金属材料控制栅26,金属材料控制栅26的材料可以为金属、合金或者金属硅化物,比如可以为TiN、TaN、RuO2、Ru、WSi合金等。
接下来,如图8所示,进行n型离子注入,在p型体区27内形成n型源区28。
最后,通过常规的金属电极工艺制备得到半导体功率器件的栅极、源极和漏极即可,该结构在本发明实施例中不再具体展示。
图1是通过本发明的一种半导体功率器件的制造方法制备得到的半导体功率器件一个实施例的剖面结构示意图,如图1所示,本发明的半导体功率器件包括n型半导体层21,n型半导体层21形成于衬底20之上。位于n型半导体层21内的若干个栅沟槽30,图1中仅示例性的示出了两个栅沟槽30结构。位于相邻的栅沟槽30之间的p型体区27,p型体区27内设有n型源区28;
位于栅沟槽30的下部内的屏蔽栅23,屏蔽栅23通过场氧化层22与n型半导体层21隔离。位于栅沟槽30的上部内的金属材料控制栅26,金属材料控制栅26的材料可以为金属、合金或者金属硅化物,比如可以为TiN、TaN、RuO2、Ru、WSi合金等。金属材料控制栅26通过栅介质层25与n型半导体层21隔离,金属材料控制栅26通过隔离介质层24与屏蔽栅23绝缘隔离。
本发明的半导体功率器件,位于栅沟槽的上部内的控制栅采用金属、合金或者金属硅化物等金属材料,可以有效降低栅极电阻,提高半导体功率器件的开关速度。本发明的半导体功率器件的制造方法,首先,形成p型体区的离子注入和高温退火工艺是在形成屏蔽栅之后,这能够避免p型体区经历对场氧化层的退火工艺,进而能够精确控制p型体区的深度,有效控制电流沟道的长度并降低寄生电容,提高半导体功率器件的开关速度;其次,金属材料控制栅在p型体区形成之后形成,避免p型体区的高温退火工艺对金属材料控制栅造成损伤。
尽管本发明的实施方案已公开如上,但其并不仅仅限于说明书和实施方式中所列运用,它完全可以被适用于各种适合本发明的领域,对于熟悉本领域的人员而言,可容易地实现另外的修改,因此在不背离权利要求及等同范围所限定的一般概念下,本发明并不限于特定的细节和这里示出与描述的图例。

Claims (7)

1.一种半导体功率器件的制造方法,其特征在于,包括:
对提供的n型半导体层进行刻蚀,在所述n型半导体层内形成若干个栅沟槽;
在所述栅沟槽的下部内形成场氧化层和屏蔽栅;
在所述屏蔽栅上方形成隔离介质层和栅介质层;
淀积多晶硅层并回刻,在所述栅沟槽的上部内形成多晶硅牺牲层;
进行p型离子注入并退火,在所述n型半导体层内形成介于相邻的两个所述栅沟槽之间的p型体区;
去除所述栅沟槽的上部内的所述多晶硅牺牲层;
淀积金属材料层并回刻,在所述栅沟槽的上部内形成金属材料控制栅。
2.如权利要求1所述的半导体功率器件的制造方法,其特征在于,在所述栅沟槽的下部内形成场氧化层和屏蔽栅,包括:
覆盖所述栅沟槽的侧壁和底部形成场氧化层;
淀积多晶硅层并回刻,在所述栅沟槽的下部内形成屏蔽栅;
刻蚀掉所述栅沟槽的上部内的所述场氧化层。
3.如权利要求1所述的半导体功率器件的制造方法,其特征在于,在所述屏蔽栅上方形成隔离介质层和栅介质层,包括:
淀积氧化硅层并回刻,在所述屏蔽栅上方形成隔离介质层;
沿所述栅沟槽的上部的侧壁对所述n型半导体层进行热氧化,在所述栅沟槽的上部的侧壁处形成栅介质层。
4.如权利要求1所述的半导体功率器件的制造方法,其特征在于,还包括:在所述p型体区内形成n型源区。
5.如权利要求1所述的半导体功率器件的制造方法,其特征在于,所述金属材料控制栅的材料为金属、合金或者金属硅化物。
6.一种半导体功率器件,其特征在于,包括:
n型半导体层;
位于所述n型半导体层内的若干个栅沟槽;
位于相邻的两个所述栅沟槽之间的p型体区,所述p型体区内设有n型源区;
位于所述栅沟槽的下部内的屏蔽栅,所述屏蔽栅通过场氧化层与所述n型半导体层隔离;
位于所述栅沟槽的上部内的金属材料控制栅,所述金属材料控制栅通过栅介质层与所述n型半导体层隔离,所述金属材料控制栅通过隔离介质层与所述屏蔽栅绝缘隔离。
7.如权利要求6所述的半导体功率器件,其特征在于,所述金属材料控制栅的材料为金属、合金或者金属硅化物。
CN202210539330.2A 2022-05-17 2022-05-17 半导体功率器件的制造方法及器件 Pending CN117116748A (zh)

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