WO2022095451A1 - 测试结构及其制作方法 - Google Patents

测试结构及其制作方法 Download PDF

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Publication number
WO2022095451A1
WO2022095451A1 PCT/CN2021/100202 CN2021100202W WO2022095451A1 WO 2022095451 A1 WO2022095451 A1 WO 2022095451A1 CN 2021100202 W CN2021100202 W CN 2021100202W WO 2022095451 A1 WO2022095451 A1 WO 2022095451A1
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Prior art keywords
isolation
substrate
groove
gate
gate structures
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English (en)
French (fr)
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王翔宇
李宁
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/606,030 priority Critical patent/US20230268238A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics

Definitions

  • the present disclosure relates to, but is not limited to, a test structure and a method of making the same.
  • the field effect transistor is one of the most commonly used process devices. In the process of preparing a field effect transistor, it is necessary to monitor various parameters of the field effect transistor, such as gate resistance, conductive plug resistance, and gate dielectric layer leakage.
  • the prior art cannot accurately obtain the resistance of the lightly doped drain structure (LDD structure).
  • Embodiments of the present disclosure provide a test structure and a manufacturing method thereof, which are beneficial to obtain accurate and effective resistance values of the lightly doped drain structure.
  • An embodiment of the present disclosure provides a method for fabricating a test structure, including: providing a substrate, and forming a gate dielectric film and a conductive film stacked in sequence on the substrate; and performing pattern etching on at least the conductive film to form a
  • the spacing between adjacent gate structures is less than or equal to 110 nm; forming gate structures on opposite sides of the gate structure isolating spacers; using the gate structure and the isolation spacers as masks, implanting dopant ions into the substrate to form a doping region, and in a direction perpendicular to the surface of the substrate, the doping
  • the doping depth of the region is less than or equal to 10 nm.
  • the process steps of forming the gate structure and the isolation spacer include: performing pattern etching on the conductive film and the gate dielectric film to form the gate structure; forming an isolation film , the isolation film covers the sidewall of the gate structure and the surface of the base; the isolation film covering the surface of the base is etched, and the remaining isolation film is used as the isolation spacer.
  • the process step of forming the gate structure and the isolation spacer includes: performing pattern etching on the conductive film, leaving the conductive film and the conductive film and the substrate on the remaining conductive film.
  • a part of the gate dielectric film in between is used as the gate structure, and the other part of the gate dielectric film is used as a protective layer; an isolation film is formed, and the isolation film covers the sidewall of the gate structure and the surface of the protective layer , the isolation film covering the sidewall of the gate structure is used as the isolation spacer, and the isolation film covering the surface of the protective layer is used as the isolation layer.
  • the isolation layer is removed by etching.
  • the isolation layer and the protective layer between the isolation layer and the substrate are removed by etching.
  • an embodiment of the present disclosure further provides a test structure, comprising: a substrate and a plurality of discrete gate structures located on the substrate, and adjacent to the gate structures in the arrangement direction of the gate structures The spacing between them is less than or equal to 110 nm; the isolation spacers are located on opposite sides of the gate structure; the doping region is located in the substrate on the side of the isolation spacers away from the gate structure, perpendicular to the gate structure. In the direction of the substrate surface, the doping depth of the doping region is less than or equal to 10 nm.
  • the substrate has a first groove and a second groove located at the bottom of the first groove, and in the arrangement direction of the gate structures, the top of the first groove is open
  • the width is equal to the spacing between the adjacent gate structures
  • the width of the top opening of the second groove is equal to the spacing between the two layers of the isolation spacers between the adjacent gate structures.
  • the gate structure includes a gate electrode and a gate dielectric layer; and further includes: a protective layer located between the isolation spacer and the substrate, and the material of the protective layer is the same as that of the gate dielectric layer. materials are the same.
  • the protective layer covers the surface of the substrate between adjacent gate structures, and the protective layer has grooves in the protective layer, and in the arrangement direction of the gate structures, the grooves The width of the top opening of the trench is equal to the spacing between adjacent gate structures.
  • it further includes: an isolation layer covering the surface of the protective layer and located between the two layers of the isolation spacers between the adjacent gate structures, the isolation layer is made of a material that is the same as that of the isolation layer.
  • the material of the isolation side wall is the same.
  • the groove includes a first groove and a second groove located at the bottom of the first groove, and in the arrangement direction of the gate structures, the top of the first groove is open
  • the width is equal to the spacing between the adjacent gate structures
  • the width of the top opening of the second groove is equal to the spacing between the two layers of the isolation spacers between the adjacent gate structures.
  • the top opening of the groove is equal to the distance between the two layers of the isolation spacers between the adjacent gate structures, and the groove is The sidewall surface of the is a continuous surface.
  • the depth of over-etching during the formation of the gate structures is further limited, so as to prevent the grooves formed by over-etching from occupying too much dopant.
  • the preset doping position of the impurity region ensures that the impurity region has a larger actual doping region, thereby accurately obtaining the resistance value of the doping region having the preset doping region.
  • the gate dielectric film is used to withstand the over-etching caused by the conductive film etching process, which is beneficial to reduce the over-etching depth of the substrate or even make the substrate not withstand the over-etching process. over-etching damage, so as to obtain a larger effective doping area; in addition, directly forming the doping area after the isolation film is formed, which is beneficial to avoid the formation of over-etching grooves in the substrate in the etching process for the isolation layer, so that the doping The impurity region has a larger effective doped region, thereby obtaining a smaller resistance value or even a minimum resistance value of the doped region.
  • etching the protective layer exposed by the gate structure and the isolation spacer can form an over-etching groove with a preset shape and a shallow depth on the surface of the substrate, thereby simulating the situation that the substrate is subjected to secondary etching in practical applications , that is, the test resistance value of the doped region is closer to the actual application resistance value.
  • 1 to 5 are schematic structural diagrams corresponding to each step of a method for making a test structure
  • 6 to 8 are schematic structural diagrams corresponding to each step of a method for making a test structure provided by an embodiment of the present invention.
  • 9 to 14 are schematic structural diagrams corresponding to each step of a method for fabricating a test structure provided in another embodiment of the present invention.
  • FIG. 1 to 5 are schematic structural diagrams corresponding to each step of a method for fabricating a test structure
  • FIG. 3 is a partial schematic diagram of the structure shown in FIG. 2 .
  • the production method of the test structure includes the following steps:
  • a substrate 10 is provided, on which a gate dielectric film 11a and a conductive film 12a are formed sequentially stacked.
  • a gate structure 13 is formed.
  • the conductive film 12a and the gate dielectric film 11a are etched to form a plurality of gate structures 13 on the substrate 10.
  • the gate structures 13 include a gate 12 and a gate dielectric layer 11, and adjacent gate structures 13 have The first width w1.
  • a first groove 141 having a first depth d1 is formed in the substrate 10 .
  • the size of the first depth d1 is related to the size of the first width w1. According to the etching load effect, the larger the first width w1 is, the larger the first depth d1 is; the smaller the first width w1 is, the smaller the first depth d1 is.
  • an isolation film 15 a covering the top surface and sidewalls of the gate structure 13 and the surface of the substrate 10 is formed.
  • isolation sidewalls 15 are formed.
  • the isolation film 15 a (refer to FIG. 4 ) covering the top surface of the gate structure 13 and the surface of the substrate 10 may be removed simultaneously by a maskless dry etching process, and the remaining isolation film 15 a serves as the isolation spacer 15 .
  • a second groove 142 at the bottom of the first groove 141 is further formed in the substrate 10 .
  • the size of the second depth d2 is related to the distance between the two layers of isolation spacers 15 between adjacent gate structures 13 , and the larger the latter, the larger the former. Meanwhile, since the width of the isolation spacers 15 in the arrangement direction of the gate structures 13 is generally fixed, the spacing between the two layers of isolation spacers 15 between adjacent gate structures 13 varies with the first width w1
  • the size of the second depth d2 is mainly related to the first width w1, and the larger the first width w1 is, the larger the second depth d2 is.
  • the first width w1 is usually equal to the distance between adjacent gate structures in the actual array region. Validity and accuracy of resistance values.
  • the ratio of the depth of the first groove 141 and the second groove 142 formed by over-etching to the preset doping depth of the doped region gradually increases, that is, the first groove 141 and the second groove 142 are gradually increased.
  • the grooves 141 and the second grooves 142 occupy more of the predetermined doping area of the doping area, resulting in the reduction of the effective doping area of the doping area, and thus the resistance of the doping area with the predetermined doping area cannot be accurately obtained. value.
  • Embodiments of the present disclosure provide a test structure and a method for fabricating the same.
  • the distance between adjacent gate structures is set within a preset range. In this way, it is beneficial to reduce the depth of over-etching during the formation of the gate structures and avoid The grooves formed by over-etching occupy too much the preset doping area of the doping area, ensuring that the doping area has a larger effective doping area, and more accurately obtaining the doping area with the preset doping area resistance value.
  • 6 to 8 are schematic structural diagrams corresponding to each step of a method for fabricating a test structure provided by an embodiment of the present disclosure.
  • a gate structure 23 is formed.
  • the conductive film and the gate dielectric film are sequentially etched by a first etching process, thereby exposing the surface of the substrate 20 .
  • the remaining conductive film is used as the gate electrode 22, the remaining gate dielectric film is used as the gate dielectric layer 21, the gate electrode 22 and the gate dielectric layer 21 constitute the gate structure 23, and there is a second width w2 between the adjacent gate structures 23, the second width w2 is less than or equal to 110 nm, for example, 90 nm, 80 nm or 70 nm.
  • the base 20 includes a substrate 201 and a well region 202, the doping ion type of the well region 202 is different from that of the substrate 201, and the doping ion concentration of the well region 202 is greater than that of the substrate 201;
  • the material of the gate dielectric film includes silicon dioxide, and the material of the conductive film includes metal, doped polysilicon, and the like.
  • isolation sidewalls 25 are formed.
  • an isolation film covering the top surface and sidewalls of the gate structure 23 and the surface of the substrate 20 is formed; and after the isolation film is formed, a second etching process is used to etch and remove the cover The top surface of the gate structure 23 and the isolation film covering the surface of the substrate 20 , and the remaining isolation film serves as the isolation spacer 25 .
  • the first etching process for forming the gate structure 23 also forms a first groove 241 in the substrate 20, and the top opening width of the first groove 241 is equal to The distance between adjacent gate structures 23 ; the isolation film formed subsequently will cover the sidewalls and the bottom surface of the first groove 241 , and the isolation spacers 25 in contact with the substrate 20 will be partially located in the substrate 20 .
  • the isolation spacers 25 are used to protect the gate structure 23, to prevent the gate structure 23 from being damaged by etching caused by the etching process, and to prevent the doping process from implanting doping ions into the gate dielectric layer 21 or the gate 22, it is ensured that the gate structure 23 has a predetermined performance.
  • the material of the isolation spacer 25 includes silicon nitride, so as to provide a good support for the gate structure 23 .
  • the second etching process will also form the second groove 242 at the bottom of the first groove 241.
  • the spacer 25 is a mask, so the width of the top opening of the second groove 242 is equal to the distance between the two layers of isolation spacers 25 between adjacent gate structures 23 .
  • the first depth d1 and the second depth d2 of the first groove 241 can be limited within a certain range, and the sum of the first depth d1 and the second depth d2 can be limited Within a certain range, it is ensured that the doped region has a larger effective doped area.
  • doped regions 26 are formed.
  • doping ions are implanted into the substrate 20 by using the gate structure 23 and the isolation spacers 25 as masks to form the doped regions 26 .
  • the orthographic projection of the gate structure 23 overlaps with the orthographic projection of the doped region 26 , and at least part of the overlapping region is located between the isolation spacer 25 and the gate structure 23 between.
  • the isolation spacers 25 can form a certain degree of shielding for the ion implantation process, when part of the isolation spacers 25 penetrate deep into the substrate 20 , some regions between the isolation spacers 25 and the gate structure 23 may not be able to Doping ions are effectively implanted. At this time, the doping ions in this region can only diffuse through other regions.
  • the doping depth of the doping region 26 is less than or equal to 10 nm, such as 9 nm, 8 nm or 7 nm, and the doping depth refers to the maximum implantation depth of the doping ions.
  • the doped region 26 with a doping depth of less than or equal to 10 nm has a larger effective doping area, that is, the sum of the depths of the first groove 241 and the second groove 242 and the doping depth
  • the ratio of ⁇ is relatively small, and by performing resistance test on the doped region 26 in the effective doped region, the resistance value of the doped region with the preset doped region can be relatively accurately obtained.
  • the depths of the first groove and the second groove are etched, so as to avoid too many grooves formed by over-etching. Occupying the preset doping position of the doping region ensures that the doping region has a larger actual doping region, and then accurately obtains the resistance value of the doping region having the preset doping region.
  • FIGS. 9 to 14 are schematic structural diagrams corresponding to each step of a method for fabricating a test structure provided in yet another embodiment of the present disclosure. For the parts that are the same as or corresponding to the previous embodiment, reference may be made to the corresponding description of the previous embodiment, which will not be repeated below.
  • gate structures 33 are formed.
  • the conductive film 32a is patterned and etched to expose the gate dielectric film 31a, and the remaining conductive film 32a serves as the gate electrode 32 and is located in the gate electrode 32.
  • Part of the gate dielectric film 31a between the substrate 30 and the substrate 30 is used as the gate dielectric layer 31, the gate dielectric layer 31 and the gate electrode 32 constitute the gate structure 33, and another part of the gate dielectric film 31a located between the adjacent gate dielectric layers 31 is used as a protective layer 34.
  • a dotted line is used to separate the gate dielectric layer 31 and the protective layer 34 for illustration.
  • the first groove 341 formed due to the over-etching problem is completely located in the protective layer 34 , that is, the lowest point of the first groove 341 is higher than the top of the substrate 30 . surface, the first groove 341 does not expose the surface of the substrate 30, and the width of the top opening of the first groove 341 is equal to the spacing between the adjacent gate structures 33; in other embodiments, the lowest point of the first groove is located on the substrate In the top surface; or, the lowest point of the first groove is located in the base, that is, the bottom of the first groove is located in the base.
  • the first width w1 can be adjusted according to the thickness of the protective layer 34, so that the first groove 341 is completely located in the protective layer 34, so as to avoid etching damage to the substrate 30 caused by the over-etching problem in the subsequent etching process , to ensure that the doped region has the maximum effective doped region, and the minimum resistance value of the doped region can be obtained.
  • isolation sidewalls 351 are formed.
  • an isolation film 35 a is formed.
  • the isolation film 35 a covers the top surface, sidewalls and the surface of the protective layer 34 of the gate structure 33 , and covers the sidewalls of the gate structure 33 .
  • the isolation film 35 a serves as the isolation sidewall 351
  • the isolation film 35 a covering the surface of the protective layer 34 serves as the isolation layer 352 .
  • the gate dielectric film serving as the protective layer 34 is not completely removed in the process of forming the gate structure 33 , after the isolation film 35 a is formed, at least part of the protective layer 34 is located between the isolation spacer 351 and the substrate 30 .
  • dopant ions are implanted into the substrate to form the doped region.
  • the substrate can also be protected to prevent the substrate from being subjected to secondary etching.
  • the isolation layer 352 (refer to FIG. 11 ) and the protective layer 34 located between the isolation layer 352 and the substrate 30 are removed by etching.
  • the etching process forms the second groove 342 in the substrate 30 , and the width of the top opening of the second groove 342 is equal to the distance between the two layers of spacers 351 between adjacent gate structures 33 .
  • the sidewall surface of the second groove 342 is a continuous surface.
  • the first groove is partially located in the base, and the second groove formed subsequently is located at the bottom of the first groove.
  • the groove located in the base is composed of the second groove and part of the first groove
  • the sidewall of the groove in the base is the splicing surface.
  • the etchant may cause secondary etching to the substrate during the etching process for other film layers.
  • the substrate of the actual array area usually has a certain degree of mis-etching, that is, the effective doped area of the doped area is smaller than the preset doped area.
  • the impact of the secondary etching on the substrate 30 is relatively different from that of the actual array.
  • the isolation layer 352 and the protection layer 34 are continuously etched by the same etching process; in other embodiments, two etching processes may be performed to etch the isolation layer and the protection layer respectively. Since the depth of the grooves formed by over-etching is related to factors such as the etching selectivity ratio, the etching time, and the width of the top opening, compared with the continuous etching of the isolation layer and the protective layer, the etching time required to etch the protective layer alone Shorter, less etchant is required, and the depth of the grooves formed by over-etching is shallow, so that the mis-etching of the substrate caused by a small dose of etchant in the processing process of the actual array area can be simulated to a certain extent. etch to obtain a more accurate effective doping area and a more accurate resistance value.
  • only the isolation layer may be etched. Referring to FIG. 13 , only the isolation layer is etched to form a second groove 442 exposing the surface of the substrate 40 , so that the substrate 40 can be subjected to secondary etching from an additional etchant, thereby simulating the actual situation of the doped region in the actual array region.
  • the second groove 442 is located at the bottom of the first groove 441, the top opening width of the first groove 441 is equal to the distance between the adjacent gate structures 43, and the top opening width of the second groove 442 is the same as that of the adjacent gate structures 43.
  • the distance between the two layers of isolation sidewalls 451 between the pole structures 43 is equal, and the sidewall surface of the groove formed by the first groove 441 and the second groove 442 is a splicing surface.
  • dopant ions are implanted into the substrate 30 to form the dopant region 36 .
  • the doping region 36 is formed, another doping region is also formed at both ends of the extending direction of the doping region 36 , and the doping ion type of the other doping region is the same as the doping ion type of the doping region 36 .
  • the types are the same, and the doped ion concentration of the other doped region is greater than that of the doped region 36 , the doped region 36 serves as the LDD structure, and the other doped region serves as the source and drain regions.
  • the gate dielectric film can be used to bear part of the over-etching damage, avoiding the formation of deep over-etching grooves in the substrate, ensuring that Test the accuracy and validity of the obtained resistance value of the doped region.
  • the distance between adjacent gate structures is set within a preset range, which is beneficial to reduce the depth of over-etching in the process of forming the gate structure and avoid the formation of over-etching.
  • the grooves of the doped region occupy too much the preset doped region of the doped region, so as to ensure that the doped region has a larger effective doped region, so as to obtain the resistance value of the doped region with the preset doped region more accurately.

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Abstract

本公开实施例提供一种测试结构及其制作方法，测试结构的制作方法包括：提供基底，并在所述基底上形成依次层叠的栅介质膜和导电膜；至少对所述导电膜进行图案化刻蚀，以形成位于所述基底上的多个分立的栅极结构，在所述栅极结构的排列方向上，相邻所述栅极结构之间的间距小于等于110nm；形成位于所述栅极结构相对两侧的隔离侧墙；以所述栅极结构和所述隔离侧墙为掩膜，向所述基底内注入掺杂离子，形成掺杂区，在垂直于所述基底表面的方向上，所述掺杂区的掺杂深度与所述基底顶面的间距小于10nm。

Description

测试结构及其制作方法
本公开要求在2020年11月06日提交中国专利局、申请号为202011233637.7、发明名称为“测试结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种测试结构及其制作方法。
背景技术
在现代存储工艺结构中，场效应管是最常用的工艺器件之一。在制备场效应管的过程中，需要对场效应管的各项参数进行监控，例如栅极电阻、导电插塞电阻以及栅介质层漏电等。
现有技术无法准确获取轻掺杂漏结构(LDD结构)的电阻。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种测试结构及其制作方法，有利于获取准确且有效的轻掺杂漏结构的阻值。
本公开实施例提供一种测试结构的制作方法，包括：提供基底，并在所述基底上形成依次层叠的栅介质膜和导电膜；至少对所述导电膜进行图案化刻蚀，以形成位于所述基底上的多个分立的栅极结构，在所述栅极结构的排列方向上，相邻所述栅极结构之间的间距小于等于110nm；形成位于所述栅极结构相对两侧的隔离侧墙；以所述栅极结构和所述隔离侧墙为掩膜，向所述基底内注入掺杂离子，形成掺杂区，在垂直于所述基底表面的方向上，所述掺杂区的掺杂深度小于等于10nm。
在一些实施例中，形成所述栅极结构和所述隔离侧墙的工艺步骤包括：对所述导电膜和所述栅介质膜进行图案化刻蚀，形成所述栅极结构；形成隔离膜， 所述隔离膜覆盖所述栅极结构侧壁和所述基底表面；刻蚀覆盖所述基底表面的所述隔离膜，剩余所述隔离膜作为所述隔离侧墙。
在一些实施例中，形成所述栅极结构和所述隔离侧墙的工艺步骤包括：对所述导电膜进行图案化刻蚀，剩余所述导电膜以及位于剩余所述导电膜和所述基底之间的部分所述栅介质膜作为所述栅极结构，另一部分所述栅介质膜作为保护层；形成隔离膜，所述隔离膜覆盖所述栅极结构侧壁和覆盖所述保护层表面，覆盖所述栅极结构侧壁的所述隔离膜作为所述隔离侧墙，覆盖所述保护层表面的所述隔离膜作为隔离层。
在一些实施例中，在形成所述隔离膜之后，刻蚀去除所述隔离层。
在一些实施例中，在形成所述隔离膜之后，刻蚀去除所述隔离层以及位于所述隔离层和所述基底之间的所述保护层。
相应地，本公开实施例还提供一种测试结构，包括：基底和位于所述基底上的多个分立的栅极结构，在所述栅极结构的排列方向上，相邻所述栅极结构之间的间距小于等于110nm；隔离侧墙，位于所述栅极结构相对两侧；掺杂区，位于所述隔离侧墙远离所述栅极结构的一侧的所述基底内，在垂直于所述基底表面的方向上，所述掺杂区的掺杂深度小于等于10nm。
在一些实施例中，所述基底内具有第一凹槽和位于所述第一凹槽底部的第二凹槽，在所述栅极结构的排列方向上，所述第一凹槽的顶部开口宽度与相邻所述栅极结构之间的间距相等，所述第二凹槽的顶部开口宽度与相邻所述栅极结构之间的两层所述隔离侧墙之间的间距相等。
在一些实施例中，所述栅极结构包括栅极和栅介质层；还包括：保护层，位于所述隔离侧墙与所述基底之间，所述保护层的材料与所述栅介质层的材料相同。
在一些实施例中，所述保护层覆盖相邻所述栅极结构之间的所述基底表面，且所述保护层内具有凹槽，在所述栅极结构的排列方向上，所述凹槽的顶部开口宽度与相邻所述栅极结构之间的间距相等。
在一些实施例中，还包括：隔离层，覆盖于所述保护层表面，且位于相邻所述栅极结构之间的两层所述隔离侧墙之间，所述隔离层的材料与所述隔离侧墙的材料相同。
在一些实施例中，所述凹槽包括第一凹槽和位于所述第一凹槽底部的第二 凹槽，在所述栅极结构的排列方向上，所述第一凹槽的顶部开口宽度与相邻所述栅极结构之间的间距相等，所述第二凹槽的顶部开口宽度与相邻所述栅极结构之间的两层所述隔离侧墙之间的间距相等。
在一些实施例中，所述基底内有凹槽，所述凹槽的顶部开口宽度与相邻所述栅极结构之间的两层所述隔离侧墙之间的间距相等，所述凹槽的侧壁表面为连续表面。
上述技术方案中，通过将相邻栅极结构之间的间距设置在预设范围内，进而限定栅极结构形成过程中的过刻蚀深度，避免过刻蚀形成的凹槽过多地占据掺杂区的预设掺杂位置，保证掺杂区具有较大的实际掺杂区域，进而准确获取具有预设掺杂区域的掺杂区的电阻阻值。
另外，在栅极结构的形成过程中，仅刻蚀去除导电膜，即利用栅介质膜承受导电膜刻蚀工艺造成的过刻蚀，有利于减薄基底的过刻蚀深度甚至使得基底不承受过刻蚀损伤，从而获取较大的有效掺杂区域；此外，在形成隔离膜之后直接形成掺杂区，有利于避免针对隔离层的刻蚀工艺在基底内形成过刻蚀凹槽，使得掺杂区具有较大的有效掺杂区域，进而获取掺杂区的较小阻值甚至最小阻值。
另外，刻蚀被栅极结构和隔离侧墙暴露的保护层，可在基底表面形成具有预设形状和深度较浅的过刻蚀凹槽，从而模拟实际应用中基底受到二次刻蚀的情况，即使得掺杂区的测试阻值更接近于实际应用阻值。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1至图5为一种测试结构的制作方法各步骤对应的结构示意图；
图6至图8为本发明一实施例提供的一种测试结构的制作方法各步骤对应 的结构示意图；
图9至图14为本发明又一实施例中提供的测试结构的制作方法各步骤对应的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
图1至图5为一种测试结构的制作方法各步骤对应的结构示意图，图3为图2所示结构的局部示意图。测试结构的制作方法包含以下步骤：
参考图1，提供基底10，在基底10上形成依次层叠的栅介质膜11a和导电膜12a。
参考图2和图3，形成栅极结构13。
对导电膜12a以及栅介质膜11a进行刻蚀，以形成位于基底10上的多个栅极结构13，栅极结构13包括栅极12和栅介质层11，相邻栅极结构13之间具有第一宽度w1。在形成栅极结构13的工艺步骤中，由于刻蚀工艺存在过刻蚀问题，因此基底10内会形成具有第一深度d1的第一凹槽141。
其中，第一深度d1的大小与第一宽度w1的大小有关。根据刻蚀负载效应可知，第一宽度w1越大，第一深度d1越大；第一宽度w1越小，第一深度d1越小。
参考图4，形成覆盖栅极结构13顶面和侧壁、以及覆盖基底10表面的隔离膜15a。
参考图5，形成隔离侧墙15。
可采用无掩膜干法刻蚀工艺同时去除覆盖栅极结构13顶面和覆盖基底10表面的隔离膜15a(参考图4)，剩余的隔离膜15a作为隔离侧墙15。
在刻蚀覆盖基底10表面的隔离膜15a的工艺步骤中，同样由于刻蚀工艺自身的过刻蚀问题，基底10内会进一步形成位于第一凹槽141底部的第二凹槽142。
根据刻蚀负载效应可知，第二深度d2的大小与相邻栅极结构13之间的两层隔离侧墙15之间的间距有关，后者越大，前者越大。同时，由于隔离侧墙15在栅极结构13的排列方向上的宽度通常是固定的，因此，相邻栅极结构13之间的两层隔离侧墙15之间的间距随着第一宽度w1的减小而减少，也就是说，第二深度d2的大小主要与第一宽度w1有关，第一宽度w1越大，第二深度d2越大。
现有技术中，在进行掺杂区的电阻测试时，第一宽度w1通常与实际阵列区的相邻栅极结构之间的间距相等，通过控制测试环境与实际应用环境相同来保证测试得到的电阻阻值的有效性和准确性。
但是随着半导体结构的特征尺寸不断缩小，因过刻蚀而形成的第一凹槽141和第二凹槽142的深度与掺杂区的预设掺杂深度的比值逐渐增大，即第一凹槽141和第二凹槽142更多地占据掺杂区的预设掺杂区域，导致掺杂区的有效掺杂区域缩小，进而无法准确获取具有预设掺杂区域的掺杂区的阻值。
本公开实施例提供一种测试结构及其制作方法，将相邻栅极结构之间的间距设置在预设范围内，如此，有利于减小栅极结构形成过程中的过刻蚀深度，避免过刻蚀形成的凹槽过多地占据掺杂区的预设掺杂区域，保证掺杂区具有较大的有效掺杂区域，进而更为准确地获取具有预设掺杂区域的掺杂区的电阻阻值。
图6至图8为本公开一实施例提供的测试结构的制作方法各步骤对应的结构示意图。
参考图6，形成栅极结构23。
本实施例中，在形成栅介质膜和导电膜之后，采用第一刻蚀工艺依次刻蚀导电膜和栅介质膜，进而暴露基底20表面。剩余导电膜作为栅极22，剩余栅介质膜作为栅介质层21，栅极22和栅介质层21构成栅极结构23，且相邻栅极结构23之间具有第二宽度w2，第二宽度w2小于等于110nm，例如为90nm、80nm或70nm。
其中，基底20包括衬底201和阱区202，阱区202的掺杂离子类型与衬底201的掺杂离子类型不同，阱区202的掺杂离子浓度大于衬底201的掺杂离子浓度；栅介质膜的材料包括二氧化硅，导电膜的材料包括金属、掺杂多晶硅等。
参考图7，形成隔离侧墙25。
本实施例中，在形成栅极结构23之后，形成覆盖栅极结构23顶面和侧壁以及覆盖基底20表面的隔离膜；且在形成隔离膜之后，采用第二刻蚀工艺刻蚀去除覆盖栅极结构23顶面和覆盖基底20表面的隔离膜，剩余隔离膜作为隔离侧墙25。
需要说明的是，由于刻蚀工艺的过刻蚀问题，形成栅极结构23的第一刻蚀工艺还会形成位于基底20内的第一凹槽241，第一凹槽241的顶部开口宽度等于相邻栅极结构23之间的间距；后续形成的隔离膜会覆盖于第一凹槽241侧壁和底面，而与基底20接触的隔离侧墙25会部分位于基底20内。
本实施例中，隔离侧墙25用于保护栅极结构23，避免栅极结构23受到刻蚀工艺造成的刻蚀损伤，以及避免掺杂工艺将掺杂离子注入至栅介质层21或栅极22内，保证栅极结构23具有预设性能。
隔离侧墙25的材料包括氮化硅，以对栅极结构23起到良好的支撑作用。
在刻蚀覆盖基底20表面的隔离膜的工艺步骤中，第二刻蚀工艺还会形成位于第一凹槽241底部的第二凹槽242，由于第二刻蚀工艺以栅极结构23和隔离侧墙25为掩膜，因此，第二凹槽242的顶部开口宽度与相邻栅极结构23之间的两层隔离侧墙25之间的间距相等。
本实施中，通过限定第二宽度w2的大小，可将第一凹槽241的第一深度d1和第二深度d2限定在一定范围内，以及将第一深度d1与第二深度d2之和限定在一定范围内，保证掺杂区具有较大的有效掺杂区域。
参考图8，形成掺杂区26。
在形成隔离侧墙25之后，以栅极结构23和隔离侧墙25为掩膜向基底20内注入掺杂离子，以形成掺杂区26。
本实施例中，在垂直于基底20表面的方向上，栅极结构23的正投影与掺杂区26的正投影存在交叠，且至少部分交叠区域位于隔离侧墙25和栅极结构 23之间。需要说明的是，由于隔离侧墙25可对离子注入工艺形成一定程度的屏蔽，当部分隔离侧墙25深入基底20内时，位于隔离侧墙25和栅极结构23之间的部分区域可能无法有效注入掺杂离子，此时，该区域的掺杂离子只能通过其他区域扩散而来。
本实施例中，掺杂区26的掺杂深度小于等于10nm，例如9nm、8nm或7nm，掺杂深度指的是掺杂离子的最大注入深度。当第二宽度w2小于等于110nm时，掺杂深度小于等于10nm的掺杂区26具有较大的有效掺杂区域，即第一凹槽241和第二凹槽242的深度之和与掺杂深度的比值较小，通过对处于有效掺杂区域的掺杂区26进行电阻测试，可相对准确地获得具有预设掺杂区域的掺杂区域的阻值。
本实施例中，通过将相邻栅极结构之间的间距设置在预设范围内，对第一凹槽和第二凹槽的深度进行刻蚀，避免过刻蚀形成的凹槽过多地占据掺杂区的预设掺杂位置，保证掺杂区具有较大的实际掺杂区域，进而准确获取具有预设掺杂区域的掺杂区的电阻阻值。
本公开又一实施例还提供一种测试结构的制作方法，与前一实施例不同的是，本实施例中，仅通过刻蚀导电膜以定义栅极结构。以下将结合图9至图14进行详细说明，图9至图14为本公开又一实施例中提供的测试结构的制作方法各步骤对应的结构示意图。与上一实施例相同或者相应的部分，可参考上一实施例的相应说明，以下不做赘述。
参考图9和图10，形成栅极结构33。
本实施例中，在基底30表面形成栅介质膜31a和导电膜32a之后，对导电膜32a进行图案化刻蚀，以暴露栅介质膜31a，剩余导电膜32a作为栅极32，位于栅极32和基底30之间的部分栅介质膜31a作为栅介质层31，栅介质层31和栅极32构成栅极结构33，位于相邻栅介质层31之间的另一部分栅介质膜31a作为保护层34。附图中采用虚线分隔栅介质层31和保护层34以进行示意。
本实施例中，在形成栅极结构33的工艺步骤中，因过刻蚀问题而形成的第一凹槽341完全位于保护层34内，即第一凹槽341的最低点高于基底30顶面，第一凹槽341不暴露基底30表面，第一凹槽341的顶部开口宽度与相邻栅极结构33之间的间距相等；在其他实施例中，第一凹槽的最低点位于基底顶面内； 或者，第一凹槽的最低点位于基底内，即第一凹槽底部位于基底内。
在测试过程中，可以根据保护层34的厚度调整第一宽度w1，以使第一凹槽341完全位于保护层34内，从而避免后续刻蚀工艺的过刻蚀问题对基底30造成刻蚀损伤，保证掺杂区具有最大有效掺杂区域，即可获取掺杂区域的最小阻值。
参考图11，形成隔离侧墙351。
本实施例中，在刻蚀导电膜32a(参考图9)之后，形成隔离膜35a，隔离膜35a覆盖栅极结构33顶面、侧壁以及保护层34表面，覆盖栅极结构33侧壁的隔离膜35a作为隔离侧墙351，覆盖保护层34表面的隔离膜35a作为隔离层352。
由于作为保护层34的栅介质膜在形成栅极结构33的过程中未被完全去除，因此在形成隔离膜35a之后，至少有部分保护层34位于隔离侧墙351和基底30之间。
在一实施例中，在形成隔离膜之后，即在保留隔离层的情况下，向基底内注入掺杂离子以形成掺杂区。如此，有利于避免针对隔离层的刻蚀工艺在基底内形成过刻蚀凹槽，进而保证掺杂区具有最大有效掺杂区域，从而获取掺杂区的最小阻值；同时，隔离层的存在还可以对基底进行保护，避免基底受到二次刻蚀。
参考图12，刻蚀去除隔离层352(参考图11)和位于隔离层352和基底30之间的保护层34。
本实施例中，刻蚀工艺会在基底30内形成第二凹槽342，第二凹槽342的顶部开口宽度与相邻栅极结构33之间的两层隔离侧墙351之间的间距相等，第二凹槽342的侧壁表面为连续表面。
在其他实施例中，第一凹槽部分位于基底内，后续形成的第二凹槽位于第一凹槽底部，此时，位于基底内的凹槽由第二凹槽和部分第一凹槽构成，基底内的凹槽侧壁为拼接表面。
由于在实际阵列区，栅极结构通常暴露基底表面，因此在进行针对其他膜层的刻蚀工艺时，刻蚀剂可能会对基底造成二次刻蚀，也就是说，在进行场效应管的实际运行时，实际阵列区的基底通常存在一定程度的误刻蚀，即掺杂区 的有效掺杂区域小于预设掺杂区域。同时，由于本实施例中不一定会存在针对其他膜层的刻蚀工艺，且对相邻栅极结构33之间的间距进行了限定，二次刻蚀对基底30造成的影响相对于实际阵列区较小，因此，直接采用刻蚀工艺形成位于基底30内的第二凹槽342，可在一定程度上模拟实际阵列区的基底受到二次刻蚀的情况，使得通过测试结构获取的掺杂区阻值更为接近实际应用阻值。
本实施例中，采用同一刻蚀工艺连续刻蚀隔离层352和保护层34；在其他实施例中，还可以进行两次刻蚀工艺，分别刻蚀隔离层和保护层。由于过刻蚀形成的凹槽的深度与刻蚀选择比、刻蚀时间以及顶部开口宽度等因素有关，相较于连续刻蚀隔离层和保护层，单独刻蚀保护层所需的刻蚀时间较短，所需的刻蚀液较少，过刻蚀所形成的凹槽的深度较浅，如此，可在一定程度上模拟实际阵列区的加工工艺中小剂量刻蚀剂对基底造成的误刻蚀，进而获取更为准确的有效掺杂区域以及更为准确的阻值。
在其他实施例中，当测试结构的制作工艺中存在可能导致二次刻蚀的工艺步骤，或需要进行二次刻蚀的模拟试验时，也可仅刻蚀隔离层。参考图13，仅刻蚀隔离层，形成暴露基底40表面的第二凹槽442，使得基底40可受到来自额外刻蚀剂的二次刻蚀，从而模拟实际阵列区的掺杂区实际情况。
其中，第二凹槽442位于第一凹槽441底部，第一凹槽441的顶部开口宽度与相邻栅极结构43之间的间距相等，第二凹槽442的顶部开口宽度与相邻栅极结构43之间的两层隔离侧墙451之间的间距相等，第一凹槽441和第二凹槽442构成的凹槽的侧壁表面为拼接表面。
参考图14，在进行第二刻蚀工艺之后，以栅极结构33和隔离侧墙351为掩膜，向基底30内注入掺杂离子，形成掺杂区36。
本实施例中，在形成掺杂区36之后，还在掺杂区36的延伸方向的两端形成另一掺杂区，另一掺杂区的掺杂离子类型与掺杂区36掺杂离子类型相同，另一掺杂区的掺杂离子浓度大于掺杂区36的掺杂离子浓度，掺杂区36作为LDD结构，另一掺杂区作为源漏区。
本实施例中，在形成栅极结构的过程中，仅刻蚀去除导电膜，如此，可利用栅介质膜承担部分过刻蚀损伤，避免基底内形成深度较深的过刻蚀凹槽，保证测试获取到的掺杂区阻值的准确性和有效性。
本领域技术人员在考虑说明书及实践的公开后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。
工业实用性
本公开所提供的测试结构及其制作方法，将相邻栅极结构之间的间距设置在预设范围内，有利于减小栅极结构形成过程中的过刻蚀深度，避免过刻蚀形成的凹槽过多地占据掺杂区的预设掺杂区域，保证掺杂区具有较大的有效掺杂区域，进而更为准确地获取具有预设掺杂区域的掺杂区的电阻阻值。

Claims (12)

  1. 一种测试结构的制作方法，其中，包括：
    提供基底，并在所述基底上形成依次层叠的栅介质膜和导电膜；
    至少对所述导电膜进行图案化刻蚀，以形成位于所述基底上的多个分立的栅极结构，在所述栅极结构的排列方向上，相邻所述栅极结构之间的间距小于等于110nm；
    形成位于所述栅极结构相对两侧的隔离侧墙；
    以所述栅极结构和所述隔离侧墙为掩膜，向所述基底内注入掺杂离子，形成掺杂区，在垂直于所述基底表面的方向上，所述掺杂区的掺杂深度小于等于10nm。
  2. 根据权利要求1所述的测试结构的制作方法，其中，形成所述栅极结构和所述隔离侧墙的工艺步骤包括：对所述导电膜和所述栅介质膜进行图案化刻蚀，形成所述栅极结构；形成隔离膜，所述隔离膜覆盖所述栅极结构侧壁和所述基底表面；刻蚀覆盖所述基底表面的所述隔离膜，剩余所述隔离膜作为所述隔离侧墙。
  3. 根据权利要求1所述的测试结构的制作方法，其中，形成所述栅极结构和所述隔离侧墙的工艺步骤包括：对所述导电膜进行图案化刻蚀，剩余所述导电膜以及位于剩余所述导电膜和所述基底之间的部分所述栅介质膜作为所述栅极结构，另一部分所述栅介质膜作为保护层；形成隔离膜，所述隔离膜覆盖所述栅极结构侧壁和覆盖所述保护层表面，覆盖所述栅极结构侧壁的所述隔离膜作为所述隔离侧墙，覆盖所述保护层表面的所述隔离膜作为隔离层。
  4. 根据权利要求3所述的测试结构的制作方法，其中，在形成所述隔离膜之后，刻蚀去除所述隔离层。
  5. 根据权利要求3所述的测试结构的制作方法，其中，在形成所述隔离膜之后，刻蚀去除所述隔离层以及位于所述隔离层和所述基底之间的所述保护层。
  6. 一种测试结构，其中，包括：
    基底和位于所述基底上的多个分立的栅极结构，在所述栅极结构的排列方向上，相邻所述栅极结构之间的间距小于等于110nm；
    隔离侧墙，位于所述栅极结构相对两侧；
    掺杂区，位于所述隔离侧墙远离所述栅极结构的一侧的所述基底内，在垂直于所述基底表面的方向上，所述掺杂区的掺杂深度小于等于10nm。
  7. 根据权利要求6所述的测试结构，其中，所述基底内具有第一凹槽和位于所述第一凹槽底部的第二凹槽，在所述栅极结构的排列方向上，所述第一凹槽的顶部开口宽度与相邻所述栅极结构之间的间距相等，所述第二凹槽的顶部开口宽度与相邻所述栅极结构之间的两层所述隔离侧墙之间的间距相等。
  8. 根据权利要求6所述的测试结构，其中，所述栅极结构包括栅极和栅介质层；还包括：保护层，位于所述隔离侧墙与所述基底之间，所述保护层的材料与所述栅介质层的材料相同。
  9. 根据权利要求8所述的测试结构，其中，所述保护层覆盖相邻所述栅极结构之间的所述基底表面，且所述保护层内具有凹槽，在所述栅极结构的排列方向上，所述凹槽的顶部开口宽度与相邻所述栅极结构之间的间距相等。
  10. 根据权利要求9所述的测试结构，其中，还包括：隔离层，覆盖于所述保护层表面，且位于相邻所述栅极结构之间的两层所述隔离侧墙之间，所述隔离层的材料与所述隔离侧墙的材料相同。
  11. 根据权利要求9所述的测试结构，其中，所述凹槽包括第一凹槽和位于所述第一凹槽底部的第二凹槽，在所述栅极结构的排列方向上，所述第一凹槽的顶部开口宽度与相邻所述栅极结构之间的间距相等，所述第二凹槽的顶部开口宽度与相邻所述栅极结构之间的两层所述隔离侧墙之间的间距相等。
  12. 根据权利要求8所述的测试结构，其中，所述基底内有凹槽，所述凹槽的顶部开口宽度与相邻所述栅极结构之间的两层所述隔离侧墙之间的间距相等，所述凹槽的侧壁表面为连续表面。
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