WO2022088733A1 - 半导体结构的形成方法 - Google Patents

半导体结构的形成方法 Download PDF

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Publication number
WO2022088733A1
WO2022088733A1 PCT/CN2021/103799 CN2021103799W WO2022088733A1 WO 2022088733 A1 WO2022088733 A1 WO 2022088733A1 CN 2021103799 W CN2021103799 W CN 2021103799W WO 2022088733 A1 WO2022088733 A1 WO 2022088733A1
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Prior art keywords
sacrificial layer
substrate
forming
semiconductor structure
sacrificial
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PCT/CN2021/103799
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English (en)
French (fr)
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夏军
白世杰
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长鑫存储技术有限公司
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Priority to US17/480,326 priority Critical patent/US11984352B2/en
Publication of WO2022088733A1 publication Critical patent/WO2022088733A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1026—Forming openings in dielectrics for dual damascene structures the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/1052—Formation of thin functional dielectric layers
    • H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
    • H01L2221/1063—Sacrificial or temporary thin dielectric films in openings in a dielectric

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a method for forming a semiconductor structure.
  • the spacing between the vias in the semiconductor structure is reduced, and the arrangement density of the vias in the semiconductor structure is not uniform, resulting in a high arrangement density of the vias in some regions, and some regions.
  • the arrangement density of the through holes is small.
  • the filling height of the through holes with high arrangement density is lower in the same filling time, resulting in different filling heights of the through holes in the semiconductor structure.
  • the subsequent process of etching to form the Damascus structure Due to the different filling heights of the via holes, etching defects are easily generated, thereby affecting the yield of the formed semiconductor structure.
  • Embodiments of the present application provide a method for forming a semiconductor structure, which avoids etching defects caused by different pattern densities.
  • embodiments of the present application provide a method for forming a semiconductor structure, including: providing a substrate having a first region and a second region, wherein a plurality of discrete through holes are also formed in the substrate, and are located in the first region.
  • the arrangement density of the through holes in one area is greater than the arrangement density of the through holes in the second area;
  • a sacrificial layer is formed to fill the through holes;
  • a part of the thickness of the substrate around the sacrificial layer is etched to form an opening, and the opening surrounds the sacrificial layer and is perpendicular to the sacrificial layer.
  • the depth of the opening is smaller than the depth of the through hole; the sacrificial layer is removed, and the opening is communicated with the corresponding through hole to form a trench.
  • 1 to 8 are schematic cross-sectional structural diagrams corresponding to each step in a method for forming a semiconductor structure provided by an embodiment of the present application.
  • the filling height of the through holes with high arrangement density is lower during the same filling time, resulting in different filling heights of the through holes in the semiconductor structure, and the subsequent process of etching to form the Damascus structure Among them, due to the different filling heights of the via holes, etching defects are easily generated, thereby affecting the yield of the formed semiconductor structure.
  • the first embodiment of the present application provides a method for forming a semiconductor structure, which includes: providing a substrate having a first region and a second region, wherein a plurality of discrete through holes are formed in the substrate and located in the first region.
  • the arrangement density of the through holes in one area is greater than the arrangement density of the through holes in the second area;
  • a sacrificial layer is formed to fill the through holes;
  • a part of the thickness of the substrate around the sacrificial layer is etched to form an opening, and the opening surrounds the sacrificial layer and is perpendicular to the sacrificial layer.
  • the depth of the opening is less than the depth of the through hole; the sacrificial layer is removed, and the opening is connected with the corresponding through hole to form a trench; the embodiment of the present application is used to avoid etching defects caused by different pattern densities .
  • 1 to 8 are schematic cross-sectional structural diagrams corresponding to each step of a method for forming a semiconductor structure provided by an embodiment of the present application, and the semiconductor structure of this embodiment will be specifically described below.
  • a substrate 100 having a first area 110 and a second area 120 is provided, and a plurality of discrete through holes 201 are also formed in the substrate 100, and the arrangement density of the through holes 201 in the first area 110 is greater than that in the first area 110.
  • the arrangement density of the through holes 201 in the two regions 120 is greater than that in the first area 110.
  • the substrate 100 includes a conductive layer 101 , a first insulating layer 102 , a dielectric layer 103 and a second insulating layer 104 which are sequentially stacked.
  • a specific structure of the substrate 100 is used to describe in detail the method for forming the semiconductor structure provided in this embodiment, which is for those skilled in the art to understand the implementation of this solution, and does not constitute a limitation to this application.
  • the method for forming a semiconductor structure provided in this embodiment can be applied to semiconductors of different structures, and those skilled in the art can select an appropriate position according to the structure of the substrate 100 to implement the method for forming a semiconductor structure provided in this embodiment. .
  • the conductive layer 101 may be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc.; the first insulating layer 102 , the materials of the dielectric layer 103 and the second insulating layer 104 include silicon nitride, silicon dioxide or silicon oxynitride; in this embodiment, the material of the conductive layer 101 is copper, and the material of the first insulating layer 102 and the second insulating layer 104 The material is silicon nitride, and the material of the dielectric layer 103 is silicon oxide.
  • the height of the through holes 201 in the first area 110 is often lower than that in the filling of the through holes in the second area 120
  • the height of 201, in the subsequent process of etching to form the opening due to the different filling heights of the through hole 201, in the process of forming the opening in the first region 110 and the second region 120, it is easy to align the through hole 201 of the first region 110.
  • the sidewall is over-etched, thereby affecting the morphology of the subsequently formed semiconductor structure, thereby affecting the yield of the subsequently formed semiconductor structure.
  • the present embodiment aims to form a sacrificial layer filling the through hole 201 , so that the sacrificial layer in the first region 110 and the sacrificial layer in the second region 120 have the same height.
  • the method for forming the sacrificial layer in this embodiment will be described in detail below with reference to the accompanying drawings.
  • a sacrificial layer 202 filling the via hole 201 is formed.
  • the height of the sacrificial layer 202 in the first region 110 is the same as the height of the sacrificial layer 202 in the second region 120 .
  • the material of the formed sacrificial layer 202 includes polysilicon, and the sacrificial layer 202 can be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD) or a furnace tube process.
  • CVD Chemical Vapor Deposition
  • the sacrificial layer 202 is formed by chemical vapor deposition, and the formed sacrificial layer 202 has good density, and can fill the through hole 201 relatively completely. Since the furnace tube process is to deposit a large number of wafers at the same time, the use of the furnace tube process to form the sacrificial layer 202 can improve the deposition efficiency of the sacrificial layer 202, thereby solving the time cost of semiconductor manufacturing.
  • the sacrificial layer 202 formed by polysilicon has a large etching selectivity ratio between the sacrificial layer 202 and the dielectric layer 103, so that when the sacrificial layer 202 is subsequently etched, the dielectric layer 103 can be prevented from being highly etched by the etching material. When the dielectric layer 103 is etched subsequently, a higher etching rate of the sacrificial layer 202 can be avoided by the etching material.
  • the sacrificial layer 202 is a hard mask formed by spin coating, and the formed hard mask and the dielectric layer 103 have a certain etching selectivity ratio, so as to achieve selectivity to the sacrificial layer 202 or the dielectric layer 103 etching.
  • the sacrificial layer 202 formed by polysilicon has a larger etching selection ratio than the hard mask. In the process of subsequent etching to form openings, Fewer parts of the sacrificial layer 202 formed by using polysilicon are etched, which ensures that the morphology of the subsequently formed semiconductor structure is complete, thereby improving the yield of the subsequently formed semiconductor structure.
  • Forming the sacrificial layer 202 filling the through hole 201 includes the following steps:
  • a sacrificial film (not shown) filling the via 201 and covering the substrate 100 is formed.
  • the arrangement density of the through holes 201 in the first region 110 is greater than the arrangement density of the through holes 201 in the second region 120, in the process of forming the sacrificial film (not shown), due to the difference in arrangement density, the filling The material required to fill the through holes 201 in the second region 120 is less, and the material required to fill the through holes 201 in the first region 110 is more; therefore, the formed sacrificial film (not shown) will be filled first in the first region 110 .
  • the through holes 201 in the two regions 120 cause the top surfaces of the sacrificial films (not shown) to be subsequently formed to cover the substrate 110 not to be at the same height, and the height of the top surfaces of the sacrificial films (not shown) in the second region 120 is higher at the height of the top surface of the sacrificial film (not shown) located in the first region 110 .
  • the sacrificial film (not shown) is planarized, and the remaining sacrificial film (not shown) is used as the sacrificial layer 202 .
  • a chemical mechanical polishing (CMP) method is used for planarization to form the sacrificial layer 202 located in the first region 110 and the second region 120 with the same height.
  • CMP chemical mechanical polishing
  • the top surface of the sacrificial film (not shown) may also be planarized by an etching process.
  • the top of the sacrificial film (not shown) is polished by chemical mechanical polishing to form the sacrificial layer 202.
  • chemical mechanical polishing has a higher removal rate, which is beneficial to shorten the process cycle.
  • this embodiment provides two morphologies of the sacrificial layer 202 formed by the planarization process.
  • the first type Referring to FIG. 2 , the sacrificial film (not shown) is planarized until the top surface of the remaining sacrificial film (not shown) is parallel to the top surface of the substrate 100 .
  • the formed sacrificial layer 202 not only fills the through hole 201 , but also the heights of the sacrificial layer 202 located in the first region 110 and the second region 120 are the same. That is, the sacrificial layer 202 covering the substrate 100 is located at the same height, for example, the top surface of the sacrificial layer 202 is parallel to the top surface of the base 100 .
  • the second type Referring to FIG. 3 , the sacrificial film (not shown) is planarized until the top surface of the substrate 100 is exposed.
  • the formed sacrificial layer 202 is only used to fill the through holes 201 located in the first region 110 and the second region 120 . That is, the height of the sacrificial layer 202 filling the through hole 201 is the same as the height of the base 100 .
  • the structure of the sacrificial layer 202 formed in the first manner in this embodiment describes the method for forming the provided semiconductor structure in detail, and the structure of the sacrificial layer 202 formed in the first manner is applicable to the formation of the semiconductor structure The method is also applicable to the structure of the sacrificial layer 202 formed in the second manner.
  • the substrate 100 with a partial thickness around the sacrificial layer 202 is etched to form an opening 301 , and the opening 301 surrounds the sacrificial layer 202 .
  • a patterned mask layer 203 is formed on the top surface of the substrate 100 , and in a direction parallel to the surface of the substrate 100 , the pattern exposed by the patterned mask layer 203 is on the substrate 100
  • the orthographic projection of completely covers the orthographic projection of the sacrificial layer 202 on the substrate 100 .
  • the orthographic projection of the pattern exposed by the patterned mask layer 203 on the substrate 100 completely covers the orthographic projection of the sacrificial layer 202 on the substrate 100 to ensure that the formed opening 301 surrounds the sacrificial layer 202 .
  • Forming the patterned mask layer 203 includes the following steps:
  • a mask layer 213 is formed on the top surface of the sacrificial layer 202 , a patterned photoresist 204 is formed on the top surface of the mask layer 213 , and the pattern exposed by the patterned photoresist 204 is on the substrate 100
  • the orthographic projection completely covers the orthographic projection of the sacrificial layer 202 on the substrate 100 .
  • part of the mask layer 213 is etched to form the patterned mask layer 203 .
  • the sacrificial layer 202 on the top surface of the substrate 100 is patterned. Since the present application is based on the sacrificial layer 202 formed in the first method as an example, the description of the formation method of the semiconductor structure is carried out. At this time, the sacrificial layer 202 is still located on the top surface of the substrate 100. If the sacrificial layer 202 formed in the second method is used , you can omit this step.
  • a partial height of the substrate 100 is etched to form an opening 301 .
  • the width of the opening 301 is based on the width of the pattern exposed by the patterned mask layer 203 . Since the arrangement density of the through holes 201 located in the first area 110 is greater than that of the through holes 201 located in the second area 120 , correspondingly, the width of the formed openings 301 located in the first area 110 is smaller than that located in the second area 120 .
  • the width of the opening 301 that is, in the direction parallel to the surface of the substrate 100 , the width of the opening 301 in the second region 120 is greater than the width of the opening 301 in the first region 110 . And in this embodiment, even if the through holes 201 are located in the same area, the smaller the arrangement density of the through holes 201 is, the larger the width of the formed openings 301 is.
  • the depth of the opening 301 is controlled by the time for etching the substrate 100 , and the longer the etching time is, the deeper the depth of the opening 301 is.
  • the arrangement density of the through holes 201 in the first area 110 is high, there are more through holes 201 in the substrate 100 of the same size, and the spacing between the through holes 201 is small, so the etching load in the first area 110 is The effect is large; the arrangement density of the through holes 202 in the second area 120 is small, there are fewer through holes 201 in the substrate 100 of the same size, and the spacing between the through holes 201 is larger, so the through holes 201 are located in the second area 120.
  • the etch loading effect is small. That is, due to different etching load effects, in the same etching time, the depths of the openings 301 formed by etching in the first region 110 and the second region 120 are different.
  • the patterned photoresist 204 and the patterned mask layer 203 are sequentially removed.
  • the remaining sacrificial layer 202 on the top surface of the substrate 100 also needs to be removed.
  • the patterned photoresist 204, the patterned mask layer 203 and the remaining sacrificial layer 202 are sequentially removed by an etching process until the top surface of the substrate 100 is exposed, and the etching process is used to ensure the formation of the semiconductor The structure is subjected to excessive impact, resulting in a collapse phenomenon that affects the yield of the semiconductor structure.
  • the patterned photoresist, the patterned mask layer, and the remaining sacrificial layer can be removed by chemical mechanical polishing. By chemical mechanical polishing, chemical mechanical polishing has higher efficiency than etching process. The removal rate is beneficial to shorten the process cycle.
  • the sacrificial layer 202 is removed, and the openings 301 are communicated with the corresponding through holes 201 to form trenches 302 .
  • the formed trench 302 includes a through hole 201 with a depth greater than the opening 301 and an opening 301 with a width greater than the through hole 201 . It can be seen that the formed trench 302 has a Damascus structure.
  • the formed Damascus structure exposes the conductive layer 101 in the substrate 100 , and the conductive structure formed by filling the Damascus structure subsequently is electrically connected to the conductive layer 101 .
  • the sacrificial layer 202 is removed by using hydrogen plasma.
  • the hydrogen plasma used to remove the sacrificial layer 202 only has the chemical reaction effect and does not have the ion effect. Specifically, radio frequency ionization of hydrogen gas is used in the furnace tube equipment to form high-energy molecules and high-energy ions, the directional high-energy ions are filtered out through the grid arranged in the furnace tube equipment, and the remaining hydrogen plasma is used to remove the sacrificial layer. 202. Removing the sacrificial layer 202 by high-energy molecules can further improve the removal efficiency of the sacrificial layer 202 .
  • the etching rate of hydrogen plasma for polysilicon is relatively high, and the etching rate for other semiconductor structures is extremely low, so the process of removing the sacrificial layer 202 by hydrogen plasma etching is adopted , has a very large etching selectivity ratio, and the etching selectivity ratio is usually greater than 1000:1. It can be considered that the hydrogen plasma only reacts with the sacrificial layer 202 and does not react with other structures in the substrate 100 .
  • the opening 301 will not be etched continuously, so that the depth of the opening 301 will not change greatly during the process of removing the sacrificial layer 202.
  • the formation of the formed semiconductor structure is prevented from being changed, that is, the formed Damascus structure will not be damaged, thereby improving the yield of the formed semiconductor structure.
  • the material of the sacrificial layer is other semiconductor materials except polysilicon
  • those skilled in the art have reasons to select plasma with a high selectivity ratio corresponding to the material of the sacrificial layer for etching.
  • the sacrificial layer can be etched by using an etch material with a relatively large etching selection ratio for the sacrificial layer and the dielectric layer. Due to the large etching selection ratio, in the process of etching the sacrificial layer, although the depth of the opening will decrease , but less impact on the formed semiconductor structure.
  • the height of the sacrificial layer filling the through hole is the same, so as to ensure that the etching caused by different pattern densities in the process of forming the Damascus structure based on the sacrificial layer etching in the subsequent process. defects, thereby improving the yield of semiconductor structures.

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Abstract

本申请实施例提供一种半导体结构的形成方法，包括：提供具有第一区域和第二区域的基底，基底内还形成有多个分立的通孔，且位于第一区域的通孔的排布密度大于位于第二区域的通孔的排布密度；形成填充通孔的牺牲层；刻蚀牺牲层周围部分厚度的基底形成开口，开口环绕牺牲层，在垂直于基底表面的方向上，开口的深度小于通孔的深度；去除牺牲层，开口与对应的通孔相连通，形成沟槽。

Description

半导体结构的形成方法
交叉引用
本申请基于申请号为202011165219.9、申请日为2020年10月27日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体领域，尤其涉及一种半导体结构的形成方法。
背景技术
随着半导体器件特征尺寸的减小，使得半导体结构中通孔之间的间距减小，半导体结构中通孔的排布密度不均一，导致存在部分区域的通孔的排布密度大，部分区域的通孔的排布密度小。
在填充通孔的过程中，相同的填充时间内，排布密度大的通孔填充的高度较低，导致半导体结构中各通孔的填充高度不同，后续在刻蚀形成大马士革结构的过程中，由于通孔填充的高度不同，容易产生刻蚀缺陷，从而影响形成的半导体结构的良率。
申请内容
本申请实施例提供一种半导体结构的形成方法，避免因不同的图案密度所产生的刻蚀缺陷。
为解决上述技术问题，本申请的实施例提供了一种半导体结构的形成方法，包括：提供具有第一区域和第二区域的基底，基底内还形成有多个分立的通孔，且位于第一区域的通孔的排布密度大于位于第二区域的通孔的排布密度；形成填充通孔的牺牲层；刻蚀牺牲层周围部分厚度的基底形成开口，开口环绕牺牲层，在垂直于基底表面的方向上，开口的深度小于通孔的深度；去除牺牲层，开口与对应的通孔相连通，形成沟槽。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申明，附图中的图不构成比例限制。
图1～图8为本申请实施例提供的半导体结构的形成方法中各步骤对应的剖面结构示意图。
具体实施方式
目前，在填充通孔的过程中，相同的填充时间内，排布密度大的通孔填充的高度较低，导致半导体结构中各通孔的填充高度不同，后续在刻蚀形成大马士革结构的过程中，由于通孔填充的高度不同，容易产生刻蚀缺陷，从而影响形成的半导体结构的良率。
为解决上述问题，本申请第一实施例提供了一种半导体结构的形成方法，包括：提供具有第一区域和第二区域的基底，基底内还形成有多个分立的通孔，且位于第一区域的通孔的排布密度大于位于第二区域的通孔的排布密度；形成填充通孔的牺牲层；刻蚀牺牲层周围部分厚度的基底形成开口，开口环绕牺牲层，在垂直于基底表面的方向上，开口的深度小于通孔的深度；去除牺牲层，开口与对应的通孔相连通，形成沟槽；本申请实施例用于避免因不同的图案密度所产生的刻蚀缺陷。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1～图8为本申请实施例提供的半导体结构的形成方法的各步骤对应的剖面结构示意图，下面对本实施例的半导体结构进行具体说明。
参考图1，提供具有第一区域110和第二区域120的基底100， 基底100内还形成有多个分立的通孔201，且位于第一区域110的通孔201的排布密度大于位于第二区域120的通孔201的排布密度。
在本实施例中，基底100包括依次堆叠形成的导电层101、第一绝缘层102、介质层103和第二绝缘层104。需要说明的是，本实施例以一种具体的基底100的结构对本实施例提供半导体结构的形成方法进行详细说明，是为了本领域技术人员了解本方案的实现方式，并不构成对本申请的限定，在具体的实现中，本实施例提供的半导体结构的形成方法可以适用于不同结构的半导体，本领域技术人员可根据基底100的结构选择合适位置进行实现本实施例提供的半导体结构的形成方法。
具体地，在本实施例中，导电层101可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等；第一绝缘层102、介质层103和第二绝缘层104的材料包括氮化硅、二氧化硅或氮氧化硅；在本实施例中导电层101的材料为铜，第一绝缘层102和第二绝缘层104的材料为氮化硅，介质层103的材料为氧化硅。
由于第一区域110和第二区域120中通孔201的排布存在密度差异，在填充通孔201时，填充第一区域110中通孔201的高度往往低于填充第二区域120中通孔201的高度，后续在刻蚀形成开口的过程中，由于通孔201被填充高度不同，在第一区域110和第二区域120内形成开口的过程中，容易对第一区域110的通孔201侧壁过刻蚀，从而影响后续形成的半导体结构的形貌，进而影响后续形成的半导体结构的良率。
本实施例旨在形成一种填充通孔201的牺牲层，使得位于第一区域110的牺牲层和位于第二区域120的牺牲层的高度齐平。下面结合附图对本实施例形成牺牲层的方法进行详细说明。
参考图2和图3，形成填充通孔201的牺牲层202。在垂直于基底100表面的方向上，位于第一区域110的牺牲层202的高度与位于第二区域120的牺牲层202的高度齐平。
在一个例子中，形成的牺牲层202的材料包括多晶硅，可采用化学气相沉积(Chemical Vapor Deposition，CVD)或炉管工艺形成牺牲层202。
具体地，采用化学气相沉积形成牺牲层202，形成的牺牲层202具有良好的致密性，可以较为完成的填充通孔201。由于炉管工艺是对大量晶圆同时进行沉积，因此采用炉管工艺形成牺牲层202，可以提高牺牲层202的沉积效率，从而解决半导体工艺制造的时间成本。
采用多晶硅形成的牺牲层202，牺牲层202与介质层103之间存在较大的刻蚀选择比，使得后续在刻蚀牺牲层202时，避免刻蚀材料对介质层103存在较高的刻蚀速率，或后续在刻蚀介质层103时，避免刻蚀材料对牺牲层202存在较高的刻蚀速率。
在另一个例子中，牺牲层202为采用旋涂方式形成的硬掩膜，形成的硬掩膜与介质层103存在一定的刻蚀选择比，从而实现对牺牲层202或介质层103的选择性刻蚀。
采用多晶硅形成的牺牲层202相比于采用旋涂方式形成的硬掩膜作为牺牲层202，多晶硅相比于硬掩膜具有更大的刻蚀选择比，在后续刻蚀形成开口的过程中，采用多晶硅形成的牺牲层202被刻蚀的部分更少，保证了后续形成的半导体结构的形貌完整，进而提高了后续形成的半导体结构的良率。
形成填充通孔201的牺牲层202，包括以下步骤：
形成填充通孔201且覆盖基底100的牺牲膜(未图示)。
具体地，由于位于第一区域110的通孔201排布密度大于第二区域120的通孔201的排布密度，在形成牺牲膜(未图示)的过程中，由于排布密度差异，填充满第二区域120的通孔201所需的材料较少，填充满第一区域110的通孔201所需的材料较多；因此，形成的牺牲膜(未图示)会先填充满位于第二区域120的通孔201，导致后续形成覆盖基底110的牺牲膜(未图示)的顶部表面并非位于同一高度，且位于第二区域120的牺牲膜(未图示)的顶部表面的高度高于位于第一区域110的牺牲膜(未图示)的顶部表面的高度。
对牺牲膜(未图示)进行平坦化处理，剩余牺牲膜(未图示)作为牺牲层202。
在本实施例中，采用化学机械研磨(chemical mechanical polish，CMP)的方式进行平坦化处理，以形成位于第一区域110和第二区域120高度一致的牺牲层202。在其他实施例中，也可以才采用刻蚀工艺对牺牲膜(未图示)的顶部表面进行平坦化处理。采用化学机械研磨的方式对牺牲膜(未图示)的顶部进行打磨，形成牺牲层202，化学机械研磨相对于刻蚀工艺具有较高的去除速率，有利于缩短工艺周期。
具体地，本实施例给出了两种采用平坦化处理形成的牺牲层202的形貌。
第一种：参考图2，对牺牲膜(未图示)进行平坦化处理，直至剩余的牺牲膜(未图示)的顶部表面与基底100顶部表面平行。形成的牺牲层202不仅填充满通孔201，且位于第一区域110和位于第二区域120的牺牲层202的高度齐平。即覆盖基底100的牺牲层202位于同一高度，例如，牺牲层202的顶部表面与基地100的顶部表面平行。
第二种：参考图3，对牺牲膜(未图示)进行平坦化处理，直至暴露出基底100顶部表面。形成的牺牲层202仅用于填充满位于第一区域110和位于第二区域120的通孔201。即填充通孔201的牺牲层202的高度与基地100的高度齐平。
需要说明的是，本实施例以第一种方式形成的牺牲层202的结构对提供的半导体结构的形成方法进行详细介绍，以第一种方式形成的牺牲层202的结构适用的半导体结构的形成方法，同样适用于以第二种方式形成的牺牲层202的结构。
参考图4～图7，刻蚀牺牲层202周围部分厚度的基底100形成开口301，开口301环绕牺牲层202，在垂直于基底100表面的方向上，开口301的深度小于通孔201的深度。
具体地，参考图4～图5，在基底100的顶部表面形成图形化的掩膜层203，在平行于基底100表面的方向上，图形化的掩膜层203 暴露出的图形在基底100上的正投影完全覆盖牺牲层202在基底100上的正投影。通过图形化的掩膜层203暴露出的图形在基底100上的正投影完全覆盖牺牲层202在基底100上的正投影保证形成的开口301环绕牺牲层202。
形成所述图形化的掩膜层203包括以下步骤：
参考图4，在牺牲层202的顶部表面形成掩膜层213，在掩膜层213的顶部表面形成图形化的光刻胶204，图形化的光刻胶204暴露出的图形在基底100上的正投影完全覆盖牺牲层202在基底100上的正投影。
参考图5，基于图形化的光刻胶，刻蚀部分掩膜层213，形成图形化的掩膜层203。
参考图6，基于图形化的掩膜层203，图形化位于基底100顶部表面的牺牲层202。由于本申请是基于第一种方式形成的牺牲层202为例，进行的半导体结构的形成方法的陈述，此时牺牲层202还位于基底100顶部表面，若以第二种方式形成的牺牲层202，则可以省略掉该步骤。
参考图7，基于图形化的掩膜层203，刻蚀部分高度的基底100，形成开口301。
在平行于基底100方向上，开口301的宽度基于图形化的掩膜层203所暴露出的图形的宽度。由于位于第一区域110的通孔201的排布密度大于位于第二区域120的通孔201的排布密度，相应地，形成的位于第一区域110的开口301的宽度小于位于第二区域120的开口301的宽度，即在平行于基底100表面的方向上，位于第二区域120的开口301的宽度大于位于第一区域110的开口301的宽度。且在本实施例中，即使位于同一区域，通孔201的排布密度越小，形成的开口301的宽度越大。
需要说明的是，开口301的深度通过刻蚀基底100的时间控制，刻蚀时间越长，形成的开口301的深度越深。
且位于第一区域110的通孔201的排布密度大，相同尺寸的基底100中存在更多的通孔201，通孔201之间的间距较小，因此位 于第一区域110的刻蚀负载效应较大；位于第二区域120的通孔202的排布密度小，相同尺寸的基底100中存在较少的通孔201，通孔201之间的间距较大，因此位于第二区域120的刻蚀负载效应较小。即由于不同的刻蚀负载效应，在相同的刻蚀时间内，在第一区域110和第二区域120中刻蚀形成开口301的深度不同，通孔201的排布密度越小，刻蚀负载效应越小，相应形成的位于通孔201周围的开口301的深度越深。形成开口301后，依次去除图形化的光刻胶204和图形化的掩膜层203。在本实施例中，还需要去除位于基底100顶部表面的剩余牺牲层202。
在本实施例中，采用刻蚀工艺依次去除图形化的光刻胶204、图形化的掩膜层203以及剩余牺牲层202，直至暴露出基底100顶部表面，采用刻蚀工艺以保证形成的半导体结构遭到过大的冲击，从而导致坍塌的现象，影响半导体结构的良率。在其他实施例中，可以化学机械研磨的方式去除图形化的光刻胶、图形化的掩膜层以及剩余牺牲层，通过化学机械研磨的方式，化学机械研磨相对于刻蚀工艺具有较高的去除速率，有利于缩短工艺周期。
参考图8，去除牺牲层202，开口301与对应的通孔201相连通，形成沟槽302。形成的沟槽302包括深度大于开口301的通孔201和宽度大于通孔201的开口301，由此可知，形成的沟槽302为大马士革结构。
在本实施例中，形成的大马士革结构暴露出基底100中的导电层101，用于后续填充大马士革结构形成的导电结构与导电层101电连接。
在本实施例中，采用氢气等离子体去除牺牲层202。
在本实施例中，去除牺牲层202采用的氢气等离子体仅具备化学反应效应，不具备离子效应。具体地，在炉管设备中采用射频电离氢气，以形成高能分子和高能离子，在通过设置在炉管设备中的网格过滤掉具有方向性的高能离子，剩余氢气等离子体用于去除牺牲层202。通过高能分子去除牺牲层202可以进一步提高牺牲层202的去除效率。
由于本实施例形成的牺牲层202的材料包括多晶硅，氢气等离子体对多晶硅的刻蚀速率较高，对其他半导体结构的刻蚀速率极低，因此采用氢气等离子体刻蚀去除牺牲层202的过程中，具有极大的刻蚀选择比，刻蚀选择比通常大于1000：1。可视为氢气等离子体只与牺牲层202反应，而不与基底100中的其他结构发生反应。
另外，由于用于去除牺牲层202的氢气等离子体离子轰击效应较弱，不会继续刻蚀开口301，使得在去除牺牲层202的过程中，开口301的深度并不会发生较大变化，通过防止形成的半导体结构的形成发生改变，即形成的大马士革结构不会遭到破坏，进而提高形成的半导体结构的良率。
需要说明的是，在其他实施例中，若牺牲层的材料为除多晶硅外的其他半导体材料，本领域技术人员有理由选择与牺牲层材料对应的具有高选择比等离子体进行刻蚀。例如，可以采用牺牲层和介质层刻蚀选择比较大的刻蚀材料对牺牲层进行刻蚀，由于存在较大的刻蚀选择比，在刻蚀牺牲层的过程中，开口的深度虽会下降，但对形成的半导体结构的影响较小。
相对于相关技术而言，通过形成牺牲层填充通孔，填充通孔的牺牲层的高度一致，从而保证后续基于牺牲层刻蚀形成大马士革结构的过程中，因不同的图案密度所产生的刻蚀缺陷，进而提高半导体结构的良率。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (11)

  1. 一种半导体结构的形成方法，其特征在于，包括：
    提供具有第一区域和第二区域的基底，所述基底内还形成有多个分立的通孔，且位于所述第一区域的所述通孔的排布密度大于位于所述第二区域的所述通孔的排布密度；
    形成填充所述通孔的牺牲层；
    刻蚀所述牺牲层周围部分厚度的所述基底形成开口，所述开口环绕所述牺牲层，在垂直于所述基底表面的方向上，所述开口的深度小于所述通孔的深度；
    去除所述牺牲层，所述开口与对应的所述通孔相连通，形成沟槽。
  2. 根据权利要求1所述的半导体结构的形成方法，其特征在于，在垂直于所述基底表面的方向上，位于所述第一区域的所述牺牲层的高度与位于所述第二区域的所述牺牲层的高度齐平，形成填充所述通孔的牺牲层，包括以下步骤：
    形成填充所述通孔且覆盖所述基底的牺牲膜；
    对所述牺牲膜进行平坦化处理，剩余所述牺牲膜作为所述牺牲层。
  3. 根据权利要求2所述的半导体结构的形成方法，其特征在于，对所述牺牲膜进行平坦化处理，直至剩余所述牺牲膜的顶部表面与所述基底顶部表面平行。
  4. 根据权利要求2所述的半导体结构的形成方法，其特征在于，对所述牺牲膜进行平坦化处理，直至暴露出所述基底的顶部表面。
  5. 根据权利要求3或4所述的半导体结构的形成方法，其特征在于，采用化学机械研磨的方式进行所述平坦化处理。
  6. 根据权利要求1所述的半导体结构的形成方法，其特征在于，所述牺牲层为采用旋涂方式形成的硬掩模。
  7. 根据权利要求1所述的半导体结构的形成方法，其特征在于，所述牺牲层的材料包括多晶硅。
  8. 根据权利要求1所述的半导体结构的形成方法，其特征在于， 在平行于所述基底表面的方向上，位于所述第二区域的所述开口的宽度大于位于所述第一区域的所述开口的宽度。
  9. 根据权利要求6所述的半导体结构的形成方法，其特征在于，采用氢气等离子体去除所述牺牲层。
  10. 根据权利要求1所述的半导体结构的形成方法，其特征在于，刻蚀所述牺牲层周围部分厚度的所述基底形成开口，包括以下步骤：
    在所述基底的顶部表面形成图形化的掩膜层，在平行于所述基底表面的方向上，所述图形化的掩膜层暴露出的图形在基底上的正投影完全覆盖所述牺牲层在所述基底上的正投影；
    基于所述图形化掩膜层，刻蚀部分高度的所述基底，形成所述开口；
    去除所述图形化的掩膜层。
  11. 根据权利要求10所述的半导体结构的形成方法，其特征在于，在所述牺牲层的顶部表面形成图形化的掩膜层，包括以下步骤：
    在所述牺牲层的顶部表面形成掩膜层；
    在所述掩膜层的顶部表面形成图形化的光刻胶，所述图形化的光刻胶暴露出的图形在所述基底上的正投影完全覆盖所述牺牲层在所述基底上的正投影；
    基于所述图形化的光刻胶，刻蚀部分所述掩膜层，形成所述图形化的掩膜层。
PCT/CN2021/103799 2020-10-27 2021-06-30 半导体结构的形成方法 WO2022088733A1 (zh)

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