WO2022077963A1 - 熔丝结构及形成方法 - Google Patents

熔丝结构及形成方法 Download PDF

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Publication number
WO2022077963A1
WO2022077963A1 PCT/CN2021/104792 CN2021104792W WO2022077963A1 WO 2022077963 A1 WO2022077963 A1 WO 2022077963A1 CN 2021104792 W CN2021104792 W CN 2021104792W WO 2022077963 A1 WO2022077963 A1 WO 2022077963A1
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WIPO (PCT)
Prior art keywords
dielectric layer
layer
forming
fuse structure
conductive plug
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PCT/CN2021/104792
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English (en)
French (fr)
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王蒙蒙
黄信斌
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长鑫存储技术有限公司
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Priority to US17/480,332 priority Critical patent/US20220115321A1/en
Publication of WO2022077963A1 publication Critical patent/WO2022077963A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections

Definitions

  • the present application relates to the field of semiconductor manufacturing, and in particular, to a fuse structure and a method for forming the same.
  • a fuse is usually set in a semiconductor integrated circuit, and the purpose of adjusting the functional parameters of the integrated circuit can be achieved by blowing the fuse.
  • the fuse can be divided into an electric fuse and a laser fuse.
  • the laser fuse generally uses a certain energy of laser beam to irradiate the fuse, and then the laser fuse is blown.
  • the structure of the fuse in the prior art is complex, which leads to great difficulty in the process, affects the output efficiency of the product, and consumes too much energy when the fuse is blown.
  • the embodiments of the present application provide a fuse structure and a method for forming the fuse structure, which simplifies the fuse structure, thereby reducing the difficulty of the process, thereby reducing the production cost, improving the output efficiency of the product, and helping to solve the problem of cost when the fuse structure is blown.
  • the problem of too much energy is a problem of too much energy.
  • embodiments of the present application provide a fuse structure and a method for forming the fuse, including: a first dielectric layer, and at least two discrete first conductive plugs penetrating the first dielectric layer; a second conductive plug plugs, the second conductive plugs are electrically connected to at least two of the first conductive plugs; a top metal layer, the top metal layer is electrically connected to the second conductive plugs and located at the second conductive plugs A side away from the first conductive plug; a second dielectric layer, the second dielectric layer is located on top of the first dielectric layer and wraps the second conductive plug and the top metal layer.
  • Embodiments of the present application further provide a method for forming a fuse structure, including: providing a first dielectric layer, wherein at least two discrete first conductive plugs penetrating the first dielectric layer are formed in the first dielectric layer ; forming a second dielectric layer on the first dielectric layer; etching the second dielectric layer to form connected through holes and trenches, the through holes are located in the trench and the first conductive plug between the plugs, and the width of the through hole is smaller than the width of the trench; a second conductive plug is formed to fill the through hole, and the second conductive plug is electrically connected to at least two of the first conductive plugs plugs; forming a top metal layer filling the trenches, the top metal layer electrically connecting the second conductive plugs.
  • the second conductive plugs are electrically connected to at least two first conductive plugs, and the top metal layer is electrically connected to the second conductive plugs.
  • the second conductive plugs are electrically connected to at least two first conductive plugs, compared with the solution of using different second conductive plugs to connect the corresponding first conductive plugs respectively, no need
  • the provision of the dielectric between the second conductive plugs simplifies the fuse structure, thereby reducing the difficulty of the process, thereby reducing the production cost and improving the output efficiency of the product; in addition, it can also solve the problem of energy consumption when the fuse structure is blown
  • the problems of too much and incomplete fusing of the fuse structure ensure accurate control of the process parameters of the integrated circuit under the condition of low energy consumption.
  • the fuse structure further includes a bottom metal layer between the first conductive plug and the second conductive plug, and the bottom metal layer is electrically connected to the first conductive plug and the second conductive plug, respectively, since the second conductive plug is electrically connected to the second conductive plug. At least two first conductive plugs are connected. Compared with the scheme of using different second conductive plugs to connect the corresponding first conductive plugs respectively, there is no need to provide a dielectric between the second conductive plugs. In the process of structure, the process steps are simplified, the process difficulty is reduced, the output efficiency of the product is improved, and at the same time, the fuse structure is blown more completely, and the process parameters of the integrated circuit can be accurately controlled.
  • FIG. 1 is a schematic cross-sectional structure diagram of a fuse structure
  • FIG. 2 is a schematic cross-sectional structure diagram of a fuse structure provided by the first embodiment of the present application.
  • 3 to 5 are schematic structural diagrams corresponding to each step in a method for forming a fuse structure according to the first embodiment of the present application;
  • 6 to 8 are schematic structural diagrams corresponding to each step in another method for forming a fuse structure provided by the first embodiment of the present application;
  • FIG. 9 is a schematic cross-sectional view of a fuse structure provided by a second embodiment of the present application.
  • 10 to 12 are schematic structural diagrams corresponding to each step in a method for forming a fuse structure according to the second embodiment of the present application;
  • FIG. 13 is a schematic structural diagram corresponding to a step in another method for forming a fuse structure according to the second embodiment of the present application.
  • a fuse structure includes: a first dielectric layer 100 , a first conductive plug 101 , a second dielectric layer 104 , a bottom metal layer 112 , a second conductive plug 102 and a top metal layer 103 .
  • the second conductive plug 102 is composed of a plurality of discrete structures, a dielectric is present between the plurality of discrete structures, and there is an underlying metal layer 112 between the first conductive plug 101 and the second conductive plug 102, resulting in melting
  • the wire structure is complex, the process is difficult, and the production cost is high.
  • the fuse structure consumes a lot of energy when blown.
  • the presence of the dielectric will cause the fuse structure to be blown. In the process, the fusing is incomplete, which causes the problem that the process parameters of the integrated circuit are difficult to control.
  • the present application provides a fuse structure and a forming method, which simplifies the fuse structure, thereby reducing the technological difficulty, thereby reducing the production cost, improving the output efficiency of the product, and helping to solve the fuse
  • the structure is blown, it consumes too much energy and the fuse structure is not completely blown.
  • FIG. 2 is a schematic cross-sectional structure diagram of the fuse structure provided by the first embodiment of the present application.
  • the fuse structure includes: a first dielectric layer 100, and at least two discrete first conductive plugs 101 penetrating the first dielectric layer 100; a second conductive plug 102, the second conductive plug The plug 102 is electrically connected to at least two first conductive plugs 101 ; the top metal layer 103 is electrically connected to the second conductive plug 102 , and is located at a position of the second conductive plug 102 away from the first conductive plug 101 . side; the second dielectric layer 104 , the second dielectric layer 104 is located on top of the first dielectric layer 100 and wraps the second conductive plug 102 and the top metal layer 103 .
  • the fuse structure of this embodiment since the second conductive plugs 102 are electrically connected to at least two first conductive plugs 101 , it is different from the solution of using different second conductive plugs 102 to connect the corresponding first conductive plugs 101 respectively. In contrast, there is no need to set a dielectric between the second conductive plugs 102, which simplifies the fuse structure, thereby reducing the difficulty of the process, thereby reducing the production cost and improving the output efficiency of the product; in addition, the fuse structure can also be solved.
  • the problems of excessive energy consumption and incomplete fusing of the fuse structure during fusing ensure accurate control of the process parameters of the integrated circuit under the condition of low energy consumption.
  • the material of the first dielectric layer 100 is silicon oxide, and the material of the first conductive plug 101 includes tungsten metal.
  • the material of the first dielectric layer 100 can also be other insulating materials such as silicon nitride or silicon oxynitride, and the material of the first conductive plug 101 can also be other conductive materials such as polysilicon or copper.
  • the first dielectric layer 100 is used as an example as a single-layer structure. In other embodiments, the first dielectric layer 100 may also be a stacked structure.
  • the material of the second conductive plug 102 is the same as the material of the top metal layer 103 , and may specifically be copper or tungsten. In this way, the second conductive plug 102 and the top metal layer 103 can be formed by one deposition, which makes the whole process simpler.
  • the material of the second conductive plug 102 and the material of the top metal layer 103 may also be different.
  • the bottom surfaces of the second conductive plugs 102 are in contact with the top surfaces of the at least two first conductive plugs 101 .
  • the second conductive plug 102 is a whole, no dielectric is mixed in the middle, and the structure of a single fuse is simple, reducing the cost of The process is difficult; and the melting point of the dielectric is high, and there is no dielectric in a single fuse structure, which is beneficial to reduce the energy consumed when the fuse structure is blown, and is beneficial to reduce the difficulty of blowing the fuse structure.
  • the second dielectric layer 104 wraps the second conductive plug 102 and the top metal layer 103 , and may be the second conductive plug 102 and the top metal layer 103 within the second dielectric layer 104 .
  • the second dielectric layer 104 may include: a first dielectric layer 105 , a barrier layer 106 and a second dielectric layer 107 stacked in sequence; the second conductive plug 102 at least penetrates the first dielectric layer 105 and the barrier layer 106 .
  • the material of the first dielectric layer 105 is the same as the material of the second dielectric layer 107 , and may specifically be silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.
  • the material of the barrier layer 106 is different from the material of the first dielectric layer 105 and the material of the second dielectric layer 107 , and may be, for example, silicon nitride.
  • the function of the barrier layer 106 includes: playing an etching stop function in the process steps of fabricating the fuse structure, so as to reduce the difficulty of the etching process.
  • the second conductive plug 102 between the first dielectric layer 100 and the second dielectric layer 107 has a first thickness
  • the top metal layer 103 has a second thickness
  • the first thickness and the second thickness may be equal
  • the relationship between the first thickness and the second thickness is related to the fabrication process of the fuse structure, that is, the second conductive plug 102 and the top metal layer 103 are fabricated using a dual-damascene process, and the dual-damascene process includes a first pass through. The hole (via first trench last) method and the via last trench first method.
  • the second dielectric layer 104 may also be a single-layer structure.
  • the fuse structure may further include: a protective layer 108 , and the protective layer 108 is located on a side of the top metal layer 103 away from the second conductive plug 102 .
  • the protective layer 108 can provide protection for the top metal layer 103, for example, to protect the top metal layer 103 from being damaged by subsequent etching processes.
  • the protective layer 108 can be a single-layer structure or a multi-layer structure of various materials, for example, the protective layer 108 is a single-layer structure of silicon nitride material, or the protective layer 108 is a multi-layer structure with a surface of silicon nitride material.
  • the fuse structure provided by this embodiment simplifies the fuse structure, thereby reducing the difficulty of the process, thereby reducing the production cost and improving the output efficiency of the product; in addition, it can also solve the problem of excessive energy consumption and excessive energy consumption when the fuse structure is blown.
  • the problem of incomplete fusing of the fuse structure ensures accurate control of the process parameters of the integrated circuit under the condition of low energy consumption.
  • FIGS. 6 to 8 are another schematic diagram of the fuse structure provided by the first embodiment of the present application.
  • a first dielectric layer 100 is provided having at least two discrete first conductive plugs 101 formed therein through the first dielectric layer 100 .
  • a second dielectric layer 104 is formed on the first dielectric layer 100 .
  • Forming the second dielectric layer 104 on the first dielectric layer 100 includes: stacking and arranging the first dielectric layer 105 , the barrier layer 106 and the second dielectric layer 107 in sequence.
  • the second dielectric layer 107 is etched until the barrier layer 106 is exposed, and an initial through hole 109 is formed.
  • the partial thickness of the second dielectric layer 107 around the initial through hole 109 is removed by etching, and the barrier layer 106 and the first dielectric layer 105 exposed by the initial through hole 109 are etched until the first conductive plug is exposed 101 , forming through holes 110 and trenches 111 .
  • the through holes 110 and the trenches 111 are formed in a manner of first forming the through holes 110 and then forming the trenches 111 .
  • the trenches 111 may be formed first and then the through holes 110 may be formed, as follows:
  • forming a second dielectric layer 104 on the first dielectric layer 100 includes: forming a first dielectric layer 105 , a barrier layer 106 and a second dielectric layer 107 by stacking them in sequence; and etching the second dielectric layer 107 until exposed
  • the barrier layer 106 forms the trench 111 .
  • the barrier layer 106 and the first dielectric layer 105 in the bottom part of the trench 111 are etched until the first conductive plug 101 is exposed, and the through hole 110 and the trench 111 are formed.
  • a second conductive plug 102 filling the through hole 110 is formed, and the second conductive plug 102 is electrically connected to at least two first conductive plugs 101 ; a top metal layer 103 filling the trench 111 is formed, the top layer is The metal layer 103 is electrically connected to the second conductive plug 102 .
  • the use of the double damascene process ensures that the overetching precision of the fuse structure is high while the fuse structure is formed; because the second conductive plug 102 is electrically connected to at least two first conductive plugs 101 Compared with the solution in which the second conductive plugs 102 are respectively connected to the corresponding first conductive plugs 101, there is no need to provide a dielectric between the second conductive plugs 102, which simplifies the fuse structure, thereby reducing the difficulty of the process, thereby reducing the The production cost improves the output efficiency of the product; in addition, it can also solve the problems of excessive energy consumption and incomplete fuse structure fusing when the fuse structure is blown, ensuring accurate control of the process parameters of the integrated circuit under the condition of low energy consumption .
  • the method further includes: forming a protective layer 108 on the surface of the top metal layer 103 .
  • a protective layer 108 on the surface of the top metal layer 103 .
  • the first embodiment of the present application provides a fuse structure and a method for forming the fuse.
  • the second conductive plug 102 is electrically connected to at least two first conductive plugs 101 , and different second conductive plugs 102 are respectively connected to corresponding first conductive plugs 102 .
  • a dielectric between the second conductive plugs 102 which simplifies the fuse structure, thereby reducing the difficulty of the process, thereby reducing the production cost and improving the output efficiency of the product; in addition It can also solve the problems of excessive energy consumption and incomplete fusing of the fuse structure when the fuse structure is blown, ensuring accurate control of the process parameters of the integrated circuit under the condition of low energy consumption.
  • the second embodiment of the present application further provides a fuse structure and a method for forming the same, which are substantially the same as the foregoing embodiments, with the main difference being that an underlying metal layer 212 is further included.
  • FIG. 9 is a schematic cross-sectional structure diagram of a fuse structure provided by a second embodiment of the present application.
  • the fuse structure includes: a first dielectric layer 200 , a first conductive plug 201 , a second conductive plug 202 , a top metal layer 203 and a second dielectric layer 204 . It also includes: a bottom metal layer 212, the bottom metal layer 212 is located between the first conductive plug 201 and the second conductive plug 202, and the bottom metal layer 212 is electrically connected to the first conductive plug 201 and the second conductive plug 202 respectively connect.
  • the second conductive plugs 202 are electrically connected to at least two first conductive plugs 201 , it is different from the solution of using different second conductive plugs 202 to connect the corresponding first conductive plugs 201 respectively. In contrast, there is no need to provide a dielectric between the second conductive plugs 202.
  • the process steps are simplified, the process difficulty is reduced, the output efficiency of the product is improved, and the fuse structure is more blown. Completely, the process parameters of the integrated circuit can be accurately controlled.
  • the second dielectric layer 204 includes: a first dielectric layer 205 , a barrier layer 206 and a second dielectric layer 207 which are stacked in sequence; the barrier layer 206 is located on a part of the top surface of the underlying metal layer 212 .
  • the material of the first dielectric layer 205 is the same as the material of the second dielectric layer 207 , and may specifically be silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.
  • the material of the barrier layer 206 is different from the material of the first dielectric layer 205 and the material of the second dielectric layer 207 , and may be, for example, silicon nitride.
  • the function of the barrier layer 206 includes: playing an etching stop function in the process steps of fabricating the fuse structure, so as to reduce the difficulty of the etching process.
  • the bottom metal layer 212 , the second conductive plug 202 and the top metal layer 203 are made of the same material, which may be copper or tungsten. In this way, the second conductive plug 202 and the top metal layer 203 can be formed by one deposition, which makes the whole process simpler.
  • the width of the second conductive plug 202 is smaller than the width of the underlying metal layer 212 in a direction parallel to the arrangement direction of the discrete first conductive plugs 201 .
  • the fuse structure provided by this embodiment simplifies the fuse structure, thereby reducing the difficulty of the process, thereby reducing the production cost and improving the output efficiency of the product; in addition, it can also solve the problem of excessive energy consumption and excessive energy consumption when the fuse structure is blown.
  • the problem of incomplete fusing of the fuse structure ensures accurate control of the process parameters of the integrated circuit under the condition of low energy consumption.
  • FIG. 10 to 12 are schematic structural diagrams corresponding to each step in a method for forming a fuse structure provided by the second embodiment of the present application
  • FIG. 13 is another method for forming a fuse structure provided by the second embodiment of the present application.
  • a first dielectric layer 200, a first conductive plug 201, and a second dielectric layer 204 are provided.
  • the formed second dielectric layer 204 includes: a first dielectric layer 205 , a barrier layer 206 and a second dielectric layer 207 which are stacked in sequence.
  • the method further includes: forming an underlying metal layer 212 penetrating the first dielectric layer 205 , the underlying metal layer 212 is in contact with the at least two first conductive plugs 201 , and the through holes 210 are formed. The underlying metal layer 212 is exposed.
  • the second dielectric layer 207 is etched until the barrier layer 206 is exposed, and an initial through hole 209 is formed.
  • a partial thickness of the second dielectric layer 207 around the initial via hole 209 is removed by etching, and the barrier layer 206 at the bottom of the initial via hole 209 is etched to expose the underlying metal layer 212 to form trenches 211 and Through holes 210 .
  • the through holes 210 and the trenches 211 are formed in a manner of first forming the through holes 210 and then forming the trenches 211 .
  • the trenches 211 may be formed first and then the through holes 210 may be formed, as follows:
  • a partial thickness of the second dielectric layer 207 is etched to form trenches 211 .
  • the second dielectric layer 207 at the bottom portion of the trench 211 is etched, and the barrier layer 206 is etched until the underlying metal layer 212 is exposed to form the trench 211 and the through hole 210.
  • the via holes 210 and the trenches 211 are formed, the via holes 210 are filled to form the second conductive plugs 202 , and the trenches 211 are filled to form the top metal layer 203 .
  • the use of the double damascene process ensures that the overetching precision of the fuse structure is high while the fuse structure is formed; Compared with the solution in which the second conductive plugs 202 are respectively connected to the corresponding first conductive plugs 201, there is no need to provide a dielectric between the second conductive plugs 202.
  • the process steps are simplified and the reduction of The process difficulty is reduced, the output efficiency of the product is improved, and the fuse structure is more completely blown, and the process parameters of the integrated circuit can be accurately controlled.
  • the method further includes: forming a protective layer 208 on the surface of the top metal layer 203 .
  • a protective layer 208 on the surface of the top metal layer 203 .
  • the second embodiment of the present application provides a fuse structure and a method for forming the fuse. Since the second conductive plug 202 is electrically connected to at least two first conductive plugs 201, it is different from using different second conductive plugs 202 to connect the corresponding first conductive plugs 202 respectively. Compared with the solution of one conductive plug 201, there is no need to provide a dielectric between the second conductive plugs 202. In the process of forming the fuse structure, the process steps are simplified, the process difficulty is reduced, and the output efficiency of the product is improved. At the same time, the fuse structure is more completely blown, and the process parameters of the integrated circuit can be accurately controlled.

Abstract

本申请公开了一种熔丝结构及形成方法，其中，熔丝结构包括：第一电介质层，以及贯穿所述第一电介质层的至少两个分立的第一导电插塞；第二导电插塞，所述第二导电插塞电连接至少两个所述第一导电插塞；顶层金属层，所述顶层金属层电连接所述第二导电插塞，且位于所述第二导电插塞远离所述第一导电插塞的一侧；第二电介质层，所述第二电介质层位于所述第一电介质层顶部，且所述第二导电插塞以及所述顶层金属层位于所述第二电介质层内。本申请实施例简化了熔丝结构，提升了熔丝结构的产出效率。

Description

熔丝结构及形成方法
交叉引用
本申请基于申请号为202011086700.9、申请日为2020年10月12日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体制造领域，尤其涉及一种熔丝结构及形成方法。
背景技术
在半导体集成电路中通常会设置一熔丝，通过熔断熔丝进而可达到对集成电路的功能参数进行修调的目的。根据熔丝的熔断方法，可以把熔丝分为电熔丝和激光熔丝，其中，激光熔丝一般采用一定能量的激光束照射熔丝，进而使激光熔丝熔断。
现有技术中的熔丝结构复杂，导致工艺难度较大，影响了产品的产出效率，并且熔丝熔断时耗费能量过大。
发明内容
本申请实施例提供一种熔丝结构及形成方法，简化了熔丝结构，进而降低了工艺难度，从而降低了生产成本，提升了产品的产出效率，并且有利于解决熔丝结构熔断时耗费能量过多的问题。
为了解决上述问题，本申请实施例提供一种熔丝结构及形成方法，包括：第一电介质层，以及贯穿所述第一电介质层的至少两个分立的第一导电插塞；第二导电插塞，所述第二导电插塞电连接至少两个所述第一导电插塞；顶层金属层，所述顶层金属层电连接所述第二导电插塞，且位于所述第二导电插塞远离所述第一导电插塞的一侧；第二电介质层，所述第二电介质层位于所述第一电介质层顶部，且包裹所述第二导电插塞以及所述顶层金属层。
本申请实施例还提供一种熔丝结构的形成方法，包括：提供第一电介质层，所述第一电介质层内形成有贯穿所述第一电介质层的至少两个分立的第一导电插塞；在所述第一电介质层上形成第二电介质层；刻蚀所述第二电介质层，形成相连通的通孔以及沟槽，所述通孔位于所述沟槽与所述第一导电插塞之间，且所述通孔的宽度小于所述沟槽的宽度；形成填充所述通孔的第二导电插塞，所述第二导电插塞电连接至少两个所述第一导电插塞；形成填充所述沟槽的顶层金属层，所述顶层金属层电连接所述第二导电插塞。
与现有技术相比，本申请实施例提供的技术方案具有以下优点：
本申请实施例提供的熔丝结构中，第二导电插塞电连接至少两个第一导电插塞，顶层金属层电连接第二导电插塞。本申请实施例的熔丝结构，由于第二导电插塞电连接至少两个第一导电插塞，与采用不同的第二导电插塞分别连接相应的第一导电插塞的方案相比，无需设置位于第二导电插塞之间的电介质，简化了熔丝结构，进而降低了工艺难度，从而降低了生产成本，提升了产品的产出效率；另外，还能 够解决熔丝结构熔断时耗费能量过多和熔丝结构熔断不完全的问题，保证了在低能耗的情况下准确控制集成电路的工艺参数。
熔丝结构还包括位于第一导电插塞和第二导电插塞之间的底层金属层，底层金属层分别与第一导电插塞和第二导电插塞电连接，由于第二导电插塞电连接至少两个第一导电插塞，与采用不同的第二导电插塞分别连接相应的第一导电插塞的方案相比，无需设置位于第二导电插塞之间的电介质，在形成熔丝结构的过程中，简化了工艺步骤，降低了工艺难度，提升了产品的产出效率，同时使得熔丝结构熔断更完全，可以准确控制集成电路的工艺参数。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为一种熔丝结构的剖面结构示意图；
图2为本申请第一实施例提供的熔丝结构的剖面结构示意图；
图3～图5为本申请第一实施例提供的熔丝结构的一种形成方法中各步骤对应的结构示意图；
图6～图8为本申请第一实施例提供的熔丝结构的另一种形成方法中各步骤对应的结构示意图；
图9为本申请第二实施例提供的熔丝结构的剖面示意图；
图10～图12为本申请第二实施例提供的熔丝结构的一种形成方法中各步骤对应的结构示意图；
图13为本申请第二实施例提供的熔丝结构的另一种形成方法中一步骤对应的结构示意图。
具体实施方式
下面结合附图对本申请提供的一种熔丝结构及形成方法的具体实施方式做详细说明。
由背景技术可知，现有技术的熔丝结构有待简化。
参考图1，一种熔丝结构包括：第一电介质层100、第一导电插塞101、第二电介质层104、底层金属层112、第二导电插塞102和顶层金属层103。
第二导电插塞102由多个分立的结构组成，在多个分立的结构之间存在电介质，并且在第一导电插塞101和第二导电插塞102之间有底层金属层112，导致熔丝结构复杂，工艺难度较大，生产成本高，而且由于第二导电插塞102之间存在电介质，所以熔丝结构熔断时耗费能量比较多，同时电介质的存在，会导致熔丝结构在熔断的过程中熔断不完全，造成集成电路工艺参数难以控制的问题。
为解决上述问题，本申请实施提供一种熔丝结构及形成方法，简化了熔丝结构，进而降低了工艺难度，从而降低了生产成本，提升了产品的产出效率，并且有利于解决熔丝结构熔断时耗费能量过多和熔丝结构熔断不完全的问题。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图2为本申请第一实施例提供的熔丝结构的剖面结构示意图。
参考图2，本实施例中，熔丝结构包括：第一电介质层100，以及贯穿第一电介质层100的至少两个分立的第一导电插塞101；第二导电插塞102，第二导电插塞102电连接至少两个第一导电插塞101；顶层金属层103，顶层金属层103电连接第二导电插塞102，且位于第二导电插塞102远离第一导电插塞101的一侧；第二电介质层104，第二电介质层104位于第一电介质层100顶部，且包裹第二导电插塞102以及顶层金属层103。
本实施例的熔丝结构，由于第二导电插塞102电连接至少两个第一导电插塞101，与采用不同的第二导电插塞102分别连接相应的第一导电插塞101的方案相比，无需设置位于第二导电插塞102之间的电介质，简化了熔丝结构，进而降低了工艺难度，从而降低了生产成本，提升了产品的产出效率；另外，还能够解决熔丝结构熔断时耗费能量过多和熔丝结构熔断不完全的问题，保证了在低能耗的情况下准确控制集成电路的工艺参数。
以下将结合附图对本实施例提供的熔丝结构进行详细说明。
本实施例中，第一电介质层100的材料为氧化硅，第一导电插塞101的材料包括钨金属。在其他实施例中，第一电介质层100的材料也可以为其他绝缘材料例如氮化硅或者氮氧化硅等，第一导电插塞101的材料也可以为其他导电材料例如为多晶硅或者铜等。
此外，还需要说明的是，本实施例中，以第一电介质层100为单层结构作为示例。在其他实施例中，第一电介质层100也可以为叠层结构。
本实施例中，第二导电插塞102的材料与顶层金属层103的材料相同，具体可以为铜或者钨。如此，可以一次沉积形成第二导电插塞102和顶层金属层103，使整个制程工艺更简单。
需要说明的是，在其他实施例中，第二导电插塞102的材料与顶层金属层103的材料也可以不同。
本实施例中，第二导电插塞102的底面与至少两个第一导电插塞101的顶面相接触。如此，在一个熔丝结构中，不同的第一导电插塞101接触同一个第二导电插塞102，第二导电插塞102为一个整体，中间不夹杂电介质，单个熔丝结构简单，降低了工艺难度；并且电介质熔点较高，单个熔丝结构中没有电介质，有利于减少熔丝结构熔断时耗费的能量，有利于降低熔断熔丝结构的难度。
第二电介质层104包裹第二导电插塞102以及顶层金属层103，可以为第二导电插塞102以及顶层金属层103位于第二电介质层104内。
第二电介质层104可以包括：依次堆叠设置的第一介质层105、 阻障层106以及第二介质层107；第二导电插塞102至少贯穿第一介质层105以及阻障层106。
第一介质层105的材料和第二介质层107的材料相同，具体可以为氧化硅、氮化硅、氮氧化硅或者碳氮氧化硅等。阻障层106的材料与第一介质层105的材料以及第二介质层107的材料不同，例如可以为氮化硅。阻障层106的作用包括：在制作熔丝结构的工艺步骤中起到刻蚀停止作用，降低刻蚀工艺难度。
本实施例中，位于第一电介质层100与第二介质层107之间的第二导电插塞102具有第一厚度，顶层金属层103具有第二厚度，且第一厚度与第二厚度可以相等。可以理解的是，有关第一厚度与第二厚度的关系，与熔丝结构的制作工艺有关，即第二导电插塞102与顶层金属层103利用双大马士革工艺制作，且双大马士革工艺包括先通孔(via first trench last)方法以及后通孔方法(via last trench first)。
需要说明的是，在其他实施例中，第二电介质层104也可以为单层结构。
本实施例中，熔丝结构还可以包括：保护层108，保护层108位于顶层金属层103远离第二导电插塞102的一侧。保护层108可以对顶层金属层103提供保护作用，例如保护顶层金属层103不被后续的工艺所刻蚀破坏。保护层108可以为单层结构，也可以为多种材质的多层结构，例如保护层108为氮化硅材质的单层结构，或者保护层108为表面为氮化硅材质的多层结构。
本实施例提供的熔丝结构，简化了熔丝结构，进而降低了工艺难度，从而降低了生产成本，提升了产品的产出效率；另外，还能够解决熔丝结构熔断时耗费能量过多和熔丝结构熔断不完全的问题，保证了在低能耗的情况下准确控制集成电路的工艺参数。
下面，将结合附图说明本实施例的熔丝结构的形成方法。图3～图5为本申请第一实施例提供的熔丝结构的一种形成方法中各步骤对应的结构示意图；图6～图8为本申请第一实施例提供的熔丝结构的另一种形成方法中各步骤对应的结构示意图。
参考图3，提供第一电介质层100，第一电介质层100内形成有贯穿第一电介质层100的至少两个分立的第一导电插塞101。
继续参考图3，在第一电介质层100上形成第二电介质层104。
在第一电介质层100上形成第二电介质层104包括：依次堆叠设置形成第一介质层105、阻障层106以及第二介质层107。
后续的工艺步骤：刻蚀第二电介质层104，形成相连通的通孔110以及沟槽111，通孔110位于沟槽111与第一导电插塞101之间，且通孔110的宽度小于沟槽111的宽度。以下将以先形成通孔110后形成沟槽111的方式形成通孔110以及沟槽111作为示例进行说明。
参考图4，刻蚀第二介质层107直至露出阻障层106，形成初始通孔109。
参考图5，刻蚀去除位于初始通孔109周围的部分厚度的第二介质层107，且刻蚀初始通孔109露出的阻障层106以及第一介质层105，直至露出第一导电插塞101，形成通孔110以及沟槽111。
需要说明的是，本实施例中，以先形成通孔110后形成沟槽111的方式形成通孔110以及沟槽111。在其他实施例中，如图6及图7所示，也可以先形成沟槽111后形成通孔110，具体如下：
参考图6，在第一电介质层100上形成第二电介质层104，包括：依次堆叠设置形成第一介质层105、阻障层106以及第二介质层107；刻蚀第二介质层107直至露出阻障层106，形成沟槽111。
参考图7，刻蚀沟槽111底部部分区域的阻障层106以及第一介质层105，直至露出第一导电插塞101，形成通孔110以及沟槽111。
参考图2或图8，形成填充通孔110的第二导电插塞102，第二导电插塞102电连接至少两个第一导电插塞101；形成填充沟槽111的顶层金属层103，顶层金属层103电连接第二导电插塞102。
如此，采用双大马士革工艺，在形成熔丝结构的同时，保证了熔丝结构的套刻精度较高；由于第二导电插塞102电连接至少两个第一导电插塞101，与采用不同的第二导电插塞102分别连接相应的第一导电插塞101的方案相比，无需设置位于第二导电插塞102之间的电介质，简化了熔丝结构，进而降低了工艺难度，从而降低了生产成本，提升了产品的产出效率；另外，还能够解决熔丝结构熔断时耗费能量过多和熔丝结构熔断不完全的问题，保证了在低能耗的情况下准确控制集成电路的工艺参数。
继续参考图2或图8，在形成顶层金属层103之后，还包括：在顶层金属层103表面形成保护层108。如此，可以保护熔丝结构形成后不被后续的工艺所刻蚀破坏。
本申请第一实施例提供一种熔丝结构及形成方法，第二导电插塞102电连接至少两个第一导电插塞101，与采用不同的第二导电插塞102分别连接相应的第一导电插塞101的方案相比，无需设置位于第二导电插塞102之间的电介质，简化了熔丝结构，进而降低了工艺难度，从而降低了生产成本，提升了产品的产出效率；另外，还能够解决熔丝结构熔断时耗费能量过多和熔丝结构熔断不完全的问题，保证了在低能耗的情况下准确控制集成电路的工艺参数。
本申请第二实施例还提供一种熔丝结构及其形成方法，与前述实施例大致相同，主要区别在于还包括底层金属层212。
以下将结合附图对本申请第二实施例提供的一种熔丝结构及形成方法进行详细说明，与前一实施例相同或者相应部分，可参考前述实施例的说明，以下将不做赘述。
图9为本申请第二实施例提供的熔丝结构的剖面结构示意图。
参考图9，本实施例中，熔丝结构包括：第一电介质层200、第一导电插塞201、第二导电插塞202、顶层金属层203以及第二电介质层204。还包括：底层金属层212，底层金属层212位于第一导电插塞201和第二导电插塞202之间，且底层金属层212分别与第一导电插塞201和第二导电插塞202电连接。
本实施例的熔丝结构，由于第二导电插塞202电连接至少两个第一导电插塞201，与采用不同的第二导电插塞202分别连接相应的第一导电插塞201的方案相比，无需设置位于第二导电插塞202之间的电介质，在形成熔丝结构的过程中，简化了工艺步骤，降低了工艺难 度，提升了产品的产出效率，同时使得熔丝结构熔断更完全，可以准确控制集成电路的工艺参数。
以下将结合附图对本实施例提供的熔丝结构进行详细说明。
第二电介质层204包括：依次堆叠设置的第一介质层205、阻障层206以及第二介质层207；阻障层206位于底层金属层212的部分顶部表面。第一介质层205的材料和第二介质层207的材料相同，具体可以为氧化硅、氮化硅、氮氧化硅或者碳氮氧化硅等。阻障层206的材料与第一介质层205的材料以及第二介质层207的材料不同，例如可以为氮化硅。阻障层206的作用包括：在制作熔丝结构的工艺步骤中起到刻蚀停止作用，降低刻蚀工艺难度。
本实施例中，底部金属层212、第二导电插塞202和顶层金属层203的材料相同，具体可以为铜或者钨。如此，可以一次沉积形成第二导电插塞202和顶层金属层203，使整个制程工艺更简单。
在平行于分立的第一导电插塞201的排列方向上，第二导电插塞202的宽度小于底层金属层212的宽度。
本实施例提供的熔丝结构，简化了熔丝结构，进而降低了工艺难度，从而降低了生产成本，提升了产品的产出效率；另外，还能够解决熔丝结构熔断时耗费能量过多和熔丝结构熔断不完全的问题，保证了在低能耗的情况下准确控制集成电路的工艺参数。
下面，将结合附图说明本实施例的熔丝结构的形成方法。图10～图12为本申请第二实施例提供的熔丝结构的一种形成方法中各步骤对应的结构示意图；图13为本申请第二实施例提供的熔丝结构的另 一种形成方法中一步骤对应的结构示意图。
参考图10，提供第一电介质层200、第一导电插塞201、第二电介质层204。
形成的第二电介质层204包括：依次堆叠设置的第一介质层205、阻障层206以及第二介质层207。
继续参考图10，在形成阻障层206之前，还包括：形成贯穿第一介质层205的底层金属层212，底层金属层212与至少两个第一导电插塞201相接触，且通孔210暴露出底层金属层212。
后续的工艺步骤：刻蚀第二电介质层204，形成相连通的通孔210以及沟槽211，通孔210位于沟槽211与第一导电插塞201之间，且通孔210的宽度小于沟槽211的宽度。以下将以先形成通孔210后形成沟槽211的方式形成通孔210以及沟槽211作为示例进行说明。
参考图11，刻蚀第二介质层207直至露出阻障层206，形成初始通孔209。
参考图12，刻蚀去除位于初始通孔209周围的部分厚度的第二介质层207，且刻蚀初始通孔209底部的阻障层206，以暴露出底层金属层212，形成沟槽211以及通孔210。
需要说明的是，本实施例中，以先形成通孔210后形成沟槽211的方式形成通孔210以及沟槽211。在其他实施例中，如图12及图13所示，也可以先形成沟槽211后形成通孔210，具体如下：
参考图13，刻蚀部分厚度的第二介质层207，形成沟槽211。
参考图12，刻蚀沟槽211底部部分区域的第二介质层207，且刻 蚀阻障层206，直至露出底层金属层212，以形成沟槽211以及通孔210。
参考图9，在形成通孔210和沟槽211之后，填充通孔210形成第二导电插塞202，填充沟槽211形成顶层金属层203。
如此，采用双大马士革工艺，在形成熔丝结构的同时，保证了熔丝结构的套刻精度较高；由于第二导电插塞202电连接至少两个第一导电插塞201，与采用不同的第二导电插塞202分别连接相应的第一导电插塞201的方案相比，无需设置位于第二导电插塞202之间的电介质，在形成熔丝结构的过程中，简化了工艺步骤，降低了工艺难度，提升了产品的产出效率，同时使得熔丝结构熔断更完全，可以准确控制集成电路的工艺参数。
继续参考图9，在形成顶层金属层203之后，还包括：在顶层金属层203表面形成保护层208。如此，可以保护熔丝结构形成后不被后续的工艺所刻蚀破坏。
本申请第二实施例提供一种熔丝结构及形成方法，由于第二导电插塞202电连接至少两个第一导电插塞201，与采用不同的第二导电插塞202分别连接相应的第一导电插塞201的方案相比，无需设置位于第二导电插塞202之间的电介质，在形成熔丝结构的过程中，简化了工艺步骤，降低了工艺难度，提升了产品的产出效率，同时使得熔丝结构熔断更完全，可以准确控制集成电路的工艺参数。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种 改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (14)

  1. 一种熔丝结构，其中，包括：
    第一电介质层，以及贯穿所述第一电介质层的至少两个分立的第一导电插塞；
    第二导电插塞，所述第二导电插塞电连接至少两个所述第一导电插塞；
    顶层金属层，所述顶层金属层电连接所述第二导电插塞，且位于所述第二导电插塞远离所述第一导电插塞的一侧；
    第二电介质层，所述第二电介质层位于所述第一电介质层顶部，且包裹所述第二导电插塞以及所述顶层金属层。
  2. 根据权利要求1所述的熔丝结构，其中，所述第二导电插塞的底面与至少两个所述第一导电插塞的顶面相接触。
  3. 根据权利要求2所述的熔丝结构，其中，所述第二电介质层包括：依次堆叠设置的第一介质层、阻障层以及第二介质层；
    所述第二导电插塞至少贯穿所述第一介质层以及所述阻障层。
  4. 根据权利要求1所述的熔丝结构，其中，还包括：
    底层金属层，所述底层金属层位于所述第一导电插塞和所述第二导电插塞之间，且所述底层金属层分别与所述第一导电插塞和所述第二导电插塞电连接。
  5. 根据权利要求4所述的熔丝结构，其中，所述第二电介质层包括：
    依次堆叠设置的第一介质层、阻障层以及第二介质层；
    所述阻障层位于所述底层金属层的部分顶部表面。
  6. 根据权利要求4所述的熔丝结构，其中，在平行于分立的所述第一导电插塞的排列方向上，所述第二导电插塞的宽度小于所述底层金属层的宽度。
  7. 根据权利要求1所述的熔丝结构，其中，还包括：
    保护层，所述保护层位于所述顶层金属层远离所述第二导电插塞的一侧。
  8. 一种熔丝结构的形成方法，其中，包括：
    提供第一电介质层，所述第一电介质层内形成有贯穿所述第一电介质层的至少两个分立的第一导电插塞；
    在所述第一电介质层上形成第二电介质层；
    刻蚀所述第二电介质层，形成相连通的通孔以及沟槽，所述通孔位于所述沟槽与所述第一导电插塞之间，且所述通孔的宽度小于所述沟槽的宽度；
    形成填充所述通孔的第二导电插塞，所述第二导电插塞电连接至少两个所述第一导电插塞；
    形成填充所述沟槽的顶层金属层，所述顶层金属层电连接所述第二导电插塞。
  9. 根据权利要求8所述的熔丝结构的形成方法，其中，所述第二电介质层包括：
    依次堆叠设置的第一介质层、阻障层以及第二介质层；
    在形成所述阻障层之前，还包括：形成贯穿所述第一介质层的底 层金属层，所述底层金属层与至少两个所述第一导电插塞相接触，且所述通孔暴露出所述底层金属层。
  10. 根据权利要求9所述的熔丝结构的形成方法，其中，形成所述通孔以及所述沟槽的工艺步骤包括：
    刻蚀所述第二介质层直至露出所述阻障层，形成初始通孔；
    刻蚀去除位于所述初始通孔周围的部分厚度的所述第二介质层，且刻蚀所述初始通孔底部的所述阻障层，以暴露出所述底层金属层，形成所述沟槽以及所述通孔。
  11. 根据权利要求9所述的熔丝结构的形成方法，其中，形成所述通孔以及所述沟槽的工艺步骤包括：
    刻蚀部分厚度的所述第二介质层，形成所述沟槽；
    刻蚀所述沟槽底部部分区域的所述第二介质层，且刻蚀所述阻障层，直至露出所述底层金属层，以形成所述沟槽以及所述通孔。
  12. 根据权利要求8所述的熔丝结构的形成方法，其中，在所述第一电介质层上形成第二电介质层，包括：
    依次堆叠设置形成第一介质层、阻障层以及第二介质层；
    形成所述通孔以及所述沟槽的工艺步骤包括：刻蚀所述第二介质层直至露出所述阻障层，形成初始通孔；
    刻蚀去除位于所述初始通孔周围的部分厚度的所述第二介质层，且刻蚀所述初始通孔露出的所述阻障层以及所述第一介质层，直至露出所述第一导电插塞，形成所述通孔以及所述沟槽。
  13. 根据权利要求8所述的熔丝结构的形成方法，其中，在所述 第一电介质层上形成第二电介质层，包括：
    依次堆叠设置形成第一介质层、阻障层以及第二介质层；
    形成所述通孔以及所述沟槽的工艺步骤包括：刻蚀所述第二介质层直至露出所述阻障层，形成所述沟槽；
    刻蚀所述沟槽底部部分区域的所述阻障层以及第一介质层，直至露出所述第一导电插塞，形成所述通孔以及所述沟槽。
  14. 根据权利要求8所述的熔丝结构的形成方法，其中，在形成所述顶层金属层之后，还包括：在所述顶层金属层表面形成保护层。
PCT/CN2021/104792 2020-10-12 2021-07-06 熔丝结构及形成方法 WO2022077963A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW384535B (en) * 1998-06-16 2000-03-11 Taiwan Semiconductor Mfg Method of forming fuse in IC
CN1499628A (zh) * 2002-11-07 2004-05-26 ���ǵ�����ʽ���� 具有包括缓冲层的熔丝结构的集成电路器件及其制造方法
CN101000906A (zh) * 2006-01-12 2007-07-18 三星电子株式会社 熔丝区及其制作方法
US20080070398A1 (en) * 2006-09-19 2008-03-20 Hynix Semiconductor Inc. Method For Fabricating Semiconductor Device Having Metal Fuse
CN102157491A (zh) * 2011-03-10 2011-08-17 上海宏力半导体制造有限公司 半导体结构及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW384535B (en) * 1998-06-16 2000-03-11 Taiwan Semiconductor Mfg Method of forming fuse in IC
CN1499628A (zh) * 2002-11-07 2004-05-26 ���ǵ�����ʽ���� 具有包括缓冲层的熔丝结构的集成电路器件及其制造方法
CN101000906A (zh) * 2006-01-12 2007-07-18 三星电子株式会社 熔丝区及其制作方法
US20080070398A1 (en) * 2006-09-19 2008-03-20 Hynix Semiconductor Inc. Method For Fabricating Semiconductor Device Having Metal Fuse
CN102157491A (zh) * 2011-03-10 2011-08-17 上海宏力半导体制造有限公司 半导体结构及其制备方法

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