WO2022062545A1 - 电容器阵列结构及其制造方法与半导体存储器件 - Google Patents

电容器阵列结构及其制造方法与半导体存储器件 Download PDF

Info

Publication number
WO2022062545A1
WO2022062545A1 PCT/CN2021/103744 CN2021103744W WO2022062545A1 WO 2022062545 A1 WO2022062545 A1 WO 2022062545A1 CN 2021103744 W CN2021103744 W CN 2021103744W WO 2022062545 A1 WO2022062545 A1 WO 2022062545A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
upper electrode
germanium
capacitor
filling
Prior art date
Application number
PCT/CN2021/103744
Other languages
English (en)
French (fr)
Inventor
李秀升
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21870924.4A priority Critical patent/EP4199086A4/en
Priority to US17/599,464 priority patent/US11411071B1/en
Publication of WO2022062545A1 publication Critical patent/WO2022062545A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a capacitor array structure, a capacitor array structure, and a semiconductor memory device.
  • DRAM Dynamic Random Access Memory
  • DRAM is a semiconductor memory device commonly used in computers, consisting of many repeated memory cells. In the DRAM process below 20 nm, DRAM mostly adopts a stacked capacitor structure, and its capacitor (Capacitor) is a column shape with a high aspect ratio.
  • the filling material in the gap will be sealed in advance, resulting in the formation of slits in the capacitor structure, resulting in leakage current of the device. increase, resulting in increased device power consumption and even device failure.
  • the purpose of the embodiments of the present disclosure is to provide a manufacturing method of a capacitor array structure, a capacitor array structure and a semiconductor memory device, which can reduce the slits in the conductive layer of the upper electrode.
  • a method for manufacturing a capacitor array structure includes:
  • Forming a capacitor structure on the substrate includes forming a lower electrode layer on the substrate, forming a capacitor dielectric layer on the surface of the lower electrode layer, and forming an upper electrode layer on the surface of the capacitor dielectric layer, wherein the There is a gap between the upper electrode layers;
  • the cover layer and the filled layer are combined to form an upper electrode conductive layer;
  • the materials of the filling layer and the cover layer include doped polysilicon, and the doped germanium atomic volume concentration in the cover layer is greater than the The atomic volume concentration of germanium doped in the filling layer.
  • FIG. 1 is a flowchart of a method for manufacturing a capacitor array structure provided by an embodiment of the present disclosure
  • FIGS. 2-4 are diagrams of manufacturing processes of a capacitor array structure according to an embodiment of the present disclosure.
  • FIG. 5-FIG. 6 is a manufacturing process diagram of a capacitor array structure provided by another embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a reaction chamber provided by an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • Embodiments of the present disclosure first provide a method for manufacturing a capacitor array structure. As shown in FIG. 1 , the method for manufacturing a capacitor array structure includes:
  • Step S100 providing a substrate
  • Step S200 forming a capacitor structure on the substrate, including forming a lower electrode layer on the substrate, and forming a capacitor dielectric layer on the surface of the lower electrode layer, and forming an upper electrode layer on the surface of the capacitor dielectric layer, wherein there is a gap between the upper electrode layers ;
  • Step S300 forming a filling layer to fill the gap
  • Step S400 forming a covering layer to cover the filling layer and the upper electrode; wherein, the covering layer and the filled layer are combined to form an upper electrode conductive layer; the materials of the filling layer and the covering layer include doped polysilicon, and the doped germanium atoms in the covering layer The volume concentration is greater than the atomic volume concentration of germanium doped in the filling layer.
  • a top electrode conductive layer is formed by combining a filling layer with a capping layer, and the volume concentration of germanium atoms in the capping layer is greater than that in the filling layer, so that the germanium atoms in the filling layer are The volume concentration is relatively small, so that the particle size of the filling molecules is relatively reduced, so that the gap can be filled more densely; at the same time, the volume concentration of germanium atoms in the cover layer is large, which can balance the structural resistance and ensure the upper electrode. Properties of the conductive layer. By reducing the slits that appear when the upper electrode conductive layer fills the gap, the leakage current of the capacitor is reduced and the performance of the capacitor is improved.
  • step S100 a substrate is provided.
  • the substrate 10 includes a substrate 110 and an insulating layer 120 , and the insulating layer 120 is provided with a plurality of storage node contact plugs 130 arranged at intervals.
  • the substrate 110 may be a semiconductor substrate 110, and the material of the semiconductor substrate 110 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC), etc., which is not described in the present disclosure. limit.
  • the contact plug 130 is used to connect the lower electrode layer 210 of the capacitor to be formed later, and the data stored in the capacitor can be read or data can be written into the capacitor through the contact plug 130 .
  • the arrangement of the contact plugs 130 is the same as the arrangement of the capacitor holes formed subsequently.
  • the plurality of contact plugs 130 may be arranged in a hexagonal array.
  • the material of the contact plug 130 is metal, and the metal may be W (tungsten), Cu (copper), Ti (titanium), Ni (nickel), Al (aluminum) or metal silicide.
  • the contact plug 130 may be formed by depositing a conductive layer and then etching the conductive layer, or by an electroplating process.
  • the material of the insulating layer 120 can be silicon oxide, silicon nitride or other suitable materials, and the material of the insulating layer 120 can be a single-layer or multi-layer stack structure.
  • the formation process of the insulating layer 120 is: forming an insulating material layer on the semiconductor substrate 110 through a deposition process, and the insulating material layer covers the contact plug 130.
  • the deposition process may be chemical vapor deposition, plasma enhanced chemical vapor deposition Deposition or low pressure chemical vapor deposition; planarization removes the insulating material layer higher than the surface of the contact plug 130 to form the insulating layer 120, and the planarization may use a chemical mechanical polishing process.
  • step S200 forming a capacitor structure on the substrate includes forming a lower electrode layer on the substrate, forming a capacitor dielectric layer on the surface of the lower electrode layer, and forming an upper electrode layer on the surface of the capacitor dielectric layer, wherein, between the upper electrode layers with gaps.
  • the capacitor structure 20 is formed on the substrate, the capacitor structure forms the lower electrode layer 210 on the substrate 10 , and the capacitor dielectric layer 220 is formed on the surface of the lower electrode layer 210 , and the capacitor dielectric layer 220 is formed on the surface The upper electrode layer 230 .
  • the lower electrode layer 210 including a plurality of columnar electrodes is formed by adopting an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process.
  • the material for forming the lower electrode layer 210 includes one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, P-type polysilicon, or a material formed by two or more of the above materials.
  • the laminate may also include compounds formed by one or both of metal nitrides and metal silicides, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide), silicon nitride (Titanium Nitride) Titanium ( TiSixNy ) and so on.
  • metal nitrides and metal silicides such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide), silicon nitride (Titanium Nitride) Titanium ( TiSixNy ) and so on.
  • the materials of the lower electrode layer 210 and the contact plugs 130 are the same, so that the lower electrode composed of the lower electrode layer 210 and the contact plugs 130 has better electrical properties.
  • the capacitive dielectric layer 220 covering the lower electrode layer 210 can be formed by using an atomic layer deposition process, chemical vapor deposition process or physical vapor deposition process, and the capacitive dielectric layer 220 simultaneously covers the surface of the substrate 10 exposed from the plurality of columnar electrodes.
  • the capacitor dielectric layer 220 can directly cover the surface of the lower electrode layer 210; when other film layers are involved between the capacitor dielectric layer 220 and the lower electrode layer 210 , the dielectric layer is not in direct contact with the lower electrode layer 210 , but relatively covers the lower electrode layer 210 .
  • the capacitor dielectric layer 220 may be a single-layer or multi-layer stack structure, and the capacitor dielectric layer 220 may be selected from a stack structure composed of strontium titanate and titanium oxide (SrTiO 3 /TiO 2 ), aluminum oxide and hafnium oxide (AlO/TiO 2 )
  • the laminated structure composed of HfO), the laminated structure composed of zirconia and alumina (ZrO/AlO/ZrO), and the composite perovskite-type ferroelectric material (BST material, the iron electrode material of the composite perovskite structure are composed of One of the solid solution composed of BaTiO 3 and SrTiO 3 in a certain proportion); silicon oxide, silicon nitride, silicon oxynitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide) can also be used , PSG (phosphorus doped silica) or BPSG (boron phosphorus doped silic
  • the upper electrode layer 230 including a plurality of columnar electrodes is formed by adopting an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process.
  • the material for forming the upper electrode layer 230 includes one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, P-type polysilicon, or two or more of the above materials.
  • the laminate may also include compounds formed by one or both of metal nitrides and metal silicides, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide), silicon nitride (Titanium Nitride) Titanium ( TiSixNy ) and so on.
  • metal nitrides and metal silicides such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide), silicon nitride (Titanium Nitride) Titanium ( TiSixNy ) and so on.
  • the material of the upper electrode layer 230 is the same as the material of the lower electrode layer 210, so as to reduce the difficulty of the process and improve the efficiency of the process.
  • the gap has a large aspect ratio (20:1-100: 1), for example, the height can be 1000nm-2000nm, and the CD (critical dimension) is 30nm-60nm.
  • the conventional method while filling the gap of the upper electrode layer, there is a phenomenon of sealing in advance, resulting in the formation of a seam in the conductive layer of the upper electrode, resulting in an increase in the leakage current of the capacitor array structure.
  • step S300 a filling layer is formed to fill the gap.
  • a filling layer 310 filling the gap may be formed in the reaction chamber 90 through a chemical vapor deposition process.
  • the material of the filling layer 310 includes germanium-doped polysilicon doped with germanium atoms.
  • SiH 4 and GeH 4 gases can be injected through a nozzle. The SiH 4 and GeH 4 gases enter the reaction chamber 90 and the chemical reaction is as follows:
  • the SiH 4 and GeH 4 gases enter the reaction chamber 90 , and through chemical reactions, Si atoms and Ge atoms are formed and deposited in the gap to form the filling layer 310 of germanium-doped polysilicon.
  • the flow rate of the SiH 4 gas is 300 sccm-700 sccm
  • the flow rate of the GeH 4 gas is 850 sccm-1300 sccm .
  • the flow rate set at the above standard ml/min can ensure a good deposition effect of the deposition material and further reduce the slits in the filling layer 310 .
  • the gas flow rates of the SiH 4 gas and the GeH 4 gas can also be outside the above-mentioned limited range, which is not limited in the present disclosure.
  • the duration of feeding SiH 4 gas and GeH 4 gas in the reaction chamber 90 is 20min-50min, such as 20min, 30min, 40min, 50min, etc.
  • the deposition time can also be greater than 20min or less than 50min, the specific time It can be set according to the actual situation of filling the gap, which is not limited in the present disclosure.
  • the material of the filling layer 310 can be germanium-boron co-doped polysilicon, and SiH 4 , GeH 4 , and BCl 3 gas can be injected simultaneously through a nozzle, and the chemical reaction of the BCl 3 gas entering the reaction chamber 90 is as follows:
  • Gases of SiH 4 , GeH 4 , and BCl 3 enter the reaction chamber 90 to generate a filling layer 310 in which Si, B, and Ge atoms are deposited in the gap through chemical reaction, so as to fill the gap.
  • the flow rate of the BCl 3 gas introduced is 500 sccm-200 sccm.
  • the gas flow rate of BCl 3 can also be outside the above-mentioned limited range, which is not limited in the present disclosure.
  • the time for passing BCl gas into the reaction chamber 90 is 20min - 50min, such as 20min, 30min, 40min, 50min, etc.
  • the deposition time can also be greater than 20min or less than 50min, and the specific time can be based on the filling gap.
  • the actual situation is set, and this disclosure does not limit it.
  • the time of passing SiH 4 , GeH 4 , and BCl 3 gas can be the same, which improves the uniformity of the deposition of each atom in the germanium-boron co-doped polysilicon, thereby improving the conductivity of the upper electrode conductive layer.
  • the aspect ratio of the gap ranges from 20:1 to 100:1, the filling layer 310 completely fills the gap, and a certain thickness of filling is also formed on the surface of the upper electrode layer 230 facing away from the substrate 10 .
  • the side surface and the cover layer 320 , the atomic volume concentration of germanium in the cover layer 320 is greater than that in the filling layer 310 , and the conductive layer is better, so that the conductivity of the upper electrode conductive layer 30 can be improved.
  • the filling layer 310 may also partially fill the gap, which is not limited in the present disclosure.
  • the temperature of the chemical vapor deposition in the reaction chamber 90 is 300°C to 600°C, such as 300°C, 400°C, 500°C, 600°C, etc.
  • the temperature of the chemical vapor deposition in the reaction chamber 90 is It may also be less than 300°C or greater than 600°C, which is not limited in the present disclosure.
  • the pressure during the chemical vapor deposition in the reaction chamber 90 is 100mtorr-600mtorr, such as 100mtorr, 200mtorr, 300mtorr, 400mtorr, 500mtorr, 600mtorr, etc.
  • the pressure during the chemical vapor deposition in the reaction chamber 90 can also be Less than 100mtorr or more than 600mtorr, this disclosure does not limit.
  • the particle size of the filling material is relatively reduced, so that the gap can be filled more densely, and the size of the slit that occurs when the germanium-boron co-doped polysilicon is filled in the gap can be reduced, so that the The leakage current of the capacitor is reduced and the performance of the capacitor is improved.
  • a cover layer is formed to cover the filling layer and the upper electrode layer; wherein, the cover layer is combined with the filled layer to form an upper electrode conductive layer; the materials of the filling layer and the cover layer include doped polysilicon, and the dopant in the cover layer is The atomic volume concentration of germanium is greater than the atomic volume concentration of germanium doped in the filling layer.
  • a chemical vapor deposition process may be used in the reaction chamber 90 to form a cover layer 320 covering the filling layer 310 and the upper electrode layer 230 , and the cover layer 320 and the upper electrode layer 230 are formed.
  • the filling layer 310 can be formed through the same reaction chamber 90 to reduce the difficulty of the process and improve the efficiency of the process.
  • the material of the cover layer 320 includes germanium-doped polysilicon doped with germanium atoms, and SiH 4 and GeH 4 gases can be injected through a nozzle. The SiH 4 and GeH 4 gases enter the reaction chamber 90 and the chemical reaction is as follows:
  • SiH 4 and GeH 4 enter the reaction chamber 90 , and through chemical reaction, Si atoms and Ge atoms are formed and deposited on the filling layer and the upper electrode layer to form the cover layer 320 doped with germanium atoms.
  • the flow rate of the SiH 4 gas is 300 sccm-700 sccm
  • the flow rate of the GeH 4 gas is 1250 sccm-1800 sccm .
  • the atomic volume concentration of germanium can be ensured, and the formed cover layer 320 has good conductivity.
  • the gas flow rates of the SiH 4 gas and the GeH 4 gas can also be outside the above-mentioned limited range, which is not limited in the present disclosure.
  • the duration of introducing SiH 4 gas and GeH 4 gas into the reaction chamber 90 is 120min-180min, such as 120min, 130min, 140min, 150min, 160min, 170min, 180min, etc.
  • the deposition time can also be less than 120min or more than 180 minutes, the specific time can be set according to the actual thickness of the cover layer 320 and other conditions, which is not limited in the present disclosure.
  • the material of the cover layer 320 may be germanium-boron co-doped polysilicon, and SiH 4 , GeH 4 , and BCl 3 gas can be injected simultaneously through a nozzle, and the BCl 3 gas enters the reaction chamber 90 for chemical reaction as follows:
  • SiH 4 , GeH 4 , and BCl 3 gases enter the reaction chamber 90 , and through chemical reactions, Si, B, and Ge atoms are deposited on the filling layer and the upper electrode layer to form the cover layer 320 of germanium-boron co-doped polysilicon, so as to The filling layer 310 covers the upper electrode layer 230 .
  • the flow rate of the BCl 3 gas introduced is 500 sccm-200 sccm.
  • the gas flow rate of BCl 3 can also be outside the above-mentioned limited range, which is not limited in the present disclosure.
  • the time for passing BCl gas into the reaction chamber 90 is 120min - 180min, such as 120min, 130min, 140min, 150min, 160min, 170min, 180min, etc.
  • the deposition time can also be less than 120min or more than 180min, specifically The time may be set according to the actual thickness of the cover layer 320 and the like, which is not limited in the present disclosure.
  • the time of passing SiH 4 , GeH 4 , and BCl 3 gas can be the same, which improves the uniformity of the deposition of each atom in the germanium-boron co-doped polysilicon, thereby improving the conductivity of the upper electrode conductive layer.
  • the temperature of the chemical vapor deposition in the reaction chamber 90 is 300°C to 600°C, such as 300°C, 400°C, 500°C, 600°C, etc.
  • the temperature of the chemical vapor deposition in the reaction chamber 90 is It may also be less than 300°C or greater than 600°C, which is not limited in the present disclosure.
  • the pressure during the chemical vapor deposition in the reaction chamber 90 is 100mtorr-600mtorr, such as 100mtorr, 200mtorr, 300mtorr, 400mtorr, 500mtorr, 600mtorr, etc.
  • the pressure during the chemical vapor deposition in the reaction chamber 90 can also be Less than 100mtorr or more than 600mtorr, this disclosure does not limit.
  • the temperature and pressure in the reaction chamber 90 are the same when the cover layer 320 and the filled layer 310 are formed, so as to reduce the difficulty of the process and improve the efficiency of the process.
  • the temperature and pressure in the reaction chamber 90 may be the same or different when the covering layer 320 and the filled layer 310 are formed, which is not limited in the present disclosure.
  • the atomic volume concentration of germanium in the cover layer 320 is greater than 30%-50% of the atomic volume concentration of germanium in the filling layer 310 .
  • the resistance of the capping layer 320 is lower, and the capping layer 320 located outside the gap has good conductivity, thereby improving the overall
  • the conductivity of the electrode conductive layer 30 avoids the situation that the conductivity of the upper electrode conductive layer 30 is affected due to the low atomic volume concentration of germanium in the filling layer 310 .
  • the device embodiments of the present disclosure can be formed by manufacturing the above-mentioned method embodiments.
  • the undisclosed specific details of the present device embodiments please refer to the relevant discussion of the above-mentioned method embodiments.
  • Embodiments of the present disclosure also provide a capacitor array structure, as shown in FIGS. 2-6 , the capacitor array structure includes: a substrate 10 , a capacitor structure 20 and an upper electrode conductive layer 30 .
  • the capacitor structure 20 is disposed on the substrate 10 .
  • the capacitor structure 20 includes a lower electrode layer 210 , a capacitor dielectric layer 220 and an upper electrode layer 230 .
  • the capacitor dielectric layer 220 covers the surface of the lower electrode layer 210 and the upper electrode layer 230 covers the surface of the capacitor dielectric layer 220 .
  • the upper electrode conductive layer 30 includes a filling layer 310 and a covering layer 320, the filling layer 310 fills the gap, the covering layer 320 covers the filling layer 310 and the upper electrode layer 230, and the covering layer 320 and
  • the material of the filling layer 310 includes doped polysilicon, and the atomic volume concentration of germanium doped in the capping layer 320 is greater than the atomic volume concentration of germanium doped in the filling layer 310 .
  • the filling layer 310 is combined with the capping layer 320 to form the upper electrode conductive layer 30, and the atomic volume concentration of germanium in the capping layer 320 is greater than that in the filling layer 310, so that the atomic volume concentration of germanium in the filling layer 310
  • the volume concentration of germanium atoms is relatively small, so that the particle size of the filling molecules is relatively reduced, so that the gap can be filled more densely; at the same time, the volume concentration of germanium atoms in the cover layer 320 is relatively large, which can balance the structural resistance and ensure that The performance of the upper electrode conductive layer 30 is improved.
  • a filling layer 310 filling the gap may be formed in the reaction chamber 90 through a chemical vapor deposition process.
  • Fill layer 310 may be formed in the reaction chamber 90 through a chemical vapor deposition process.
  • the material of the filling layer 310 includes germanium-doped polysilicon doped with germanium atoms.
  • SiH 4 and GeH 4 gases can be injected through a nozzle.
  • the SiH 4 and GeH 4 gases enter the reaction chamber 90 and the chemical reaction is as follows:
  • the material of the filling layer 310 can be germanium-boron co-doped polysilicon, and SiH 4 , GeH 4 , and BCl 3 gas can be injected simultaneously through a nozzle, and the chemical reaction of the BCl 3 gas entering the reaction chamber 90 is as follows:
  • Gases of SiH 4 , GeH 4 , and BCl 3 enter the reaction chamber 90 to generate a filling layer 310 in which Si, B, and Ge atoms are deposited in the gap through chemical reaction, so as to fill the gap.
  • the flow rate of SiH 4 is 300sccm-700sccm
  • the flow rate of SiH 4 is 850sccm-1300sccm
  • the flow rate of SiH 4 is 500sccm -200sccm. Setting the SiH 4 , GeH 4 , and BCl 3 gases at the flow rate of the above standard ml/min can ensure a good deposition effect of the deposition material and further reduce the slits in the filling layer 310 .
  • the gas flow rates of SiH 4 , GeH 4 , and BCl 3 can also be outside the above-mentioned limited range, which is not limited in the present disclosure.
  • the atomic volume concentration of germanium in the filling layer 310 is 45%-80%, such as 45%, 50%, 55%, 65%, 70%, 75%, 80%, and the like.
  • the filling layer 310 completely fills the gap, and a certain thickness of the filling layer 310 is also formed on the surface of the upper electrode layer 230 away from the substrate 10 ; as shown in FIG. 5 , the filling layer 310 is only The gap is completely filled, and the material of the filling layer 310 is not formed on the surface of the upper electrode layer 230 away from the substrate 10 to expose the surface of the upper electrode layer 230 away from the substrate 10 and the cover layer 320 , the germanium in the cover layer 320 When the atomic volume concentration is greater than the atomic volume concentration of germanium in the filling layer 310 , the conductive layer is better, so that the conductivity of the upper electrode conductive layer 30 can be improved.
  • the filling layer 310 may also partially fill the gap, which is not limited in the present disclosure.
  • the temperature of the chemical vapor deposition in the reaction chamber 90 is 300°C to 600°C, such as 300°C, 400°C, 500°C, 600°C, etc.
  • the temperature of the chemical vapor deposition in the reaction chamber 90 is It may also be less than 300°C or greater than 600°C, which is not limited in the present disclosure.
  • the pressure during the chemical vapor deposition in the reaction chamber 90 is 100mtorr-600mtorr, such as 100mtorr, 200mtorr, 300mtorr, 400mtorr, 500mtorr, 600mtorr, etc.
  • the pressure during the chemical vapor deposition in the reaction chamber 90 can also be Less than 100mtorr or more than 600mtorr, this disclosure does not limit.
  • the deposition time of the filling layer 310 by chemical vapor deposition in the reaction chamber 90 is 20min-50min, such as 20min, 30min, 40min, 50min, etc.
  • the deposition time can also be greater than 20min or less than 50min, and the specific time It can be set according to the actual situation of filling the gap, which is not limited in the present disclosure.
  • a chemical vapor deposition process can be used in the reaction chamber 90 to form a capping layer 320 covering the filling layer 310 and the upper electrode layer 230 , and the capping layer 320 and the filling layer 310 can pass through the same
  • the reaction chamber 90 is formed to reduce the difficulty of the process and improve the efficiency of the process.
  • Gases of SiH 4 , GeH 4 , and BCl 3 enter the reaction chamber 90 to generate a filling layer 310 in which Si, B, and Ge atoms are deposited in the gap through chemical reaction, so as to cover the filling layer 310 and the upper electrode layer 230 .
  • the flow rate of SiH 4 is 300sccm-700sccm
  • the flow rate of SiH 4 is 1250sccm-1800sccm
  • the flow rate of SiH 4 is 500sccm -200sccm. Setting the SiH 4 , GeH 4 , and BCl 3 gases at the flow rate of the above standard ml/min can ensure a good deposition effect of the deposition material and further reduce the slits in the filling layer 310 .
  • the gas flow rates of SiH 4 , GeH 4 , and BCl 3 can also be outside the above-mentioned limited range, which is not limited in the present disclosure.
  • the atomic volume concentration of germanium in the cover layer 320 is 55%-85%, such as 55%, 60%, 65%, 75%, 80%, 85%, etc.; the atomic volume concentration of germanium in the cover layer 320 is greater than that in the filling layer 310 30%-50% of the atomic volume concentration of germanium, such as 30%, 35%, 40%, 45%, 50%, etc.
  • the gap has a large aspect ratio (20:1 to 100:1)
  • the filling layer 310 with a relatively small volume concentration of germanium atoms, the particle size of the filling material is relatively reduced, so that the gap can be more densely packed. Filling reduces the size of the slit that occurs when the germanium-boron co-doped polysilicon is filled in the gap, thereby reducing the leakage current of the capacitor and improving the performance of the capacitor.
  • the resistance of the capping layer 320 is lower, and the capping layer 320 located outside the gap has good conductivity, thereby improving the overall
  • the conductivity of the electrode conductive layer 30 avoids the situation that the conductivity of the upper electrode conductive layer 30 is affected due to the low atomic volume concentration of germanium in the filling layer 310 .
  • the substrate 10 includes a substrate 110 and an insulating layer 120 , and the insulating layer 120 is provided with a plurality of storage node contact plugs 130 arranged at intervals.
  • the substrate 110 may be a semiconductor substrate 110, and the material of the semiconductor substrate 110 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC), etc., which is not described in the present disclosure. limit.
  • the contact plug 130 is used to connect the lower electrode layer 210 of the capacitor to be formed later, and the data stored in the capacitor can be read or data can be written into the capacitor through the contact plug 130 .
  • the arrangement of the contact plugs 130 is the same as the arrangement of the capacitor holes formed subsequently.
  • the plurality of contact plugs 130 may be arranged in a hexagonal array.
  • the material of the contact plug 130 is metal, and the metal may be W (tungsten), Cu (copper), Ti (titanium), Ni (nickel), Al (aluminum) or metal silicide.
  • the contact plug 130 may be formed by depositing a conductive layer and then etching the conductive layer, or by an electroplating process.
  • the material of the insulating layer 120 can be silicon oxide, silicon nitride or other suitable materials, and the material of the insulating layer 120 can be a single-layer or multi-layer stack structure.
  • the formation process of the insulating layer 120 is: forming an insulating material layer on the semiconductor substrate 110 through a deposition process, and the insulating material layer covers the contact plug 130.
  • the deposition process may be chemical vapor deposition, plasma enhanced chemical vapor deposition Deposition or low pressure chemical vapor deposition; planarization removes the insulating material layer higher than the surface of the contact plug 130 to form the insulating layer 120, and the planarization may use a chemical mechanical polishing process.
  • the capacitor structure 20 includes a lower electrode layer 210 , a capacitor dielectric layer 220 and an upper electrode layer 230 .
  • the material of the lower electrode layer 210 includes a stack formed by one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, P-type polysilicon, or two or more of the above materials. It can also include compounds formed by one or both of metal nitrides and metal silicides, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide), silicon titanium nitride (Titanium Nitride) TiSixNy ) and so on.
  • the materials of the lower electrode layer 210 and the contact plugs 130 are the same, so that the lower electrode composed of the lower electrode layer 210 and the contact plugs 130 has better electrical properties.
  • the capacitor dielectric layer 220 may be a single-layer or multi-layer stack structure, and the capacitor dielectric layer 220 may be selected from a stack structure composed of strontium titanate and titanium oxide (SrTiO 3 /TiO 2 ), aluminum oxide and hafnium oxide (AlO/TiO 2 )
  • the laminated structure composed of HfO), the laminated structure composed of zirconia and alumina (ZrO/AlO/ZrO), and the composite perovskite-type ferroelectric material (BST material, the iron electrode material of the composite perovskite structure are composed of One of the solid solution composed of BaTiO 3 and SrTiO 3 in a certain proportion); silicon oxide, silicon nitride, silicon oxynitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide) can also be used , PSG (phosphorus doped silica) or BPSG (boron phosphorus doped silic
  • the material for forming the upper electrode layer 230 includes one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, P-type polysilicon, or two or more of the above materials.
  • the laminate may also include compounds formed by one or both of metal nitrides and metal silicides, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide), silicon nitride (Titanium Nitride) Titanium ( TiSixNy ) and so on.
  • the material of the upper electrode layer 230 is the same as the material of the lower electrode layer 210, so as to reduce the difficulty of the process and improve the efficiency of the process.
  • Embodiments of the present disclosure also provide a semiconductor memory device, the semiconductor memory device includes the above-mentioned capacitor array structure, the substrate further includes a transistor, and the capacitor structure is electrically connected to the transistor; the above-mentioned capacitor array structure can be formed by the above-mentioned manufacturing method of the capacitor array structure .
  • the semiconductor memory device may be, but is not limited to, dynamic random access memory (DRAM).

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

一种电容器阵列结构的制造方法、电容器阵列结构与半导体存储器件，该制造方法包括：提供一基底；在所述基底上形成电容结构，包括在所述基底上形成下电极层，和在所述下电极层表面形成电容介质层，以及在所述电容介质层表面的形成上电极层，其中，所述上电极层之间具有间隙；形成填充层填充所述间隙；形成覆盖层覆盖所述填充层与所述上电极；其中，所述覆盖层与所填充层结合形成上电极导电层；所述填充层和所述覆盖层的材质包括掺杂多晶硅，且所述覆盖层中的掺杂的锗原子体积浓度大于所述填充层中掺杂的锗原子体积浓度。本公开通过的电容器阵列结构的制造方法，能够减少上电极导电层中的狭缝。

Description

电容器阵列结构及其制造方法与半导体存储器件
相关申请的交叉引用
本申请要求于2020年09月28日递交的、名称为《电容器阵列结构及其制造方法与半导体存储器件》的中国专利申请第202011068522.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种电容器阵列结构的制造方法、电容器阵列结构与半导体存储器件。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。在20nm以下的DRAM制程中，DRAM大多采用堆栈式的电容构造，其电容器(Capacitor)是高深宽比的柱体形状。
其中，上电极上用于导电的覆盖在填充上电极的间隙时，由于间隙具有高深宽比，在间隙中填充材料会出现提前封口的现象，导致电容结构内产生狭缝，造成器件漏电流的增加，进而导致器件功耗增大，甚至导致器件失效。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开实施例的目的在于提供一种电容器阵列结构的制造方法、电容器阵列结构与半导体存储器件，能够减少上电极导电层中的狭缝。
根据本公开实施例的第一方面，提供了一种电容器阵列结构的制造方法，该电容器阵列结构的制造方法包括：
提供一基底；
在所述基底上形成电容结构，包括在所述基底上形成下电极层，和在所述下电极层表面形成电容介质层，以及在所述电容介质层表面的形成上电极层，其中，所述上电极层之间具有间隙；
形成填充层填充所述间隙；
形成覆盖层覆盖所述填充层与所述上电极；
其中，所述覆盖层与所填充层结合形成上电极导电层；所述填充层和所述覆盖层的材质包括掺杂多晶硅，且所述覆盖层中的掺杂的锗原子体积浓度大于所述填充层中掺杂的锗原子体积浓度。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开的一种实施例提供的电容器阵列结构的制造方法的流程图；
图2-图4为本公开的一种实施例提供的电容器阵列结构的制造工序图；
图5-图6为本公开的另一种实施例提供的电容器阵列结构的制造工序图；
图7为本公开的一种实施例提供的反应腔室的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一 个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有特定细节中的一个或更多，或者可以采用其它的方法、装置、步骤等。在其它情况下，不详细示出或描述公知方法、装置、实现或者操作以避免模糊本公开的各方面。
附图中所示的流程图仅是示例性说明，不是必须包括所有的内容和步骤，也不是必须按所描述的顺序执行。例如，有的步骤还可以分解，而有的步骤可以合并或部分合并，因此实际执行的顺序有可能根据实际情况改变。用语“一个”、“一”和“上述”等用以表示存在一个或多个要素/组成部分/等。术语“包含”、“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本公开的实施例首先提供了一种电容器阵列结构的制造方法，如图1所示，电容器阵列结构的制造方法包括：
步骤S100、提供一基底；
步骤S200、在基底上形成电容结构，包括在基底上形成下电极层，和在下电极层表面形成电容介质层，以及在电容介质层表面的形成上电极层，其中，上电极层之间具有间隙；
步骤S300、形成填充层填充间隙；
步骤S400、形成覆盖层覆盖填充层与上电极；其中，覆盖层与所填充层结合形成上电极导电层；填充层和覆盖层的材质包括掺杂多晶硅，且覆盖层中的掺杂的锗原子体积浓度大于填充层中掺杂的锗原子体积浓度。
本公开提供的电容器阵列结构的制造方法，通过填充层与覆盖层结合形成上电极导电层，且覆盖层中的锗原子体积浓度大于填充层中的锗原子体积浓度，使得填充层中的锗原子体积浓度相对较小，进而使填充分子的粒径相对减小，从而能够将间隙填充的更加致密；同时，使覆盖层中的锗原子体积浓度较大，能够平衡结构阻值，保证了上电极导电层的性能。通过减小上电极导电层填充间隙时出现的狭缝，降低了电容器的漏电流，提高了电容器的性能。
下面，将对本示例实施方式中的电容器阵列结构的制造方法的各步骤进行进一步的说明。
在步骤S100中，提供一基底。
具体地，如图2所示，基底10包括衬底110和绝缘层120，绝缘层120中设置有多个间隔布置的存储节点接触塞130。其中，衬底110可为半导体衬底110，半导体衬底110的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)等，本公开对此不做限制。
其中，接触塞130用于连接后续形成的电容的下电极层210，通过接触塞130可以读取电容中存储的数据或者向电容中写入数据。若干接触塞130的排布方式与后续形成的电容孔的排布方式相同。在一实施例中，多个接触塞130可以呈六方阵列排布。其中，接触塞130的材料为金属，金属可以为W(钨)、Cu(铜)、Ti(钛)、Ni(镍)、Al(铝)或金属硅化物。形成接触塞130可以通过沉积一层导电层，然后对导电层进行刻蚀形成，或者通过电镀工艺形成。
其中，绝缘层120的材料可以为氧化硅、氮化硅或其他合适的材料，绝缘层120材料可以为单层或多层堆叠结构。在一实施例中，绝缘层120的形成过程为：在半导体衬底110上通过沉积工艺形成一层绝缘材料层，绝缘材料层覆盖接触塞130，沉积工艺可以是化学气相沉积，等离子增强化学气相沉积或低压化学气相沉积；平坦化去除高于接触塞130表面的绝缘材料层，形成绝缘层120，平坦化可采用化学机械研磨工艺。
在步骤S200中，在基底上形成电容结构，包括在基底上形成下电极层，和在下电极层表面形成电容介质层，以及在电容介质层表面的形成上电极层，其中，上电极层之间具有间隙。
具体地，如图2所示，在基底上形成电容结构20，电容结构在基底10上形成下电极层210，和在下电极层210表面形成电容介质层220，以及在电容介质层220表面的形成上电极层230。
其中，通过采用原子层沉积工艺(Atomic Layer Deposition)或化学气相沉积工艺(Chemical Vapor Deposition)或物理气相沉积(Physical Vapor Deposition)的工艺形成包括多个柱状电极的下电极层210。其中， 形成下电极层210的材料包括钨、钛、镍、铝、铂、氮化钛、N型多晶硅、P型多晶硅中的一种或上述材料所组成群组中的两种以上所形成的叠层，还可以包括金属氮化物及金属硅化物中的一种或两种所形成的化合物，如氮化钛(Titanium Nitride)，硅化钛(Titanium Silicide)，硅化镍(Titanium Silicide)，硅氮化钛(TiSi xN y)等。在一实施例中，下电极层210与接触塞130的材料一致，以使得下电极层210与接触塞130所组成的下电极具有较好的电学性能。
其中，可通过采用原子层沉积工艺或化学气相沉积工艺或物理气相沉积的工艺形成覆盖下电极层210的电容介质层220，电容介质层220同时覆盖从多个柱状电极露出的基底10的表面。当电容介质层220与下电极层210之间无其它膜层时，电容介质层220可直接覆盖在下电极层210的表面上；当电容介质层220与下电极层210之间涉及其它膜层时，介质层与下电极层210不直接接触，但相对覆盖下电极层210。其中，电容介质层220可以为单层或多层堆叠结构，电容介质层220可选自钛酸锶和氧化钛(SrTiO 3/TiO 2)构成的叠层结构、氧化铝和氧化铪(AlO/HfO)构成的叠层结构、氧化锆和氧化铝(ZrO/AlO/ZrO)构成的叠层结构以及复合钙铁矿型铁电材料(BST材料，复合钙铁矿结构的铁电极材料，是由BaTiO 3和SrTiO 3按一定比例组成的固溶体)中的一种；还可采用氧化硅、氮化硅、氮氧化硅、FSG(掺氟的二氧化硅)、BSG(掺硼的二氧化硅)、PSG(掺磷的二氧化硅)或BPSG(掺硼磷的二氧化硅)或上述的组合的材料形成。电容介质层220的介电常数介于4～400之间，电容介质层220优选高K介质材料，以提高单位面积电容器的电容值。
其中，通过采用原子层沉积工艺或化学气相沉积工艺或物理气相沉积的工艺形成包括多个柱状电极的上电极层230。其中，形成上电极层230的材料包括钨、钛、镍、铝、铂、氮化钛、N型多晶硅、P型多晶硅中的一种或上述材料所组成群组中的两种以上所形成的叠层，还可以包括金属氮化物及金属硅化物中的一种或两种所形成的化合物，如氮化钛(Titanium Nitride)，硅化钛(Titanium Silicide)，硅化镍(Titanium Silicide)，硅氮化钛(TiSi xN y)等。在一实施例中，上电极层230的材 料与下电极层210的材料一致，以降低工艺难度，提高工艺效率。
如图2所示，上电极层230覆盖电容介质层220后，相邻的柱状电极之间的上电极层230之间存在间隙，该间隙具有较大的深宽比(20：1～100：1)，示例的，高度可为1000nm-2000nm，CD(关键尺寸)为30nm-60nm。传统方法在对上电极层的间隙进行填充的同时，会有提前封口的现象，导致上电极导电层内产生狭缝(seam)，导致电容器阵列结构的漏电流增加。
在步骤S300中，形成填充层填充间隙。
具体地，如图3和图7所示，可在反应腔室90内通过化学气相沉积工艺，形成填充间隙的填充层310。填充层310的材质包括掺杂的锗原子的掺锗多晶硅，可通过喷嘴喷入通入SiH 4与GeH 4气体，SiH 4与GeH 4气体进入反应腔室90内化学反应如下：
SiH 4(g)→Si(s)+2H 2(g)
GeH 4(g)→Ge(s)+2H 2(g)
SiH 4与GeH 4气体进入反应腔室90内，通过化学反应生成Si原子与Ge原子沉积在间隙中，以形成掺锗多晶硅的填充层310。
其中，在反应腔室90内通过化学气相沉积进行填充层310的沉积时，通入SiH 4气体的流速为300sccm-700sccm，通入GeH 4的流速为850sccm-1300sccm，将通入GeH 4气体设定在上述标准毫升/分钟的流速下，能够保证沉积材料的良好的沉积效果，进一步减少填充层310中的狭缝。当然，将SiH 4气体与GeH 4气体的气体流速也可在上述限定范围以外，本公开对此不做限制。
其中，在反应腔室90内通入SiH 4气体与GeH 4气体的持续时间为20min-50min，例如20min、30min、40min、50min等，当然，沉积的时间也可大于20min或小于50min，具体时间可根据填充间隙的实际情况进行设定，本公开对此不做限制。
示例的，填充层310的材质可为锗硼共掺多晶硅，可通过喷嘴同时喷入通入SiH 4、GeH 4、BCl 3气体，BCl 3气体进入反应腔室90内化学反应如下：
2BCl 3(g)→2B(s)+3Cl 2(g)
SiH 4、GeH 4、BCl 3气体进入反应腔室90内，通过化学反应生成Si、B、Ge原子沉积在间隙中的填充层310，以将间隙填充。其中，在反应腔室90内通过化学气相沉积进行填充层310的沉积时，通入BCl 3气体的流速为500sccm-200sccm。当然，将BCl 3的气体流速也可在上述限定范围以外，本公开对此不做限制。其中，在反应腔室90内通入BCl 3气体的时间为20min-50min，例如20min、30min、40min、50min等，当然，沉积的时间也可大于20min或小于50min，具体时间可根据填充间隙的实际情况进行设定，本公开对此不做限制。其中，通入SiH 4、GeH 4、BCl 3气体的时间可相同，已提升锗硼共掺多晶硅中各原子沉积的均匀性，从而提升上电极导电层的导电性。
如图3所示，间隙的深宽比范围为20：1～100：1，填充层310将间隙完全填充，并在上电极层230背离基底10的一侧表面上也形成了一定厚度的填充层310；如图5所示，填充层310仅将间隙完全填充，并未在上电极层230背离基底10的一侧表面上形成填充层310材料，以露出上电极层230背离基底10的一侧表面与覆盖层320，覆盖层320中的锗原子体积浓度大于填充层310中的锗原子体积浓度，导电层较好，从而能够提升上电极导电层30的导电性。当然，填充层310也可部分填充间隙，本公开对此不做限制。
其中，反应腔室90内进行化学气相沉积时的温度为300℃-600℃，例如300℃、400℃、500℃、600℃等，当然，反应腔室90内进行化学气相沉积时的温度为也可小于300℃或大于600℃，本公开对此不做限制。其中，反应腔室90内进行化学气相沉积时的压力为100mtorr-600mtorr，例如100mtorr、200mtorr、300mtorr、400mtorr、500mtorr、600mtorr等，当然，反应腔室90内进行化学气相沉积时的压力为也可小于100mtorr或大于600mtorr，本公开对此不做限制。
通过采用锗原子体积浓度相对较小的填充层310，填充材料的粒径相对减小，从而能够更加致密的将间隙填充，减少间隙中填充锗硼共掺多晶硅时出现的狭缝大小，从而使得电容器的漏电流减少，提高了电容器的性能。
在步骤S400中，形成覆盖层覆盖填充层与上电极层；其中，覆盖 层与所填充层结合形成上电极导电层；填充层和覆盖层的材质包括掺杂多晶硅，且覆盖层中的掺杂的锗原子体积浓度大于填充层中掺杂的锗原子体积浓度。
具体地，具体地，如图4、图6和图7所示，可在反应腔室90内通过化学气相沉积工艺，形成覆盖填充层310与上电极层230的覆盖层320，覆盖层320与填充层310可通过同一反应腔室90形成，以降低工艺难度，提高工艺效率。覆盖层320的材质包括掺杂的锗原子的掺锗多晶硅，可通过喷嘴喷入通入SiH 4与GeH 4气体，SiH 4与GeH 4气体进入反应腔室90内化学反应如下：
SiH 4(g)→Si(s)+2H 2(g)
GeH 4(g)→Ge(s)+2H 2(g)
SiH 4与GeH 4气体进入反应腔室90内，通过化学反应生成Si原子与Ge原子沉积在填充层与上电极层上，以形成掺杂锗原子的覆盖层320。
其中，在反应腔室90内通过化学气相沉积进行覆盖层320的沉积时，通入SiH 4气体的流速为300sccm-700sccm，通入GeH 4的流速为1250sccm-1800sccm，将通入GeH 4气体设定在上述标准毫升/分钟的流速下，能够保证锗原子体积浓度，形成的覆盖层320具有良好的导电性。当然，将SiH 4气体与GeH 4气体的气体流速也可在上述限定范围以外，本公开对此不做限制。
其中，在反应腔室90内通入SiH 4气体与GeH 4气体的持续时间为120min-180min，例如120min、130min、140min、150min、160min、170min、180min等，当然，沉积的时间也可小于120min或大于180min，具体时间可根据覆盖层320的实际厚度等情况进行设定，本公开对此不做限制。
示例的，覆盖层320的材质可为锗硼共掺多晶硅，可通过喷嘴同时喷入通入SiH 4、GeH 4、BCl 3气体，BCl 3气体进入反应腔室90内化学反应如下：
2BCl 3(g)→2B(s)+3Cl 2(g)
SiH 4、GeH 4、BCl 3气体进入反应腔室90内，通过化学反应生成Si、B、Ge原子沉积在填充层与上电极层上，以形成锗硼共掺多晶硅的覆盖 层320，以将填充层310与上电极层230覆盖。其中，在反应腔室90内通过化学气相沉积进行覆盖层320的沉积时，通入BCl 3气体的流速为500sccm-200sccm。当然，将BCl 3的气体流速也可在上述限定范围以外，本公开对此不做限制。其中，在反应腔室90内通入BCl 3气体的时间为120min-180min，例如120min、130min、140min、150min、160min、170min、180min等，当然，沉积的时间也可小于120min或大于180min，具体时间可根据覆盖层320的实际厚度等情况进行设定，本公开对此不做限制。其中，通入SiH 4、GeH 4、BCl 3气体的时间可相同，已提升锗硼共掺多晶硅中各原子沉积的均匀性，从而提升上电极导电层的导电性。
其中，反应腔室90内进行化学气相沉积时的温度为300℃-600℃，例如300℃、400℃、500℃、600℃等，当然，反应腔室90内进行化学气相沉积时的温度为也可小于300℃或大于600℃，本公开对此不做限制。其中，反应腔室90内进行化学气相沉积时的压力为100mtorr-600mtorr，例如100mtorr、200mtorr、300mtorr、400mtorr、500mtorr、600mtorr等，当然，反应腔室90内进行化学气相沉积时的压力为也可小于100mtorr或大于600mtorr，本公开对此不做限制。
其中，覆盖层320与所填充层310形成时反应腔室90内温度与压力相同，以降低工艺难度，提高工艺效率。当然，覆盖层320与所填充层310形成时反应腔室90内温度与压力相同也可不同，本公开对此不做限制。
其中，覆盖层320中的锗原子体积浓度大于填充层310中的锗原子体积浓度的30％-50％。通过使覆盖层320中的锗原子体积浓度大于填充层310中的锗原子体积浓度，覆盖层320的阻值较低，位于间隙外的覆盖层320具有良好的导电性，从而能够整体上改善上电极导电层30的导电性，避免了因填充层310中锗原子体积浓度较低导致影响上电极导电层30的导电性的情况出现。
下面，为本公开的装置实施例，本公开的装置实施例可通过上述方法实施例制造形成，本装置实施例未公开的具体细节，请参照上述方法实施例的相关论述。
本公开的实施例还提供了一种电容器阵列结构，如图2-图6所示，该电容器阵列结构包括：基底10、电容结构20和上电极导电层30。电容结构20设于基底10上，电容结构20包括下电极层210，电容介质层220和上电极层230，电容介质层220覆盖下电极层210的表面，上电极层230覆盖电容介质层220的表面，且上电极层230之间形成有间隙；上电极导电层30包括填充层310与覆盖层320，填充层310填充间隙，覆盖层320覆盖填充层310与上电极层230，覆盖层320与填充层310的材质包括掺杂多晶硅，且覆盖层320中掺杂的锗原子体积浓度大于填充层310中掺杂的锗原子体积浓度。
本公开提供的电容器阵列结构，填充层310与覆盖层320结合形成上电极导电层30，且覆盖层320中的锗原子体积浓度大于填充层310中的锗原子体积浓度，使得填充层310中的锗原子体积浓度相对较小，进而使填充分子的粒径相对减小，从而能够将间隙填充的更加致密；同时，使覆盖层320中的锗原子体积浓度较大，能够平衡结构阻值，保证了上电极导电层30的性能。通过减小上电极导电层30填充间隙时出现的狭缝，降低了电容器的漏电流，提高了电容器的性能。
具体地，如图3和图7所示，可在反应腔室90内通过化学气相沉积工艺，形成填充间隙的填充层310。填充层310
填充层310的材质包括掺杂的锗原子的掺锗多晶硅，可通过喷嘴喷入通入SiH 4与GeH 4气体，SiH 4与GeH 4气体进入反应腔室90内化学反应如下：
SiH 4(g)→Si(s)+2H 2(g)
GeH 4(g)→Ge(s)+2H 2(g)
示例的，填充层310的材质可为锗硼共掺多晶硅，可通过喷嘴同时喷入通入SiH 4、GeH 4、BCl 3气体，BCl 3气体进入反应腔室90内化学反应如下：
2BCl 3(g)→2B(s)+3Cl 2(g)
SiH 4、GeH 4、BCl 3气体进入反应腔室90内，通过化学反应生成Si、B、Ge原子沉积在间隙中的填充层310，以将间隙填充。
其中，在反应腔室90内通过化学气相沉积进行填充层310的沉积时， 通入SiH 4的流速为300sccm-700sccm，通入SiH 4的流速为850sccm-1300sccm，通入SiH 4的流速为500sccm-200sccm。将SiH 4、GeH 4、BCl 3气体设定在上述标准毫升/分钟的流速下，能够保证沉积材料的良好的沉积效果，进一步减少填充层310中的狭缝。当然，将SiH 4、GeH 4、BCl 3的气体流速也可在上述限定范围以外，本公开对此不做限制。其中，填充层310的锗原子体积浓度为45％-80％，例如45％、50％、55％、65％、70％、75％、80％等。
其中，如图3所示，填充层310将间隙完全填充，并在上电极层230背离基底10的一侧表面上也形成了一定厚度的填充层310；如图5所示，填充层310仅将间隙完全填充，并未在上电极层230背离基底10的一侧表面上形成填充层310材料，以露出上电极层230背离基底10的一侧表面与覆盖层320，覆盖层320中的锗原子体积浓度大于填充层310中的锗原子体积浓度，导电层较好，从而能够提升上电极导电层30的导电性。当然，填充层310也可部分填充间隙，本公开对此不做限制。
其中，反应腔室90内进行化学气相沉积时的温度为300℃-600℃，例如300℃、400℃、500℃、600℃等，当然，反应腔室90内进行化学气相沉积时的温度为也可小于300℃或大于600℃，本公开对此不做限制。其中，反应腔室90内进行化学气相沉积时的压力为100mtorr-600mtorr，例如100mtorr、200mtorr、300mtorr、400mtorr、500mtorr、600mtorr等，当然，反应腔室90内进行化学气相沉积时的压力为也可小于100mtorr或大于600mtorr，本公开对此不做限制。其中，在反应腔室90内通过化学气相沉积进行填充层310的沉积的时间为20min-50min，例如20min、30min、40min、50min等，当然，沉积的时间也可大于20min或小于50min，具体时间可根据填充间隙的实际情况进行设定，本公开对此不做限制。
如图4、图6和图7所示，可在反应腔室90内通过化学气相沉积工艺，形成覆盖填充层310与上电极层230的覆盖层320，覆盖层320与填充层310可通过同一反应腔室90形成，以降低工艺难度，提高工艺效率。SiH 4、GeH 4、BCl 3气体进入反应腔室90内，通过化学反应生成Si、 B、Ge原子沉积在间隙中的填充层310，以将填充层310与上电极层230覆盖。
其中，在反应腔室90内通过化学气相沉积进行填充层310的沉积时，通入SiH 4的流速为300sccm-700sccm，通入SiH 4的流速为1250sccm-1800sccm，通入SiH 4的流速为500sccm-200sccm。将SiH 4、GeH 4、BCl 3气体设定在上述标准毫升/分钟的流速下，能够保证沉积材料的良好的沉积效果，进一步减少填充层310中的狭缝。当然，将SiH 4、GeH 4、BCl 3的气体流速也可在上述限定范围以外，本公开对此不做限制。其中，覆盖层320的锗原子体积浓度为55％-85％，例如55％、60％、65％、75％、80％、85％等；覆盖层320中的锗原子体积浓度大于填充层310中的锗原子体积浓度的30％-50％，例如30％、35％、40％、45％、50％等。
由于该间隙具有较大的深宽比(20：1～100：1)，通过采用锗原子体积浓度相对较小的填充层310，填充材料的粒径相对减小，从而能够更加致密的将间隙填充，减少间隙中填充锗硼共掺多晶硅时出现的狭缝大小，从而使得电容器的漏电流减少，提高了电容器的性能。通过使覆盖层320中的锗原子体积浓度大于填充层310中的锗原子体积浓度，覆盖层320的阻值较低，位于间隙外的覆盖层320具有良好的导电性，从而能够整体上改善上电极导电层30的导电性，避免了因填充层310中锗原子体积浓度较低导致影响上电极导电层30的导电性的情况出现。
具体地，如图2所示，基底10包括衬底110和绝缘层120，绝缘层120中设置有多个间隔布置的存储节点接触塞130。其中，衬底110可为半导体衬底110，半导体衬底110的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)等，本公开对此不做限制。
其中，接触塞130用于连接后续形成的电容的下电极层210，通过接触塞130可以读取电容中存储的数据或者向电容中写入数据。若干接触塞130的排布方式与后续形成的电容孔的排布方式相同。在一实施例中，多个接触塞130可以呈六方阵列排布。其中，接触塞130的材料为金属，金属可以为W(钨)、Cu(铜)、Ti(钛)、Ni(镍)、Al(铝)或金属硅化物。形成接触塞130可以通过沉积一层导电层，然后对导电 层进行刻蚀形成，或者通过电镀工艺形成。
其中，绝缘层120的材料可以为氧化硅、氮化硅或其他合适的材料，绝缘层120材料可以为单层或多层堆叠结构。在一实施例中，绝缘层120的形成过程为：在半导体衬底110上通过沉积工艺形成一层绝缘材料层，绝缘材料层覆盖接触塞130，沉积工艺可以是化学气相沉积，等离子增强化学气相沉积或低压化学气相沉积；平坦化去除高于接触塞130表面的绝缘材料层，形成绝缘层120，平坦化可采用化学机械研磨工艺。
其中，电容结构20包括下电极层210，电容介质层220和上电极层230。下电极层210的材料包括钨、钛、镍、铝、铂、氮化钛、N型多晶硅、P型多晶硅中的一种或上述材料所组成群组中的两种以上所形成的叠层，还可以包括金属氮化物及金属硅化物中的一种或两种所形成的化合物，如氮化钛(Titanium Nitride)，硅化钛(Titanium Silicide)，硅化镍(Titanium Silicide)，硅氮化钛(TiSi xN y)等。在一实施例中，下电极层210与接触塞130的材料一致，以使得下电极层210与接触塞130所组成的下电极具有较好的电学性能。
其中，电容介质层220可以为单层或多层堆叠结构，电容介质层220可选自钛酸锶和氧化钛(SrTiO 3/TiO 2)构成的叠层结构、氧化铝和氧化铪(AlO/HfO)构成的叠层结构、氧化锆和氧化铝(ZrO/AlO/ZrO)构成的叠层结构以及复合钙铁矿型铁电材料(BST材料，复合钙铁矿结构的铁电极材料，是由BaTiO 3和SrTiO 3按一定比例组成的固溶体)中的一种；还可采用氧化硅、氮化硅、氮氧化硅、FSG(掺氟的二氧化硅)、BSG(掺硼的二氧化硅)、PSG(掺磷的二氧化硅)或BPSG(掺硼磷的二氧化硅)或上述的组合的材料形成。电容介质层220的介电常数介于4～400之间，电容介质层220优选高K介质材料，以提高单位面积电容器的电容值。
其中，形成上电极层230的材料包括钨、钛、镍、铝、铂、氮化钛、N型多晶硅、P型多晶硅中的一种或上述材料所组成群组中的两种以上所形成的叠层，还可以包括金属氮化物及金属硅化物中的一种或两种所形成的化合物，如氮化钛(Titanium Nitride)，硅化钛(Titanium Silicide)， 硅化镍(Titanium Silicide)，硅氮化钛(TiSi xN y)等。在一实施例中，上电极层230的材料与下电极层210的材料一致，以降低工艺难度，提高工艺效率。
本公开的实施例还提供了一种半导体存储器件，半导体存储器件包括上述的电容器阵列结构，基底还包括晶体管，电容结构与晶体管电连接；上述电容器阵列结构可由上述的电容器阵列结构的制造方法形成。半导体存储器件具有地有益效果请参照上述关于电容器阵列结构的论述，在此不再赘述。示例的，半导体存储器件可以为但不仅限于动态随机存储器(DRAM)。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (15)

  1. 一种电容器阵列结构的制造方法，其中，包括：
    提供一基底；
    在所述基底上形成电容结构，包括在所述基底上形成下电极层，和在所述下电极层表面形成电容介质层，以及在所述电容介质层表面的形成上电极层，其中，所述上电极层之间具有间隙；
    形成填充层填充所述间隙；
    形成覆盖层覆盖所述填充层与所述上电极层；
    其中，所述覆盖层与所填充层结合形成上电极导电层；所述填充层和所述覆盖层的材质包括掺杂多晶硅，且所述覆盖层中的掺杂的锗原子体积浓度大于所述填充层中掺杂的锗原子体积浓度。
  2. 根据权利要求1所述的制造方法，其中，通过化学气相沉积法，形成所述填充层与所述覆盖层。
  3. 根据权利要求2所述的制造方法，其中，在形成所述填充层时通入GeH 4气体；
    其中，所述通入GeH 4气体的流速为850sccm-1300sccm。
  4. 根据权利要求3所述的制造方法，其中，所述通入GeH 4气体的持续时间为20min-50min。
  5. 根据权利要求2所述的制造方法，其中，在形成所述覆盖层时通入GeH 4气体；
    其中，所述通入GeH 4气体的流速为1250sccm-1800sccm。
  6. 根据权利要求5所述的制造方法，其中，所述通入GeH 4气体的持续时间为120min-180min。
  7. 根据权利要求1所述的制造方法，其中，所述覆盖层中的锗原子体积浓度大于所述填充层中的锗原子体积浓度的30％-50％。
  8. 根据权利要求2所述的制造方法，其中，所述化学气相沉积时的温度为300℃-600℃。
  9. 根据权利要求2所述的制造方法，其中，所述化学气相沉积时腔室内的压力为100mtorr-600mtorr。
  10. 根据权利要求2所述的制造方法，其中，形成所述填充层与所 述覆盖层时，同时通入GeH 4气体、SiH 4气体和BCl 3气体；
    其中，所述通入SiH 4气体的流速为300sccm～700sccm，所述通入BCl 3气体的流速为50sccm～200sccm。
  11. 一种电容器阵列结构，其中，包括：
    基底；
    电容结构，设于所述基底上，包括下电极层，电容介质层和上电极层，所述电容介质层覆盖所述下电极层的表面，所述上电极层覆盖所述电容介质层的表面，且所述上电极层之间形成有间隙；
    上电极导电层，包括填充层与覆盖层，所述填充层填充所述间隙，所述覆盖层覆盖所述填充层与所述上电极层，所述覆盖层与所述填充层的材质包括掺杂多晶硅，且所述覆盖层中掺杂的锗原子体积浓度大于所述填充层中掺杂的锗原子体积浓度。
  12. 根据权利要求11所述的电容器阵列结构，其中，所述覆盖层中的锗原子体积浓度大于所述填充层中的锗原子体积浓度的30％-50％。
  13. 根据权利要求11所述的电容器阵列结构，其中，所述填充层的锗原子体积浓度为45％-80％，所述覆盖层的锗原子体积浓度为55％-85％。
  14. 根据权利要求11所述的电容器阵列结构，其中，所述填充层至少填充所述间隙，且所述间隙的深宽比范围为20：1～100：1。
  15. 一种半导体存储器件，其中，包括权利要求11-14任一项所述的电容器阵列结构，所述基底还包括晶体管，所述电容结构与所述晶体管电连接。
PCT/CN2021/103744 2020-09-28 2021-06-30 电容器阵列结构及其制造方法与半导体存储器件 WO2022062545A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP21870924.4A EP4199086A4 (en) 2020-09-28 2021-06-30 CAPACITOR ARRAY STRUCTURE, MANUFACTURING METHOD THEREFOR AND SEMICONDUCTOR STORAGE DEVICE
US17/599,464 US11411071B1 (en) 2020-09-28 2021-06-30 Capacitor array structure and method for manufacturing a capacitor array structure, and semiconductor memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011068522.7 2020-09-28
CN202011068522.7A CN114284216A (zh) 2020-09-28 2020-09-28 电容器阵列结构及其制造方法与半导体存储器件

Publications (1)

Publication Number Publication Date
WO2022062545A1 true WO2022062545A1 (zh) 2022-03-31

Family

ID=80846194

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/103744 WO2022062545A1 (zh) 2020-09-28 2021-06-30 电容器阵列结构及其制造方法与半导体存储器件

Country Status (4)

Country Link
US (1) US11411071B1 (zh)
EP (1) EP4199086A4 (zh)
CN (1) CN114284216A (zh)
WO (1) WO2022062545A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116133436A (zh) * 2021-11-12 2023-05-16 联华电子股份有限公司 半导体元件及其制作方法
CN116056558B (zh) * 2023-03-28 2023-08-29 长鑫存储技术有限公司 一种半导体结构的制作方法及其结构

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050064660A1 (en) * 2001-01-15 2005-03-24 Sang-Jeong Oh Methods of fabricating integrated circuit devices that utilize doped poly-Si1-xGex conductive plugs as interconnects
CN101101922A (zh) * 2007-08-01 2008-01-09 中电华清微电子工程中心有限公司 Npn型的锗硅异质结双极晶体管及其制造方法
CN102487073A (zh) * 2010-12-03 2012-06-06 台湾积体电路制造股份有限公司 具有提高的载体迁移率的源极/漏极应力源及其制造方法
CN107910327A (zh) * 2017-11-07 2018-04-13 睿力集成电路有限公司 电容器阵列结构及其制造方法
CN107968044A (zh) * 2017-12-19 2018-04-27 睿力集成电路有限公司 电容器阵列结构、半导体存储器及制备方法
CN108155152A (zh) * 2017-12-19 2018-06-12 睿力集成电路有限公司 导体结构、电容器阵列结构及制备方法
CN111326513A (zh) * 2018-12-14 2020-06-23 夏泰鑫半导体(青岛)有限公司 半导体器件

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100618869B1 (ko) * 2004-10-22 2006-09-13 삼성전자주식회사 커패시터를 포함하는 반도체 소자 및 그 제조방법
KR100655691B1 (ko) * 2005-09-21 2006-12-08 삼성전자주식회사 커패시터 및 이의 제조 방법.
CN105374684A (zh) 2014-08-30 2016-03-02 中芯国际集成电路制造(上海)有限公司 Pmos结构及其形成方法
US9431551B2 (en) 2014-09-15 2016-08-30 Infineon Technologies Ag Circuit arrangement and method of forming a circuit arrangement

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050064660A1 (en) * 2001-01-15 2005-03-24 Sang-Jeong Oh Methods of fabricating integrated circuit devices that utilize doped poly-Si1-xGex conductive plugs as interconnects
CN101101922A (zh) * 2007-08-01 2008-01-09 中电华清微电子工程中心有限公司 Npn型的锗硅异质结双极晶体管及其制造方法
CN102487073A (zh) * 2010-12-03 2012-06-06 台湾积体电路制造股份有限公司 具有提高的载体迁移率的源极/漏极应力源及其制造方法
CN107910327A (zh) * 2017-11-07 2018-04-13 睿力集成电路有限公司 电容器阵列结构及其制造方法
CN107968044A (zh) * 2017-12-19 2018-04-27 睿力集成电路有限公司 电容器阵列结构、半导体存储器及制备方法
CN108155152A (zh) * 2017-12-19 2018-06-12 睿力集成电路有限公司 导体结构、电容器阵列结构及制备方法
CN111326513A (zh) * 2018-12-14 2020-06-23 夏泰鑫半导体(青岛)有限公司 半导体器件

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4199086A4 *

Also Published As

Publication number Publication date
CN114284216A (zh) 2022-04-05
EP4199086A4 (en) 2024-02-14
EP4199086A1 (en) 2023-06-21
US11411071B1 (en) 2022-08-09

Similar Documents

Publication Publication Date Title
TWI817083B (zh) 3d dram結構及製造方法
KR100655139B1 (ko) 캐패시터 제조 방법
WO2022062545A1 (zh) 电容器阵列结构及其制造方法与半导体存储器件
JP2008166360A (ja) 半導体集積回路装置
US8828821B2 (en) Fabrication of semiconductor stacks with ruthenium-based materials
KR101417728B1 (ko) 지르코늄 유기산질화막 형성방법 및 이를 이용하는 반도체장치 및 그 제조방법
JP2011060825A (ja) 半導体装置及びその製造方法
JP2006161163A (ja) チタン窒化膜形成方法及びそのチタン窒化膜を利用した金属−絶縁体−金属キャパシタの下部電極形成方法
KR100811271B1 (ko) 반도체 소자의 캐패시터 형성방법
US20040012043A1 (en) Novel dielectric stack and method of making same
JP2006060230A (ja) ３次元半導体キャパシタおよびその製造方法
KR20190031806A (ko) 반도체 장치 및 그 제조 방법
KR101515471B1 (ko) 지르코늄 산화막과 지르코늄 산질화막 형성방법 및 이를이용하는 반도체 장치 및 그 제조방법
JP2008288408A (ja) 半導体装置及びその製造方法
JP2014135311A (ja) 半導体装置
JP4282450B2 (ja) 半導体装置の製造方法
KR20060062365A (ko) 금속-절연막-금속 커패시터 및 그 제조방법
KR100670726B1 (ko) 반도체 소자의 캐패시터 및 그 형성방법
KR20100050788A (ko) 반도체 장치의 형성 방법
KR100533981B1 (ko) 반도체 장치의 캐패시터 제조방법
KR100513804B1 (ko) 반도체 소자의 캐패시터 제조방법
US20230223428A1 (en) Semiconductor structure and manufacturing method thereof
KR100935727B1 (ko) 캐패시터의 하부 전극 형성방법
KR100585092B1 (ko) 측벽에 산화알루미늄 스페이서를 갖는 반도체 소자의커패시터 및 그 형성방법
KR20100025820A (ko) 반도체 소자의 커패시터 및 형성 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21870924

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 21870924.4

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2021870924

Country of ref document: EP

Effective date: 20230313

NENP Non-entry into the national phase

Ref country code: DE