WO2022062373A1 - 半导体结构的制备方法及半导体结构 - Google Patents

半导体结构的制备方法及半导体结构 Download PDF

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Publication number
WO2022062373A1
WO2022062373A1 PCT/CN2021/087414 CN2021087414W WO2022062373A1 WO 2022062373 A1 WO2022062373 A1 WO 2022062373A1 CN 2021087414 W CN2021087414 W CN 2021087414W WO 2022062373 A1 WO2022062373 A1 WO 2022062373A1
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Prior art keywords
drift region
shallow trench
substrate
region
layer
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English (en)
French (fr)
Inventor
杨斌
李春旭
刘晨晨
黄刚
黄宇
曹瑞彬
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular, to a method for preparing a semiconductor structure and a semiconductor structure.
  • a shallow trench isolation structure (Shallow Trench Isolation, STI) is generally used as a field plate.
  • STI shallow Trench Isolation
  • a method of fabricating a semiconductor structure is provided.
  • a preparation method of a semiconductor structure comprising:
  • a first drift region surrounding the shallow trench and a second drift region directly below the shallow trench are formed in the substrate, wherein the thickness of the first patterned mask layer and the thickness of the first patterned mask layer are controlled.
  • the energy of the ion implantation makes the doping concentration of the first drift region different from the doping concentration of the second drift region;
  • a dielectric layer is formed in the shallow trench, and the dielectric layer fills the shallow trench.
  • the above-mentioned preparation method of the semiconductor structure firstly forms a shallow trench in the substrate, and then forms a liner layer on the sidewall and bottom of the shallow trench, so as to eliminate the damage formed in the process of etching the shallow trench, and at the same time for the subsequent A protective layer is provided when filling the shallow trench; then a first drift region surrounding the shallow trench and a second drift region directly below the shallow trench are formed in the substrate, and controlled
  • the thickness of the first patterned mask layer and the energy of ion implantation make the doping concentration of the first drift region and the doping concentration of the second drift region different to improve the impurity concentration on the current path, which can effectively Improve the on-resistance of the device.
  • the depth of the second drift region formed directly under the shallow trench is deeper than that of the drift region formed in this part in the traditional semiconductor fabrication process, which can Increasing the cross-sectional area of the overcurrent can further improve the on-resistance of the device.
  • the process of high-temperature trapping in the drift region is simultaneously realized in the process of annealing the liner layer, compared with the traditional process flow, the high-temperature annealing of the liner layer and the high-temperature trapping of the ion implantation region need to be carried out in two separate steps. It is carried out in different process steps, which effectively reduces the steps of the process flow. Therefore, the present application reduces the on-resistance of the device while ensuring the high withstand voltage value of the fabricated semiconductor device, and reduces the number of process steps, thereby improving the yield of the fabricated device while reducing the fabrication cost of the semiconductor device.
  • a semiconductor structure includes a substrate and a drift region, the substrate is provided with a shallow trench isolation structure, the shallow trench isolation structure includes a shallow trench, a liner layer and a dielectric layer, the liner layer is located in the the sidewall and bottom of the shallow trench, the dielectric layer is located in the shallow trench and fills the shallow trench; the drift region is located in the substrate, and the drift region includes a surrounding a first drift region around the shallow trench, a second drift region directly below the shallow trench, and a third drift region formed in the second drift region, wherein the third drift region is adjacent
  • the doping concentration of the bottom region of the shallow trench is greater than the doping concentration of the first drift region.
  • FIG. 1 shows a flow chart of a method for fabricating a semiconductor structure provided in an embodiment of the present application.
  • FIGS. 2 to 4 are schematic cross-sectional structural views of the structure obtained in step S1 in a method for fabricating a semiconductor structure provided in an embodiment of the present application.
  • FIG. 5 is a schematic cross-sectional structure diagram of a structure obtained in step S2 in a method for fabricating a semiconductor structure provided in an embodiment of the present application.
  • 6 to 7 are schematic cross-sectional structural views of the structure obtained in step S3 in a method for fabricating a semiconductor structure provided in an embodiment of the present application.
  • FIGS. 8 to 9 are schematic cross-sectional structures of the structure obtained in step S5 in a method for fabricating a semiconductor structure provided in an embodiment of the present application.
  • FIG. 10 to FIG. 11 are schematic cross-sectional structural diagrams of a structure obtained by a method for fabricating a semiconductor structure provided in another embodiment of the present application.
  • FIG. 12 is a schematic cross-sectional structure diagram of the structure obtained in the embodiment shown in FIG. 11 using a conventional process of forming an STI in a substrate and then forming a drift region.
  • FIG. 13 is a schematic cross-sectional structural diagram of the structure obtained in the embodiment shown in FIG. 11 using a conventional process of forming a drift region before forming an STI in a substrate.
  • Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes shown may be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing, the regions shown in the figures are schematic in nature and their shapes are not intended to The actual shapes of the regions of the device are shown and are not intended to limit the scope of this application.
  • a method for preparing a semiconductor structure provided in an embodiment of the present application includes the following steps:
  • Step S1 providing a substrate, forming a first patterned mask layer on the upper surface of the substrate, and etching the substrate based on the first patterned mask layer to form a shallow layer in the substrate groove;
  • Step S2 forming a liner layer on the sidewall and bottom of the shallow trench
  • Step S3 forming a first drift region surrounding the shallow trench and a second drift region directly under the shallow trench in the substrate, wherein the first patterned mask layer is controlled by The thickness of and the energy of ion implantation make the doping concentration of the first drift region and the doping concentration of the second drift region different;
  • Step S4 annealing the obtained structure
  • Step S5 A dielectric layer is formed in the shallow trench, and the dielectric layer fills the shallow trench.
  • a shallow trench is first formed in the substrate, and then a liner layer is formed on the sidewall and bottom of the shallow trench to eliminate the etching of the shallow trench.
  • a protective layer is provided for the subsequent filling of the shallow trench; and then a first drift region surrounding the shallow trench and a first drift region directly below the shallow trench are formed in the substrate.
  • the second drift region is improved by controlling the thickness of the first patterned mask layer and the energy of ion implantation so that the doping concentration of the first drift region is different from the doping concentration of the second drift region.
  • the impurity concentration on the current path can effectively improve the on-resistance of the device.
  • the depth of the second drift region formed directly under the shallow trench is deeper than that of the drift region formed in this part in the traditional semiconductor fabrication process, which can Increasing the cross-sectional area of the overcurrent can further improve the on-resistance of the device.
  • the process of high-temperature trapping in the drift region is simultaneously realized in the process of annealing the liner layer, compared with the traditional process flow, the high-temperature annealing of the liner layer and the high-temperature trapping of the ion implantation region need to be carried out in two separate steps. It is carried out in different process steps, which effectively reduces the steps of the process flow. Therefore, the present application reduces the on-resistance of the semiconductor device while ensuring the high withstand voltage value of the semiconductor device, and reduces the number of process steps, thereby reducing the manufacturing cost of the semiconductor device and improving the yield of the fabricated device.
  • step S1 referring to step S1 in FIG. 1 , FIG. 2 and FIG. 3 , a substrate 10 is provided, and a first patterned mask layer 11 is formed on the upper surface of the substrate 10 . Based on the first pattern The chemical mask layer 11 is used to etch the substrate 10 to form shallow trenches 20 in the substrate 10 .
  • the substrate 10 may include, but is not limited to, a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, and the like.
  • the material of the semiconductor layer is silicon, germanium or silicon germanium.
  • Those skilled in the art can select the type of the substrate according to the type of transistors formed on the substrate 10. Therefore, the type of the substrate 10 should not limit the protection scope of the present application.
  • step S1 may include the following steps:
  • Step S10 forming a first patterned mask layer 11 on the upper surface of the substrate 10 , and an opening (not shown) is formed in the patterned mask layer 11 , and the opening defines the surface of the shallow trench 20 . location and shape.
  • Step S12 based on the first patterned mask layer 11 , the upper surface of the substrate 10 is etched by a dry etching process or a wet etching process, so as to obtain the shallow trench 20 .
  • the parameters of the dry etching process used include: the gas includes fluorocarbon gas, one or more of HBr and Cl2, and a carrier gas, and the fluorocarbon gas includes CF4, CHF3, CH2F2 or CH3F, the carrier gas is an inert gas, such as He, the gas flow is 50sccm-400sccm, and the pressure is 3mtorr-8mtorr.
  • the etching solution used in the wet etching process can be a mixed solution of hydrofluoric acid and hydrogen peroxide.
  • the number of the shallow trenches 20 in step S12 may be multiple, and the depths of the shallow trenches may be the same or different; the widths of the shallow trenches 20 may be the same or different; The depth is less than the thickness of the substrate 10 .
  • forming the first patterned mask layer on the upper surface of the substrate 10 in step S10 may include the following steps:
  • Step S101 forming a first mask layer (not shown) on the upper surface of the substrate 10 ;
  • Step S102 Coating a first photoresist layer (not shown) on the upper surface of the first mask layer (not shown), and performing patterning treatment to form a first patterned photoresist layer (not shown) not shown);
  • Step S103 etching the first mask layer based on the first patterned photoresist layer to form the first patterned mask layer 11 , wherein the first patterned mask layer 11 is formed with a first opening pattern, the first opening pattern defines the position and shape of the shallow trench;
  • Step S104 removing the first patterned photoresist layer 11 .
  • the first patterned mask layer formed may include a hard mask layer, and the hard mask layer may be a single-layer structure or a multi-layer stack structure, and its material may be silicon oxide;
  • the film layer is coated with photoresist, and a series of steps such as exposure and development are performed to form a patterned photoresist layer.
  • the patterned photoresist layer defines the position and shape of the shallow trench, and then based on the patterned light
  • the resist layer etches the hard mask layer to form a patterned mask layer, and then removes the patterned photoresist layer.
  • the patterned photoresist layer may also be retained in the process of forming the first patterned mask layer, and the patterned photoresist layer may be removed after etching the substrate. glue layer.
  • step S2 please refer to step S2 in FIG. 1 and FIG. 4 , a liner layer 30 is formed on the sidewall and bottom of the shallow trench 20 , and the liner layer 30 covers the surface of the shallow trench 20 and the top of the substrate 10 . surface.
  • an oxidation process may be used to form the liner layer 30 on the sidewall and bottom of the shallow trench 20 .
  • the oxidation process includes thermal oxidation process, wet oxidation process or chemical oxidation process.
  • a thermal oxidation process is preferably used to form a liner layer 30 on the surface of the shallow trench 20 and the upper surface of the substrate 10 , and the liner layer 30 may include, but is not limited to, a silicon oxide layer.
  • a thermal oxidation process may be used to form the liner layer 30 on the sidewall and bottom of the shallow trench 20 .
  • the damage to the surface of the substrate 10 during the previous etching process can be repaired.
  • the liner layer 30 can also protect the surface of the substrate 10 in subsequent processes.
  • step S3 may include the following steps:
  • Step S32 forming a second patterned mask layer (not shown) on the upper surface of the substrate, a second opening pattern (not shown) is formed in the second patterned mask layer, and the second opening
  • the graph defines the positions and shapes of the first drift region 41 and the second drift region 42 .
  • Step S34 performing ion implantation on the substrate 10 based on the second patterned mask layer to form the first drift region 41 and the second drift region 42 .
  • step S3 may include the following steps:
  • the structure obtained in FIG. 5 is processed by an ion implantation process, and a first drift region 41 surrounding the shallow trench 20 and a second drift region 42 located directly under the shallow trench are formed in the substrate 10,
  • the doping concentration of the first drift region 41 is different from that of the second drift region 42 by controlling the thickness of the first patterned mask layer 11 and the energy of ion implantation.
  • the doping concentration of the first drift region 41 formed is higher than that of the first drift region 41 .
  • the doping concentration of the second drift region 42 is small. Due to the existence of the shallow trench isolation structure, in the process of forming the second drift region 42 by the ion implantation process, compared with the ion implantation process before the formation of the shallow trench isolation structure, a smaller ion implantation energy can be used to The formed second drift region 42 has a larger depth value, which is beneficial to widen the current path of the drift region.
  • the energy values of the ion implantation for forming the first drift region 41 and the ion implantation for forming the second drift region 42 may be controlled to be different.
  • a low-energy ion implantation step is added to form the third drift region 43 in the second drift region 42 , and the formed third drift region 43 includes the third upper drift region 431 and the third upper drift region 431 located directly under the shallow trench 20 .
  • the lower drift region 432 wherein the third upper drift region 431 is located between the shallow trench 20 and the third lower drift region 432, and the bottom of the third drift region 43 is lower than the bottom of the third lower drift region 432;
  • the first drift region 41 is shielded by the first patterned mask layer on the top surface, so that after the low-energy ion implantation process, the doping concentration of the first drift region 41 is smaller than that of the first drift region 41.
  • the doping concentration of the three upper drift regions 431, the doping concentration of the third upper drift region 431 is greater than the doping concentration of the third lower drift region 432, which is beneficial to reduce the on-resistance and increase the cross-sectional area of the current flow path .
  • 7 shows that the bottom of the first drift region 41 is lower than the bottom of the shallow trench 20 , in other embodiments of the present application, the bottom of the first drift region 41 may also be set higher than or equal to the bottom of the shallow trench 20 .
  • the structure obtained in FIG. 7 may be subjected to high-temperature annealing treatment in step S4 , and at the same time, the process of high-temperature well pushing on the first drift region 41 and the second drift region 42 may be implemented, so that the surface of the liner layer 30 is densified. , the voids in the liner layer 30 are repaired.
  • the annealing process can be a wet annealing process or a dry annealing process; the parameters of the annealing process can include: the temperature is 800°C-1500°C, for example, the annealing temperature can be 800°C, 900°C, 1000°C, 1100°C, 1200°C , 1300°C, 1400°C or 1500°C; the annealing gas includes one or more combinations of H2, O2, N2, Ar and He, and the annealing time is 1.5 hours-2.5 hours, for example, the annealing time can be 1.5 hours, 2.0 hours or 2.5 hours. Wherein, when the annealing gas includes H2 and O2, the annealing process is a wet annealing process.
  • step S5 may include the following steps:
  • Step S52 forming a dielectric material layer 51 on the surface of the backing layer 30 ;
  • Step S54 removing the first patterned mask layer 11 on the upper surface of the substrate 10 and the dielectric material layer 51 on the upper surface of the first patterned mask layer 11 , so as to remain in the shallow
  • the dielectric material layer in the trench is the dielectric layer 50 .
  • the formation process of the dielectric material layer 51 in step S52 may be a fluid chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD) process, a high density plasma deposition (High Density Plasma, HDP) process, plasma enhanced deposition one or more of the processes.
  • FCVD Flowable Chemical Vapor Deposition
  • HDP High Density Plasma
  • the HDP process is preferably used to form the dielectric material layer 51 on the surface of the liner layer 30 .
  • the dielectric material layer 51 includes, but is not limited to, silicon oxide.
  • a chemical mechanical polishing process may be used to remove the first patterned mask layer 11 located on the upper surface of the substrate 10 and the upper surface of the first patterned mask layer 11
  • steam annealing is performed on the dielectric material layer 51 to release stress, densify the dielectric material layer 51, and repair the dielectric material layer 51. gap.
  • the method further includes:
  • Step S62 forming a well region in the substrate, and the well region is located on one side of the first drift region.
  • an ion implantation process can be used to form a well region 43 in the substrate 10 , and the well region 43 is located on one side of the first drift region.
  • Step S64 forming a gate electrode 70 on the upper surface of the substrate 10 ;
  • Step S66 forming a source region 80 , a drain region 60 and a body region 90 in the substrate 10 ; the source region 80 is located in the well region 43 and located on the side of the gate 70 away from the first drift region; the drain region 60 is located in the first drift region and is located on the side of the shallow trench away from the well region 43 ; the body region 90 is located in the well region 43 and located on the side of the source region 80 away from the shallow trench.
  • a semiconductor structure including a substrate 10 and a drift region.
  • the substrate 10 is provided with a shallow trench isolation structure, and the shallow trench isolation structure includes : a shallow trench, a liner layer 30 and a dielectric layer 50, the liner layer 30 is located on the sidewall and bottom of the shallow trench, the dielectric layer 50 is located in the shallow trench and fills the shallow trench.
  • the drift region is located in the substrate 10; the drift region includes a first drift region 41 surrounding the shallow trench, a second drift region 42 directly below the shallow trench, and a second drift region 42 formed in the The third drift region 43 in the second drift region 42, wherein the doping concentration of the third drift region 43 adjacent to the bottom of the shallow trench is greater than the doping concentration of the first drift region.
  • the damage formed in the process of etching the shallow trench is eliminated, and at the same time, a protective layer is provided for the subsequent filling of the shallow trench; the first drift
  • the doping concentration of the region 41 is different from the doping concentration of the second drift region 42, which improves the impurity concentration on the current path and can effectively improve the on-resistance of the device. Comparing FIG. 11 with FIGS.
  • the semiconductor device prepared based on the semiconductor device structure provided by the present application has a higher withstand voltage value and a lower on-resistance; and the semiconductor device structure provided by the present application has fewer process flow steps, so it has a lower on-resistance. low manufacturing cost and high device yield.
  • the formed third drift region 43 includes a third upper drift region 431 and a third lower drift region 432 located directly under the shallow trench, and the third upper drift region 431 Located between the shallow trench and the third lower drift region 432, the doping concentration of the third upper drift region 431 can be set to be greater than the doping concentration of the first doping region 41, so as to ensure the semiconductor device
  • the high withstand voltage value reduces the on-resistance of the device while increasing the cross-sectional area of the current flow path.
  • the semiconductor structure further includes a drain 60 , a gate 70 , a source region 80 , a body region 90 and a well region 43 , and the gate 70 is located on the substrate 10
  • the upper surface of the well region 43 is located in the substrate 10 and is located on one side of the first drift region; the source region 80 is located in the well region 43 and located on the side of the gate 70 away from the first drift region;
  • the drain 60 is located in the first drift region and is located on the side of the shallow trench away from the well region 43; the body region 90 is located in the well region 43 and located on the side of the source region 80 away from the shallow trench .
  • the number of shallow trenches 20 formed in the substrate 10 may be set according to actual needs, and the number of shallow trenches 20 may be one or multiple.
  • the present application provides a method for preparing a semiconductor structure and a semiconductor structure, which eliminates the damage formed in the process of etching the shallow trench during the process of forming the liner layer, and at the same time prevents the subsequent filling of the shallow trench.
  • providing a protective layer then forming a first drift region surrounding the shallow trench and a second drift region directly under the shallow trench in the substrate, and controlling the first patterning mask.
  • the thickness of the layer and the energy of ion implantation make the doping concentration of the first drift region and the doping concentration of the second drift region different to improve the impurity concentration on the current path; it can be set to be formed in the second drift region.
  • the doping concentration of the third drift region in the region adjacent to the bottom of the shallow trench is greater than the doping concentration of the first drift region, which can effectively improve the on-resistance of the device.
  • the depth of the second drift region formed directly under the shallow trench is deeper than that of the drift region formed in this part in the traditional semiconductor fabrication process, which can Increasing the cross-sectional area of the overcurrent can further improve the on-resistance of the device.
  • the process of high-temperature trapping in the drift region is simultaneously realized in the process of annealing the liner layer, compared with the traditional process flow, the high-temperature annealing of the liner layer and the high-temperature trapping of the ion implantation region need to be carried out in two separate steps. It is carried out in different process steps, which effectively reduces the steps of the process flow. Therefore, the present application reduces the on-resistance of the semiconductor device while ensuring the high withstand voltage value of the semiconductor device, and reduces the number of process steps, thereby reducing the manufacturing cost of the semiconductor device and improving the yield of the fabricated device.

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Abstract

一种半导体结构的制备方法，包括：提供衬底，于所述衬底的上表面形成第一图形化掩膜层，基于所述第一图形化掩膜层刻蚀所述衬底，以于所述衬底内形成浅沟槽；于所述浅沟槽的侧壁及底部形成衬垫层；于所述衬底内形成环绕所述浅沟槽四周的第一漂移区及位于所述浅沟槽正下方的第二漂移区，其中，通过控制所述第一图形化掩膜层的厚度及离子注入的能量使得所述第一漂移区的掺杂浓度与所述第二漂移区的掺杂浓度不同；对所得结构进行退火处理；于所述浅沟槽内形成介质层，所述介质层填满所述浅沟槽。本申请能够在保证制成半导体器件的高耐压值的情况下降低器件的导通电阻，并减少了工艺流程步骤。

Description

半导体结构的制备方法及半导体结构 技术领域
本申请涉及半导体制造技术领域，特别是涉及半导体结构的制备方法及半导体结构。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成示例性技术。
随着集成电路制程的快速发展，对半导体产品的集成度的要求越来越高。而随着半导体产品的积集化，半导体器件的尺寸及半导体器件的隔离结构的尺寸也随之减小。现有的中高压BCD工艺为了在获取较高的器件集成度的同时提高器件的击穿电压，往往在漂移区离子注入后增加一步长时间的高温退火，来形成浓度均匀变化的漂移区掺杂。
并且，传统的半导体制造工艺中为了弥补浅沟槽内的多晶硅边缘栅氧耐压不足的问题，一般会采用浅沟槽隔离结构(Shallow Trench Isolation，STI)等作为场板。但是这种工艺做出来的BCD器件，因为开态时的电流需要从场板底部“绕行”，一般都有很大的导通电阻，并且增加了工艺流程，在增加半导体器件制造成本的同时容易降低器件的良品率。
发明内容
根据本申请的各种实施例，提供一种半导体结构的制备方法。
一种半导体结构的制备方法，包括：
提供衬底，于所述衬底的上表面形成第一图形化掩膜层，基于所述第一图形化掩膜层刻蚀所述衬底，以于所述衬底内形成浅沟槽；
于所述浅沟槽的侧壁及底部形成衬垫层；
于所述衬底内形成环绕所述浅沟槽四周的第一漂移区及位于所述浅沟槽正下方的第二漂移区，其中，通过控制所述第一图形化掩膜层的厚度及离子注入的能量使得所述第一漂移区的掺杂浓度与所述第二漂移区的掺杂浓度不同；
对所得结构进行退火处理；
于所述浅沟槽内形成介质层，所述介质层填满所述浅沟槽。
上述半导体结构的制备方法，首先于衬底内形成浅沟槽，然后于所述浅沟槽的侧壁及底部形成衬垫层，以消除刻蚀浅沟槽的过程形成的损伤，同时为后续填充所述浅沟槽时提供保护层；然后于所述衬底内形成环绕所述浅沟槽四周的第一漂移区及位于所述浅沟槽正下方的第二漂移区，并通过控制所述第一图形化掩膜层的厚度及离子注入的能量使得所述第一漂移区的掺杂浓度与所述第二漂移区的掺杂浓度不同，来改善电流路径上的杂质浓度，可以有效改善器件的导通电阻。利用形成浅沟槽隔离结构后的衬底表面具备显著台阶差异的特性，使得形成于浅沟槽正下方第二漂移区的深度较传统半导体制备工艺中该部位形成的漂移区的深度更深，可以增加过电流的横截面积，能够进一步改善器件的导通电阻。由于在对衬垫层进行退火处理的过程中同时实现了对漂移区高温推阱的过程，相对于传统工艺流程中对衬垫层进行高温退火及对离子注入区进行高温推阱需要分别在两个不同的工艺步骤中进行，有效地减少了工艺流程的步骤。因此，本申请在保证制成半导体器件的高耐压值的情况下降低器件的导通电阻，并且减少了工艺流程步骤，在减少半导体器件制造成本的同时提高制成器件的良品率。
一种半导体结构，包括衬底及漂移区，所述衬底内设置有浅沟槽隔离结 构，所述浅沟槽隔离结构包括浅沟槽、衬垫层及介质层，所述衬垫层位于所述浅沟槽的侧壁及底部，所述介质层位于所述浅沟槽内，且填满所述浅沟槽；所述漂移区位于所述衬底内，所述漂移区包括环绕所述浅沟槽四周的第一漂移区、位于所述浅沟槽的正下方的第二漂移区及形成于所述第二漂移区内的第三漂移区，其中，所述第三漂移区临近所述浅沟槽底部区域的掺杂浓度大于所述第一漂移区的掺杂浓度。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1显示为本申请一实施例中提供的一种半导体结构的制备方法的流程图。
图2至图4显示为本申请一实施例中提供的一种半导体结构的制备方法中步骤S1所得结构的截面结构示意图。
图5显示为本申请一实施例中提供的一种半导体结构的制备方法中步骤S2所得结构的截面结构示意图。
图6至图7显示为本申请一实施例中提供的一种半导体结构的制备方法中步骤S3所得结构的截面结构示意图。
图8至图9显示为本申请一实施例中提供的一种半导体结构的制备方法中步骤S5所得结构的截面结构示意图。
图10至图11显示为本申请另一实施例中提供的一种半导体结构的制备方法所得结构的截面结构示意图。
图12显示为图11中所示实施例中采用传统的一种在衬底内形成STI之后形成漂移区的工艺中所得结构的截面结构示意图。
图13显示为图11中所示实施例中采用传统的一种在衬底内形成STI之前形成漂移区的工艺中所得结构的截面结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
这里参阅作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述申请的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本申请的范围。
请参阅图1-图13。需要说明的是，本实施例中所提供的图示仅以示意方式说明本申请的基本构想，虽图示中仅显示与本申请中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
请参阅图1，在本申请的一个实施例中提供的一种半导体结构的制备方法中，包括如下步骤：
步骤S1：提供衬底，于所述衬底的上表面形成第一图形化掩膜层，基于所述第一图形化掩膜层刻蚀所述衬底，以于所述衬底内形成浅沟槽；
步骤S2：于所述浅沟槽的侧壁及底部形成衬垫层；
步骤S3：于所述衬底内形成环绕所述浅沟槽四周的第一漂移区及位于所述浅沟槽正下方的第二漂移区，其中，通过控制所述第一图形化掩膜层的厚度及离子注入的能量使得所述第一漂移区的掺杂浓度与所述第二漂移区的掺 杂浓度不同；
步骤S4：对所得结构进行退火处理；
步骤S5：于所述浅沟槽内形成介质层，所述介质层填满所述浅沟槽。
具体地，于上述实施例中的半导体结构的制备方法中，首先于衬底内形成浅沟槽，然后于所述浅沟槽的侧壁及底部形成衬垫层，以消除刻蚀浅沟槽的过程形成的损伤，同时为后续填充所述浅沟槽时提供保护层；然后于所述衬底内形成环绕所述浅沟槽四周的第一漂移区及位于所述浅沟槽正下方的第二漂移区，并通过控制所述第一图形化掩膜层的厚度及离子注入的能量使得所述第一漂移区的掺杂浓度与所述第二漂移区的掺杂浓度不同，来改善电流路径上的杂质浓度，可以有效改善器件的导通电阻。利用形成浅沟槽隔离结构后的衬底表面具备显著台阶差异的特性，使得形成于浅沟槽正下方第二漂移区的深度较传统半导体制备工艺中该部位形成的漂移区的深度更深，可以增加过电流的横截面积，能够进一步改善器件的导通电阻。由于在对衬垫层进行退火处理的过程中同时实现了对漂移区高温推阱的过程，相对于传统工艺流程中对衬垫层进行高温退火及对离子注入区进行高温推阱需要分别在两个不同的工艺步骤中进行，有效地减少了工艺流程的步骤。因此，本申请在保证制成半导体器件的高耐压值的情况下降低器件的导通电阻，并且减少了工艺流程步骤，在减少半导体器件制造成本的同时提高制成器件的良品率。
在步骤S1中，请参阅图1中的S1步骤、图2及图3，提供衬底10，于所述衬底10的上表面形成第一图形化掩膜层11，基于所述第一图形化掩膜层11刻蚀所述衬底10，以于所述衬底10内形成浅沟槽20。
作为示例，所述衬底10可以包括但不仅限于硅衬底、硅锗衬底及绝缘体上硅衬底等。所述半导体层的材料为硅、锗或硅锗，本领域的技术人员可以根据衬底10上形成的晶体管类型选择衬底类型，因此衬底10的类型不应限制本申请的保护范围。
作为示例，步骤S1可以包括如下步骤：
步骤S10：于衬底10的上表面形成第一图形化掩膜层11，所述图形化掩 膜层11内形成有开口(未示出)，所述开口定义出所述浅沟槽20的位置及形状。
步骤S12：基于所述第一图形化掩膜层11采用干法刻蚀工艺或湿法刻蚀工艺对衬底10的上表面进行刻蚀，以得到浅沟槽20。
在本实施例中，采用的干法刻蚀工艺的参数包括：气体包括碳氟气体、HBr和Cl2中的一种或多种、以及载气，所述碳氟气体包括CF4、CHF3、CH2F2或CH3F，所述载气为惰性气体，例如He，气体流量为50sccm-400sccm，压力为3毫托-8毫托。采用的湿法刻蚀工艺的刻蚀液可以为氢氟酸和双氧水的混合溶液。
作为示例，步骤S12中的浅沟槽20的数量可以为多个，各浅沟槽的深度可以相同，也可以不同；各浅沟槽20的宽度可以相同，也可以不同；浅沟槽20的深度小于衬底10的厚度。
作为示例，步骤S10中于衬底10的上表面形成第一图形化掩膜层可以包括如下步骤：
步骤S101：于所述衬底10的上表面形成第一掩膜层(未图示)；
步骤S102：于所述第一掩膜层(未图示)的上表面涂覆第一光刻胶层(未图示)，并进行图形化处理，以形成第一图形化光刻胶层(未图示)；
步骤S103：基于所述第一图形化光刻胶层刻蚀所述第一掩膜层，以形成所述第一图形化掩膜层11，所述第一图形化掩膜层11内形成有第一开口图形，所述第一开口图形定义出所述浅沟槽的位置及形状；
步骤S104：去除所述第一图形化光刻胶层11。
作为示例，形成的第一图形化掩膜层可以包括硬掩膜层，硬掩膜层可以是单层结构，也可以是多层堆叠结构，其材质可以是氧化硅；之后在所述硬掩膜层上涂覆光刻胶，并经曝光、显影等一系列步骤，形成图形化的光刻胶层，图形化的光刻胶层定义浅沟槽的位置及形状，再基于图形化的光刻胶层刻蚀硬掩膜层以形成图形化掩膜层，然后去除图形化的光刻胶层。当然，在本申请的其他实施例中，也可以在形成第一图形化掩膜层的过程中保留图形 化的光刻胶层，在刻蚀衬底后，再去除所述图形化的光刻胶层。
在步骤S2中，请参阅图1中的S2步骤及图4，于浅沟槽20的侧壁及底部形成衬垫层30，衬垫层30覆盖浅沟槽20的表面及衬底10的上表面。
作为示例，可以采用氧化工艺于浅沟槽20的侧壁及底部形成衬垫层30。所述氧化工艺包括热氧化工艺、湿法氧化工艺或化学氧化工艺。本申请中优选采用热氧化工艺于浅沟槽20的表面及衬底10的上表面形成衬垫层30，衬垫层30可以包括但不仅限于氧化硅层。
作为示例，可以采用热氧化工艺于浅沟槽20的侧壁及底部形成衬垫层30。热氧化形成衬垫层30的过程中能够修复衬底10表面在前序刻蚀工艺过程中受到的损伤。而且，衬垫层30还能够在后续制程中保护衬底10的表面。
作为示例，请参阅图5，步骤S3中可以包括如下步骤：
步骤S32：于衬底的上表面形成第二图形化掩膜层(未图示)，所述第二图形化掩膜层内形成有第二开口图形(未图示)，所述第二开口图形定义出第一漂移区41及第二漂移区42的位置及形状。
步骤S34：基于所述第二图形化掩膜层对所述衬底10进行离子注入，以形成所述第一漂移区41及所述第二漂移区42。
作为示例，请参阅图6-图7，步骤S3中可以包括如下步骤：
对图5中所得结构采用离子注入工艺处理，于所述衬底10内形成环绕所述浅沟槽20四周的第一漂移区41及位于所述浅沟槽正下方的第二漂移区42，其中，通过控制所述第一图形化掩膜层11的厚度及离子注入的能量使得所述第一漂移区41的掺杂浓度与所述第二漂移区42的掺杂浓度不同。
作为示例，请参阅图6，在对图5中所得结构采用离子注入工艺处理的过程中，由于第一图形化掩膜层11的阻挡，使得形成的第一漂移区41的掺杂浓度比第二漂移区42的掺杂浓度小。由于浅沟槽隔离结构的存在，在采用离子注入工艺形成第二漂移区42的过程中，相比于在形成浅沟槽隔离结构之前采用离子注入工艺处理，可以采用较小的离子注入能量来使得形成的第二漂移区42具备较大的深度值，有利于拓宽漂移区电流路径。
作为示例，请参阅图7，可以在对图5中所得结构采用离子注入工艺处理的过程中，控制形成第一漂移区41与形成第二漂移区42的离子注入的能量值不同，例如，可以增加一步低能量的离子注入工序，在第二漂移区42内形成第三漂移区43，并使得形成的第三漂移区43包括位于浅沟槽20正下方的第三上漂移区431及第三下漂移区432，其中，第三上漂移区431位于浅沟槽20与第三下漂移区432之间，第三漂移区43的底部低于第三下漂移区432的底部；而在所述低能量的离子注入工序中，所述第一漂移区41因顶面的第一图形化掩膜层的遮挡，使得在低能量的离子注入工序之后，第一漂移区41的掺杂浓度小于第三上漂移区431的掺杂浓度，第三上漂移区431的掺杂浓度大于第三下漂移区432的掺杂浓度，有利于减小导通电阻的同时增大电流流通路径的横截面积。图7中示意第一漂移区41的底部低于浅沟槽20的底部，在本申请的其他实施例中，也可以设置第一漂移区41的底部高于或等于浅沟槽20的底部。
作为示例，步骤S4中可以对图7中所得结构进行高温退火处理，同时实现了对第一漂移区41及第二漂移区42进行高温推阱的过程，使得衬垫层30表面致密(densify)化，修复衬垫层30中的空隙。退火工艺可以为湿法退火工艺或干法退火工艺；所述退火工艺的参数可以包括：温度为800℃-1500℃，例如退火温度可以为800℃、900℃、1000℃、1100℃、1200℃、1300℃、1400℃或1500℃；退火气体包括H2、O2、N2、Ar和He中的一种或多种组合，退火时间为1.5小时-2.5小时，例如退火时间可以为1.5小时、2.0小时或2.5小时。其中，当退火气体包括H2和O2时，所述退火工艺为湿法退火工艺。
作为示例，请参阅图8及图9，步骤S5中可以包括如下步骤：
步骤S52：于衬垫层30的表面形成介质材料层51；
步骤S54：去除位于所述衬底10的上表面的第一图形化掩膜层11及位于所述第一图形化掩膜层11上表面的所述介质材料层51，使得保留于所述浅沟槽内的所述介质材料层为所述介质层50。
作为示例，参阅图8，步骤S52中介质材料层51的形成工艺可以为流体化学气相沉积(Flowable Chemical Vapor Deposition，FCVD)工艺、高密度等离子沉积(High Density Plasma，HDP)工艺、等离子体增强沉积工艺中的一种或多种。本申请中优选采用HDP工艺于衬垫层30的表面形成介质材料层51。介质材料层51包括但不限于氧化硅。
作为示例，请参阅图10，步骤S54中可以采用化学机械研磨工艺去除位于所述衬底10的上表面的第一图形化掩膜层11及位于所述第一图形化掩膜层11上表面的所述介质材料层51；较佳的，在化学机械研磨之前，对介质材料层51进行水蒸汽退火，以释放应力，并使介质材料层51致密(densify)化，修复介质材料层51中的空隙。
作为示例，请继续参阅图10，于所述浅沟槽内形成所述介质层之后还包括：
步骤S62：于所述衬底内形成阱区，所述阱区位于所述第一漂移区的一侧。
作为示例，请继续参阅图10，可以采用离子注入工艺于衬底10内形成阱区43，阱区43位于所述第一漂移区的一侧。
步骤S64：于所述衬底10的上表面形成栅极70；
步骤S66：于所述衬底10内形成源区80、漏区60及体区90；源区80位于阱区43内，且位于栅极70远离所述第一漂移区的一侧；漏区60位于所述第一漂移区内，且位于所述浅沟槽远离阱区43的一侧；体区90位于阱区43内，且位于源区80远离所述浅沟槽的一侧。
作为示例，请参阅图11，在本申请的一个实施例中提供一种半导体结构，包括衬底10及漂移区，衬底10内设置有浅沟槽隔离结构，所述浅沟槽隔离结构包括：浅沟槽、衬垫层30及介质层50，衬垫层30位于所述浅沟槽的侧壁及底部，所述介质层50位于所述浅沟槽内，且填满所述浅沟槽；漂移区位于所述衬底10内；所述漂移区包括环绕所述浅沟槽四周的第一漂移区41、位于所述浅沟槽的正下方的第二漂移区42及形成于所述第二漂移区42内的 第三漂移区43，其中，所述第三漂移区43临近所述浅沟槽底部区域的掺杂浓度大于所述第一漂移区的掺杂浓度。
具体地，请继续参阅图11，在形成衬垫层30的过程中消除了刻蚀浅沟槽的过程形成的损伤，同时为后续填充所述浅沟槽时提供保护层；所述第一漂移区41的掺杂浓度与所述第二漂移区42的掺杂浓度不同，改善了电流路径上的杂质浓度，可以有效改善器件的导通电阻。对比图11与图12、13可以发现，本申请提供的半导体结构中不仅临近浅沟槽底部的漂移区的掺杂浓度明显比传统工艺中制备半导体结构中对应部位的掺杂浓度更高，而且第二漂移区的深度较传统半导体制备工艺中该部位形成的漂移区的深度更深，有利于拓宽电流路径，能够有效减小器件导通电阻。因此，基于本申请提供的半导体器件结构制备的半导体器件具备较高耐压值的同时具备较低的导通电阻；并且本申请提供的半导体器件结构具备较少的工艺流程步骤，因而具备较低的制造成本且具备较高的器件制成的良品率。
作为示例，请继续参阅图11，形成的所述第三漂移区43包括位于所述浅沟槽正下方的第三上漂移区431及第三下漂移区432，所述第三上漂移区431位于所述浅沟槽与所述第三下漂移区432之间，可以设置所述第三上漂移区431的掺杂浓度大于所述第一掺杂区41的掺杂浓度，在保证半导体器件的高耐压值的情况下降低器件的导通电阻，同时增加电流流通路径的横截面积。
在本申请的一个实施例中，请继续参阅图11，所述半导体结构还包括漏极60、栅极70、源区80、体区90及阱区43，栅极70位于所述衬底10的上表面；阱区43位于衬底10内，且位于所述第一漂移区的一侧；源区80位于阱区43内，且位于栅极70远离所述第一漂移区的一侧；漏极60位于所述第一漂移区内，且位于所述浅沟槽远离阱区43的一侧；体区90位于阱区43内，且位于源区80远离所述浅沟槽的一侧。
作为示例，衬底10内形成的浅沟槽20的数量可以根据实际需要进行设定，浅沟槽20的数量可以为一个，也可以为多个。
综上所述，本申请提供一种半导体结构的制备方法及半导体结构，在形成衬垫层的过程中消除了刻蚀浅沟槽的过程形成的损伤，同时为后续填充所述浅沟槽时提供保护层；然后于所述衬底内形成环绕所述浅沟槽四周的第一漂移区及位于所述浅沟槽正下方的第二漂移区，并通过控制所述第一图形化掩膜层的厚度及离子注入的能量使得所述第一漂移区的掺杂浓度与所述第二漂移区的掺杂浓度不同，来改善电流路径上的杂质浓度；可以设置形成于所述第二漂移区内的第三漂移区临近所述浅沟槽底部区域的掺杂浓度大于所述第一漂移区的掺杂浓度，可以有效改善器件的导通电阻。利用形成浅沟槽隔离结构后的衬底表面具备显著台阶差异的特性，使得形成于浅沟槽正下方第二漂移区的深度较传统半导体制备工艺中该部位形成的漂移区的深度更深，可以增加过电流的横截面积，能够进一步改善器件的导通电阻。由于在对衬垫层进行退火处理的过程中同时实现了对漂移区高温推阱的过程，相对于传统工艺流程中对衬垫层进行高温退火及对离子注入区进行高温推阱需要分别在两个不同的工艺步骤中进行，有效地减少了工艺流程的步骤。因此，本申请在保证制成半导体器件的高耐压值的情况下降低器件的导通电阻，并且减少了工艺流程步骤，在减少半导体器件制造成本的同时提高制成器件的良品率。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (12)

  1. 一种半导体结构的制备方法，其特征在于，包括如下步骤：
    提供衬底，于所述衬底的上表面形成第一图形化掩膜层，基于所述第一图形化掩膜层刻蚀所述衬底，以于所述衬底内形成浅沟槽；
    于所述浅沟槽的侧壁及底部形成衬垫层；
    于所述衬底内形成环绕所述浅沟槽四周的第一漂移区及位于所述浅沟槽正下方的第二漂移区，其中，通过控制所述第一图形化掩膜层的厚度及离子注入的能量使得所述第一漂移区的掺杂浓度与所述第二漂移区的掺杂浓度不同；
    对所得结构进行退火处理；
    于所述浅沟槽内形成介质层，所述介质层填满所述浅沟槽。
  2. 根据权利要求1所述的半导体结构的制备方法，其特征在于，于所述衬底的上表面形成第一图形化掩膜层包括：
    于所述衬底的上表面形成第一掩膜层；
    于所述第一掩膜层的上表面涂覆第一光刻胶层，并进行图形化处理，以形成第一图形化光刻胶层；
    基于所述第一图形化光刻胶层刻蚀所述第一掩膜层，以形成所述第一图形化掩膜层，所述第一图形化掩膜层内形成有第一开口图形，所述第一开口图形定义出所述浅沟槽的位置及形状。
  3. 根据权利要求1所述的半导体结构的制备方法，其特征在于，采用热氧化工艺于所述浅沟槽的侧壁及底部形成氧化成作为所述衬垫层。
  4. 根据权利要求1所述的半导体结构的制备方法，其特征在于，于所述衬底内形成环绕所述浅沟槽四周的第一漂移区及位于所述浅沟槽正下方的第二漂移区的步骤包括：
    于所述衬底的上表面形成第二图形化掩膜层，所述第二图形化掩膜层内形成有第二开口图形，所述第二开口图形定义出所述第一漂移区及所述第二漂移区的位置及形状；
    基于所述第二图形化掩膜层对所述衬底进行离子注入，以形成所述第一漂移区及所述第二漂移区；
    去除所述第二图形化掩膜层。
  5. 根据权利要求1所述的半导体结构的制备方法，其特征在于，于所述浅沟槽内形成所述介质层包括：
    于所述衬垫层的表面形成介质材料层；
    去除位于所述衬底的上表面的第一图形化掩膜层及位于所述第一图形化掩膜层上表面的所述介质材料层，使得保留于所述浅沟槽内的所述介质材料层为所述介质层。
  6. 根据权利要求1所述的半导体结构的制备方法，其特征在于，对所得结构进行退火处理的步骤包括：
    采用湿法退火工艺或干法退火工艺对所得结构进行退火处理的同时，对所述第一漂移区及所述第二漂移区进行高温推阱。
  7. 根据权利要求1所述的半导体结构的制备方法，其特征在于，于所述衬底内形成的所述第一漂移区的掺杂浓度小于所述第二漂移区的掺杂浓度。
  8. 根据权利要求1至7任一项所述的半导体结构的制备方法，其特征在于，通过控制所述第一图形化掩膜层的厚度及离子注入的能量使得所述第一漂移区的掺杂浓度与所述第二漂移区的掺杂浓度不同的步骤包括：
    采用低能量的离子注入工序于所述第二漂移区内形成第三漂移区，并使得所述第三漂移区包括位于所述浅沟槽正下方的第三上漂移区及第三下漂移区，所述第三上漂移区位于所述浅沟槽与所述第三下漂移区之间。
  9. 根据权利要求8所述的半导体结构的制备方法，其特征在于，形成的所述第三上漂移区的掺杂浓度大于所述第三下漂移区的掺杂浓度。
  10. 根据权利要求9所述的半导体结构的制备方法，其特征在于，于所述浅沟槽内形成所述介质层之后还包括：
    于所述衬底内形成阱区，所述阱区位于所述第一漂移区的一侧；
    于所述衬底的上表面形成栅极；
    于所述衬底内形成源区、漏区及体区；所述源区位于所述阱区内，且位于所述栅极远离所述第一漂移区的一侧；所述漏区位于所述第一漂移区内，且位于所述浅沟槽远离所述阱区的一侧；所述体区位于所述阱区内，且位于所述源区远离所述浅沟槽的一侧。
  11. 一种半导体结构，其特征在于，所述半导体结构包括：
    衬底，所述衬底内设置有浅沟槽隔离结构，所述浅沟槽隔离结构包括：浅沟槽、衬垫层及介质层，所述衬垫层位于所述浅沟槽的侧壁及底部，所述介质层位于所述浅沟槽内，且填满所述浅沟槽；
    漂移区，位于所述衬底内，所述漂移区包括环绕所述浅沟槽四周的第一漂移区、位于所述浅沟槽的正下方的第二漂移区及形成于所述第二漂移区内的第三漂移区，其中，所述第三漂移区临近所述浅沟槽底部区域的掺杂浓度大于所述第一漂移区的掺杂浓度。
  12. 根据权利要求11所述的半导体结构，其特征在于，还包括：
    栅极，位于所述衬底的上表面；
    阱区，位于所述衬底内，且位于所述第一漂移区的一侧；
    源区，位于所述阱区内，且位于所述栅极远离所述第一漂移区的一侧；
    漏极，位于所述第一漂移区内，且位于所述浅沟槽远离所述阱区的一侧；
    体区，位于所述阱区内，且位于所述源区远离所述浅沟槽的一侧。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867979A (zh) * 2014-02-26 2015-08-26 丰田自动车株式会社 半导体装置
CN106653855A (zh) * 2016-12-07 2017-05-10 杰华特微电子（杭州）有限公司 横向双扩散晶体管及其漂移区的制造方法
CN107785423A (zh) * 2016-08-30 2018-03-09 中芯国际集成电路制造(北京)有限公司 一种ldmos晶体管结构
CN110176454A (zh) * 2018-02-20 2019-08-27 马克西姆综合产品公司 多晶体管器件
CN110571263A (zh) * 2018-06-06 2019-12-13 艾普凌科有限公司 半导体装置及其制造方法
CN110649100A (zh) * 2014-03-06 2020-01-03 德州仪器公司 具有经改进rds*cgd的ldmos晶体管及形成所述ldmos晶体管的方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102664181B (zh) * 2012-05-15 2014-10-22 上海先进半导体制造股份有限公司 一种超高压bcd半导体工艺以及超高压bcd器件
CN107564816B (zh) * 2016-06-30 2020-05-08 中芯国际集成电路制造(上海)有限公司 Ldmos晶体管及其形成方法
CN106952961A (zh) * 2017-04-28 2017-07-14 杰华特微电子（杭州）有限公司 Mos器件及其漂移区的制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867979A (zh) * 2014-02-26 2015-08-26 丰田自动车株式会社 半导体装置
CN110649100A (zh) * 2014-03-06 2020-01-03 德州仪器公司 具有经改进rds*cgd的ldmos晶体管及形成所述ldmos晶体管的方法
CN107785423A (zh) * 2016-08-30 2018-03-09 中芯国际集成电路制造(北京)有限公司 一种ldmos晶体管结构
CN106653855A (zh) * 2016-12-07 2017-05-10 杰华特微电子（杭州）有限公司 横向双扩散晶体管及其漂移区的制造方法
CN110176454A (zh) * 2018-02-20 2019-08-27 马克西姆综合产品公司 多晶体管器件
CN110571263A (zh) * 2018-06-06 2019-12-13 艾普凌科有限公司 半导体装置及其制造方法

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