WO2022032863A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2022032863A1
WO2022032863A1 PCT/CN2020/121851 CN2020121851W WO2022032863A1 WO 2022032863 A1 WO2022032863 A1 WO 2022032863A1 CN 2020121851 W CN2020121851 W CN 2020121851W WO 2022032863 A1 WO2022032863 A1 WO 2022032863A1
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Prior art keywords
transistor
light
oxide
node
layer
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PCT/CN2020/121851
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English (en)
French (fr)
Inventor
陈碧
Original Assignee
武汉华星光电半导体显示技术有限公司
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Priority to US17/266,971 priority Critical patent/US20220310731A1/en
Publication of WO2022032863A1 publication Critical patent/WO2022032863A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a display device.
  • Polysilicon thin film transistors have high mobility, so in the existing pixel driving circuits of OLED display panels, low temperature polysilicon (LTPS) thin film transistors are usually used to drive pixel light emission.
  • LTPS low temperature polysilicon
  • OLED display panels using low temperature polysilicon thin film transistors have lower refresh rates. Under the frequency, there will be a problem that the stability of the light-emitting stage is weak, resulting in a poor display effect.
  • the existing display panel has the technical problem that the stability of the pixel driving circuit is weak, and needs to be improved.
  • the present application provides a display panel, comprising a plurality of light-emitting devices arranged in an array and a pixel driving circuit for driving the light-emitting devices to emit light, the pixel driving circuit comprising:
  • a first initialization transistor configured to input an initialization signal to the first node under the control of the first scan signal
  • a switch transistor for inputting a data signal to the second node under the control of the second scan signal
  • a driving transistor for driving the light-emitting device to emit light under the control of the potentials of the first node and the second node;
  • a compensation transistor connected to the driving transistor through the first node and the third node, and used for compensating the threshold voltage of the driving transistor under the control of the third scan signal;
  • a second initialization transistor configured to input an initialization signal to the anode of the light-emitting device under the control of the third scan signal
  • a first light-emitting control transistor connected to the driving transistor through the second node, for turning on the current flowing from the high-potential signal line of the power supply to the driving transistor under the control of the light-emitting control signal;
  • a second light-emitting control transistor connected to the driving transistor through the third node, and configured to turn on the current flowing from the driving transistor to the anode of the light-emitting device under the control of the light-emitting control signal;
  • a storage capacitor connected to the drive transistor through the first node, and connected to the power supply high-potential signal line through the fourth node, for storing the data signal
  • the compensation transistor, the first initialization transistor and the second initialization transistor are oxide transistors, the switching transistor, the driving transistor, the first light-emitting control transistor and the second light-emitting control transistor For low temperature polysilicon transistors.
  • the compensation transistor, the first initialization transistor and the second initialization transistor are N-type transistors
  • the second light-emitting control transistor is a P-type transistor.
  • the display panel includes a substrate, a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a first A source-drain layer and a second source-drain layer, the first semiconductor layer forms the polysilicon active layer of each low temperature polysilicon transistor, and the second semiconductor layer forms the oxide active layer of each oxide transistor.
  • the projections of the polysilicon active layer and the oxide active layer on the substrate at least partially overlap.
  • the first metal layer is patterned to form a top gate of each oxide transistor, the oxide active layer forms a channel region of each oxide transistor, and the second metal layer is patterned A bottom gate of each oxide transistor is formed, and the projection of the channel region on the substrate falls within the projection range of the corresponding bottom gate on the substrate.
  • the first metal layer is patterned to form a first electrode plate of the storage capacitor
  • the second metal layer is patterned to form a second electrode plate of the storage capacitor.
  • the first source/drain layer is patterned to form a power high potential signal line
  • the second source/drain layer is patterned to form a first blocking member
  • the first blocking member and the The power high potential signal line is connected
  • the projection of the first blocking member on the first metal layer covers at least a part of the first plate of the storage capacitor.
  • the projection of the first blocking member on the oxide active layer covers the channel region of the compensation transistor and the channel region of the first initialization transistor.
  • the second source-drain layer is patterned to form a second blocking member, the second blocking member is connected to the second light-emitting control transistor and the anode of the light-emitting device, and
  • the projection of the oxide active layer covers the channel region of the second initialization transistor.
  • the present application also provides a display device, comprising:
  • a first initialization transistor configured to input an initialization signal to the first node under the control of the first scan signal
  • a switch transistor for inputting a data signal to the second node under the control of the second scan signal
  • a driving transistor for driving the light-emitting device to emit light under the control of the potentials of the first node and the second node;
  • a second initialization transistor configured to input an initialization signal to the anode of the light-emitting device under the control of the third scan signal
  • the first initialization transistor and the second initialization transistor are oxide transistors, and the switch transistor and the second initialization transistor are transistors of different types.
  • the switching transistor is a low temperature polysilicon transistor.
  • the switching transistor is a P-type transistor
  • the first initialization transistor and the second initialization transistor are N-type transistors.
  • the display device includes a substrate, a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a first A source-drain layer and a second source-drain layer, the first semiconductor layer forms a polysilicon active layer of the low temperature polysilicon transistor, and the second semiconductor layer forms an oxide active layer of the oxide transistor.
  • the projections of the polysilicon active layer and the oxide active layer on the substrate at least partially overlap.
  • the second metal layer is patterned to form the bottom gate of each oxide transistor
  • the third metal layer is patterned to form the top gate of each oxide transistor
  • the oxide active layer is formed
  • the projection of the channel region on the substrate falls within the projection range of the corresponding bottom gate on the substrate.
  • the display device further includes a storage capacitor, the storage capacitor is connected to the driving transistor through the first node, and is connected to the power supply high potential signal line through the fourth node, used for The data signal is stored, the first metal layer is patterned to form a first electrode plate of the storage capacitor, and the second metal layer is patterned to form a second electrode plate of the storage capacitor.
  • the first source-drain layer is patterned to form a power high potential signal line
  • the second source-drain layer is patterned to form a first blocking member
  • the first blocking member and the The power high potential signal line is connected
  • the projection of the first blocking member on the first metal layer covers at least a part of the first plate of the storage capacitor.
  • the projection of the first blocking member on the oxide active layer covers the channel region of the first initialization transistor.
  • the display device further includes:
  • a first light-emitting control transistor connected to the driving transistor through the second node, for turning on the current flowing from the high-potential signal line of the power supply to the driving transistor under the control of the light-emitting control signal;
  • a second light-emitting control transistor connected to the driving transistor through the third node, and configured to turn on the current flowing from the driving transistor to the anode of the light-emitting device under the control of the light-emitting control signal;
  • the driving transistor, the first light emission control transistor and the second light emission control transistor are polysilicon transistors.
  • the second source and drain layers are patterned to form a second blocking member, the second blocking member is connected to the second light-emitting control transistor and the anode of the light-emitting device, and the second blocking member is connected to the anode of the light-emitting device.
  • the projection of the oxide active layer covers the channel region of the second initialization transistor.
  • the display device further includes a compensation transistor, and the compensation transistor is connected to the driving transistor through the first node and the third node, and is used for compensation under the control of the third scan signal.
  • the threshold voltage of the driving transistor, and the compensation transistor is an oxide transistor.
  • the projection of the first blocking member on the oxide active layer covers the channel region of the compensation transistor.
  • the present application provides a display panel and a display device.
  • the display panel includes a plurality of light-emitting devices arranged in an array and a pixel driving circuit for driving the light-emitting devices to emit light.
  • the pixel driving circuit includes: a first initialization transistor for Under the control of the first scan signal, an initialization signal is input to the first node; a switch transistor is used to input a data signal to the second node under the control of the second scan signal; a drive transistor is used to input a data signal to the first node Under the control of the potential of the second node and the second node, the light-emitting device is driven to emit light; the compensation transistor is connected to the driving transistor through the first node and the third node, and is used for compensation under the control of the third scan signal.
  • the second initialization transistor is used for inputting an initialization signal to the anode of the light-emitting device under the control of the third scan signal;
  • the first light-emitting control transistor is connected to the light-emitting device through the second node
  • the driving transistor is connected to the driving transistor, and is used to turn on the current flowing to the driving transistor from the high-potential signal line of the power supply under the control of the light-emitting control signal;
  • the second light-emitting control transistor is connected to the driving transistor through the third node, using Under the control of the light-emitting control signal, the current flowing from the driving transistor to the anode of the light-emitting device is turned on;
  • the storage capacitor is connected to the driving transistor through the first node, and is connected to the power supply through the fourth node connected to a high-potential signal line for storing the data signal;
  • the compensation transistor, the first initialization transistor and the second initialization transistor are oxide transistors, the switch transistor, the drive transistor, the The first light-
  • the present application can utilize the low leakage current characteristics of oxide transistors and the high mobility characteristics of low temperature polysilicon transistors at the same time , thereby making the pixel driving circuit more stable and improving the display effect of the display panel.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit in a display panel according to an embodiment of the present application.
  • FIG. 2 is a timing diagram of each signal in a pixel driving circuit in a display panel according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of each film layer in a display panel according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a planar superposition structure of each film layer in a display panel according to an embodiment of the present application.
  • FIG. 5 is a schematic plan view of a first semiconductor layer in a display panel according to an embodiment of the present application.
  • FIG. 6 is a schematic plan view of a first metal layer in a display panel according to an embodiment of the present application.
  • FIG. 7 is a schematic plan view of a second metal layer in a display panel according to an embodiment of the present application.
  • FIG. 8 is a schematic plan view of a second semiconductor layer in a display panel according to an embodiment of the present application.
  • FIG. 9 is a schematic plan view of a third metal layer in a display panel according to an embodiment of the present application.
  • FIG. 10 is a schematic plan view of a first source and drain layer in a display panel according to an embodiment of the present application.
  • FIG. 11 is a schematic plan view of a second source and drain layer in a display panel according to an embodiment of the present application.
  • Embodiments of the present application provide a display panel and a display device, which are used to alleviate the technical problem of poor stability of a pixel driving circuit in an existing display panel.
  • the present application provides a display panel, which includes a plurality of light-emitting devices D1 arranged in an array and a pixel driving circuit for driving the light-emitting devices D1 to emit light.
  • the pixel driving circuit includes:
  • the first initialization transistor T4 is used for inputting the initialization signal VI to the first node Q under the control of the first scan signal Scan 1;
  • a switch transistor T2 for inputting the data signal Vdata to the second node A under the control of the second scan signal Scan 2;
  • a driving transistor T1 for driving the light-emitting device D1 to emit light under the control of the potentials of the first node Q and the second node A;
  • the compensation transistor T3 is connected to the driving transistor T1 through the first node Q and the third node B, and is used for compensating the threshold voltage of the driving transistor T1 under the control of the third scan signal Scan 3;
  • the second initialization transistor T7 is used to input the initialization signal VI to the anode of the light-emitting device under the control of the third scan signal Scan 3;
  • the first light-emitting control transistor T5 is connected to the driving transistor T1 through the second node A, and is used to turn on the current flowing from the high-potential signal line of the power supply to the driving transistor T1 under the control of the light-emitting control signal EM;
  • the second light-emitting control transistor T6 is connected to the driving transistor T1 through the third node B, and is used to turn on the current flowing from the driving transistor T1 to the anode C of the light-emitting device D1 under the control of the light-emitting control signal EM;
  • the storage capacitor C1 is connected to the driving transistor T1 through the first node Q, and is connected to the power supply high potential signal line through the fourth node D, for storing the data signal Vdata;
  • the compensation transistor T3, the first initialization transistor T4 and the second initialization transistor T7 are oxide transistors, and the switching transistor T2, the driving transistor T1, the first light emission control transistor T5 and the second light emission control transistor T6 are low temperature polysilicon transistors.
  • the gate of the first initialization transistor T4 is connected to the first scan signal Scan 1 , the first electrode is connected to the initialization signal VI, and the second electrode is connected to the first node Q.
  • the gate of the switching transistor T2 is connected to the second scan signal Scan 2 , the first electrode is connected to the data signal Vdata, and the second electrode is connected to the second node A.
  • the gate of the driving transistor T1 is connected to the first node Q, the first electrode is connected to the second node A, and the second electrode is connected to the third node B.
  • the gate of the compensation transistor T3 is connected to the third scan signal Scan 3 , the first electrode is connected to the third node B, and the second electrode is connected to the first node Q.
  • the gate of the second initialization transistor T7 is connected to the third scan signal Scan 3, the first electrode is connected to the initialization signal VI, and the second electrode is connected to the anode C of the light emitting device D1.
  • the gate of the first light-emitting control transistor T5 is connected to the light-emitting control signal EM, the second electrode is connected to the power high potential signal Vdd, and the first electrode is connected to the second node A.
  • the gate of the second light-emitting control transistor T6 is connected to the light-emitting control signal EM, the first electrode is connected to the third node B, the second electrode is connected to the anode C of the light-emitting device D1, and the cathode of the light-emitting device D1 is connected to the power low potential signal Vss.
  • the first plate of the storage capacitor C1 is connected to the power high potential signal Vdd, and the second plate is connected to the first node Q.
  • one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode.
  • FIG. 2 it is a timing diagram of the pixel driving circuit of the present application in the display stage.
  • the compensation transistor T3, the first initialization transistor T4 and the second initialization transistor T7 are N-type transistors
  • the switching transistor T2 the driving transistor T1, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are P-type transistor.
  • the second scan signal Scan 2 is at a high level
  • the switching transistor T2 is turned off
  • the third scan signal Scan 3 is at a low level
  • the compensation transistor T3 and the second initialization transistor T7 are turned off
  • the light-emitting control signal EM is at a high level
  • the third scan signal Scan 3 is at a low level.
  • a light-emitting control signal T5 and a second light-emitting control signal T6 are turned off
  • the first scan signal Scan1 is high
  • the first initialization transistor T4 is turned on
  • an initialization signal is input to the first node Q to pull down the potential of the first node Q.
  • the first scan signal Scan 1 is at a low level
  • the first initialization transistor T4 is turned off
  • the second scan signal Scan 2 is at a low level
  • the switch transistor T2 is turned on
  • the third scan signal Scan 3 is at a high level
  • compensation The transistor T3 and the second initialization transistor T7 are turned on. Since the potential of the first node Q is low, the gate of the driving transistor T1 and the second electrode are short-circuited after the compensation transistor T3 is turned on. A voltage difference is generated between the gate electrode and the first electrode. At this time, the driving transistor T1 is turned on, and the switching transistor T2 inputs the data signal Vdata to the second node A.
  • the data signal Vdata contains the compensated threshold voltage and is input to the driving transistor.
  • the gate of T1 thereby compensating for the threshold voltage deviation of the driving transistor T1.
  • the written data signal Vdata charges the first node Q through the driving transistor T1 until the voltage of the first node Q becomes Vdata-Vth, and the driving transistor T1 is turned off.
  • the second initialization transistor T7 since the second initialization transistor T7 is turned on, the anode of the light emitting device D1 receives the initialization signal and is reset.
  • the light-emitting control signal EM is at a low level
  • the first light-emitting control signal T5 and the second light-emitting control signal T6 are turned on
  • the current of the high-potential signal line VDD of the power supply is turned on to flow to the driving transistor T1
  • the driving transistor T1 flows to the light-emitting device
  • the light-emitting device D1 works and emits light under the action of the driving current I.
  • the compensation transistor T3, the first initialization transistor T4 and the second initialization transistor T7 are oxide transistors
  • the switching transistor T2, the driving transistor T1, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are low temperature transistors
  • the compensation transistor T3 in the light-emitting stage t3, can keep the potential of the first node Q and the third node B stable by using the low leakage current characteristics of the oxide thin film transistor, and the first initialization transistor T4 can keep the first node Q.
  • the potential is stable, and the second initialization transistor T7 can keep the potential of the anode C of the light-emitting device D1 stable, so as to alleviate the light-emitting brightness change caused by the leakage current of the light-emitting device D1, especially in the case of a lower refresh frequency. question.
  • the response speed of the switching transistor T2 and the driving transistor T1 is fast, so that the data can be written quickly, avoiding the long opening time.
  • the present application adopts a pixel driving circuit in which low-temperature polysilicon transistors and oxide transistors are combined with each other, and makes full use of the high mobility and fast driving speed of low-temperature polysilicon transistors and the low leakage current characteristics of oxide transistors, which can make the display of the display panel more stable. and lower power consumption.
  • FIG. 3 a schematic diagram of a film layer structure of a display panel according to an embodiment of the present application is shown.
  • the display panel includes a substrate 100 , a first semiconductor layer 300 , a first metal layer 400 , a second metal layer 500 , a second semiconductor layer 600 , a third metal layer 700 , and a first source and drain layer, which are stacked from bottom to top. 800 and a second source and drain layer 900, wherein the first semiconductor layer 300 forms the polysilicon active layer of each low temperature polysilicon transistor, and the second semiconductor layer 600 forms the oxide active layer of each oxide transistor.
  • the transistor on the left in FIG. 3 has a film structure of a low temperature polysilicon transistor
  • the transistor on the right has a film structure of an oxide transistor
  • the switching transistor T2 the driving transistor T1, the first light-emitting control transistor T5 and the second light-emitting control transistor in the pixel driving circuit
  • the structure of the transistor T6 is the same as that of the transistor on the left side of FIG. 3
  • the structures of the compensation transistor T3 , the first initialization transistor T4 and the second initialization transistor T7 are the same as those of the transistor on the right side of FIG. 3 .
  • FIG. 4 is a schematic plan view of each film layer in a display panel provided in an embodiment of the present application
  • FIG. 5 to FIG. 11 are schematic plan views of each film layer, respectively.
  • the film structure of each transistor in the pixel driving circuit will be described in detail below with reference to FIG. 3 to FIG. 11 .
  • the substrate 100 may include a rigid substrate or a flexible substrate, when the substrate 100 is a rigid substrate, the material may be metal or glass, and when the substrate 100 is a flexible substrate, the material may include acrylic At least one of resin, methacrylic resin, polyisoprene, vinyl resin, epoxy-based resin, polyurethane-based resin, cellulose resin, siloxane resin, polyimide-based resin, polyamide-based resin kind.
  • the present application does not limit the material of the substrate 100 .
  • a buffer layer 200 is usually formed on the substrate 100, and the buffer layer 200 may include inorganic materials, such as at least one of silicon nitride or silicon oxide, to prevent foreign impurities under the substrate 100 from infiltrating into the transistors in the upper layer, And improve the bonding strength between the substrate 100 and the upper film layer.
  • the buffer layer 200 may be omitted according to the type of the substrate 100, process conditions, and the like.
  • the first semiconductor layer 300 is patterned to form a polysilicon active layer of the switching transistor T2 , the driving transistor T1 , the first light emission control transistor T5 and the second light emission control transistor T6 , and each transistor
  • the polycrystalline silicon active layers are connected to each other, and the polycrystalline silicon active layer can be formed by crystallization of amorphous silicon, and the crystallization methods can include rapid thermal annealing (RTA), solid phase crystallization (SPC), excimer laser annealing (ELA) , Metal Induced Crystallization (MIC), Metal Induced Lateral Crystallization (MILC) and Sequential Lateral Solidification (SLS).
  • RTA rapid thermal annealing
  • SPC solid phase crystallization
  • EVA excimer laser annealing
  • MIC Metal Induced Crystallization
  • MILC Metal Induced Lateral Crystallization
  • SLS Sequential Lateral Solidification
  • a first gate insulating layer 10 is formed on the first semiconductor layer 300 , and the material of the first gate insulating layer 10 includes silicon oxide.
  • the first metal layer 400 is formed on the first gate insulating layer 10 , and is patterned to form a plurality of first layer scanning signal lines and the first electrode plate of the storage capacitor. 403.
  • the scan signal lines of the first layer specifically include a first scan signal line 401 and a second scan signal line 402, wherein the second scan signal line 402 is a light emission control signal line.
  • the projection of the first scanning signal line 401 and the polysilicon active layer on the substrate 100 has an intersection area, and the part where the first scanning signal line 401 is located in the intersecting area forms the gate of the switching transistor T2, and the polysilicon active layer is located in the intersection area.
  • the part of the intersecting region forms the channel region of the switching transistor T2, the second scanning signal line 402 and the projection of the polysilicon active layer on the substrate 100 have an intersecting region, and the part of the second scanning signal line 402 located in the intersecting region respectively.
  • the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 are formed, and the part of the polysilicon active layer located in the intersection area forms the channel region of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 respectively.
  • the channel region of the storage capacitor, the projection of the first plate 403 of the storage capacitor and the polysilicon active layer on the substrate 100 also has an intersection area, and the part of the first plate 403 of the storage capacitor located in this intersection area forms the driving transistor T1.
  • the gate, and the portion of the polysilicon active layer in the intersecting region forms the channel region of the driving transistor T1.
  • Parts of the polysilicon active layer other than the above-mentioned channel regions are ion-doped to form source regions and drain regions of each low-temperature polysilicon transistor.
  • the connection between the second electrode of the switching transistor T2, the second electrode of the first light-emitting control transistor T5, the first electrode of the driving transistor T1, and the driving transistor are realized by ion doping and the intersecting arrangement of the scanning signal lines of the first layer.
  • the material of the first metal layer 400 may include molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium At least one metal of (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), and tungsten (W).
  • a second gate insulating layer 20 is formed on the first metal layer 400 , and the material of the second gate insulating layer 20 includes silicon nitride.
  • the second metal layer 500 is formed on the second gate insulating layer 20 , and a plurality of second layer scanning signal lines and the second electrode plate 505 of the storage capacitor are formed by patterning.
  • the two-layer scan signal lines specifically include a third scan signal line 501 , a third scan signal line 502 , a fifth scan signal line 503 and a sixth scan signal line 504 , wherein the third scan signal line 501 is an initialization signal line VI. It should be noted that in FIG.
  • the uppermost third scanning signal line 501 is the scanning signal line in the pixel driving circuit corresponding to the previous light-emitting device, and the lowermost third scanning signal line 501 is the pixel corresponding to the next light-emitting device. Scanning signal lines in the drive circuit.
  • the material of the second metal layer 500 may include molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium At least one metal of (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), and tungsten (W).
  • a first interlayer dielectric layer 30 is formed on the second metal layer 500 , and the material includes at least one of silicon nitride and silicon oxide.
  • the second semiconductor layer 600 is formed on the first interlayer dielectric layer 30 , and the oxides of the compensation transistor T3 , the first initialization transistor T4 and the second initialization transistor T7 are formed by patterning. source layer, wherein the oxide active layers of the compensation transistor T3 and the first initialization transistor T4 are connected to each other, and the oxide active layer of the second initialization transistor T7 is independent from other transistors.
  • the oxide active layer material may include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium oxide At least one of zinc tin (IZTO).
  • a third gate insulating layer 40 is formed on the second semiconductor layer 600 , and the material of the third gate insulating layer 40 includes silicon oxide.
  • the third metal layer 700 is formed on the third gate insulating layer 40 , and is patterned to form a plurality of third layer scan signal lines, including the seventh scan signal line 701 and the eighth scan signal line 701 .
  • the portion of the eighth scan signal line 702 located in the intersection area forms the top gate of the compensation transistor T3
  • the portion of the oxide active layer located in the intersection area forms the channel region of the compensation transistor T3
  • the projection of 703 and the oxide active layer on the substrate 100 also has an intersection area, the portion of the ninth scan signal line 703 located in the intersection area forms the top gate of the second initialization transistor T7, and the oxide active layer is located at the intersection Part of the region forms the channel region of the second initialization transistor T7.
  • the parts of the oxide active layer other than the above-mentioned channel regions form the source and drain regions of the oxide transistors.
  • the material of the third metal layer 700 may include molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium At least one metal of (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), and tungsten (W).
  • a second interlayer dielectric layer 50 is formed on the third metal layer 700 , and the material includes at least one of silicon nitride and silicon oxide.
  • a first source and drain layer 800 is formed on the second interlayer dielectric layer 50 , and patterned to form a data signal line 801 , a power high potential signal line 802 , and a first connection line 803 , a second connection line 804 , a third connection line 805 , a fourth connection line 806 and a fourth connection line 807 .
  • the material of the first source and drain layer 800 includes at least one of elements or alloys of Mo, Al, Cu, Ti and the like.
  • the data signal line 801 is connected to the polysilicon active layer of the switching transistor T2 through the first via hole 001; the power high potential signal line 802 is connected to the polysilicon active layer of the first light-emitting control signal line T5 through the second via hole 002,
  • the three vias 003 are connected to the first plate 505 of the storage capacitor C1 and need to pass through the capacitor vias 5051 formed in the second plate 505 of the storage capacitor during connection;
  • the first connection line 803 is connected to the fourth via 004
  • the oxide active layer of the first initialization transistor T4 is connected to form the first electrode of the first initialization transistor T4, and is then connected to the initialization signal line VI through the fifth via hole 005;
  • the second connection line 804 is connected to the initialization signal line VI through the sixth via hole 006.
  • the gate of the driving transistor T1 is connected to the second plate 403 of the storage capacitor C1, and is connected to the oxide active layer of the first initialization transistor T4 through the seventh via hole 007 to form the second electrode of the first initialization transistor T4;
  • the three connecting lines 805 are connected to the polysilicon active layers of the driving transistor T1 and the second light-emitting control transistor T6 through the eighth via hole 008 to form the second electrode of the driving transistor T1 and the first electrode of the second light-emitting control transistor T6.
  • the nine via holes 009 are connected to the oxide active layer of the compensation transistor T3 to form the second electrode of the compensation transistor T3; the fourth connection line 806 is connected to the polysilicon active layer of the second light-emitting control transistor T6 through the tenth via hole 010, The second electrode of the second light-emitting control transistor T6 is formed, which is connected to the oxide active layer of the second initialization transistor T7 through the eleventh via hole 011 to form the second electrode of the second initialization transistor T7; the fifth connection line 807 passes through The twelfth via hole 012 is connected to the oxide active layer of the second initialization transistor T7 to form the first electrode of the second initialization transistor T7, and is then connected to the initialization signal line VI through the thirteenth via hole 013.
  • a passivation layer 60 is formed on the third metal layer 800 , and the material of the passivation layer is usually at least one of silicon nitride (SiNx) and silicon oxide (SiOx).
  • a first planarization layer 70 is formed on the passivation layer 60 , and the material of the first planarization layer 70 is usually polyimide.
  • a second source and drain layer 900 is formed on the passivation layer 70 , and the material of the second source and drain layer 900 includes simple substances or alloys such as Mo, Al, Cu, Ti, etc. at least one of them.
  • the second source-drain layer 900 is patterned to form a first blocking member 901, the first blocking member 901 is connected to the power high potential signal line 802, and the projection of the first blocking member 901 on the first metal layer 400 covers at least part of the storage capacitor The first plate 403 .
  • the first blocking member 901 is connected to the power high potential signal line 802 through the fourteenth via hole 014.
  • the projection of the first blocking member 901 on the first metal layer 400 covers at least part of the first plate 403 of the storage capacitor, Should cover the area, a coupling capacitance can be generated between the first blocking member 901 and the first plate 403 of the storage capacitor, and the coupling capacitance and the storage capacitor are superimposed, so that the ability of the circuit to store charges is increased, and the first plate 403 of the storage capacitor is again As the gate of the driving transistor T1, the first blocking member 901 can improve the stability of the gate of the driving transistor T1, that is, the first node Q.
  • the influence of the light emitting device D1 makes the brightness change of the light emitting device D1 smaller, and improves the stability of the pixel driving circuit.
  • the projection of the first blocking member 901 on the first metal layer 400 covers the entire area of the first plate 403 of the storage capacitor, the generated coupling capacitance is the largest, and the effect of improving stability is the best.
  • the projection of the first blocking member 901 on the oxide active layer covers the channel region of the compensation transistor T3 and the channel region of the first initialization transistor T4. Since the oxide active layer is sensitive to light, the first blocking member 901 has The material is an opaque metal, so it can block the ambient light incident from the side of the first blocking member 901 away from the oxide active layer, prevent it from interfering with the compensation transistor T3 and the first initialization transistor T4, and improve the performance of each oxide transistor. stability.
  • the material of the first blocking member 901 is metal, it can be used as a hydrogen blocking layer to block the influence of the hydrogen ions generated by the upper film layer on the oxide active layer during the manufacturing process, so as to avoid the threshold voltage shift of the oxide transistor, and further Improve the stability of the circuit.
  • the first blocking member 901 corresponds to the driving transistor T1, the compensation transistor T3 and the first initialization transistor T4, and can simultaneously function as a light shielding layer, a hydrogen blocking layer and a coupling capacitor to jointly improve the stability of the pixel driving circuit.
  • the process is simple and the cost is low.
  • the second source-drain layer 900 is further patterned to form a second blocking member 902, and the second blocking member 902 forms the second drain of the second light-emitting control transistor T6, which is connected to the second light-emitting control transistor T6 through the fifteenth via hole 015.
  • the second electrode is connected to the anode of the light emitting device D1 through the sixteenth via hole 016, and the projection on the oxide active layer covers the channel region of the second initialization transistor T7.
  • the second blocking member 902 can block the ambient light incident from the side of the second blocking member 902 away from the oxide active layer, preventing it from causing interference to the second initialization transistor T7, and improving the stability of the second initialization transistor T7 , can also be used as a hydrogen blocking layer to block the influence of the hydrogen ions generated by the upper film layer on the oxide active layer during the process, and further improve the stability of the circuit.
  • the second blocking member 902 can simultaneously serve as the second drain, the light shielding layer and the hydrogen blocking layer of the second light-emitting control transistor T6, which together improve the stability of the pixel driving circuit, and the fabrication process is simple and the cost is low.
  • a second planarization layer 80 is formed on the second source and drain layers 900 , and the material of the second planarization layer 80 is usually polyimide.
  • the light emitting device anode 1000 is formed in the second planarization layer 80 and includes a single layer or a stack of a high work function conductive material and a reflective material, wherein the high work function conductive material may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium oxide (In 2 O 3 ), etc.
  • the reflective material may include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), lithium (Li), calcium (Ca) or a mixture thereof.
  • the pixel definition layer 90 is formed on the anode 1000 of the light emitting device, and includes a plurality of opening regions exposing the anode 1000.
  • the material of the pixel definition layer 90 may include photoresist, polyimide resin, acrylic resin, silicon compound or polyamide. Acrylic resin, etc.
  • the organic light-emitting layer 1010 is formed in the opening area, and the cathode of the light-emitting device (not shown in the figure) is located on the organic light-emitting layer 1010 and extends to cover the pixel definition layer 90 .
  • the anode 1000, the organic light-emitting layer 1010 and the cathode electrode together constitute a light-emitting device.
  • the display panel is an OLED display panel
  • the light-emitting device is an OLED light-emitting device.
  • the topmost is the encapsulation layer 1020, the material of which includes a combination of organic materials and inorganic materials.
  • the projections of the polysilicon active layer and the oxide active layer on the substrate 100 at least partially overlap.
  • each transistor is a low-temperature polysilicon transistor, and the active layer of each transistor is arranged on the same layer and connected to each other, so it occupies a large space.
  • the polysilicon active layer is and the oxide active layer are arranged in different layers, and the projection of the substrate 100 at least partially overlaps, so the occupied space can be reduced, so that the occupied area of the entire pixel driving circuit is smaller, so the area of the opaque area is reduced, so that the The light transmittance of the display panel is improved, which improves the display effect.
  • the plurality of second-layer scan signal lines form the bottom gates of the oxide transistors corresponding to the channel regions of the oxide transistors, and the projection of the channel regions on the substrate 100 falls on the corresponding bottom gates on the substrate within the projection range of the base 100. Since the oxide active layer is more sensitive to light, the material of the second metal layer 500 is opaque metal, and the projection of the channel region on the substrate 100 falls within the projection range of the corresponding bottom gate on the substrate 100, Therefore, the ambient light incident from the side of the second metal layer 500 away from the oxide active layer can be blocked, so as to prevent it from interfering with each oxide transistor, thereby improving the stability of each oxide transistor.
  • the plurality of second-layer scan signal lines input variable voltages when the oxide transistors are operating, so as to adjust the threshold voltages of the corresponding oxide transistors.
  • the threshold voltage drift phenomenon will occur, and the threshold voltage will be positively or negatively biased, so that the written data signal cannot be displayed correctly.
  • a potential signal is input to the gate, and the threshold voltage drift is corrected and adjusted, so that the driving current flowing through the light-emitting device D1 is stable. Since the threshold voltage will drift to different degrees with time, after detecting the magnitude of the threshold voltage drift, a variable voltage can be input when the oxide transistor is working, and the adjustment effect of the threshold voltage is more accurate. Better stability.
  • the material of the second metal layer 500 is metal, it can be used as a hydrogen barrier layer to block the influence of the hydrogen ions generated by the underlying film layer on the oxide active layer during the manufacturing process, so as to avoid the threshold voltage shift of the oxide transistor, and further Improve the stability of the circuit.
  • the second metal layer 500 forms a bottom gate corresponding to each oxide transistor, and can function as a light shielding layer, a hydrogen barrier layer and a threshold voltage adjustment at the same time, which together improve the stability of the pixel driving circuit, and the fabrication process is simple and the cost is relatively low. Low.
  • the pixel driving circuit of the present application by setting the compensation transistor T3, the first initializing transistor T4 and the second initializing transistor T7 as oxide transistors, and improving the structure of each film layer, the pixel driving is improved together.
  • the stability of the circuit improves the display effect.
  • the present application also provides a display device, including a display panel and a driving chip.
  • the display panel is the display panel described in any one of the above.
  • the compensation transistor T3, the first initialization transistor T4 and the second initialization transistor T7 in the display panel It is an oxide transistor, and the structure of each film layer is improved, which jointly improves the stability of the pixel driving circuit and improves the display effect.
  • the present application also provides a display device, the specific structure of which can be seen in FIG. 1 , the display device includes:
  • the first initialization transistor T4 is used for inputting the initialization signal VI to the first node Q under the control of the first scan signal Scan 1;
  • a switch transistor T2 for inputting the data signal Vdata to the second node A under the control of the second scan signal Scan 2;
  • a driving transistor T1 for driving the light-emitting device D1 to emit light under the control of the potentials of the first node Q and the second node A;
  • the second initialization transistor T7 is used to input the initialization signal VI to the anode of the light-emitting device under the control of the third scan signal Scan 3;
  • the first initialization transistor T4 and the second initialization transistor T7 are oxide transistors, and the switch transistor T2 and the second initialization transistor T7 are different types of transistors.
  • the switching transistor T2 is a low temperature polysilicon transistor and is a P-type transistor
  • the first initialization transistor T4 and the second initialization transistor T7 are N-type transistors.
  • FIG. 2 shows the timing diagram of each signal in the display stage of the display device.
  • the first initialization transistor T4 and the second initialization transistor T7 are oxide transistors
  • the switching transistor T2 is a low-temperature polysilicon transistor.
  • the first initialization transistor T4 can keep the potential of the first node Q stable
  • the second initialization transistor T7 can keep the potential of the anode C of the light-emitting device D1 stable, and relieve the light-emitting device D1.
  • the change of luminous brightness due to the influence of leakage current can especially alleviate the problem of poor display effect under the condition of lower refresh frequency.
  • the switching transistor T2 has a faster response speed, so that the data can be written quickly and avoid insufficient charging due to a long opening time.
  • the present application adopts a pixel driving circuit in which low-temperature polysilicon transistors and oxide transistors are combined with each other, and makes full use of the high mobility and fast driving speed of low-temperature polysilicon transistors and the low leakage current characteristics of oxide transistors, which can make the display of the display panel more stable. and lower power consumption.
  • the display device of the present application includes a substrate 100, a first semiconductor layer 300, a first metal layer 400, a second metal layer 500, a second semiconductor layer 600, The third metal layer 700, the first source and drain layers 800 and the second source and drain layers 900, wherein the first semiconductor layer 300 forms the polysilicon active layer of each low temperature polysilicon transistor, and the second semiconductor layer 600 forms each oxide transistor oxide active layer.
  • the projections of the polysilicon active layer and the oxide active layer on the substrate 100 at least partially overlap.
  • each transistor is a low-temperature polysilicon transistor, and the active layer of each transistor is arranged on the same layer and connected to each other, so it occupies a large space.
  • the polysilicon active layer and the oxide The physical active layers are arranged on different layers, and the projections of the substrate 100 overlap at least partially, so the occupied space can be reduced, so that the entire pixel driving circuit occupies a smaller area, thus reducing the area of the opaque area, making the display device The light transmittance is improved, and the display effect is improved.
  • the projection of each oxide transistor channel region on the substrate 100 falls within the projection range of the corresponding bottom gate on the substrate 100 . Since the oxide active layer is more sensitive to light, the material of the second metal layer 500 is opaque metal, and the projection of the channel region on the substrate 100 falls within the projection range of the corresponding bottom gate on the substrate 100, Therefore, the ambient light incident from the side of the second metal layer 500 away from the oxide active layer can be blocked, so as to prevent it from interfering with each oxide transistor, thereby improving the stability of each oxide transistor.
  • a variable voltage is input to the scan signal line of the second layer when the oxide transistor is operating, so as to adjust the threshold voltage of the corresponding oxide transistor.
  • the threshold voltage drift phenomenon will occur, and the threshold voltage will be positively or negatively biased, so that the written data signal cannot be displayed correctly.
  • a potential signal is input to the gate, and the threshold voltage drift is corrected and adjusted, so that the driving current flowing through the light-emitting device D1 is stable. Since the threshold voltage will drift to different degrees with time, after detecting the magnitude of the threshold voltage drift, a variable voltage can be input when the oxide transistor is working, and the adjustment effect of the threshold voltage is more accurate. Better stability.
  • the material of the second metal layer 500 is metal, it can be used as a hydrogen barrier layer to block the influence of the hydrogen ions generated by the underlying film layer on the oxide active layer during the manufacturing process, so as to avoid the threshold voltage shift of the oxide transistor, and further Improve the stability of the circuit.
  • the second metal layer 500 forms a bottom gate corresponding to each oxide transistor, and can function as a light shielding layer, a hydrogen barrier layer and a threshold voltage adjustment at the same time, which together improve the stability of the pixel driving circuit, and the fabrication process is simple and the cost is relatively low. Low.
  • the display device further includes a storage capacitor C1, the first node Q of the storage capacitor C1 is connected to the driving transistor T1, and the fourth node D is connected to the power high potential signal line for storing the data signal Vdata, the first The metal layer 400 is patterned to form the first electrode plate 403 of the storage capacitor C1, and the second metal layer 500 is patterned to form the second electrode plate 505 of the storage capacitor C1.
  • the first source-drain layer 800 is patterned to form a power high-potential signal line 802
  • the second source-drain layer 900 is patterned to form a first blocking member 901
  • the first blocking member 901 is connected to the power high-potential signal line 802
  • the first The projection of the blocking member 901 on the first metal layer 400 covers at least part of the first electrode plate 403 of the storage capacitor. Since the projection of the first blocking member 901 on the first metal layer 400 covers at least a partial area of the first plate 403 of the storage capacitor, corresponding to the coverage area, the space between the first blocking member 901 and the first plate 403 of the storage capacitor can be A coupling capacitor is generated, and the coupling capacitor is superimposed with the storage capacitor, which increases the ability of the circuit to store charges.
  • the first plate 403 of the storage capacitor also acts as the gate of the driving transistor T1, so the first blocking member 901 can improve the gate of the driving transistor T1. That is, the stability of the first node Q, even if there is a leakage current in the circuit, it can be released through the coupling capacitor to reduce the influence of the leakage current, so that the brightness change of the light-emitting device D1 is small, and the stability of the pixel driving circuit is improved.
  • the projection of the first blocking member 901 on the first metal layer 400 covers the entire area of the first plate 403 of the storage capacitor, the generated coupling capacitance is the largest, and the effect of improving stability is the best.
  • the projection of the first blocking member 901 on the oxide active layer covers the channel region of the first initialization transistor T4. Since the oxide active layer is more sensitive to light, and the material of the first blocking member 901 is opaque metal, therefore The ambient light incident from the side of the first blocking member 901 away from the oxide active layer can be blocked to prevent it from interfering with the first initialization transistor T4, thereby improving the stability of each oxide transistor.
  • the material of the first blocking member 901 is metal, it can be used as a hydrogen blocking layer to block the influence of the hydrogen ions generated by the upper film layer on the oxide active layer during the manufacturing process, so as to avoid the threshold voltage shift of the oxide transistor, and further Improve the stability of the circuit.
  • the first blocking member 901 corresponds to the first initialization transistor T4, and can simultaneously function as a light shielding layer, a hydrogen blocking layer and a coupling capacitor to improve the stability of the pixel driving circuit, and the fabrication process is simple and the cost is low.
  • the display device further includes: a first light-emitting control transistor T5 and a second light-emitting control transistor T6, the first light-emitting control transistor T5 is connected to the driving transistor T1 through the second node A, and is used for the light-emitting control signal EM Under the control of the power supply high-potential signal line, the current flowing to the driving transistor T1 is turned on; the second light-emitting control transistor T6 is connected to the driving transistor T1 through the third node B, and is used to turn on the driving transistor under the control of the light-emitting control signal EM.
  • the current T1 flows to the anode C of the light-emitting device D1; wherein, the driving transistor T1, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are low temperature polysilicon transistors.
  • the response speed of the driving transistor T1 is relatively fast, so that the data can be written quickly and avoid insufficient charging caused by the long turn-on time.
  • the first light-emitting control transistor T5 and the second light-emitting The response speed of the control transistor T6 is fast, so that the driving current I quickly flows into the light-emitting device D1, so as to avoid the display screen hysteresis caused by turning on too slowly.
  • the second source-drain layer 900 is further patterned to form a second blocking member 902, and the second blocking member 902 forms the second drain of the second light-emitting control transistor T6, which is connected to the second light-emitting control transistor T6 through the fifteenth via hole 015.
  • the second electrode is connected to the anode of the light emitting device D1 through the sixteenth via hole 016, and the projection on the oxide active layer covers the channel region of the second initialization transistor T7.
  • the second blocking member 902 can block the ambient light incident from the side of the second blocking member 902 away from the oxide active layer, preventing it from causing interference to the second initialization transistor T7, and improving the stability of the second initialization transistor T7 , can also be used as a hydrogen blocking layer to block the influence of the hydrogen ions generated by the upper film layer on the oxide active layer during the process, and further improve the stability of the circuit.
  • the second blocking member 902 can simultaneously serve as the second drain, the light shielding layer and the hydrogen blocking layer of the second light-emitting control transistor T6, which together improve the stability of the pixel driving circuit, and the fabrication process is simple and the cost is low.
  • the display device further includes a compensation transistor T3, which is connected to the driving transistor T1 through the first node Q and the third node B, for compensating the driving transistor under the control of the third scan signal Scan 3
  • the compensation transistor T3 is also an oxide transistor.
  • the compensation transistor T3 can keep the potentials of the first node Q and the third node B stable by utilizing the low leakage current characteristic of the oxide thin film transistor.
  • the projection of the first blocking member 901 on the oxide active layer covers the channel region of the compensation transistor T3. Therefore, the first blocking member 901 corresponds to the driving transistor T1, the compensation transistor T3 and the first initialization transistor T4, and can simultaneously function as a light shielding layer , hydrogen barrier layer and coupling capacitor, which together improve the stability of the pixel driving circuit, and the manufacturing process is simple and the cost is low.
  • the present application provides a display panel and a display device.
  • the display panel includes a plurality of light-emitting devices arranged in an array and a pixel driving circuit for driving the light-emitting devices to emit light.
  • the pixel driving circuit includes: a first initialization transistor for controlling a first scan signal Under the control of the second scanning signal, the switching transistor is used to input the data signal to the second node; the driving transistor is used to input the data signal to the second node under the control of the potential of the first node and the second node.
  • the light-emitting device is driven to emit light;
  • the compensation transistor is connected to the driving transistor through the first node and the third node, and is used for compensating the threshold voltage of the driving transistor under the control of the third scanning signal;
  • the second initialization transistor is used for the third scanning Under the control of the signal, an initialization signal is input to the anode of the light-emitting device;
  • the first light-emitting control transistor is connected to the driving transistor through the second node, and is used to turn on the current flowing from the high-potential signal line of the power supply to the driving transistor under the control of the light-emitting control signal
  • the second light-emitting control transistor is connected to the driving transistor through the third node, and is used to turn on the current flowing from the driving transistor to the anode of the light-emitting device under the control of the light-emitting control signal;
  • the storage capacitor is connected to the driving transistor through the first node, and is connected to the driving transistor through the first node.
  • the fourth node is connected to the high-potential signal line of the power supply for storing the data signal; wherein, the compensation transistor, the first initialization transistor and the second initialization transistor are oxide transistors, the switching transistor, the driving transistor, the first light-emitting control transistor and the second
  • the light emission control transistor is a low temperature polysilicon transistor.
  • a display panel and a display device provided by the embodiments of the present application have been introduced in detail above.
  • the principles and implementations of the present application are described in this article by using specific examples. The descriptions of the above embodiments are only used to help understand the present application.
  • Those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements to some of the technical features; and these modifications or replacements, and The essence of the corresponding technical solutions is not deviated from the scope of the technical solutions of the embodiments of the present application.

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Abstract

一种显示面板和显示装置，显示面板包括多个发光器件（D1）和驱动发光器件（D1）发光的像素驱动电路，通过将像素驱动电路中补偿晶体管（T3）、第一初始化晶体管（T4）和第二初始化晶体管（T7）设置为氧化物晶体管，其他晶体管设置为低温多晶硅晶体管，可同时利用氧化物晶体管的低漏电流特性和低温多晶硅晶体管的高迁移率特性，使电路更加稳定。

Description

显示面板和显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板和显示装置。
 背景技术
多晶硅类薄膜晶体管具有高迁移率，因此现有的OLED显示面板的像素驱动电路中，通常采用低温多晶硅（LTPS）薄膜晶体管进行驱动像素发光，然而，使用低温多晶硅薄膜晶体管的OLED显示面板较低刷新频率下，会出现发光阶段稳定性较弱的问题，造成显示效果较差。
因此，现有的显示面板存在像素驱动电路稳定性较弱的技术问题，需要改进。
 技术问题
本申请实施例提供一种显示面板和显示装置，用以缓解现有的显示面板中像素驱动电路稳定性较弱的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种显示面板，包括阵列设置的多个发光器件和驱动所述发光器件发光的像素驱动电路，所述像素驱动电路包括：
第一初始化晶体管，用于在第一扫描信号的控制下，向第一节点输入初始化信号；
开关晶体管，用于在第二扫描信号的控制下，向第二节点输入数据信号；
驱动晶体管，用于在所述第一节点和所述第二节点电位的控制下，驱动所述发光器件发光；
补偿晶体管，通过所述第一节点和第三节点与所述驱动晶体管相连，用于在第三扫描信号的控制下，补偿所述驱动晶体管的阈值电压；
第二初始化晶体管，用于在所述第三扫描信号的控制下，向所述发光器件阳极输入初始化信号；
第一发光控制晶体管，通过所述第二节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通电源高电位信号线流向所述驱动晶体管的电流；
第二发光控制晶体管，通过所述第三节点与所述驱动晶体管相连，用于在所述发光控制信号的控制下，导通所述驱动晶体管流向所述发光器件阳极的电流；
存储电容，通过所述第一节点与所述驱动晶体管相连，通过第四节点与所述电源高电位信号线相连，用于存储所述数据信号；
其中，所述补偿晶体管、所述第一初始化晶体管和所述第二初始化晶体管为氧化物晶体管，所述开关晶体管、所述驱动晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管为低温多晶硅晶体管。
在本申请的显示面板中，所述补偿晶体管、所述第一初始化晶体管和所述第二初始化晶体管为N型晶体管，所述开关晶体管、所述驱动晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管为P型晶体管。
在本申请的显示面板中，所述显示面板包括自下而上层叠设置的衬底、第一半导体层、第一金属层、第二金属层、第二半导体层、第三金属层、第一源漏极层和第二源漏极层，所述第一半导体层形成各低温多晶硅晶体管的多晶硅有源层，所述第二半导体层形成各氧化物晶体管的氧化物有源层。
在本申请的显示面板中，所述多晶硅有源层和所述氧化物有源层在所述衬底的投影至少部分重叠。
在本申请的显示面板中，所述第一金属层图案化形成各氧化物晶体管的顶栅，所述氧化物有源层形成各氧化物晶体管的沟道区，所述第二金属层图案化形成各氧化物晶体管的底栅，所述沟道区在所述衬底的投影落在对应的底栅在所述衬底的投影范围内。
在本申请的显示面板中，所述第一金属层图案化形成所述存储电容的第一极板，所述第二金属层图案化形成所述存储电容的第二极板。
在本申请的显示面板中，所述第一源漏极层图案化形成电源高电位信号线，所述第二源漏极层图案化形成第一阻挡构件，所述第一阻挡构件与所述电源高电位信号线连接，且所述第一阻挡构件在所述第一金属层的投影覆盖所述存储电容的第一极板的至少部分区域。
在本申请的显示面板中，所述第一阻挡构件在所述氧化物有源层的投影覆盖所述补偿晶体管的沟道区和所述第一初始化晶体管的沟道区。
在本申请的显示面板中，所述第二源漏极层图案化形成第二阻挡构件，所述第二阻挡构件与所述第二发光控制晶体管和所述发光器件阳极相连，且在所述氧化物有源层的投影覆盖所述第二初始化晶体管的沟道区。
本申请还提供一种显示装置，包括：
第一初始化晶体管，用于在第一扫描信号的控制下，向第一节点输入初始化信号；
开关晶体管，用于在第二扫描信号的控制下，向第二节点输入数据信号；
驱动晶体管，用于在所述第一节点和所述第二节点电位的控制下，驱动发光器件发光；
第二初始化晶体管，用于在所述第三扫描信号的控制下，向所述发光器件阳极输入初始化信号；
其中，所述第一初始化晶体管和所述第二初始化晶体管为氧化物晶体管，所述开关晶体管和所述第二初始化晶体管为不同类型晶体管。
在本申请的显示装置中，所述开关晶体管为低温多晶硅晶体管。
在本申请的显示装置中，所述开关晶体管为P型晶体管，所述第一初始化晶体管和所述第二初始化晶体管为N型晶体管。
在本申请的显示装置中，所述显示装置包括自下而上层叠设置的衬底、第一半导体层、第一金属层、第二金属层、第二半导体层、第三金属层、第一源漏极层和第二源漏极层，所述第一半导体层形成所述低温多晶硅晶体管的多晶硅有源层，所述第二半导体层形成所述氧化物晶体管的氧化物有源层。
在本申请的显示装置中，所述多晶硅有源层和所述氧化物有源层在所述衬底的投影至少部分重叠。
在本申请的显示装置中，所述第二金属层图案化形成各氧化物晶体管的底栅，所述第三金属层图案化形成各氧化物晶体管的顶栅，所述氧化物有源层形成各氧化物晶体管的沟道区，所述沟道区在所述衬底的投影落在对应的底栅在所述衬底的投影范围内。
在本申请的显示装置中，所述显示装置还包括存储电容，所述存储电容通过所述第一节点与所述驱动晶体管相连，通过第四节点与所述电源高电位信号线相连，用于存储所述数据信号，所述第一金属层图案化形成所述存储电容的第一极板，所述第二金属层图案化形成所述存储电容的第二极板。
在本申请的显示装置中，所述第一源漏极层图案化形成电源高电位信号线，所述第二源漏极层图案化形成第一阻挡构件，所述第一阻挡构件与所述电源高电位信号线连接，且所述第一阻挡构件在所述第一金属层的投影覆盖所述存储电容的第一极板的至少部分区域。
在本申请的显示装置中，所述第一阻挡构件在所述氧化物有源层的投影覆盖所述第一初始化晶体管的沟道区。
在本申请的显示装置中，所述显示装置还包括：
第一发光控制晶体管，通过所述第二节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通电源高电位信号线流向所述驱动晶体管的电流；
第二发光控制晶体管，通过所述第三节点与所述驱动晶体管相连，用于在所述发光控制信号的控制下，导通所述驱动晶体管流向所述发光器件阳极的电流；
所述驱动晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管为多晶硅晶体管。
在本申请的显示装置中，所述第二源漏极层图案化形成第二阻挡构件，所述第二阻挡构件与所述第二发光控制晶体管和所述发光器件阳极相连，且在所述氧化物有源层的投影覆盖所述第二初始化晶体管的沟道区。
在本申请的显示装置中，所述显示装置还包括补偿晶体管，所述补偿晶体管通过所述第一节点和第三节点与所述驱动晶体管相连，用于在第三扫描信号的控制下，补偿所述驱动晶体管的阈值电压，所述补偿晶体管为氧化物晶体管。
在本申请的显示装置中，所述第一阻挡构件在所述氧化物有源层的投影覆盖所述补偿晶体管的沟道区。
 有益效果
有益效果：本申请提供一种显示面板和显示装置，显示面板包括阵列设置的多个发光器件和驱动所述发光器件发光的像素驱动电路，所述像素驱动电路包括：第一初始化晶体管，用于在第一扫描信号的控制下，向第一节点输入初始化信号；开关晶体管，用于在第二扫描信号的控制下，向第二节点输入数据信号；驱动晶体管，用于在所述第一节点和所述第二节点电位的控制下，驱动所述发光器件发光；补偿晶体管，通过所述第一节点和第三节点与所述驱动晶体管相连，用于在第三扫描信号的控制下，补偿所述驱动晶体管的阈值电压；第二初始化晶体管，用于在所述第三扫描信号的控制下，向所述发光器件阳极输入初始化信号；第一发光控制晶体管，通过所述第二节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通电源高电位信号线流向所述驱动晶体管的电流；第二发光控制晶体管，通过所述第三节点与所述驱动晶体管相连，用于在所述发光控制信号的控制下，导通所述驱动晶体管流向所述发光器件阳极的电流；存储电容，通过所述第一节点与所述驱动晶体管相连，通过第四节点与所述电源高电位信号线相连，用于存储所述数据信号；其中，所述补偿晶体管、所述第一初始化晶体管和所述第二初始化晶体管为氧化物晶体管，所述开关晶体管、所述驱动晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管为低温多晶硅晶体管。本申请通过将补偿晶体管、第一初始化晶体管和第二初始化晶体管设置为氧化物晶体管，其他晶体管设置为低温多晶硅晶体管，可以同时利用氧化物晶体管的低漏电流特性和低温多晶硅晶体管的高迁移率特性，从而使得像素驱动电路更加稳定，提升了显示面板的显示效果。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板中像素驱动电路的结构示意图。
图2为本申请实施例提供的显示面板中像素驱动电路中各信号的时序图。
图3为本申请实施例提供的显示面板中各膜层的结构示意图。
图4为本申请实施例提供的显示面板中各膜层的平面叠加结构示意图。
图5为本申请实施例提供的显示面板中第一半导体层的平面结构示意图。
图6为本申请实施例提供的显示面板中第一金属层的平面结构示意图。
图7为本申请实施例提供的显示面板中第二金属层的平面结构示意图。
图8为本申请实施例提供的显示面板中第二半导体层的平面结构示意图。
图9为本申请实施例提供的显示面板中第三金属层的平面结构示意图。
图10为本申请实施例提供的显示面板中第一源漏极层的平面结构示意图。
图11为本申请实施例提供的显示面板中第二源漏极层的平面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相近的单元是用以相同标号表示。
本申请实施例提供一种显示面板和显示装置，用以缓解现有的显示面板中像素驱动电路稳定性较弱的技术问题。
如图1所示，本申请提供一种显示面板，包括阵列设置的多个发光器件D1和驱动发光器件D1发光的像素驱动电路，像素驱动电路包括：
第一初始化晶体管T4，用于在第一扫描信号Scan 1的控制下，向第一节点Q输入初始化信号VI；
开关晶体管T2，用于在第二扫描信号Scan 2的控制下，向第二节点A输入数据信号Vdata；
驱动晶体管T1，用于在第一节点Q和第二节点A电位的控制下，驱动发光器件D1发光；
补偿晶体管T3，通过第一节点Q和第三节点B与驱动晶体管T1相连，用于在第三扫描信号Scan 3的控制下，补偿驱动晶体管T1的阈值电压；
第二初始化晶体管T7，用于在第三扫描信号Scan 3的控制下，向发光器件阳极输入初始化信号VI；
第一发光控制晶体管T5，通过第二节点A与驱动晶体管T1相连，用于在发光控制信号EM的控制下，导通电源高电位信号线流向驱动晶体管T1的电流；
第二发光控制晶体管T6，通过第三节点B与驱动晶体管T1相连，用于在发光控制信号EM的控制下，导通驱动晶体管T1流向发光器件D1阳极C的电流；
存储电容C1，通过第一节点Q与驱动晶体管T1相连，通过第四节点D与电源高电位信号线相连，用于存储数据信号Vdata；
其中，补偿晶体管T3、第一初始化晶体管T4和第二初始化晶体管T7为氧化物晶体管，开关晶体管T2、驱动晶体管T1、第一发光控制晶体管T5和第二发光控制晶体管T6为低温多晶硅晶体管。
具体地，第一初始化晶体管T4的栅极接入第一扫描信号Scan 1，第一电极接入初始化信号VI，第二电极接入第一节点Q。
开关晶体管T2的栅极接入第二扫描信号Scan 2，第一电极接入数据信号Vdata，第二电极连接第二节点A。
驱动晶体管T1的栅极接入第一节点Q，第一电极接入第二节点A，第二电极接入第三节点B。
补偿晶体管T3的栅极接入第三扫描信号Scan 3，第一电极接入第三节点B，第二电极接入第一节点Q。
第二初始化晶体管T7的栅极接入第三扫描信号Scan 3，第一电极接入初始化信号VI，第二电极连接发光器件D1阳极C。
第一发光控制晶体管T5的栅极接入发光控制信号EM，第二电极接入电源高电位信号Vdd，第一电极连接第二节点A。
第二发光控制晶体管T6的栅极接入发光控制信号EM，第一电极连接第三节点B，第二电极连接发光器件D1阳极C，发光器件D1阴极连接电源低电位信号Vss。
存储电容C1的第一极板连接电源高电位信号Vdd，第二极板连接第一节点Q。
晶体管T1至T7中，第一电极和第二电极中的其中一个是源电极，另一个是漏电极。
如图2所示，为本申请的像素驱动电路在显示阶段的时序图。本申请的像素驱动电路中，补偿晶体管T3、第一初始化晶体管T4和第二初始化晶体管T7为N型晶体管，开关晶体管T2、驱动晶体管T1、第一发光控制晶体管T5和第二发光控制晶体管T6为P型晶体管。
在复位阶段t1，第二扫描信号Scan 2为高电位，开关晶体管T2关闭，第三扫描信号Scan 3为低电位，补偿晶体管T3和第二初始化晶体管T7关闭，发光控制信号EM为高电位，第一发光控制信号T5和第二发光控制信号T6关闭，第一扫描信号Scan 1为高电位，第一初始化晶体管T4打开，向第一节点Q输入初始化信号，将第一节点Q的电位拉低。
在数据写入阶段t2，第一扫描信号Scan 1为低电位，第一初始化晶体管T4关闭，第二扫描信号Scan 2为低电位，开关晶体管T2打开，第三扫描信号Scan 3为高电位，补偿晶体管T3和第二初始化晶体管T7打开，由于第一节点Q的电位为低，补偿晶体管T3打开后将驱动晶体管T1的栅极和第二电极短接，通过驱动晶体管T1的阈值电压在驱动晶体管T1的栅电极与第一电极之间生成电压差，此时，驱动晶体管T1开启，开关晶体管T2向第二节点A输入数据信号Vdata，该数据信号Vdata包含补偿的阈值电压，并被输入至驱动晶体管T1的栅极，从而补偿了驱动晶体管T1的阈值电压偏差。写入的数据信号Vdata通过驱动晶体管T1给第一节点Q充电，直至第一节点Q的电压变为Vdata-Vth，驱动晶体管T1截止。此外，由于第二初始化晶体管T7开启，因此发光器件D1的阳极接收初始化信号而被复位。
在发光阶段t3，发光控制信号EM为低电位，第一发光控制信号T5和第二发光控制信号T6打开，导通电源高电位信号线VDD流向驱动晶体管T1的电流、以及驱动晶体管T1流向发光器件D1阳极C的电流，此时流经发光器件D1的驱动电流满足公式I＝1/2K[Vdd-(Vdata-Vth)-Vth] 2=1/2K[Vdd-Vdata] 2。发光器件D1在驱动电流I的作用下工作发光。
在本申请实施例中，补偿晶体管T3、第一初始化晶体管T4和第二初始化晶体管T7为氧化物晶体管，开关晶体管T2、驱动晶体管T1、第一发光控制晶体管T5和第二发光控制晶体管T6为低温多晶硅晶体管，在发光阶段t3，利用氧化薄膜晶体管低漏电流的特性，补偿晶体管T3可以保持住第一节点Q和第三节点B的电位稳定，第一初始化晶体管T4可以保持住第一节点Q的电位稳定，第二初始化晶体管T7可以保持住发光器件D1阳极C的电位稳定，缓解发光器件D1因受到漏电流影响造成的发光亮度变化，尤其可以缓解在较低刷新频率情况下显示效果较差的问题。同时，利用低温多晶硅晶体管高迁移率和高驱动速度的特性，在数据写入阶段t2，开关晶体管T2、驱动晶体管T1的响应速度较快，使得数据可以被迅速写入，避免因打开时间较长而造成充电不足，在发光阶段t3，第一发光控制晶体管T5和第二发光控制晶体管T6响应速度较快，使得驱动电流I迅速流入发光器件D1中，避免开启过慢引起显示画面迟滞。本申请采用低温多晶硅晶体管和氧化物晶体管相互结合的像素驱动电路，充分利用低温多晶硅晶体管高迁移率和较快驱动速度、以及氧化物晶体管低漏电流的特性，可以使显示面板的显示更加稳定，且功耗更低。
如图3所示，为本申请实施例提供的显示面板的膜层结构示意图。显示面板包括自下而上层叠设置的衬底100、第一半导体层300、第一金属层400、第二金属层500、第二半导体层600、第三金属层700、第一源漏极层800和第二源漏极层900，其中，第一半导体层300形成各低温多晶硅晶体管的多晶硅有源层，第二半导体层600形成各氧化物晶体管的氧化物有源层。
图3中左侧晶体管为低温多晶硅晶体管的膜层结构，右侧晶体管为氧化物晶体管的膜层结构，像素驱动电路中开关晶体管T2、驱动晶体管T1、第一发光控制晶体管T5和第二发光控制晶体管T6的结构均与图3左侧的晶体管结构相同，补偿晶体管T3、第一初始化晶体管T4和第二初始化晶体管T7的结构均与图3右侧的晶体管结构相同。图4为本申请实施例提供的显示面板中各膜层平面叠加示意图，图5至图11分别为各膜层的平面示意图。下面结合图3至图11对像素驱动电路中各晶体管的膜层结构进行具体说明。
如图3所示，衬底100可以包括刚性衬底或柔性衬底，当衬底100为刚性衬底时，材料可以是金属或玻璃，当衬底100为柔性衬底时，材料可以包括丙烯酸树脂、甲基丙烯酸树脂、聚异戊二烯、乙烯基树脂、环氧基树脂、聚氨酯基树脂、纤维素树脂、硅氧烷树脂、聚酰亚胺基树脂、聚酰胺基树脂中的至少一种。本申请对衬底100的材料不做限制。
在衬底100上通常形成有缓冲层200，缓冲层200可以包括无机材料，如氮化硅或氧化硅中的至少一种，用来防止衬底100下方的外界杂质渗入至上层的晶体管中，以及改善衬底100与上方膜层间的结合强度。根据衬底100的类型、工艺条件等，缓冲层200可被省略。
如图3、图4和图5所示，第一半导体层300图案化形成开关晶体管T2、驱动晶体管T1、第一发光控制晶体管T5和第二发光控制晶体管T6的多晶硅有源层，且各晶体管的多晶硅有源层相互连接，多晶硅有源层可通过使非晶硅结晶化来形成，结晶方法的可包括快速热退火(RTA)、固相结晶化(SPC)、准分子激光退火(ELA)、金属诱导结晶化(MIC)、金属诱导横向结晶化(MILC)和顺序横向凝固(SLS)等。
如图3所示，在第一半导体层300上形成有第一栅绝缘层10，第一栅绝缘层10的材料包括氧化硅。
如图3、图4、图5和图6所示，第一金属层400形成在第一栅绝缘层10上，图案化形成多条第一层扫描信号线、以及存储电容的第一极板403，第一层扫描信号线具体包括第一扫描信号线401和第二扫描信号线402，其中第二扫描信号线402为发光控制信号线。其中，第一扫描信号线401与多晶硅有源层在衬底100上的投影存在一相交区域，第一扫描信号线401位于该相交区域的部分形成开关晶体管T2的栅极，多晶硅有源层位于该相交区域的部分形成开关晶体管T2的沟道区，第二扫描信号线402与多晶硅有源层在衬底100上的投影存在一相交区域，第二扫描信号线402位于该相交区域的部分分别形成第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极，多晶硅有源层位于该相交区域的部分分别形成第一发光控制晶体管T5的沟道区和第二发光控制晶体管T6的沟道区，存储电容的第一极板403与多晶硅有源层在衬底100上的投影也存在一相交区域，存储电容的第一极板403位于该相交区域的部分形成驱动晶体管T1的栅极，多晶硅有源层位于该相交区域的部分形成驱动晶体管T1的沟道区。
多晶硅有源层除了上述各沟道区之外的部分进行离子掺杂，形成各低温多晶硅晶体管的源区和漏区。通过离子掺杂及各第一层扫描信号线的相交设置，实现了开关晶体管T2的第二电极与第一发光控制晶体管T5的第二电极、驱动晶体管T1的第一电极的连接，以及驱动晶体管T1的第二电极与第二发光控制晶体管T6的第一电极间的连接。
第一金属层400的材料可包括钼(Mo)、铝(Al)、铂(Pt)、钯(Pd)、银(Ag)、镁(Mg)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、钙(Ca)、钛(Ti)、钽(Ta)和钨(W)中的至少一种金属。
如图3所示，在第一金属层400上形成有第二栅绝缘层20，第二栅绝缘层20的材料包括氮化硅。
如图3、图4和图7所示，第二金属层500形成在第二栅绝缘层20上，图案化形成多条第二层扫描信号线、以及存储电容的第二极板505，第二层扫描信号线具体包括第三扫描信号线501、第三扫描信号线502、第五扫描信号线503和第六扫描信号线504，其中第三扫描信号线501为初始化信号线VI。需要说明的是，在图7中最上一条第三扫描信号线501为上一发光器件对应的像素驱动电路中的扫描信号线，最下一条第三扫描信号线501为下一发光器件对应的像素驱动电路中的扫描信号线。
第二金属层500的材料可包括钼(Mo)、铝(Al)、铂(Pt)、钯(Pd)、银(Ag)、镁(Mg)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、钙(Ca)、钛(Ti)、钽(Ta)和钨(W)中的至少一种金属。
如图3所示，在第二金属层500上形成有第一层间介质层30，材料包括氮化硅和氧化硅中的至少一种。
如图3、图4和图8所示，第二半导体层600形成在第一层间介质层30上，图案化形成补偿晶体管T3、第一初始化晶体管T4和第二初始化晶体管T7的氧化物有源层，其中补偿晶体管T3和第一初始化晶体管T4的氧化物有源层相互连接，第二初始化晶体管T7的氧化物有源层与其他晶体管独立。氧化物有源层材料可以包括氧化锌(ZnO)、氧化锌锡(ZTO)、氧化锌铟(ZIO)、氧化铟(InO)、氧化钛(TiO)、氧化铟镓锌(IGZO)、氧化铟锌锡(IZTO)中的至少一种。
如图3所示，在第二半导体层600上形成有第三栅绝缘层40，第三栅绝缘层40的材料包括氧化硅。
如图3、图4和图9所示，第三金属层700形成在第三栅绝缘层40上，图案化形成多条第三层扫描信号线，包括第七扫描信号线701、第八扫描信号线702和第九扫描信号线703，其中，第七扫描信号线701与氧化物有源层在衬底100上的投影存在一相交区域，第七扫描信号线701位于该相交区域的部分形成第一初始化晶体管T4的顶栅，氧化物有源层位于该相交区域的部分形成第一初始化晶体管T4的沟道区，第八扫描信号线702与氧化物有源层在衬底100上的投影存在一相交区域，第八扫描信号线702位于该相交区域的部分形成补偿晶体管T3的顶栅，氧化物有源层位于该相交区域的部分形成补偿晶体管T3的沟道区，第九扫描信号线703与氧化物有源层在衬底100上的投影也存在一相交区域，第九扫描信号线703位于该相交区域的部分形成第二初始化晶体管T7的顶栅，氧化物有源层位于该相交区域的部分形成第二初始化晶体管T7的沟道区。
氧化物有源层除了上述各沟道区之外的部分形成各氧化物晶体管的源区和漏区，通过各第三层扫描信号线的相交设置，实现了补偿晶体管T3的第二电极与第一初始化晶体管T4的第二电极的连接，以及第一初始化晶体管T4的第一电极与第二初始化晶体管T7的第一电极间的连接。
第三金属层700的材料可包括钼(Mo)、铝(Al)、铂(Pt)、钯(Pd)、银(Ag)、镁(Mg)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、钙(Ca)、钛(Ti)、钽(Ta)和钨(W)中的至少一种金属。
如图3所示，在第三金属层700上形成有第二层间介质层50，材料包括氮化硅和氧化硅中的至少一种。
如图3、图4和图10所示，第二层间介质层50上形成有第一源漏极层800，图案化形成数据信号线801、电源高电位信号线802、第一连接线803、第二连接线804、第三连接线805、第四连接线806和第四连接线807。第一源漏极层800的材料包括Mo、Al、Cu、Ti等的单质或合金中的至少一种。
数据信号线801通过第一过孔001与开关晶体管T2的多晶硅有源层连接；电源高电位信号线802通过第二过孔002与第一发光控制信号线T5的多晶硅有源层连接，通过第三过孔003与存储电容C1的第一极板505连接，且连接时需要穿过存储电容的第二极板505中形成的电容过孔5051；第一连接线803通过第四过孔004与第一初始化晶体管T4的氧化物有源层连接，形成第一初始化晶体管T4的第一电极，再通过第五过孔005与初始化信号线VI连接；第二连接线804通过第六过孔006与驱动晶体管T1的栅极和存储电容C1的第二极板403连接，通过第七过孔007与第一初始化晶体管T4的氧化物有源层连接，形成第一初始化晶体管T4的第二电极；第三连接线805通过第八过孔008与驱动晶体管T1和第二发光控制晶体管T6的多晶硅有源层连接，形成驱动晶体管T1的第二电极和第二发光控制晶体管T6的第一电极，通过第九过孔009与补偿晶体管T3的氧化物有源层连接，形成补偿晶体管T3的第二电极；第四连接线806通过第十过孔010与第二发光控制晶体管T6的多晶硅有源层连接，形成第二发光控制晶体管T6的第二电极，通过第十一过孔011与第二初始化晶体管T7的氧化物有源层连接，形成第二初始化晶体管T7的第二电极；第五连接线807通过第十二过孔012与第二初始化晶体管T7的氧化物有源层连接，形成第二初始化晶体管T7的第一电极，再通过第十三过孔013与初始化信号线VI连接。
如图3所示，在第三金属层800上形成有钝化层60，钝化层的材料通常为氮化硅(SiNx)和氧化硅(SiOx)中的至少一种。在钝化层60上形成有第一平坦化层70，第一平坦化层70的材料通常为聚酰亚胺。
如图3、图4和图11所示，在钝化层70上形成有第二源漏极层900，第二源漏极层900的材料包括Mo、Al、Cu、Ti等的单质或合金中的至少一种。
第二源漏极层900图案化形成第一阻挡构件901，第一阻挡构件901与电源高电位信号线802连接，且第一阻挡构件901在第一金属层400的投影覆盖至少部分存储电容的第一极板403。第一阻挡构件901通过第十四过孔014与电源高电位信号线802连接，由于第一阻挡构件901在第一金属层400的投影覆盖存储电容的第一极板403的至少部分区域，对应该覆盖区域，第一阻挡构件901与存储电容的第一极板403之间可以产生耦合电容，该耦合电容与存储电容叠加，使得电路存储电荷的能力增加，存储电容的第一极板403又作为驱动晶体管T1的栅极，因此第一阻挡构件901可以提高驱动晶体管T1栅极也即第一节点Q的稳定性，即使电路中有漏电流产生，也可以通过耦合电容释放以减小漏电流的影响，使得发光器件D1的亮度变化较小，提高了像素驱动电路的稳定性。当第一阻挡构件901在第一金属层400的投影覆盖存储电容的第一极板403的全部区域时，产生的耦合电容最大，提升稳定性的作用最好。
第一阻挡构件901在氧化物有源层的投影覆盖补偿晶体管T3的沟道区和第一初始化晶体管T4的沟道区，由于氧化物有源层对光照较为敏感，而第一阻挡构件901的材料为不透光金属，因此可以阻挡从第一阻挡构件901远离氧化物有源层一侧入射的环境光，防止其对补偿晶体管T3和第一初始化晶体管T4造成干扰，提高了各氧化物晶体管的稳定性。
此外，由于第一阻挡构件901材料为金属，因此可以作为氢阻挡层，阻挡上方膜层在制程过程中产生的氢离子对氧化物有源层的影响，避免造成氧化物晶体管阈值电压漂移，进一步提高电路的稳定性。
综上，第一阻挡构件901对应驱动晶体管T1、补偿晶体管T3和第一初始化晶体管T4，可以同时起到遮光层、氢阻挡层以及耦合电容的作用，共同提高像素驱动电路的稳定性，且制作工艺简单，成本较低。
第二源漏极层900还图案化形成第二阻挡构件902，第二阻挡构件902形成第二发光控制晶体管T6的第二漏极，通过第十五过孔015与第二发光控制晶体管T6的的第二电极连接，通过第十六过孔016与发光器件D1的阳极连接，且在氧化物有源层的投影覆盖第二初始化晶体管T7的沟道区。同样地，第二阻挡构件902可以阻挡从第二阻挡构件902远离氧化物有源层一侧入射的环境光，防止其对第二初始化晶体管T7造成干扰，提高了第二初始化晶体管T7的稳定性，也可以作为氢阻挡层，阻挡上方膜层在制程过程中产生的氢离子对氧化物有源层的影响，进一步提高电路的稳定性。综上，第二阻挡构件902可以同时作为第二发光控制晶体管T6的第二漏极、遮光层和氢阻挡层，共同提高像素驱动电路的稳定性，且制作工艺简单，成本较低。
如图3所示，第二源漏极层900上形成有第二平坦化层80，第二平坦化层80的材料通常为聚酰亚胺。发光器件阳极1000形成在第二平坦化层80中，包括高功函数的导电材料和反射材料的单层或叠层，其中高功函数的导电材料可包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)或氧化铟(In 2O 3)等，反射材料可包括银(Ag)、镁(Mg)、铝(Al)、铂(Pt)，钯(Pd)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、锂(Li)、钙(Ca)或它们的混合物。像素定义层90形成在发光器件阳极1000上，包括暴露出阳极1000的多个开口区，像素定义层90的材料可包括光致抗蚀剂、聚酰亚胺树脂、丙烯酸树脂、硅化合物或聚丙烯酸树脂等。有机发光层1010形成在开口区内，发光器件阴极（图未示出）位于有机发光层1010上，且延伸覆盖像素定义层90。上述阳极1000、有机发光层1010和阴电极共同构成发光器件，在本申请中，显示面板为OLED显示面板，发光器件为OLED发光器件。最上方为封装层1020，其材质包括有机材料与无机材料的组合。
在一种实施例中，多晶硅有源层和氧化物有源层在衬底100的投影至少部分重叠。在现有技术的像素驱动电路中，各晶体管均为低温多晶硅晶体管，各晶体管的有源层设置在同层且相互连接，因此占用空间较大，本申请的像素驱动电路中，多晶硅有源层和氧化物有源层设置在不同层，且衬底100的投影至少部分重叠，因此可以减小占用空间，使得整个像素驱动电路占用面积较小，因此减小了不透光区域的面积，使得显示面板的透光率提升，提高了显示效果。
在一种实施例中，多条第二层扫描信号线对应各氧化物晶体管沟道区形成各氧化物晶体管的底栅，且沟道区在衬底100的投影落在对应的底栅在衬底100的投影范围内。由于氧化物有源层对光照较为敏感，而第二金属层500的材料为不透光金属，且沟道区在衬底100的投影落在对应的底栅在衬底100的投影范围内，因此可以阻挡从第二金属层500远离氧化物有源层一侧入射的环境光，防止其对各氧化物晶体管造成干扰，提高了各氧化物晶体管的稳定性。
在一种实施例中，多条第二层扫描信号线在氧化物晶体管工作时输入可变电压，以调节对应氧化物晶体管的阈值电压。由于氧化物晶体管在长时间使用时，会出现阈值电压漂移现象，阈值电压会发生正偏或负偏，使得写入的数据信号不能被正确显示出，此时，可以向各氧化物晶体管的底栅输入电位信号，对阈值电压漂移进行校正调整，使得流过发光器件D1中的驱动电流稳定。由于阈值电压会随着时间的长短产生不同程度的漂移，因此可以在侦测阈值电压漂移的大小后，在氧化物晶体管工作时输入可变电压，对阈值电压的调节效果更为准确，电路的稳定性更好。
此外，由于第二金属层500材料为金属，因此可以作为氢阻挡层，阻挡下方膜层在制程过程中产生的氢离子对氧化物有源层的影响，避免造成氧化物晶体管阈值电压漂移，进一步提高电路的稳定性。
综上，第二金属层500对应各氧化物晶体管形成底栅，可以同时起到遮光层、氢阻挡层以及阈值电压调节的作用，共同提高像素驱动电路的稳定性，且制作工艺简单，成本较低。
通过上述实施例可知，本申请的像素驱动电路，通过将补偿晶体管T3、第一初始化晶体管T4和第二初始化晶体管T7设置为氧化物晶体管，并对各膜层结构进行改进，共同提高了像素驱动电路的稳定性，提高了显示效果。
本申请还提供一种显示装置，包括显示面板和驱动芯片，显示面板为上述任一项所述的显示面板，通过将显示面板中补偿晶体管T3、第一初始化晶体管T4和第二初始化晶体管T7设置为氧化物晶体管，并对各膜层结构进行改进，共同提高了像素驱动电路的稳定性，提高了显示效果。
本申请还提供一种显示装置，具体结构可参加图1，显示装置包括：
第一初始化晶体管T4，用于在第一扫描信号Scan 1的控制下，向第一节点Q输入初始化信号VI；
开关晶体管T2，用于在第二扫描信号Scan 2的控制下，向第二节点A输入数据信号Vdata；
驱动晶体管T1，用于在第一节点Q和第二节点A电位的控制下，驱动发光器件D1发光；
第二初始化晶体管T7，用于在第三扫描信号Scan 3的控制下，向发光器件阳极输入初始化信号VI；
其中，第一初始化晶体管T4和第二初始化晶体管T7为氧化物晶体管，开关晶体管T2和第二初始化晶体管T7为不同类型晶体管。
在一种实施例中，开关晶体管T2为低温多晶硅晶体管，且为P型晶体管，第一初始化晶体管T4和第二初始化晶体管T7为N型晶体管。
图2示出了显示装置在显示阶段各信号的时序图，在本申请实施例中，第一初始化晶体管T4和第二初始化晶体管T7为氧化物晶体管，开关晶体管T2为低温多晶硅晶体管，则在发光阶段t3，利用氧化薄膜晶体管低漏电流的特性，第一初始化晶体管T4可以保持住第一节点Q的电位稳定，第二初始化晶体管T7可以保持住发光器件D1阳极C的电位稳定，缓解发光器件D1因受到漏电流影响造成的发光亮度变化，尤其可以缓解在较低刷新频率情况下显示效果较差的问题。同时，利用低温多晶硅晶体管高迁移率和高驱动速度的特性，在数据写入阶段t2，开关晶体管T2响应速度较快，使得数据可以被迅速写入，避免因打开时间较长而造成充电不足，本申请采用低温多晶硅晶体管和氧化物晶体管相互结合的像素驱动电路，充分利用低温多晶硅晶体管高迁移率和较快驱动速度、以及氧化物晶体管低漏电流的特性，可以使显示面板的显示更加稳定，且功耗更低。
结合图3至图11所示，本申请的显示装置包括自下而上层叠设置的衬底100、第一半导体层300、第一金属层400、第二金属层500、第二半导体层600、第三金属层700、第一源漏极层800和第二源漏极层900，其中，第一半导体层300形成各低温多晶硅晶体管的多晶硅有源层，第二半导体层600形成各氧化物晶体管的氧化物有源层。
在一种实施例中，多晶硅有源层和氧化物有源层在衬底100的投影至少部分重叠。在现有技术的显示装置中，各晶体管均为低温多晶硅晶体管，各晶体管的有源层设置在同层且相互连接，因此占用空间较大，本申请的显示装置中，多晶硅有源层和氧化物有源层设置在不同层，且衬底100的投影至少部分重叠，因此可以减小占用空间，使得整个像素驱动电路占用面积较小，因此减小了不透光区域的面积，使得显示装置的透光率提升，提高了显示效果。
在一种实施例中，各氧化物晶体管沟道区在衬底100的投影落在对应的底栅在衬底100的投影范围内。由于氧化物有源层对光照较为敏感，而第二金属层500的材料为不透光金属，且沟道区在衬底100的投影落在对应的底栅在衬底100的投影范围内，因此可以阻挡从第二金属层500远离氧化物有源层一侧入射的环境光，防止其对各氧化物晶体管造成干扰，提高了各氧化物晶体管的稳定性。
在一种实施例中，第二层扫描信号线在氧化物晶体管工作时输入可变电压，以调节对应氧化物晶体管的阈值电压。由于氧化物晶体管在长时间使用时，会出现阈值电压漂移现象，阈值电压会发生正偏或负偏，使得写入的数据信号不能被正确显示出，此时，可以向各氧化物晶体管的底栅输入电位信号，对阈值电压漂移进行校正调整，使得流过发光器件D1中的驱动电流稳定。由于阈值电压会随着时间的长短产生不同程度的漂移，因此可以在侦测阈值电压漂移的大小后，在氧化物晶体管工作时输入可变电压，对阈值电压的调节效果更为准确，电路的稳定性更好。
此外，由于第二金属层500材料为金属，因此可以作为氢阻挡层，阻挡下方膜层在制程过程中产生的氢离子对氧化物有源层的影响，避免造成氧化物晶体管阈值电压漂移，进一步提高电路的稳定性。
综上，第二金属层500对应各氧化物晶体管形成底栅，可以同时起到遮光层、氢阻挡层以及阈值电压调节的作用，共同提高像素驱动电路的稳定性，且制作工艺简单，成本较低。
在一种实施例中，显示装置还包括存储电容C1，存储电容C1第一节点Q与驱动晶体管T1相连，通过第四节点D与电源高电位信号线相连，用于存储数据信号Vdata，第一金属层400图案化形成存储电容C1的第一极板403，第二金属层500图案化形成存储电容C1的第二极板505。
第一源漏极层800图案化形成电源高电位信号线802，第二源漏极层900图案化形成第一阻挡构件901，第一阻挡构件901与电源高电位信号线802连接，且第一阻挡构件901在第一金属层400的投影覆盖至少部分存储电容的第一极板403。由于第一阻挡构件901在第一金属层400的投影覆盖存储电容的第一极板403的至少部分区域，对应该覆盖区域，第一阻挡构件901与存储电容的第一极板403之间可以产生耦合电容，该耦合电容与存储电容叠加，使得电路存储电荷的能力增加，存储电容的第一极板403又作为驱动晶体管T1的栅极，因此第一阻挡构件901可以提高驱动晶体管T1栅极也即第一节点Q的稳定性，即使电路中有漏电流产生，也可以通过耦合电容释放以减小漏电流的影响，使得发光器件D1的亮度变化较小，提高了像素驱动电路的稳定性。当第一阻挡构件901在第一金属层400的投影覆盖存储电容的第一极板403的全部区域时，产生的耦合电容最大，提升稳定性的作用最好。
第一阻挡构件901在氧化物有源层的投影覆盖第一初始化晶体管T4的沟道区，由于氧化物有源层对光照较为敏感，而第一阻挡构件901的材料为不透光金属，因此可以阻挡从第一阻挡构件901远离氧化物有源层一侧入射的环境光，防止其对第一初始化晶体管T4造成干扰，提高了各氧化物晶体管的稳定性。
此外，由于第一阻挡构件901材料为金属，因此可以作为氢阻挡层，阻挡上方膜层在制程过程中产生的氢离子对氧化物有源层的影响，避免造成氧化物晶体管阈值电压漂移，进一步提高电路的稳定性。
综上，第一阻挡构件901对应第一初始化晶体管T4，可以同时起到遮光层、氢阻挡层以及耦合电容的作用，共同提高像素驱动电路的稳定性，且制作工艺简单，成本较低。
在一种实施例中，显示装置还包括：第一发光控制晶体管T5和第二发光控制晶体管T6，第一发光控制晶体管T5通过第二节点A与驱动晶体管T1相连，用于在发光控制信号EM的控制下，导通电源高电位信号线流向驱动晶体管T1的电流；第二发光控制晶体管T6通过第三节点B与驱动晶体管T1相连，用于在发光控制信号EM的控制下，导通驱动晶体管T1流向发光器件D1阳极C的电流；其中，驱动晶体管T1、第一发光控制晶体管T5和第二发光控制晶体管T6为低温多晶硅晶体管。在数据写入阶段t2，驱动晶体管T1的响应速度较快，使得数据可以被迅速写入，避免因打开时间较长而造成充电不足，在发光阶段t3，第一发光控制晶体管T5和第二发光控制晶体管T6响应速度较快，使得驱动电流I迅速流入发光器件D1中，避免开启过慢引起显示画面迟滞。
第二源漏极层900还图案化形成第二阻挡构件902，第二阻挡构件902形成第二发光控制晶体管T6的第二漏极，通过第十五过孔015与第二发光控制晶体管T6的的第二电极连接，通过第十六过孔016与发光器件D1的阳极连接，且在氧化物有源层的投影覆盖第二初始化晶体管T7的沟道区。同样地，第二阻挡构件902可以阻挡从第二阻挡构件902远离氧化物有源层一侧入射的环境光，防止其对第二初始化晶体管T7造成干扰，提高了第二初始化晶体管T7的稳定性，也可以作为氢阻挡层，阻挡上方膜层在制程过程中产生的氢离子对氧化物有源层的影响，进一步提高电路的稳定性。综上，第二阻挡构件902可以同时作为第二发光控制晶体管T6的第二漏极、遮光层和氢阻挡层，共同提高像素驱动电路的稳定性，且制作工艺简单，成本较低。
在一种实施例中，显示装置还包括补偿晶体管T3，补偿晶体管T3通过第一节点Q和第三节点B与驱动晶体管T1相连，用于在第三扫描信号Scan 3的控制下，补偿驱动晶体管T1的阈值电压，补偿晶体管T3也为氧化物晶体管。在发光阶段t3，利用氧化薄膜晶体管低漏电流的特性，补偿晶体管T3可以保持住第一节点Q和第三节点B的电位稳定。
第一阻挡构件901在氧化物有源层的投影覆盖补偿晶体管T3的沟道区，因此，第一阻挡构件901对应驱动晶体管T1、补偿晶体管T3和第一初始化晶体管T4，可以同时起到遮光层、氢阻挡层以及耦合电容的作用，共同提高像素驱动电路的稳定性，且制作工艺简单，成本较低。
根据以上实施例可知：
本申请提供一种显示面板和显示装置，显示面板包括阵列设置的多个发光器件和驱动发光器件发光的像素驱动电路，像素驱动电路包括：第一初始化晶体管，用于在第一扫描信号的控制下，向第一节点输入初始化信号；开关晶体管，用于在第二扫描信号的控制下，向第二节点输入数据信号；驱动晶体管，用于在第一节点和第二节点电位的控制下，驱动发光器件发光；补偿晶体管，通过第一节点和第三节点与驱动晶体管相连，用于在第三扫描信号的控制下，补偿驱动晶体管的阈值电压；第二初始化晶体管，用于在第三扫描信号的控制下，向发光器件阳极输入初始化信号；第一发光控制晶体管，通过第二节点与驱动晶体管相连，用于在发光控制信号的控制下，导通电源高电位信号线流向驱动晶体管的电流；第二发光控制晶体管，通过第三节点与驱动晶体管相连，用于在发光控制信号的控制下，导通驱动晶体管流向发光器件阳极的电流；存储电容，通过第一节点与驱动晶体管相连，通过第四节点与电源高电位信号线相连，用于存储数据信号；其中，补偿晶体管、第一初始化晶体管和第二初始化晶体管为氧化物晶体管，开关晶体管、驱动晶体管、第一发光控制晶体管和第二发光控制晶体管为低温多晶硅晶体管。本申请通过将补偿晶体管、第一初始化晶体管和第二初始化晶体管设置为氧化物晶体管，其他晶体管设置为低温多晶硅晶体管，可以同时利用氧化物晶体管的低漏电流特性和低温多晶硅晶体管的高迁移率特性，从而使得像素驱动电路更加稳定，提升了显示面板的显示效果。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板和显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (22)

  1. 一种显示面板，其包括阵列设置的多个发光器件和驱动所述发光器件发光的像素驱动电路，所述像素驱动电路包括：
    第一初始化晶体管，用于在第一扫描信号的控制下，向第一节点输入初始化信号；
    开关晶体管，用于在第二扫描信号的控制下，向第二节点输入数据信号；
    驱动晶体管，用于在所述第一节点和所述第二节点电位的控制下，驱动所述发光器件发光；
    补偿晶体管，通过所述第一节点和第三节点与所述驱动晶体管相连，用于在第三扫描信号的控制下，补偿所述驱动晶体管的阈值电压；
    第二初始化晶体管，用于在所述第三扫描信号的控制下，向所述发光器件阳极输入初始化信号；
    第一发光控制晶体管，通过所述第二节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通电源高电位信号线流向所述驱动晶体管的电流；
    第二发光控制晶体管，通过所述第三节点与所述驱动晶体管相连，用于在所述发光控制信号的控制下，导通所述驱动晶体管流向所述发光器件阳极的电流；
    存储电容，通过所述第一节点与所述驱动晶体管相连，通过第四节点与所述电源高电位信号线相连，用于存储所述数据信号；
    其中，所述补偿晶体管、所述第一初始化晶体管和所述第二初始化晶体管为氧化物晶体管，所述开关晶体管、所述驱动晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管为低温多晶硅晶体管。
  2. 如权利要求1所述的显示面板，其中，所述补偿晶体管、所述第一初始化晶体管和所述第二初始化晶体管为N型晶体管，所述开关晶体管、所述驱动晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管为P型晶体管。
  3. 如权利要求1所述的显示面板，其中，所述显示面板包括自下而上层叠设置的衬底、第一半导体层、第一金属层、第二金属层、第二半导体层、第三金属层、第一源漏极层和第二源漏极层，所述第一半导体层形成各低温多晶硅晶体管的多晶硅有源层，所述第二半导体层形成各氧化物晶体管的氧化物有源层。
  4. 如权利要求3所述的显示面板，其中，所述多晶硅有源层和所述氧化物有源层在所述衬底的投影至少部分重叠。
  5. 如权利要求3所述的显示面板，其中，所述第一金属层图案化形成各氧化物晶体管的顶栅，所述氧化物有源层形成各氧化物晶体管的沟道区，所述第二金属层图案化形成各氧化物晶体管的底栅，所述沟道区在所述衬底的投影落在对应的底栅在所述衬底的投影范围内。
  6. 如权利要求3所述的显示面板，其中，所述第一金属层图案化形成所述存储电容的第一极板，所述第二金属层图案化形成所述存储电容的第二极板。
  7. 如权利要求6所述的显示面板，其中，所述第一源漏极层图案化形成电源高电位信号线，所述第二源漏极层图案化形成第一阻挡构件，所述第一阻挡构件与所述电源高电位信号线连接，且所述第一阻挡构件在所述第一金属层的投影覆盖所述存储电容的第一极板的至少部分区域。
  8. 如权利要求7所述的显示面板，其中，所述第一阻挡构件在所述氧化物有源层的投影覆盖所述补偿晶体管的沟道区和所述第一初始化晶体管的沟道区。
  9. 如权利要求3所述的显示面板，其中，所述第二源漏极层图案化形成第二阻挡构件，所述第二阻挡构件与所述第二发光控制晶体管和所述发光器件阳极相连，且在所述氧化物有源层的投影覆盖所述第二初始化晶体管的沟道区。
  10. 一种显示装置，其包括：
    第一初始化晶体管，用于在第一扫描信号的控制下，向第一节点输入初始化信号；
    开关晶体管，用于在第二扫描信号的控制下，向第二节点输入数据信号；
    驱动晶体管，用于在所述第一节点和所述第二节点电位的控制下，驱动发光器件发光；
    第二初始化晶体管，用于在所述第三扫描信号的控制下，向所述发光器件阳极输入初始化信号；
    其中，所述第一初始化晶体管和所述第二初始化晶体管为氧化物晶体管，所述开关晶体管和所述第二初始化晶体管为不同类型晶体管。
  11. 如权利要求10所述的显示装置，其中，所述开关晶体管为低温多晶硅晶体管。
  12. 如权利要求11所述的显示装置，其中，所述开关晶体管为P型晶体管，所述第一初始化晶体管和所述第二初始化晶体管为N型晶体管。
  13. 如权利要求11所述的显示装置，其中，所述显示装置包括自下而上层叠设置的衬底、第一半导体层、第一金属层、第二金属层、第二半导体层、第三金属层、第一源漏极层和第二源漏极层，所述第一半导体层形成低温多晶硅晶体管的多晶硅有源层，所述第二半导体层形成氧化物晶体管的氧化物有源层。
  14. 如权利要求13所述的显示装置，其中，所述多晶硅有源层和所述氧化物有源层在所述衬底的投影至少部分重叠。
  15. 如权利要求13所述的显示装置，其中，所述第二金属层图案化形成各氧化物晶体管的底栅，所述第三金属层图案化形成各氧化物晶体管的顶栅，所述氧化物有源层形成各氧化物晶体管的沟道区，所述沟道区在所述衬底的投影落在对应的底栅在所述衬底的投影范围内。
  16. 如权利要求13所述的显示装置，其中，所述显示装置还包括存储电容，所述存储电容通过所述第一节点与所述驱动晶体管相连，通过第四节点与所述电源高电位信号线相连，用于存储所述数据信号，所述第一金属层图案化形成所述存储电容的第一极板，所述第二金属层图案化形成所述存储电容的第二极板。
  17. 如权利要求16所述的显示装置，其中，所述第一源漏极层图案化形成电源高电位信号线，所述第二源漏极层图案化形成第一阻挡构件，所述第一阻挡构件与所述电源高电位信号线连接，且所述第一阻挡构件在所述第一金属层的投影覆盖所述存储电容的第一极板的至少部分区域。
  18. 如权利要求17所述的显示装置，其中，所述第一阻挡构件在所述氧化物有源层的投影覆盖所述第一初始化晶体管的沟道区。
  19. 如权利要求13所述的显示装置，其中，所述显示装置还包括：
    第一发光控制晶体管，通过所述第二节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通电源高电位信号线流向所述驱动晶体管的电流；
    第二发光控制晶体管，通过所述第三节点与所述驱动晶体管相连，用于在所述发光控制信号的控制下，导通所述驱动晶体管流向所述发光器件阳极的电流；
    所述驱动晶体管、第一发光控制晶体管和所述第二发光控制晶体管为多晶硅晶体管。
  20. 如权利要求19所述的显示装置，其中，所述第二源漏极层图案化形成第二阻挡构件，所述第二阻挡构件与所述第二发光控制晶体管和所述发光器件阳极相连，且在所述氧化物有源层的投影覆盖所述第二初始化晶体管的沟道区。
  21. 如权利要求17所述的显示装置，其中，所述显示装置还包括补偿晶体管，所述补偿晶体管通过所述第一节点和第三节点与所述驱动晶体管相连，用于在第三扫描信号的控制下，补偿所述驱动晶体管的阈值电压，所述补偿晶体管为氧化物晶体管。
  22. 如权利要求21所述的显示装置，其中，所述第一阻挡构件在所述氧化物有源层的投影覆盖所述补偿晶体管的沟道区。
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