WO2022012336A1 - 半导体结构制作方法 - Google Patents

半导体结构制作方法 Download PDF

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Publication number
WO2022012336A1
WO2022012336A1 PCT/CN2021/103708 CN2021103708W WO2022012336A1 WO 2022012336 A1 WO2022012336 A1 WO 2022012336A1 CN 2021103708 W CN2021103708 W CN 2021103708W WO 2022012336 A1 WO2022012336 A1 WO 2022012336A1
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layer
etching
dielectric layer
trench
semiconductor structure
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English (en)
French (fr)
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鲍锡飞
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/449,555 priority Critical patent/US11862513B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

Definitions

  • the embodiments of the present application relate to a method for fabricating a semiconductor structure.
  • Dynamic random access memory (DRAM) memory cells include capacitors for storing charge and transistors that act as switches. As the geometric size of DRAM memory cells continues to decrease according to Moore's Law, the aspect ratio of capacitors gradually increases.
  • An embodiment of the present application provides a method for fabricating a semiconductor structure, including: providing a substrate; forming a blocking layer on the substrate; forming a sacrificial layer on the blocking layer; using a photolithography process on the sacrificial layer forming an opening pattern above; using the blocking layer as an etch stop layer, etching the sacrificial layer according to the opening pattern to form a first trench; filling the first trench with a dielectric layer material; The blocking layer is an etch stop layer, the sacrificial layer is etched to form a second trench; the hard mask layer material is filled in the second trench; the blocking layer is used as an etch stop layer to etch The dielectric layer material forms a hard mask layer.
  • 1 is a schematic cross-sectional view of a semiconductor structure
  • FIGS. 2 to 14 are schematic cross-sectional structural diagrams corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present application.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor structure.
  • the semiconductor structure includes: a dielectric layer 11 and a hard mask layer 12 located above the dielectric layer 11.
  • the same etching process has relatively small etching options for the hard mask layer 12 and the dielectric layer 11, and the hard mask layer 12 has a relatively high etch selectivity. hardness and greater thickness.
  • the hard mask layer 12 In the process of etching the hard mask layer 12 to form the opening pattern 13, since the hard mask layer 12 has high hardness and large thickness, it is easy to cause the sidewall of the opening pattern 13 formed by the final etching to be not vertical. on the surface of the dielectric layer 11 .
  • an opening pattern 13 with etching defects is used for selective etching to form a plurality of discrete capacitor holes, the problem of penetrating through adjacent capacitor holes may occur.
  • the etching selection of the hard mask layer 12 and the dielectric layer 11 in the same etching process is relatively small, after the opening pattern 13 is formed by etching, the excess etchant is in contact with the dielectric layer 11, thereby causing damage to the dielectric layer 11. Mis-etched. Mis-etching may lead to changes in the performance of the dielectric layer 11 , such as weakening of the support capability, damage to electronic components located inside the dielectric layer 11 , and the like.
  • the present application provides a method for fabricating a semiconductor structure, which adjusts the difficulty of etching by controlling the material of the sacrificial layer, so as to ensure that the first trench formed by etching has a preset shape, so as to make the subsequently formed trenches consistent with the first trenches.
  • a second trench that is complementary to the trench and the hard mask layer filled in the second trench have a predetermined shape; in addition, a blocking layer that can be used as an etch stop layer is formed on the substrate, which is beneficial to avoid the same
  • the etching process causes etching damage to the substrate.
  • FIGS. 2 to 11 are schematic cross-sectional structural diagrams corresponding to each step of a method for fabricating a semiconductor structure provided by an embodiment of the present application. details as follows:
  • a substrate 21 is provided; a blocking layer 22 is formed on the substrate 21; a sacrificial layer 23 is formed on the blocking layer 22; an opening pattern 244 is formed on the sacrificial layer 23 by a photolithography process.
  • the substrate 21 is a multi-layered structure
  • the multi-layered structure includes a conductive structure 210 , a second dielectric layer 213 , a second support layer 214 , a first dielectric layer 215 and a first Support layer 216 .
  • the first support layer 216 and the second support layer 214 play a supporting role in the substrate 21 to prevent the substrate 21 from collapsing during the process of forming the capacitor hole;
  • the conductive structure 210 includes an insulating medium 211 and a conductive layer 212, and the conductive layer
  • the material of 212 includes tungsten or a compound of tungsten.
  • the blocking layer 22 is used as an etching stop layer, so that the etching process stops etching after the sacrificial layer 23 is penetrated and the surface of the blocking layer 22 is exposed, so as to avoid the etching process causing mis-etching of the substrate 21, thereby ensuring The substrate 21 has good properties.
  • the etching selectivity ratio between the sacrificial layer 23 and the blocking layer 22 is greater than 100; the material of the sacrificial layer 23 includes carbon-containing materials, and the carbon-containing materials include organic carbides (such as resins) and inorganic carbides (such as silicon carbide) , the material of the blocking layer 22 includes titanium nitride.
  • the hardness of the sacrificial layer 23 is smaller than the hardness of the subsequently formed hard mask layer. In this way, it is beneficial to avoid etching defects caused by excessive material hardness, and when the sacrificial layer 23 is etched to form a trench, it can be ensured that the formed trench has a preset shape.
  • the pattern transfer layer 24 is formed on the sacrificial layer 23 , and the pattern transfer layer 24 includes the isolation layer 241 , the anti-reflection layer and the Coating 242 and photoresist layer 243.
  • the isolation layer 241 is used to isolate the sacrificial layer 23 and the photoresist layer 243 to avoid damage to the sacrificial layer 23 caused by the removal process of the photoresist layer 243 or to change the material properties of the sacrificial layer 23 .
  • the removal process of the photoresist layer 243 includes an ashing process.
  • the ashing process is usually used to remove carbides such as organic materials.
  • the material of the sacrificial layer 23 is a carbide material that will be affected by the ashing process, a certain thickness of isolation is used.
  • the layer 241 isolates the sacrificial layer 23 and the photoresist layer 243, which is beneficial to avoid damage to the sacrificial layer 23 caused by the ashing process, remove part of the sacrificial layer 23 or change the performance of the material of the sacrificial layer 23, and ensure that the first trench formed subsequently has better shape.
  • the isolation layer 241 is used for isolation, which is beneficial to prevent the polysilicon from being oxidized by the ashing process to form silicon dioxide, thereby ensuring that the sacrificial layer 23 has preset physical properties, especially Hardness properties.
  • the isolation layer 231 may not be needed.
  • the material of the isolation layer 231 includes at least one of nitride or silicide.
  • a pre-opening 241a is formed in the anti-reflection coating 242 and the isolation layer 241 according to the opening pattern 244;
  • the photoresist layer 243 is removed after the pre-opening 241a.
  • the exposed area refers to the area exposed to the air or the process environment.
  • an oxygen plasma is formed by ionizing an oxygen source gas to perform dry etching, and the exposed area is an area that can be contacted by the oxygen plasma or the oxygen source gas.
  • Removing the photoresist layer 243 in advance enables the etchant in the process of removing the photoresist layer 243 to only contact the bottom surface area of the pre-opening 241a instead of the material of the sacrificial layer 23 on the sidewall of the first trench.
  • the etching defect will be etched through the pre-opening 241a in the subsequent sacrificial layer 23 to form
  • the topography of the formed first trench will not deviate from the preset topography due to damage, removal or modification of the material of the sacrificial layer 23 on the sidewall of the first trench, so as to ensure the first trench. Accurate and complete groove topography.
  • the first step can be formed in the sacrificial layer 23 directly through the opening pattern 244 (refer to FIG. 2 ) disposed in the photoresist layer 243 (refer to FIG. 2 ). a groove.
  • the sacrificial layer 23 is etched according to the pre-opening 241 a (refer to FIG. 3 ) to form the first trench 231 .
  • a maskless dry process may be used to etch and remove part of the sacrificial layer 23 to form the first trench 231 .
  • the anti-reflection coating 242 (refer to FIG. 3 ) on the top surface of the isolation layer 241 is removed.
  • the material of the sacrificial layer 23 is organic carbide.
  • organic carbides have lower hardness, are easier to be etched, and have better trench morphology after etching. In this way, it is beneficial to shorten the process time and ensure that the trench has a good shape.
  • the dielectric layer material 251 is filled in the first trench 231 (refer to FIG. 3 ), and the isolation layer 241 (refer to FIG. 3 ) is removed.
  • the mask used in the photolithography process is the existing mask.
  • the orthographic projection of the opening of the existing mask and the conductive layer in the conductive structure 210 are at least partially overlapped, that is, the first trench 231 is etched to form a capacitor hole exposing the conductive layer 212 .
  • the capacitor hole exposing the conductive layer 212 can be formed by etching the hard mask layer, it is necessary to fill the dielectric layer material 251 in the first trench 231 to occupy a physical position, and to selectively etch by adjusting the etching process Remove the sacrificial layer 23 in a certain area, and after the etching of the sacrificial layer 23 is completed, fill the hard mask material to the original position of the sacrificial layer 23, so that the hard mask material surrounds and fills the space between the adjacent dielectric layer materials 251 . In this way, the hard mask layer can be formed after the dielectric layer material 251 is removed, and the hard mask layer has openings that can be etched to form capacitor holes.
  • the hard mask layer material may be directly filled in the first trench, and the sacrificial layer may be removed by etching to form the hard mask layer. It should be noted that, in order to ensure that the capacitor hole exposing the conductive layer can be etched through the opening of the hard mask layer, when this technical solution is adopted, the mask used in the photolithography process is complementary to the existing mask. , that is, the opening position of the mask is opposite.
  • the etching selection ratio between the material of the sacrificial layer 23 and the material of the hard mask should also be considered.
  • the same etching process has relatively small etching choices for the sacrificial layer 23 material and the hard mask material, which may damage, consume or modify the hard mask material in the process of etching the sacrificial layer 23, the existing mask.
  • the dielectric layer material 251 can be filled so that the dielectric layer material 251 and the sacrificial layer 23 material, as well as the dielectric layer material 251 and the hard mask material have a larger etching selectivity ratio, so as to avoid etching the sacrificial layer 23 and etching
  • the etching process of the dielectric layer material 251 changes the trench morphology, thereby ensuring that a plurality of discrete capacitor holes can be finally formed.
  • the first trench 231 can be filled with the dielectric layer material 251 first, and then a planarization process is performed to remove the excess dielectric layer material 251 and the isolation layer 241; the isolation layer 241 can also be removed first, and then the A trench 231 is filled with dielectric layer material 251 and a planarization process is performed.
  • the etching selectivity ratio between the dielectric layer material 251 and the blocking layer 22 is greater than 100. In this way, it is beneficial to prevent the blocking layer 22 from being cut through, and to ensure that the performance of the substrate 21 is not affected.
  • the dielectric layer material 251 includes one of oxide and nitride, for example, one of silicon oxide, silicon nitride or silicon oxynitride.
  • FIG. 6 is a schematic top view of the semiconductor structure shown in FIG. 5 .
  • the sacrificial layer 23 is a continuous and complete film layer, the dielectric layer material 251 is located in a plurality of through holes in the sacrificial layer 23 , and the arrangement pattern of the through holes is the same as that of the conductive layer 212 .
  • the dielectric layer materials 251 in adjacent rows/columns are arranged in dislocation; correspondingly, the conductive layers 212 in adjacent rows/columns are arranged in dislocation.
  • the spacing between adjacent through holes is related to the characteristic parameters of the capacitor to be formed subsequently, and the characteristic parameters include the thickness of the electrode layers, the distance between adjacent electrode layers, and whether the electrode layers are shared.
  • the characteristic parameters include the thickness of the electrode layers, the distance between adjacent electrode layers, and whether the electrode layers are shared.
  • the spacing between adjacent vias is also related to the following characteristic parameters, including: the etching selectivity ratio of the sacrificial layer 23 and the barrier layer 22 in the same etching process, the dielectric layer material 251 and the barrier layer in the same etching process The etching selectivity ratio of 22, and the thickness of the columnar capacitor formed subsequently.
  • the same etching process has a relatively high etching selection for other materials and the blocking layer 22, which only means that the etching rate of the etchant on the blocking layer 22 is relatively low, and the etching is still will occur, therefore, the blocking layer 22, which is the etching stop layer, will definitely be etched during the process of etching the sacrificial layer 23 and the subsequent etching of the dielectric layer material 251, and as long as the etching occurs, there may be errors.
  • etching condition The degree of mis-etching is related to the etching selectivity ratio of other materials and the blocking layer 22 in the same etching process. The higher the etching selectivity ratio, the lower the mis-etching degree.
  • the mis-etching in the blocking layer 22 will be gradually enlarged, so that the gap between adjacent capacitor holes will be gradually enlarged.
  • the minimum spacing is gradually reduced.
  • the lower the mis-etching degree of the blocking layer 22 the larger the minimum distance between adjacent capacitor holes, and the higher the degree of separation of adjacent capacitor holes; the thinner the thickness of the columnar capacitor, the greater the degree of mis-etching. The lower it is, the more discrete the adjacent capacitive holes are.
  • the spacing between adjacent through holes needs to be controlled according to the above multiple characteristic parameters, so as to ensure that the adjacent capacitor holes have a high degree of separation, thereby ensuring the performance of the finally formed semiconductor structure.
  • the sacrificial layer 23 (refer to FIG. 5 ) is etched by using the blocking layer 22 as an etch stop layer to form a second trench 232 .
  • the second trench 232 is complementary to the first trench, and the second trench 232 is used for for filling hard mask material.
  • the material of the dielectric layer 251 and the material of the sacrificial layer 23 have a relatively high selection ratio. In this way, when the sacrificial layer 23 is etched, the sacrificial layer 23 can be etched and removed by using a maskless dry etching process, without setting an additional mask and forming an additional mask layer, which is beneficial to reduce the process cost and process step.
  • a hard mask material is filled in the second trench, and the hard mask material is used to form the hard mask layer 261 .
  • the selection of the hard mask material can be made according to process requirements, and the process requirements include: hardness, etching selection ratio with the dielectric layer material 251, and the like.
  • the hard mask layer formed by using the hard mask material can better define the dry etching process. ensure that the sidewall of the third groove formed by etching is perpendicular to the top surface of the conductive structure 210, thereby ensuring the separation of the capacitor holes; correspondingly, the higher the etching selection ratio of the dielectric layer material 251, In the process of etching the dielectric layer material 251 to form the hard mask layer 261, the less damage to the hard mask material by the etching process, the higher the perpendicularity between the sidewall of the hard mask layer 261 and the substrate 21, so that the The hard mask layer 261 can better define the etching direction of the dry etching process, thereby ensuring the separation of the capacitor holes.
  • the perpendicularity refers to the closeness of the included angle between two straight lines to the right angle (ie, 90° angle). The higher the perpendicularity, the higher the closeness, and the lower the perpendicularity, the lower the closeness.
  • the hard mask material includes polysilicon; in other embodiments, the hard mask material further includes an organic material with higher hardness such as polyimide. Compared with organic materials, polysilicon is a common material with low cost. Using polysilicon as a hard mask material is beneficial to reduce process costs.
  • the same etching process may have a lower etching selectivity ratio for the two. Therefore, the organic material is used as the hard mask.
  • the film materials and the two etching options are relatively low, it is suitable to use the existing mask to form the capacitor hole.
  • the hard mask material and the sacrificial layer material will not exist at the same time, and by controlling the type of the dielectric layer material, the dielectric layer material and the hard mask material, as well as the dielectric layer material and the sacrificial layer material can be improved.
  • the etching selectivity ratio of the material further ensures that the finally formed hard mask layer has a good sidewall morphology, that is, the sidewall of the hard mask layer and the top surface of the substrate 21 have a high verticality.
  • an existing mask can be used to form the capacitor holes, or another mask complementary to the existing mask can be used to form the capacitor holes.
  • another complementary mask is used as the capacitor hole, since the same etching process has a relatively high selection for etching polysilicon and organic carbide, it can ensure that the sidewall of the final hard mask layer 261 has a good morphology. , and the process steps can be reduced, which is beneficial to shorten the process cycle.
  • the dielectric layer material is etched to form a hard mask layer 261 .
  • the blocking layer 22 , the first support layer 216 , the first dielectric layer 215 , the second support layer 214 , and the second dielectric layer 213 are sequentially etched based on the hard mask layer 261 to form a third trench exposing the conductive layer 212 Slot 211.
  • different etchants can be selected according to the material properties of the etched object, or the same etchant can be selected.
  • the hardness of the first support layer 216 and the second support layer 214 is generally greater than that of the materials of the first dielectric layer 215 and the second dielectric layer 213 due to the need to play a supporting role.
  • different etchants with different main etching components or different concentrations of main etching components can be used to etch the first support layer 216 and the first dielectric layer 215 respectively, so as to ensure that the overall etching process has Higher etching rate, shorten the process cycle.
  • the same etching process has a relatively high etch selection for the hard mask layer 261 and the blocking layer 22 , the first support layer 216 , the first dielectric layer 215 , the second support layer 214 and the second dielectric layer 213 .
  • the hard mask layer 261 can always maintain a high sidewall profile.
  • the hard mask layer 261 (refer to FIG. 12) and the blocking layer 22 (refer to FIG. 12) are removed.
  • the specific process for removing the hard mask layer 261 and the blocking layer 22 it should be considered to avoid the generation of large tensile stress, so as to avoid the collapse of the structure or the dislocation of the adjacent film layers due to the excessive tensile stress.
  • the movement ensures that the sidewall of the third groove 211 has a high verticality, thereby ensuring that a film layer with good quality can be formed on the sidewall and bottom of the third groove 211 , and improving the quality of the finally formed columnar capacitor structure.
  • a first conductive layer 221 is formed on the sidewall and bottom of the third trench 211 (refer to FIG. 13 ); a part of the first support layer is removed, a part of the first dielectric layer is removed, a part of the second support layer is removed, and a part is removed
  • the second dielectric layer; the dielectric layer 231 and the second conductive layer 241 are formed to form a columnar capacitor structure.
  • the columnar capacitor structure is a double-layer columnar capacitor structure. Since the outermost layer of each double-layer columnar capacitor structure is the second conductive layer 241, the outermost conductive layer of the adjacent double-layer columnar capacitor structure can be shared.
  • the formation process of the double-layer columnar capacitor structure includes the following steps:
  • the setting of layer 231 reserves space.
  • a maskless etching process can be directly used, and no special mask is required, which is beneficial to reduce the process cost;
  • the vacant area of is filled with conductive material to form a second conductive layer 241 that completely surrounds the dielectric layer 231 and can be shared by adjacent columnar capacitor structures, which is beneficial to improve the capacitance and space utilization of the columnar capacitor structures.
  • part of the first support layer, part of the first dielectric layer, part of the second support layer may be removed to form a part of the second conductive layer surrounding the dielectric layer, and/or a second conductive layer that cannot be shared may be formed.
  • Two conductive layers When this type of columnar capacitor structure is designed, other elements can be formed in the dielectric material not occupied by the second conductive layer, thereby improving the integration degree of the semiconductor structure.
  • a dielectric layer 231 is respectively formed on the inner sidewall and the outer sidewall of the first conductive layer 221;
  • the second conductive layer 241 between the dielectric layers 231 shortens the process cycle of the semiconductor structure.
  • the etching difficulty of the sacrificial layer can be adjusted by controlling the material of the sacrificial layer, and the etching selectivity ratio of the dielectric layer material and the hard mask layer material can be controlled by controlling the material of the dielectric layer, so as to avoid the effect of the etching process on the hard mask layer. Damage to the film layer ensures that the finally formed hard mask layer has a good shape; in addition, a barrier layer is formed on the substrate, and the arrangement of the barrier layer is beneficial to avoid mis-etching of the substrate by the etching process.

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Abstract

本申请实施例提供一种半导体结构制作方法，包括：提供一衬底；在衬底上方形成一阻拦层；在阻拦层上方形成一牺牲层；利用光刻工艺在牺牲层上方形成一开口图案；以阻拦层为刻蚀停止层，根据开口图案刻蚀牺牲层，形成第一沟槽；在第一沟槽中填充介质层材料；以阻拦层为刻蚀停止层，刻蚀牺牲层，形成第二沟槽；在第二沟槽中填充硬掩膜层材料；以阻拦层为刻蚀停止层，刻蚀介质层材料，形成硬掩膜层。

Description

半导体结构制作方法
交叉引用
本申请要求于2020年7月14日递交的名称为“半导体结构制作方法”、申请号为202010672968.4的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及一种半导体结构制作方法。
背景技术
动态随机存取存储器(DRAM)存储单元包括用于存储电荷的电容器和当作开关的晶体管。随着DRAM存储单元的几何尺寸按照摩尔定律不断减小，电容的深宽比逐渐增大。
发明内容
本申请实施例提供一种半导体结构制作方法，包括：提供一衬底；在所述衬底上方形成一阻拦层；在所述阻拦层上方形成一牺牲层；利用光刻工艺在所述牺牲层上方形成一开口图案；以所述阻拦层为刻蚀停止层，根据所述开口图案刻蚀所述牺牲层，形成第一沟槽；在所述第一沟槽中填充介质层材料；以所述阻拦层为刻蚀停止层，刻蚀所述牺牲层，形成第二沟槽；在所述第二沟槽中填充硬掩膜层材料；以所述阻拦层为刻蚀停止层，刻蚀所述介质层材料，形成硬掩膜层。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为一种半导体结构的剖面示意图；
图2至图14为本申请一实施例提供的半导体结构制作方法各步骤对应的剖面结构示意图。
具体实施方式
参考图1，图1为一种半导体结构的剖面示意图。半导体结构包括：介质层11和位于介质层11上方的硬掩膜层12，同一刻蚀工艺对硬掩膜层12和介质层11的刻蚀选择比较小，硬掩膜层12具有较高的硬度和较大的厚度。
在刻蚀硬掩膜层12以形成开口图案13的过程中，由于硬掩膜层12具有较高的硬度和较大的厚度，容易导致最终刻蚀形成的开口图案13的侧壁并不垂直于介质层11的表面。在利用这一类带有刻蚀缺陷的开口图案13进行选择性刻蚀，以形成多个分立的电容孔时，可能出现相邻电容孔贯通的问题。
此外，由于同一刻蚀工艺对硬掩膜层12和介质层11的刻蚀选择比较小，在刻蚀形成开口图案13后，多余的刻蚀剂与介质层11接触，进而对介质层11造成误刻蚀。误刻蚀可能会导致介质层11的性能发生改变，如支撑能力减弱，位于介质层11内部的电子元件被破坏等等。
为解决上问题，本申请实施提供一种半导体结构制作方法，通过控制牺牲层的材料来调整刻蚀难度，保证刻蚀形成的第一沟槽具有预设形貌，进而使得后续形成的与第一沟槽互补的第二沟槽、以及填充于第二沟槽的硬掩膜层具有预设形貌；此外，在衬底上形成有可作为刻蚀停止层的阻拦层，有利于避免同一刻蚀工艺对衬底造成刻蚀损伤。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图2至图11本申请一实施例提供的半导体结构制作方法各步骤对应的剖面结构示意图。具体如下：
参考图2，提供一衬底21；在衬底21上方形成一阻拦层22；在阻拦层22上方形成一牺牲层23；利用光刻工艺在牺牲层23上方形成一开口图案244。
本实施例中，衬底21为多层叠层结构，多层叠层结构包括向同一方向依次叠放的导电结构210、第二介质层213、第二支撑层214、第一介质层215以 及第一支撑层216。其中，第一支撑层216和第二支撑层214在衬底21中起到支撑作用，避免形成电容孔的过程中衬底21发生坍塌；导电结构210包括绝缘介质211和导电层212，导电层212的材料包括钨或钨的化合物。
本实施例中，阻拦层22用作刻蚀停止层，使得刻蚀工艺在贯穿牺牲层23且暴露阻拦层22表面后停止刻蚀，避免刻蚀工艺对衬底21造成误刻蚀，从而保证衬底21具有良好性能。
本实施例中，牺牲层23与阻拦层22的刻蚀选择比大于100；牺牲层23的材料包括含碳材料，含碳材料包括有机碳化物(例如树脂)和无机碳化物(例如碳化硅)，阻拦层22的材料包括氮化钛。
本实施例中，牺牲层23的硬度小于后续形成的硬掩膜层的硬度。如此，有利于避免材料硬度过大导致的刻蚀缺陷，在刻蚀牺牲层23形成沟槽时，能够保证形成的沟槽具有预设的形貌。
本实施例中，在进行光刻工艺以形成开口图案244之前，在牺牲层23上方形成图案转移层24，图案转移层24包括在远离衬底21的方向上依次层叠的隔离层241、抗反射涂层242以及光刻胶层243。其中，隔离层241用于隔离牺牲层23和光刻胶层243，避免光刻胶层243的去除工艺对牺牲层23造成损伤或者改变牺牲层23的材料的特性。
光刻胶层243的去除工艺包括灰化工艺，灰化工艺通常用于去除有机材料等碳化物，在牺牲层23的材料为会受到灰化工艺影响的碳化物材料时，采用一定厚度的隔离层241隔离牺牲层23和光刻胶层243，有利于避免灰化工艺对牺牲层23造成损伤、去除部分牺牲层23或者改变牺牲层23的材料的性能，保证后续形成的第一沟槽具有较好的形貌。
此外，当牺牲层23的材料为多晶硅时，采用隔离层241进行隔离，有利于避免灰化工艺会对多晶硅造成氧化而形成二氧化硅，从而保证牺牲层23具有预设的物理特性，尤其是硬度特性。
相应的，当灰化工艺不会对牺牲层23的材料造成损伤，以及不会改变牺牲层23的材料特性时，也可以不需要隔离层231。其中，隔离层231的材料包括氮化物或硅化物中的至少一者。
参考图3，在光刻胶层243(参考图2)内形成开口图案244(参考图2)之后，根据开口图案244在抗反射涂层242和隔离层241内形成预开口241a；且在形成预开口241a之后去除光刻胶层243。
由于后续需要刻蚀牺牲层23以形成第一沟槽，而第一沟槽的侧壁面积通常大于预开口241a的底面面积，因此，第一沟槽的形成会增加牺牲层23的暴露面积，暴露面积指的是暴露在空气中或者工艺环境下的面积。举例来说，灰化工艺为通过电离氧源气体形成氧等离子体以进行干法刻蚀，暴露面积为氧等离子体或氧源气体可接触的面积。
预先去除光刻胶层243，能够使得光刻胶层的243的去除工艺中的刻蚀剂仅与预开口241a的底面面积接触，而并非与第一沟槽侧壁的牺牲层23材料接触。如此，即便刻蚀剂会损伤、去除或改性预开口241a底部的部分牺牲层23材料，形成一定的刻蚀缺陷，这一刻蚀缺陷也会在后续通过预开口241a刻蚀牺牲层23以形成第一沟槽时被消除，而不会因为损伤、去除或改性第一沟槽侧壁的牺牲层23的材料，导致形成的第一沟槽的形貌偏离预设形貌，保证第一沟槽形貌的准确和完整。
当灰化工艺不会影响牺牲层23而无需设置隔离层241时，可直接通过设置于光刻胶层243(参考图2)内的开口图案244(参考图2)在牺牲层23内形成第一沟槽。
参考图4，以阻拦层22作为刻蚀停止层，根据预开口241a(参考图3)刻蚀牺牲层23，形成第一沟槽231。
需要说明的是，当隔离层241的材料硬度大于牺牲层23的材料硬度时，可以采用无掩膜干法工艺刻蚀去除部分牺牲层23，形成第一沟槽231。在执行无掩膜干法刻蚀工艺时，位于隔离层241顶面的抗反射涂层242(参考图3)会被去除。
本实施例中，牺牲层23的材料为有机碳化物。通常情况下，有机碳化物相较于无机碳化物而言，具有更低的硬度，更容易被刻蚀，且刻蚀之后具有更好的沟槽形貌。如此，有利于缩短工艺耗时，以及保证沟槽具有良好形貌。
参考图5，在第一沟槽231(参考图3)中填充介质层材料251，并去除隔离层241(参考图3)。
本实施例中，进行光刻工艺所使用的掩膜版为现有掩膜版，在垂直于衬底21表面的方向上，现有掩膜版的开口的正投影与导电结构210中导电层212的正投影至少部分重合，即可通过第一沟槽231刻蚀形成暴露导电层212的电容孔。
因此，为保证能够通过硬掩模层刻蚀形成暴露导电层212的电容孔，需要在第一沟槽231内填充介质层材料251，占据物理位置，并通过调整刻蚀工艺，选择性刻蚀去除一定区域内的牺牲层23，以及在完成牺牲层23的刻蚀后，填充硬掩模材料至原有的牺牲层23所在位置，使得硬掩模材料环绕填充相邻介质层材料251之间。如此，才能在去除介质层材料251后形成硬掩模层，且硬掩模层具有可用于刻蚀形成电容孔的开口。
在其他实施例中，可直接在第一沟槽中填充硬掩膜层材料，并刻蚀去除牺牲层，以形成硬掩膜层。需要说明的是，为保证通过硬掩膜层的开口能够刻蚀出暴露导电层的电容孔，在采用这一技术方案时，进行光刻工艺所使用的掩膜版与现有掩膜版互补，即掩膜版的开口位置相反。
需要说明的是，在选择不同的掩膜版以形成电容孔时，除了要考虑掩膜版的获取难度以外，还要考虑牺牲层23的材料与硬掩模材料的刻蚀选择比。当同一刻蚀工艺对牺牲层23材料和对硬掩模材料的刻蚀选择比较小，导致在刻蚀牺牲层23的过程中可能损伤、消耗或改性硬掩模材料时，可采用现有掩膜版。如此，可通过填充介质层材料251，使得介质层材料251与牺牲层23材料、以及介质层材料251和硬掩模材料都具有较大的刻蚀选择比，避免刻蚀牺牲层23和刻蚀介质层材料251的刻蚀工艺改变沟槽形貌，从而保证最终能够形成多个分立的电容孔。
本实施例中，可先在第一沟槽231内填充满介质层材料251，再进行平坦化工艺，去除多余的介质层材料251以及隔离层241；也可以先去除隔离层241，再在第一沟槽231内填充满介质层材料251并进行平坦化工艺。
本实施例中，介质层材料251与阻拦层22的刻蚀选择比大于100。如此，有利于避免阻拦层22被刻穿，保证基底21的性能不受影响。
其中，介质层材料251包括氧化物、氮化物的一种，例如氧化硅、氮化硅或氮氧化硅中的一种。
参考图6，图6为图5所示半导体结构的俯视结构示意图。
牺牲层23为连续完整的膜层，介质层材料251位于牺牲层23内的若干个通孔中，通孔的排列图案与导电层212的排列图案相同。
本实施例中，相邻行/列的介质层材料251呈错位排列；相应地，相邻行/列的导电层212呈错位排列。如此，有利于提高空间利用率，增加同一横截面积内所能形成的通孔/导电层212的数量，提高半导体结构的集成度。
本实施例中，相邻通孔之间的间距与后续所要形成的电容的特征参数有关，特征参数包括电极层的厚度、相邻电极层之间的距离以及电极层是否共用。在控制相邻通孔之间的间距时，既要保证有足够间距去形成电极层，又要保证相邻电极层之间的介电层不会因为过薄而发生击穿或漏电，还要保证电极层与介电层构成的电容的电容值满足预设要求。
此外，相邻通孔之间的间距还与以下特征参数有关，其中包括：同一刻蚀工艺对牺牲层23与阻挡层22的刻蚀选择比、同一刻蚀工艺对介质层材料251与阻挡层22的刻蚀选择比、以及后续形成的柱状电容的厚度。
具体来说，由于在半导体结构的实际制造过程中，同一刻蚀工艺对其他材料和阻拦层22刻蚀选择比较高，仅代表刻蚀剂对阻拦层22的刻蚀速率较低，刻蚀依旧会发生，因此，作为刻蚀停止层的阻拦层22，在刻蚀牺牲层23以及后续刻蚀介质层材料251的工艺过程中一定会被刻蚀，而只要发生了刻蚀，就可能存在误刻蚀的情况。误刻蚀的程度与同一刻蚀工艺对其他材料和阻拦层22的刻蚀选择比有关，刻蚀选择比越高，误刻蚀的程度就越低。
在后续形成分立的电容孔的工艺过程中，即从刻蚀阻拦层22到暴露导电层212的工艺过程中，阻拦层22中的误刻蚀会被逐渐放大，使得相邻电容孔之间的最小间距逐渐缩小。此时，阻拦层22的误刻蚀程度越低，相邻电容孔之间的最小间距越大，相邻电容孔的分立程度越高；柱状电容的厚度越薄，误刻蚀被放大的程度越低，相邻电容孔的分立程度越高。
本实施例中，需要根据以上多个特征参数控制相邻通孔之间的间距，从而保证相邻电容孔具有较高的分立程度，进而保证最终形成的半导体结构的性能。
参考图7，以阻拦层22为刻蚀停止层，刻蚀牺牲层23(参考图5)，形成第二沟槽232，第二沟槽232与第一沟槽互补，第二沟槽232用于填充硬掩膜材料。
本实施例中，介质层材料251与牺牲层23的材料具有较高的选择比。如此，在刻蚀牺牲层23时，可采用无掩膜干法刻蚀工艺刻蚀去除牺牲层23，无需设置额外的掩膜版以及形成额外的掩膜层，有利于降低工艺成本以及减少工艺步骤。
参考图8和图9，在第二沟槽内填充硬掩膜材料，硬掩膜材料用于形成硬掩膜层261。
硬掩模材料的选择可以根据工艺要求进行，工艺要求包括：硬度、与介质层材料251的刻蚀选择比等。
硬掩膜材料的硬度越高，在后续形成第三凹槽的工艺过程中，越难被刻蚀，如此，采用硬掩膜材料形成的硬掩膜层可以更好地限定干法刻蚀工艺的刻蚀方向，保证刻蚀形成的第三凹槽的侧壁垂直于导电结构210的顶面，进而保证电容孔的相互分立；相应地，与介质层材料251的刻蚀选择比越高，在刻蚀介质层材料251形成硬掩膜层261的过程中，刻蚀工艺对硬掩膜材料的损伤越小，硬掩膜层261的侧壁与衬底21的垂直度越高，从而使得硬掩膜层261能够更好地限定干法刻蚀工艺的刻蚀方向，从而保证电容孔的分立。
垂直度指的是两条直线之间的夹角与直角(即90°角)的接近程度，垂直度越高，接近程度越高，垂直度越低，接近程度越低。
本实施例中，硬掩模材料包括多晶硅；在其他实施例中，硬掩模材料还包括聚酰亚胺等具有较高硬度的有机材料。相较于有机材料而言，多晶硅为常见材料，成本较低，采用多晶硅作为硬掩膜材料有利于降低工艺成本。
此外，由于作为硬掩膜材料的有机材料和作为牺牲层材料的有机碳化物同属于含碳化合物，同一刻蚀工艺对两者的刻蚀选择比可能较低，因此，采用有机材料作为硬掩膜材料，且两者刻蚀选择比较低时，适合采用现有掩膜版形成电容孔。如此，在同一刻蚀工艺过程中，硬掩膜材料和牺牲层材料不会同时存在，且可通过控制介质层材料的类型，提高介质层材料与硬掩膜材料、以及介质层材料与牺牲层材料的刻蚀选择比，进而保证最终形成的硬掩膜层具有良 好的侧壁形貌，即硬掩膜层的侧壁与衬底21顶面具有较高的垂直度。
相应的，采用多晶硅作为硬掩膜材料时，既可选用现有掩膜版形成电容孔，也可以选用与现有掩膜版互补的另一掩膜版形成电容孔。选用互补的另一掩膜版作为电容孔时，由于同一刻蚀工艺对多晶硅和有机碳化物的刻蚀选择比较高，因此，既可以保证最终形成的硬掩膜层261的侧壁形貌良好，又可以减少工艺步骤，有利于缩短工艺周期。
参考图10和图11，以阻拦层22为刻蚀停止层，刻蚀介质层材料，形成硬掩膜层261。参考图12，基于硬掩膜层261依次刻蚀阻拦层22、第一支撑层216、第一介质层215、第二支撑层214、第二介质层213，形成暴露导电层212的第三沟槽211。
在形成第三沟槽211的过程中，可针对刻蚀对象的材料特性选用不同的刻蚀剂，也可以选用同一种刻蚀剂。
具体来说，第一支撑层216和第二支撑层214由于需要起到支撑作用，其硬度通常大于第一介质层215和第二介质层213的材料，在刻蚀第一支撑层216和第一介质层215的过程中，可选用主要刻蚀成分不同或者主要刻蚀成分浓度不同的不同刻蚀剂，分别刻蚀第一支撑层216和第一介质层215，从而保证整体刻蚀工艺具有较高的刻蚀速率，缩短工艺周期。
本实施例中，同一刻蚀工艺对硬掩膜层261与阻拦层22、第一支撑层216、第一介质层215、第二支撑层214以及第二介质层213的刻蚀选择比较高，在刻蚀阻拦层22、第一支撑层216、第一介质层215、第二支撑层214以及第二介质层213，硬掩膜层261始终能够保持较高的侧壁形貌。
参考图13，利用刻蚀工艺，去除硬掩膜层261(参考图12)和阻拦层22(参考图12)。
需要说明的是，在选用去除硬掩膜层261以及阻拦层22的具体工艺时，应当考虑尽量避免较大的拉应力产生，从而避免拉应力过大而导致结构坍塌或者相邻膜层发生错位移动，保证第三凹槽211侧壁具有较高的垂直度，进而保证能够在第三凹槽211侧壁和底部形成质量良好的膜层，提高最终形成的柱状电容结构的质量。
参考图14，在第三沟槽211(参考图13)的侧壁和底部形成第一导电层221；去除部分第一支撑层、去除部分第一介质层、去除部分第二支撑层、去除部分第二介质层；形成介电层231和第二导电层241，以形成柱状电容结构。
本实施例中，柱状电容结构为双层柱状电容结构，由于每一双层柱状电容结构的最外侧都是第二导电层241，因此，相邻双层柱状电容结构的最外层导电层可以共用。双层柱状电容结构的形成工艺包括以下步骤：
在形成第一导电层221之后，去除相邻第一导电层221之间的所有第一支撑层、第一介质层、第二支撑层和第二介质层，为第二导电层241和介电层231的设置预留空间。
本实施例中，刻蚀相邻第一导电层221之间的所有材料时，可直接采用无掩膜刻蚀工艺，无需专门设置掩膜版，有利于降低工艺成本；此外，向刻蚀后的空置区域填充导电材料，可形成完全环绕介电层231的且可被相邻柱状电容结构共用的第二导电层241，有利于提高柱状电容结构的电容量和空间利用率。
在其他实施例中，也可以去除部分第一支撑层、去除部分第一介质层、去除部分第二支撑层，形成部分环绕介电层的第二导电层，和/或形成不可被共用的第二导电层。采用这一类柱状电容结构设计时，可以在未被第二导电层占据的介质材料内形成其他元件，进而提高半导体结构的集成度。
在去除工艺完成后，在第一导电层221的内侧壁和外侧壁分别形成介电层231；在形成介电层231之后，可采用沉积工艺，同时形成位于介电层231内部的以及相邻介电层231之间的第二导电层241，缩短半导体结构的工艺周期。
本实施例中，可通过控制牺牲层的材料调整牺牲层的刻蚀难度，以及可通过控制介质层材料控制介质层材料与硬掩膜层材料的刻蚀选择比，避免刻蚀工艺对硬掩膜层造成损伤，保证最终形成的硬掩膜层具有较好的形貌；此外，在衬底上形成有阻拦层，阻拦层的设置有利于避免刻蚀工艺对衬底造成误刻蚀。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为 准。

Claims (10)

  1. 一种半导体结构制作方法，包括：
    提供一衬底；
    在所述衬底上方形成一阻拦层；
    在所述阻拦层上方形成一牺牲层；
    利用光刻工艺在所述牺牲层上方形成一开口图案；
    以所述阻拦层为刻蚀停止层，根据所述开口图案刻蚀所述牺牲层，形成第一沟槽；
    在所述第一沟槽中填充介质层材料；
    以所述阻拦层为刻蚀停止层，刻蚀所述牺牲层，形成第二沟槽；
    在所述第二沟槽中填充硬掩膜层材料；
    以所述阻拦层为刻蚀停止层，刻蚀所述介质层材料，形成硬掩膜层。
  2. 根据权利要求1所述的半导体结构制作方法，其中，所述牺牲层的硬度小于所述硬掩膜层的硬度。
  3. 根据权利要求1所述的半导体结构制作方法，其中，所述牺牲层与所述阻拦层的刻蚀选择比、所述介质层材料与所述阻拦层的刻蚀选择比均大于100。
  4. 根据权利要求1所述的半导体结构制作方法，其中，在所述形成一开口图案之前，还包括：
    在所述牺牲层上方形成一介质层；所述开口图案位于所述介质层中。
  5. 根据权利要求1所述的半导体结构制作方法，其中，所述阻拦层包括氮化钛，所述牺牲层包括含碳材料，所述介质层材料包括氧化物、氮化物的一种，所述硬掩膜层材料包括多晶硅。
  6. 根据权利要求1所述的半导体结构制作方法，其中，所述第一沟槽在所述阻拦层上的投影形状包括圆形、正四边形、正六边形、正八边形、正十六边形的一种。
  7. 根据权利要求1所述的半导体结构制作方法，其中，所述衬底包括：
    第一支撑层，位于所述阻拦层下方；
    第一介质层，位于所述第一支撑层下方；
    第二支撑层，位于所述第一介质层下方；
    第二介质层，位于所述第二支撑层下方；
    导电结构，位于所述第二介质层下方。
  8. 根据权利要求7所述的半导体结构制作方法，其中，根据所述硬掩膜层依次刻蚀所述阻拦层、所述第一支撑层、所述第一介质层、所述第二支撑层、所述第二介质层，形成第三沟槽暴露所述导电结构。
  9. 根据权利要求8所述的半导体结构制作方法，其中，利用刻蚀工艺去除所述硬掩膜层和所述阻拦层。
  10. 根据权利要求9所述的半导体结构制作方法，其中，在所述第三沟槽的侧壁和底部形成第一导电层；去除部分所述第一支撑层；去除所述第一介质层；去除部分所述第二支撑层；去除部分所述第二介质层；形成介电层和第二导电层，以形成柱状电容结构。
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