WO2022012128A1 - 半导体结构的形成方法及半导体结构 - Google Patents

半导体结构的形成方法及半导体结构 Download PDF

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Publication number
WO2022012128A1
WO2022012128A1 PCT/CN2021/092896 CN2021092896W WO2022012128A1 WO 2022012128 A1 WO2022012128 A1 WO 2022012128A1 CN 2021092896 W CN2021092896 W CN 2021092896W WO 2022012128 A1 WO2022012128 A1 WO 2022012128A1
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Prior art keywords
layer
forming
air gap
bit line
semiconductor structure
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Ceased
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PCT/CN2021/092896
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English (en)
French (fr)
Inventor
廖楚贤
朱煜寒
应战
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/575,149 priority Critical patent/US12193217B2/en
Publication of WO2022012128A1 publication Critical patent/WO2022012128A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H10W20/0765—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches the thin functional dielectric layers being temporary, e.g. sacrificial layers

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a method for forming a semiconductor structure and a semiconductor structure.
  • the distance between adjacent conductive structures decreases, for example, the distance between the bit line structure and the capacitor contact window, the distance between the bit line structure and the capacitor contact pad, The distance between the bit line structure and the bit line structure is reduced.
  • the parasitic capacitance between the conductive structures increases, resulting in poor performance of the formed semiconductor device.
  • the parasitic capacitance between the conductive structures is reduced by forming an air gap.
  • Embodiments of the present application provide a method for forming a semiconductor structure and a semiconductor structure.
  • a first air gap and a second air gap By forming a first air gap and a second air gap, the effect of reducing parasitic capacitance is good, and the formed air gap can be easily sealed.
  • embodiments of the present application provide a method for forming a semiconductor structure, including: providing a substrate on which a discrete bit line structure is formed; forming a first sacrificial layer on the sidewall of the bit line structure; forming a filling bit
  • the first dielectric layer in the gap between the line structures; the patterned first dielectric layer and the first sacrificial layer form through holes, and in the direction extending along the bit line structure, the through holes are connected to the remaining first dielectric layer and the first sacrificial layer.
  • the through holes expose the active regions in the substrate and the sidewalls of the bit line structure; a second sacrificial layer is formed on the sidewalls of the through holes, and the through holes are filled to form contact plugs; a contact structure is formed on the contact plugs ; Remove the first sacrificial layer to form a first air gap, and remove the second sacrificial layer to form a second air gap.
  • the first sacrificial layer is formed on the sidewall of the bit line structure, and the second sacrificial layer is formed on the sidewall of the contact plug; in the subsequent manufacturing, the first sacrificial layer and the second sacrificial layer are removed to form A first air gap is located on the sidewall of the bit line structure and a second air gap is located on the sidewall of the contact plug.
  • the effect of reducing parasitic capacitance is better by forming two layers of air gap, and the formed air gap is easy to be sealed.
  • patterning the first dielectric layer and the first sacrificial layer to form through holes includes: forming a first mask layer on the bit line structure and the first dielectric layer; patterning the first mask layer to form a first etching opening , in the extending direction of the bit line structure, the first mask layer and the first etching opening are alternately arranged; based on the first etching opening, the exposed first dielectric layer and the first layer on the side wall of the bit line structure are etched sacrificial layer to form vias.
  • patterning the first dielectric layer and the first sacrificial layer to form through holes includes: forming a first mask layer on the bit line structure and the first dielectric layer; patterning the first mask layer to form a first etching opening , in the extending direction of the bit line structure, the first mask layer and the first etching opening are alternately arranged; use the first etching opening to remove part of the first dielectric layer; form a second mask on the remaining first dielectric layer film layer; patterning the second mask layer to form a second etching opening, the second etching opening exposes the first sacrificial layer on the sidewall of the first etching opening; removing the second etching based on the second etching opening The first sacrificial layer on the sidewall of the opening forms a through hole.
  • the substrate exposed by the through hole is partially etched.
  • the method further includes: removing the first dielectric layer to form a dielectric opening; and forming a second dielectric layer filling the dielectric opening.
  • filling the through hole to form the contact plug includes: forming a bottom conductive layer filling the through hole;
  • the method further includes: forming an isolation layer on the sidewall of the through hole.
  • the method further includes: forming an electrical connection layer on the contact plug.
  • forming an electrical connection layer between the contact plug and the contact structure the transmission loss of current between the contact plug and the contact structure is reduced.
  • the method also includes: sealing the first air gap and the second air gap to form a sealing layer on the top of the first air gap and the second air gap.
  • the method further includes: forming a barrier layer on the sidewall of the contact structure.
  • a barrier layer between the contact structure and the sealing layer, the conductive particles in the contact structure are prevented from diffusing into the sealing layer, thereby forming an electrical connection between the discrete contact structures.
  • Embodiments of the present application further provide a semiconductor structure, including: a substrate and discrete bit line structures on top of the substrate; a dielectric layer and a contact plug, wherein the dielectric layer and the contact plug are located in the gaps between the discrete bit line structures , and in the extending direction of the bit line structure, the contact plugs and the dielectric layer are alternately arranged; the contact structure is located on the contact plug; the first air gap is located between the dielectric layer and the bit line structure; the second air gap, The contact plug is surrounded, and a portion of the second air gap is located between the bit line structure and the contact plug.
  • the first air gap located on the sidewall of the bit line structure communicates with the second air gap.
  • the width of the second air gap is greater than the width of the first air gap.
  • an isolation layer is also included, and the isolation layer is located between the second air gap and the contact plug.
  • the width of the first air gap ranges from 0.1 nm to 5 nm.
  • the width of the second air gap ranges from 1 nm to 6 nm.
  • the contact plugs are distributed in an aligned array, and the contact structures are distributed in a staggered array.
  • the contact structures are partially located in the gaps between the bit line structures.
  • the semiconductor structure further includes an isolation layer located between the second air gap and the contact plug.
  • the present embodiment includes a first air gap located on the sidewall of the bit line structure and a second air gap located on the sidewall of the contact plug.
  • the two-layer air gap has a better effect of reducing parasitic capacitance, and the formed air gap is easy to be sealed.
  • FIG. 1 to 22 are schematic top-view structural diagrams and cross-sectional structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present application;
  • 23 and 24 are partially enlarged schematic views of forming an air gap in a method for forming a semiconductor structure provided by an embodiment of the present application.
  • an embodiment of the present application provides a method for forming a semiconductor structure, including: providing a substrate on which discrete bit line structures are formed; forming a first sacrificial layer on the sidewalls of the bit line structures; forming filling bits The first dielectric layer in the gap between the line structures; the patterned first dielectric layer and the first sacrificial layer form through holes, and in the direction extending along the bit line structure, the through holes are connected to the remaining first dielectric layer and the first sacrificial layer.
  • the through holes expose the active regions in the substrate and the sidewalls of the bit line structure; a second sacrificial layer is formed on the sidewalls of the through holes, and the through holes are filled to form contact plugs; a contact structure is formed on the contact plugs ; Remove the first sacrificial layer to form a first air gap, and remove the second sacrificial layer to form a second air gap.
  • FIG. 22 are schematic cross-sectional structural diagrams corresponding to each step of the method for forming a semiconductor structure according to an embodiment of the present application, and the method for forming a semiconductor structure in this embodiment will be specifically described below.
  • a substrate 100 is provided on which discrete bit line structures 103 are formed.
  • a substrate 100 including active regions 101 and word line structures 102 is provided.
  • a plurality of active regions 101 are arranged parallel to each other at intervals, the word line structure 102 and the bit line structure 103 are perpendicular to each other, and a single active region 101 intersects with two word line structures 102 .
  • the substrate 100 also includes other semiconductor structures other than the word line structure 102 and the active region 101 , such as the shallow trench isolation structure 110 (refer to FIG. 2 ), etc., since the other semiconductor structures are not related to this application The core technology is not repeated here; those skilled in the art can understand that the substrate 100 also includes other semiconductor structures except the word line structure 102 and the active region 101 for normal operation of the semiconductor structure.
  • the material of the substrate 100 may include sapphire, silicon, silicon carbide, gallium arsenide, aluminum nitride or zinc oxide, etc.
  • the substrate 100 is made of silicon material, and those skilled in the art will know that this embodiment uses silicon material as the substrate 100 is for the convenience of those skilled in the art to understand the subsequent formation method, and does not constitute a limitation. In the actual application process, a suitable substrate material can be selected according to requirements.
  • discrete bit line structures 103 are formed on a substrate 100 .
  • the extending direction of the bit line structure 103 and the extending direction of the word line structure 102 are perpendicular to each other.
  • the bit line structure 103 includes a bit line contact layer 113 , a metal layer 123 and a top dielectric layer 133 which are stacked in sequence.
  • On a cross section perpendicular to the extending direction of the bit line structures 103 only one bit line structure 103 in the adjacent two bit line structures 103 is connected to the active region 101 in the substrate 100 .
  • the material of the bit line contact layer 113 includes tungsten or polysilicon; the metal layer 123 can be a conductive material or is composed of a variety of conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten and tungsten composites, etc.; the top layer dielectric
  • the material of the layer 133 includes silicon nitride, silicon dioxide or silicon oxynitride. In this embodiment, the material of the top dielectric layer 133 is silicon nitride.
  • a first sacrificial layer 104 is formed on the sidewall of the bit line structure 103 .
  • the first sacrificial layer 104 is located on the sidewall of the bit line structure 103 for subsequent etching to form a first air gap located on the sidewall of the bit line structure 103 , that is, the first sacrificial layer 104 is made of a material that is easily etched.
  • the material of the first sacrificial layer 104 is a carbon-containing material, and in the subsequent process of removing the first sacrificial layer 104 to form the first air gap, the sacrificial layer can be removed by ashing; the ashing gas reacts with the carbon-containing material Carbon dioxide gas is generated, and the first sacrificial layer 104 is converted into gaseous carbon dioxide, thereby removing the first sacrificial layer 104; and in the process of forming the air gap, a large impact is formed on the sidewall of the air isolation structure, thereby avoiding the collapse that occurs Phenomenon.
  • the first sacrificial layer may be a material with a high etch selectivity to surrounding materials, such as silicon oxide.
  • the first sacrificial layer is removed by a wet etching process, thereby forming a first air gap.
  • the thickness of the first sacrificial layer 104 is 0.1 nm ⁇ 5 nm, such as 0.5 nm, 1.0 nm, 1.5 nm, 2.0 nm, 2.5 nm, 3.0 nm, 3.5 nm , 4.0nm or 4.5nm.
  • a first sacrificial film is formed on the sidewall of the bit line structure 103 and the top surface of the substrate 100 .
  • the first sacrificial film is formed by the atomic layer deposition process, and the first sacrificial film formed by the atomic layer deposition process has good coverage; in other embodiments, for example, 500° C. or 600° C.
  • the first sacrificial film is formed by chemical vapor deposition at °C. It should be noted that the above description of the specific temperature parameters using chemical vapor deposition is only to facilitate the understanding of those skilled in the art, and does not constitute a limitation to this scheme. In practical applications, as long as the parameters within the above range are within within the scope of protection of this application.
  • the first sacrificial film on the top surface of the substrate 100 is removed to form a first sacrificial layer 104 .
  • the first sacrificial layer 104 formed at this time is only located on the sidewall of the bit line structure 103 .
  • a first dielectric layer 106 is formed to fill the gap between adjacent bit line structures 103 , the first dielectric layer 106 and the first sacrificial layer 104 are patterned to form through holes 107 , and the through holes 107 expose the substrate 100 In the active region 101, and along the extending direction of the bit line structure 103, the through holes 107 are alternately arranged with the remaining first dielectric layers 106 and the first sacrificial layers 104, and the side walls of the through holes 107 expose the bit lines
  • a second sacrificial layer 108 is formed on the sidewall of the structure 103 , and a second sacrificial layer 108 is formed on the sidewall of the through hole 107 , and the through hole 107 is filled to form a contact plug 109 .
  • a first dielectric layer 106 filling the gaps between adjacent bit line structures 103 is formed.
  • patterning the first dielectric layer 106 and the first sacrificial layer 104 to form through holes 107 includes: forming a first mask layer on the bit line structure 103 and the first dielectric layer 106 .
  • the first mask layer is patterned to form first etching openings, and in the direction in which the bit line structure 103 extends, the first mask layers and the first etching openings are alternately arranged.
  • the exposed first dielectric layer 106 and the first sacrificial layer 104 on the sidewall of the bit line structure 103 are etched based on the first etch opening to form the through hole 107 .
  • the first dielectric layer 106 and the top dielectric layer 133 are formed of different materials, and the first etching opening is a linear pattern intersecting with the extending direction of the bit line structure 103.
  • the linear pattern and the first dielectric layer are used.
  • the etching selectivity of 106 and the top dielectric layer 133 is higher than that of self-aligned etching to form through holes 107 .
  • the material of the top dielectric layer 133 is silicon nitride
  • the material of the first dielectric layer 106 is silicon oxide
  • the material of the first sacrificial layer 104 is carbon-containing material, such as amorphous carbon, silicon oxycarbide, and the like.
  • the silicon oxide and carbon-containing layers are removed by self-aligned etching using the etching selectivity ratio of silicon oxide to silicon nitride and the etching selectivity ratio of carbon-containing layer to silicon nitride to form through holes 107 .
  • part of the substrate at the bottom of the first dielectric layer also needs to be etched to expose the active region in the substrate.
  • patterning the first dielectric layer and the first sacrificial layer to form through holes includes: forming a first mask layer on the bit line structure and the first dielectric layer; patterning the first mask layer to form a first mask layer Etching openings, the first mask layers and the first etching openings are alternately arranged in the extending direction of the bit line structure; using the first etching openings to remove part of the first dielectric layer; on the remaining first dielectric layer forming a second mask layer, patterning the second mask layer, forming a second etching opening, the second etching opening exposing the first sacrificial layer on the sidewall of the first etching opening; based on the second etching opening and removing the first sacrificial layer on the sidewall of the second etched opening to form the through hole.
  • the first dielectric layer is first etched using the first mask layer and the first etching opening, and then the first sacrificial layer is etched using the second mask layer and the second etching opening. Adjustability. In addition, part of the substrate at the bottom of the first dielectric layer may also be etched to expose the active region in the substrate.
  • a second sacrificial layer 108 is formed on the sidewall of the through hole 107 .
  • the second sacrificial layer 108 is located on the sidewall of the through hole 107 for subsequent etching to form a second air gap surrounding the sidewall of the through hole 107 , that is, the second sacrificial layer 108 is made of a material that is easily etched.
  • the material of the second sacrificial layer 108 is a carbon-containing material, and in the subsequent process of removing the second sacrificial layer 108 to form an air gap, the sacrificial layer can be removed by ashing; the ashing gas reacts with the carbon-containing material to generate carbon dioxide gas to convert the solid second sacrificial layer 108 into gaseous carbon dioxide, thereby removing the sacrificial layer; and avoiding the collapse phenomenon that occurs when a large impact is formed on the sidewall of the air isolation structure in the process of forming the air gap.
  • the method for forming the second sacrificial layer 108 is the same as the method for forming the first sacrificial layer 104 described above, and details are not described here.
  • first sacrificial layer 104 and the second sacrificial layer 108 may be removed by wet etching.
  • the thickness of the second sacrificial layer 108 is greater than that of the first sacrificial layer 104 . Since the second sacrificial layer 108 formed around the contact plug 109 has corners, the second sacrificial layer 108 is more difficult to remove than the first sacrificial layer 104 under the same width, and the thickness of the second sacrificial layer 108 is greater than that of the first sacrificial layer 104 to ensure that the second sacrificial layer 108 can be completely removed.
  • the thickness of the second sacrificial layer 108 is 1 nm ⁇ 6 nm, for example, 1 nm, 2 nm, 3 nm, 4 nm or 5 nm.
  • the thickness of the second sacrificial layer can also be set to be the same as that of the first sacrificial layer, or the thickness of the second sacrificial layer is smaller than that of the first sacrificial layer.
  • the method before forming the bottom conductive layer filling the through hole 107, the method further includes: forming an isolation layer 105 on the sidewall of the second sacrificial layer 108.
  • the through holes 107 are filled to form contact plugs 109 .
  • the via hole 107 is filled to form a bottom conductive layer 119 , the height of the bottom conductive layer 119 is consistent with the height of the bit line structure 103 , and the material of the bottom conductive layer is polysilicon or silicon germanium, which is used in the substrate 100
  • the active region 101 forms an electrical connection.
  • a portion of the bottom conductive layer 119 is etched to form contact plugs 109 whose height is lower than that of the top surface of the bit line structure 103 .
  • the method further includes: forming an electrical connection layer (not shown) on the contact plugs 109 .
  • an electrical connection layer (not shown) between the contact plug 109 and the contact structure, the transmission loss of current between the contact plug 109 and the contact structure is reduced.
  • the method further includes: removing the remaining first dielectric layer 106 to form a dielectric opening; forming a dielectric opening; A second dielectric layer 201 filling the dielectric openings.
  • the first dielectric layer 106 can be self-aligned to form dielectric openings, which saves process costs.
  • the through holes 107 are formed by etching on the first dielectric layer 106, and the second dielectric layer 201 is used to replace the first dielectric layer 106 as an isolation medium, so that the adjustment redundancy of the process is greater.
  • silicon oxide which is easy to be etched is used as the first dielectric layer 106 to reduce the etching difficulty of the through holes 107
  • silicon nitride is used as the second dielectric layer 201 to achieve better isolation effect.
  • a contact structure 202 is formed on the contact plug 109 .
  • a top conductive layer 212 is formed on the top surface of the contact plug 109 and the top surface of the bit line structure 103.
  • the top conductive layer 212 can be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc.
  • the top conductive layer 212 is made of tungsten material. , the resistance of tungsten is small, which can further reduce the transmission loss of current.
  • the top conductive layer 212 is patterned to form a contact structure 202 .
  • the contact structure 202 includes a portion above the top surface of the bit line structure 103 and a portion below the top surface of the bit line structure 103 , wherein the portion below the bit line
  • the top surface portion of the structure 103 together with the contact plug 109 constitutes a contact window.
  • the portion of the top surface higher than the bit line structure 103 serves as a landing pad for forming an electrical connection with a subsequently formed memory cell.
  • the first sacrificial layer 104 is removed to form a first air gap 203
  • the second sacrificial layer 108 is removed to form a second air gap.
  • FIGS. 23 and 24 for schematic diagrams of partial methods.
  • the first sacrificial layer 104 and the second sacrificial layer 108 are removed by ashing or wet etching.
  • an ashing process is used to remove the sacrificial layer to form an air gap, and the width of the formed air gap is approximately equal to the thickness of the sacrificial layer.
  • the process parameters of the ashing process include: ashing gas flow rate of 10,000 sccm to 15,000 sccm, temperature of 150° C. to 350° C., and pressure of 500 to 800 mT.
  • the airflow rate can be 11000 sccm, 12000 sccm, 13000 sccm or 14000 sccm;
  • the temperature can be 200 °C, 250 °C or 300 °C;
  • the pressure can be 600 mT or 700 mT.
  • the ashing gas used in the ashing process includes one or a combination of nitrogen, hydrogen or oxygen; the ashing gas chemically reacts with the sacrificial layer formed of carbon-containing materials, and the solid sacrificial layer reacts to generate gaseous carbon dioxide , changing from a solid state to a gaseous state, thereby forming an air gap.
  • the ashing process is used to form the air gap, a large impact force will not be caused to the side wall of the air gap, and the phenomenon of the collapse of the outer layer side wall is avoided.
  • the second air gap 204 formed at this time is located between the isolation layer 105 and the bit line structure 103, and also between the isolation layer 105 and the second dielectric layer 201, and the first air gap 203 formed is located between the bit line structure 103 and the second dielectric layer 201.
  • the first air gap 203 between the dielectric layers 201 and between the bit line structures 103 is communicated with the second air gap 204 .
  • adjacent bit line structures 103 include a first air gap 203 , a second air gap 204 , an isolation layer 105 , a contact plug 109 and a second dielectric layer 201 .
  • the first air gap 203 is located between the bit line structure 103 and the second dielectric layer 201; along the extending direction of the bit line structure 203, the second dielectric layer 201 and the contact plugs 109 are alternately arranged, located in the contact plugs 109
  • the isolation layer 105 on the sidewall, the second air gap 204 surrounds the sidewall of the isolation layer 105 , and the first air gap 203 on the sidewall of the bit line structure 103 communicates with the second air gap 204 .
  • the position of the second dielectric layer may also be the first dielectric layer.
  • adjacent bit line structures 103 include a first air gap, a second air gap 204 , a contact plug 109 and a second dielectric layer 201 .
  • the first air gap 203 is located between the bit line structure 103 and the second dielectric layer 201; along the extending direction of the bit line structure 203, the second dielectric layer 201 and the contact plugs 109 are alternately arranged, and the second air gap 204 surrounds the sidewall of the contact plug 109 , and the first air gap 203 located on the sidewall of the bit line structure 103 communicates with the second air gap 204 .
  • the position of the second dielectric layer may also be the first dielectric layer.
  • a barrier layer 205 is formed on the top surface and sidewalls of the contact structure.
  • the first air gap and the second air gap are sealed to form a sealing layer 206 at the top of the air gap.
  • the height of the top surface of the sealing layer 206 is greater than the height of the top surface of the contact structure 202 .
  • the first sacrificial layer is formed on the sidewall of the bit line structure, and the second sacrificial layer is formed on the sidewall of the contact plug; in the subsequent manufacturing, the first sacrificial layer and the second sacrificial layer are removed to form A first air gap is located on the sidewall of the bit line structure and a second air gap is located on the sidewall of the contact plug.
  • the effect of reducing parasitic capacitance is better by forming two layers of air gap, and the formed air gap is easy to be sealed.
  • the second embodiment of the present application relates to a semiconductor structure.
  • the semiconductor structure includes: a substrate 100 and discrete bit line structures 103 on the substrate 100 ; a dielectric layer 201 and contact plugs 109 located in the gaps between the discrete bit line structures 103 and in the direction in which the bit line structures 103 extend On the top, the contact plugs 109 and the dielectric layer 201 are alternately arranged; the contact structure 202 is located on the contact plug 109; the first air gap 203 is located between the dielectric layer 201 and the bit line structure 103; the second air gap 204 is surrounded by The contact plug 109 is contacted, and a portion of the second air gap 204 is located between the bit line structure 103 and the contact plug 109 .
  • the material of the substrate 100 may include sapphire, silicon, silicon carbide, gallium arsenide, aluminum nitride or zinc oxide, etc.
  • the substrate 100 is made of silicon material, and those skilled in the art will know that this embodiment uses silicon material as the substrate 100 is for the convenience of those skilled in the art to understand the subsequent formation method, and does not constitute a limitation. In the actual application process, a suitable substrate material can be selected according to requirements.
  • a plurality of edge regions 101 are arranged in parallel and spaced apart from each other, the word line structure 102 and the bit line structure 103 are perpendicular to each other, and a single active region 101 intersects with two word line structures 102 .
  • the substrate 100 also includes other semiconductor structures other than the word line structure 102 and the active region 101 , such as the shallow trench isolation structure 110 (refer to FIG. 2 ), etc., since the other semiconductor structures are not related to this application The core technology is not repeated here; those skilled in the art can understand that the substrate 100 also includes other semiconductor structures except the word line structure 102 and the active region 101 for normal operation of the semiconductor structure.
  • the extending direction of the bit line structure 103 and the extending direction of the word line structure 102 are perpendicular to each other.
  • the bit line structure 103 includes a bit line contact layer 113 , a metal layer 123 and a top dielectric layer 133 which are stacked in sequence.
  • On a cross section perpendicular to the extending direction of the bit line structures 103 only one bit line structure 103 in the adjacent two bit line structures 103 is connected to the active region 101 in the substrate 100 .
  • the material of the bit line contact layer 113 includes tungsten or polysilicon; the metal layer 123 can be a conductive material or is composed of a variety of conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten and tungsten composites, etc.; the top layer dielectric
  • the material of the layer 133 includes silicon nitride, silicon dioxide or silicon oxynitride. In this embodiment, the top dielectric layer 133 is made of silicon nitride material.
  • the material of the dielectric layer 201 is the same as that of the top dielectric layer 133 ; the material of the contact plug 109 is polysilicon or silicon germanium, which is used to form an electrical connection with the active region 101 in the substrate 100 .
  • the contact structure 202 includes a portion above the top surface of the bit line structure 103 and a gap between the bit line structures 103 , wherein the portion below the top surface of the bit line structure 103 and the contact plug 109 together form a contact window.
  • the portion of the top surface higher than the bit line structure 103 serves as a contact pad for forming an electrical connection with a subsequently formed memory cell.
  • the contact plugs 109 are distributed in an aligned array, and the contact structures 202 are distributed in a staggered array.
  • the projection of the contact structure 202 and the contact plug 109 on the substrate partially intersect, so that the first sacrificial layer 104 and the second sacrificial layer 108 are at least partially exposed to facilitate subsequent etching to form an air gap.
  • the contact structure 202 may be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc.
  • the contact structure 202 is made of tungsten material, and the resistance of tungsten is small, which can further reduce the transmission loss of current.
  • the first air gap 203 located on the sidewall of the bit line structure 103 communicates with the second air gap 204 .
  • the width of the second air gap 204 is greater than the width of the first air gap 203 .
  • the width of the second air gap 204 is 1 nm ⁇ 6 nm, such as 1 nm, 2 nm, 3 nm, 4 nm or 5 nm;
  • the width of the first air gap 203 is 0.1 nm ⁇ 5 nm, such as 0.5 nm, 1.0 nm, 1.5 nm, 2.0 nm nm, 2.5 nm, 3.0 nm, 3.5 nm, 4.0 nm or 4.5 nm.
  • the semiconductor structure further includes an isolation layer 105 , and the isolation layer 105 is located between the second air gap 204 and the contact plug 109 , that is, the isolation layer 105 is disposed around the sidewall of the contact plug 109 , and the second air gap 204 It is arranged around the sidewall of the isolation layer 105 .
  • the material of the isolation layer 105 is an insulating material, such as silicon nitride, silicon oxynitride or silicon oxide.
  • the material of the isolation layer 105 is the same as the material of the top dielectric layer 133 , that is, the isolation layer 105 is made of silicon nitride material.
  • the present embodiment includes a first air gap located on the sidewall of the bit line structure and a second air gap located on the sidewall of the contact plug.
  • the two-layer air gap has a better effect of reducing parasitic capacitance, and the formed air gap is easy to be sealed.

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Abstract

提供一种半导体结构的形成方法及半导体结构，半导体结构的形成方法，包括：提供基底(100)，基底(100)上形成有分立的位线结构(103)；在位线结构(103)侧壁形成第一牺牲层(104)；形成填充位线结构(103)之间间隙的第一介质层(106)；图形化第一介质层(106)与第一牺牲层(104)形成通孔(107)，通孔(107)与剩余的第一介质层(106)和第一牺牲层(104)交替排布；在通孔(107)的侧壁形成第二牺牲层(108)，并填充通孔(107)形成接触插塞(109)；于接触插塞(109)上形成接触结构(202)；去除第一牺牲层(104)形成第一空气间隙(203)，去除第二牺牲层(108)形成第二空气间隙(204)。

Description

半导体结构的形成方法及半导体结构
交叉引用
本申请引用于2020年7月14日递交的名称为“半导体结构的形成方法及半导体结构”的第202010673713.X号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请涉及半导体领域，特别涉及一种半导体结构的形成方法及半导体结构。
背景技术
随着半导体器件集成度的提高，相邻导电结构之间的距离减小，例如，位线结构和电容接触窗之间的距离减小、位线结构和电容接触垫之间的距离减小、位线结构和位线结构之间的距离减小。由于导电结构之间的距离减小，会导致导电结构之间的寄生电容增加，从而造成形成的半导体器件性能变差。
相关技术中，通过形成空气间隙，以减少导电结构之间的寄生电容。
然而申请人发现：相关技术的制造过程中，若将空气间隙尺寸做的太宽，则后续不容易对空气间隙进行密封；若将空气间隙尺寸做的太窄，则空气间隙轮廓均匀性较差且降低寄生电容的效果较差。
发明内容
本申请实施例提供一种半导体结构的形成方法及半导体结构，通过形成第一空气间隙和第二空气间隙，降低寄生电容的效果较好，且形成的空气间隙容易进行密封。
为解决上述技术问题，本申请实施例提供了一种半导体结构的形成方法，包括：提供基底，基底上形成有分立的位线结构；在位线结构侧壁形成第一牺牲层；形成填充位线结构之间间隙的第一介质层；图形化第一介质层与第一牺牲层形成通孔，在沿位线结构延伸的方向上，通孔与剩余的第一介质层和第一牺牲层交替排布，通孔暴露出基底中的有源区以及位线结构侧壁；在通孔的侧壁形成第二牺牲层，并填充通孔形成接触插塞；于接触插塞上形成接触结构；去除第一牺牲层形成第一空气间隙，去除第二牺牲层形成第二空气间隙。
与相关技术相比，在位线结构侧壁形成第一牺牲层，并在接触插塞的侧壁形成第二牺牲层；在后续的制造中通过去除第一牺牲层和第二牺牲层，形成位于位线结构侧壁的第一空气间隙和位于接触插塞侧壁的第二空气间隙。通过形成两层空气间隙与相关技术仅形成一层空气间隙相比，降低寄生电容的效果较好，且形成的空气间隙容易进行密封。
另外，图形化第一介质层与第一牺牲层形成通孔，包括：在位线结构以及第一介质层上形成第一掩膜层；图形化第一掩膜层，形成第一刻蚀开口，在位线结构延伸的方向上，第一掩膜层与第一刻蚀开口交替排布；基于第一刻蚀开口刻蚀暴露出的第一介质层和位线结构侧壁上的第一牺牲层，形成通孔。
另外，图形化第一介质层与第一牺牲层形成通孔，包括：在位线结构以及第一介质层上形成第一掩膜层；图形化第一掩膜层，形成第一刻蚀开口，在位线结构延伸的方向上，第一掩膜层与第一刻蚀开口交替排布；利用第一刻蚀开口去除部分第一介质层；在剩余的第一介质层上形成第二掩膜层；图形化第二掩膜层，形成第二刻蚀开口，第二刻蚀开口暴露出第一刻蚀开口侧壁的第一牺牲层；基于第二刻蚀开口，去除第二刻蚀开口侧壁的第一牺牲层，形成通孔。
另外，还包括：通孔暴露出的基底被部分刻蚀。
另外，填充通孔形成接触插塞之后，且于接触插塞上形成接触结构之前，还包括：去除第一介质层形成介质开口；形成填充介质开口的第二介质层。
另外，第二牺牲层的厚度大于第一牺牲层的厚度。另外，填充通孔形成接触插塞，包括：形成填充通孔的底导电层；刻蚀部分底导电层形成接触插塞，接触插塞顶部表面的高度低于位线结构顶部表面的高度。
另外，形成填充通孔的底导电层之前，还包括：在通孔的侧壁形成隔离层。
另外，填充通孔形成接触插塞之后，且于接触插塞顶部形成接触结构之前，还包括：在接触插塞上形成电连接层。通过形成接触插塞与接触结构之间的电连接层，降低电流在接触插塞与接触结构之间的传输损耗。
另外，还包括：对第一空气间隙和第二空气间隙进行封口处理，形成位于第一空气间隙和第二空气间隙顶部的封口层。
另外，对第一空气间隙和第二空气间进行封口处理之前，还包括：在接触结构的侧壁形成阻挡层。通过在接触结构与封口层之间形成阻挡层，防止接触结构中的导电粒子扩散到封口层之中，从而使分立的接触结构之间形成电连接。
本申请实施例还提供了一种半导体结构，包括：基底以及位于基底顶部的分立的位线结构；介质层以及接触插塞，介质层与接触插塞位于分立的位线结构之间的间隙中，且于位线结构延伸的方向上，接触插塞与介质层交替排布；接触结构，位于接触插塞上；第一空气间隙，位于介质层与位线结构之间；第二空气间隙，环绕接触插塞，且部分第二空气间隙位于位线结构与接触插塞之 间。
另外，位于位线结构侧壁的第一空气间隙与第二空气间隙相连通。
另外，第二空气间隙的宽度大于第一空气间隙的宽度。
另外，还包括隔离层，隔离层位于第二空气间隙与接触插塞之间。
另外，第一空气间隙的宽度范围为0.1nm-5nm。
另外，第二空气间隙的宽度范围为1nm-6nm。
另外，接触结构和接触插塞在基底上的投影部分相交。
另外，接触插塞呈对齐阵列分布，接触结构呈交错阵列分布。
另外，接触结构部分位于位线结构之间的间隙中。
另外，半导体结构还包括隔离层，所述隔离层位于所述第二空气间隙与所述接触插塞之间。
与相关技术相比，本实施例包括位于位线结构侧壁的第一空气间隙和位于接触插塞侧壁的第二空气间隙。两层空气间隙与相关技术的一层空气间隙相比，降低寄生电容的效果较好，且形成的空气间隙容易进行密封。
附图说明
图1至图22为本申请一实施例提供的半导体结构的形成方法中各步骤对应的俯视结构示意图以及剖面结构示意图；
图23和图24为本申请一实施例提供的半导体结构的形成方法中的形成空气间隙的局部放大示意图。
具体实施方式
相关技术的制造过程中，若将空气间隙尺寸做的太宽，则不容易后续对空气间隙进行密封；若将空气间隙尺寸做的太窄，则空气间隙轮廓均匀性较差 且降低寄生电容的效果较差。
为解决上述问题，本申请一实施例提供了一种半导体结构的形成方法，包括：提供基底，基底上形成有分立的位线结构；在位线结构侧壁形成第一牺牲层；形成填充位线结构之间间隙的第一介质层；图形化第一介质层与第一牺牲层形成通孔，在沿位线结构延伸的方向上，通孔与剩余的第一介质层和第一牺牲层交替排布，通孔暴露出基底中的有源区以及位线结构侧壁；在通孔的侧壁形成第二牺牲层，并填充通孔形成接触插塞；于接触插塞上形成接触结构；去除第一牺牲层形成第一空气间隙，去除第二牺牲层形成第二空气间隙。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1至图22为本申请实施例提供的半导体结构的形成方法各步骤对应的剖面结构示意图，下面对本实施例的半导体结构的形成方法进行具体说明。
参考图1和图2，提供基底100，基底100上形成有分立的位线结构103。
参考图1，提供包括有源区101和字线结构102的基底100。
多个有源区101相互平行间隔排布，字线结构102和位线结构103相互垂直，单个有源区101和两个字线结构102相交。需要说明的是，基底100中还包括除字线结构102和有源区101外的其他半导体结构，例如浅沟槽隔离结 构110(参考图2)等，由于其他半导体结构并不涉及到本申请的核心技术，在此不过多进行赘述；本领域技术人员可以理解基底100中还包括除字线结构102和有源区101外的其他半导体结构，用于半导体结构的正常运行。
基底100的材料可以包括蓝宝石、硅、碳化硅、砷化镓、氮化铝或者氧化锌等；在本实施例中基底100采用硅材料，本领域技术人员清楚，本实施例采用硅材料作为基底100是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底的材料。
参考图1和图2，在基底100上形成分立的位线结构103。
位线结构103延伸的方向与字线结构102延伸的方向相互垂直。位线结构103包括依次堆叠设置的位线接触层113、金属层123以及顶层介质层133。在垂直位线结构103延伸方向上的截面上，相邻的两个位线结构103中只有一个位线结构103连接基底100中的有源区101。
位线接触层113的材料包括钨或多晶硅；金属层123可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等；顶层介质层133的材料包括氮化硅、二氧化硅或氮氧化硅，在本实施例中，顶层介质层133的材料为氮化硅。
参考图3和图4，在位线结构103侧壁形成第一牺牲层104。
第一牺牲层104位于位线结构103侧壁，用于后续刻蚀形成位于位线结构103侧壁的第一空气间隙，即第一牺牲层104采用容易被刻蚀的材料。
具体地，第一牺牲层104的材料为含碳材料，后续在去除第一牺牲层104形成第一空气间隙的过程中，可采用灰化的方式去除牺牲层；灰化气体与含碳材料反应生成二氧化碳气体，将第一牺牲层104转换成气体二氧化碳，从而除 去第一牺牲层104；并且避免了在形成空气间隙的过程中对空气隔离结构的侧壁形成较大的冲击，从而发生的坍塌现象。在其他实施例中，第一牺牲层可以采用与周围材料具有高刻蚀选择比的材料，例如氧化硅。采用湿法刻蚀工艺去除所述第一牺牲层，从而形成第一空气间隙。
在本实施例中，在平行于基底100表面的方向上，第一牺牲层104的厚度为0.1nm～5nm，例如0.5nm、1.0nm、1.5nm、2.0nm、2.5nm、3.0nm、3.5nm、4.0nm或者4.5nm。
具体地，在位线结构103侧壁以及基底100顶部表面形成第一牺牲膜。在本实施例中，采用原子层沉积工艺的方式形成第一牺牲膜，采用原子层沉积工艺形成的第一牺牲膜具有良好的覆盖性；在其他实施例中，例如，可以采用500℃或600℃下进行化学气相沉积的方法形成第一牺牲膜。需要说明是的，上述采用化学气相沉积的具体温度参数的举例说明，仅便于本领域技术人员的理解，并不构成对本方案的限定，在实际应用中只要符合上述范围中的参数都应落入本申请的保护范围中。
去除基底100顶部表面的第一牺牲膜，形成第一牺牲层104。此时形成的第一牺牲层104仅位于位线结构103的侧壁。
参考图5至图14，形成填充相邻位线结构103之间间隙的第一介质层106，图形化第一介质层106与第一牺牲层104形成通孔107，通孔107暴露出基底100中的有源区101，且在沿位线结构103延伸的方向上，通孔107与剩余的第一介质层106和第一牺牲层104交替排布，且通孔107侧壁暴露出位线结构103侧壁，在通孔107侧壁形成第二牺牲层108，并填充通孔107形成接触插塞109。
具体地，参考图5和图6，形成填充相邻位线结构103之间间隙的第一 介质层106。
参考图7和图8，本实施例中，图形化第一介质层106与第一牺牲层104形成通孔107，包括：在位线结构103以及第一介质层106上形成第一掩膜层。图形化第一掩膜层，形成第一刻蚀开口，在位线结构103延伸的方向上，第一掩膜层与第一刻蚀开口交替排布。基于第一刻蚀开口刻蚀暴露出的第一介质层106和位线结构103侧壁上的第一牺牲层104，形成所述通孔107。具体的，形成的第一介质层106与顶层介质层133的材料不相同，所述第一刻蚀开口为与位线结构103延伸方向相交的线状图形，利用线状图形以及第一介质层106和顶层介质层133的刻蚀选择比自对准的刻蚀形成通孔107。
在一个例子中，顶层介质层133的材料为氮化硅，第一介质层106的材料为氧化硅，第一牺牲层104的材料为含碳材料，如无定形碳，碳氧化硅等。利用氧化硅与氮化硅的刻蚀选择比，以及含碳层与氮化硅的刻蚀选择比自对准的刻蚀去除氧化硅与含碳层以形成通孔107。在其他实施例中，还需要刻蚀第一介质层底部的部分基底，以暴露出基底中的有源区。
在其他实施例中，图形化第一介质层与第一牺牲层形成通孔，包括：在位线结构以及第一介质层上形成第一掩膜层；图形化第一掩膜层，形成第一刻蚀开口，在位线结构延伸的方向上，第一掩膜层与第一刻蚀开口交替排布；利用第一刻蚀开口去除部分第一介质层；在剩余的第一介质层上形成第二掩膜层，图形化第二掩膜层，形成第二刻蚀开口，所述第二刻蚀开口暴露出第一刻蚀开口侧壁的第一牺牲层；基于第二刻蚀开口，去除第二刻蚀开口侧壁的第一牺牲层，形成所述通孔。
具体的，先利用第一掩膜层和第一刻蚀开口刻蚀第一介质层，再利用第 二掩膜层和第二刻蚀开口刻蚀第一牺牲层，如此设置，增大工艺的可调性。此外，还可以刻蚀第一介质层底部的部分基底，以暴露出基底中的有源区。参考图9和图10，在通孔107侧壁形成第二牺牲层108。第二牺牲层108位于通孔107侧壁，用于后续刻蚀形成环绕通孔107侧壁的第二空气间隙，即第二牺牲层108采用容易被刻蚀的材料。
具体地，第二牺牲层108的材料为含碳材料，后续在去除第二牺牲层108形成空气间隙的过程中，可采用灰化的方式去除牺牲层；灰化气体与含碳材料反应生成二氧化碳气体，将固体第二牺牲层108转换成气体二氧化碳，从而除去牺牲层；并且避免了在形成空气间隙的过程中对空气隔离结构的侧壁形成较大的冲击，从而发生的坍塌现象。在本实施例中，形成第二牺牲层108的方法与上述形成第一牺牲层104的方式相同，在此不过多赘述。
在其他实施例中，可以采用湿法刻蚀的方法去除第一牺牲层104和第二牺牲层108。
在本实施例中，第二牺牲层108的厚度大于第一牺牲层104的厚度。由于围绕接触插塞109形成的第二牺牲层108具有拐角，同宽度情况下第二牺牲层108相较于第一牺牲层104会更难去除，第二牺牲层108的厚度大于第一牺牲层104的厚度以保证第二牺牲层108可以被完全去除。
在本实施例中，第二牺牲层108的厚度为1nm～6nm，例如1nm、2nm、3nm、4nm或者5nm。
需要说明的是，在其他实施例中，第二牺牲层也可以设置为与第一牺牲层的厚度相同，或者第二牺牲层的厚度小于第一牺牲层。
在本实施例中，在形成填充通孔107的底导电层之前，还包括：在第二 牺牲层108侧壁形成隔离层105。
参考图11至图13，填充通孔107形成接触插塞109。
具体地，参考图12，填充通孔107形成底导电层119，底导电层119的高度与位线结构103的高度一致，底导电层的材料为多晶硅或锗化硅，用于与基底100中的有源区101形成电连接。
参考图13，刻蚀部分底导电层119形成接触插塞109，接触插塞109的高度低于位线结构103顶部表面的高度。
填充通孔107形成接触插塞109之后，且于所述接触插塞109上形成接触结构之前，还包括：在接触插塞109上形成电连接层(未图示)。通过形成接触插塞109与接触结构之间的电连接层(未图示)，降低电流在接触插塞109与接触结构之间的传输损耗。
本实施例中，参考图14，填充通孔107形成接触插塞109之后，且于所述接触插塞109上形成接触结构之前，还包括：去除剩余的第一介质层106形成介质开口；形成填充所述介质开口的第二介质层201。具体地，利用第一介质层106和周围的顶层介质层133以及接触插塞109的材质不同，可以自对准的刻蚀第一介质层106形成介质开口，节约工艺成本。同时，通过在第一介质层106上刻蚀形成通孔107，以及通过第二介质层201取代第一介质层106作为隔离介质，使得工艺的调整冗余度更大。例如，采用容易刻蚀的氧化硅作为第一介质层106以减少通孔107的刻蚀难度，采用氮化硅作为第二介质层201以起到更好的隔离效果。
参考图15至图17，于接触插塞109上形成接触结构202。
具体地，参考图15，在接触插塞109顶部表面以及位线结构103顶部表 面形成顶导电层212。
顶导电层212可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，顶导电层212采用钨材料，钨的电阻小，可以进一步减少电流的传输损耗。
参考图16以及图17，图形化所述顶导电层212形成接触结构202，接触结构202包括高于位线结构103顶部表面部分以及低于位线结构103顶部表面部分，其中，低于位线结构103顶部表面部分与接触插塞109共同构成接触窗。高于位线结构103顶部表面部分作为接触垫(landing pad)用于与后续形成的存储单元形成电连接。
参考图18和图19，去除第一牺牲层104形成第一空气间隙203，去除第二牺牲层108形成第二空气间隙，其局部方法示意图参考图23和图24。
在本实施例中，采用灰化或湿法刻蚀的方式去除第一牺牲层104和第二牺牲层108。
具体的，采用灰化工艺去除牺牲层形成空气间隙，形成的空气间隙的宽度约等于牺牲层的厚度。其中，灰化工艺的工艺参数包括：灰化气体流量为10000sccm～15000sccm，温度为150℃～350℃，压强为500～800mT。具体地，气流流量可以为11000sccm、12000sccm、13000sccm或14000sccm；温度可以为200℃、250℃或300℃；压强可以为600mT或700mT。需要说明是的，上述对气体流量参数、温度参数和压强参数的举例说明，仅为便于本领域技术人员的理解，并不构成对本方案的限定，在实际应用中只要符合上述范围中的参数都应落入本申请的保护范围中。
灰化工艺采用的灰化气体包括氮气、氢气或氧气其中的一种或几种的组 合；灰化气体与采用含碳材料形成的牺牲层发生化学反应，固态的牺牲层反应后生成气态的二氧化碳，从固态变为气态，从而形成空气间隙。采用灰化工艺形成空气间隙时，不会对空气间隙的侧壁造成较大的冲击力，避免了外层侧壁坍塌的现象。
此时形成的第二空气间隙204位于隔离层105与位线结构103之间，还位于隔离层105与第二介质层201之间，形成的第一空气间隙203位于位线结构103与第二介质层201之间，且位于位线结构103之间的第一空气间隙203与第二空气间隙204相连通。
参考图23，相邻位线结构103结构之间包括第一空气间隙203、第二空气间隙204、隔离层105、接触插塞109和第二介质层201。其中第一空气间隙203位于位线结构103与第二介质层201之间；在沿着位线结构203延伸的方向上，第二介质层201与接触插塞109交替排布，位于接触插塞109侧壁的隔离层105，第二空气间隙204环绕隔离层105的侧壁，且位于位线结构103侧壁的第一空气间隙203与第二空气间隙204相连通。在其他实施例中，第二介质层的位置也可以为第一介质层。
在其他实施例不形成隔离层的工艺中，参考图24，相邻位线结构103结构之间包括第一空气间隙、第二空气间隙204、接触插塞109和第二介质层201。其中第一空气间隙203位于位线结构103与第二介质层201之间；在沿着位线结构203延伸的方向上，第二介质层201与接触插塞109交替排布，第二空气间隙204环绕接触插塞109的侧壁，且位于位线结构103侧壁的第一空气间隙203与第二空气间隙204相连通。在其他实施例中，第二介质层的位置也可以为第一介质层。
参考图20和图21，在接触结构顶部表面以及侧壁形成阻挡层205。通过在接触结构202与后续形成的封口层之间形成阻挡层，防止接触结构202中的导电粒子扩散到封口层之中，从而使分立的接触结构202之间形成电连接。
参考图22，对第一空气间隙和第二空气间隙进行封口处理，形成位于空气间隙顶部的封口层206，封口层206的顶部表面的高度大于接触结构202顶部表面的高度。
与相关技术相比，在位线结构侧壁形成第一牺牲层，并在接触插塞的侧壁形成第二牺牲层；在后续的制造中通过去除第一牺牲层和第二牺牲层，形成位于位线结构侧壁的第一空气间隙和位于接触插塞侧壁的第二空气间隙。通过形成两层空气间隙与相关技术仅形成一层空气间隙相比，降低寄生电容的效果较好，且形成的空气间隙容易进行密封。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请第二实施例涉及一种半导体结构。
参考图20和图22，以下将结合附图对本实施例提供的半导体结构进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
半导体结构，包括：基底100以及位于基底100上分立的位线结构103；介质层201以及接触插塞109，位于分立的位线结构103之间的间隙中，且于位线结构103延伸的方向上，接触插塞109与介质层201交替排布；接触结构202，位于接触插塞109上；第一空气间隙203，位于介质层201与位线结构103 之间；第二空气间隙204，环绕接触插塞109，且部分第二空气间隙204位于位线结构103与接触插塞109之间。
基底100的材料可以包括蓝宝石、硅、碳化硅、砷化镓、氮化铝或者氧化锌等；在本实施例中基底100采用硅材料，本领域技术人员清楚，本实施例采用硅材料作为基底100是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底的材料。
多个有缘区101相互平行间隔排布，字线结构102和位线结构103相互垂直，单个有源区101和两个字线结构102相交。需要说明的是，基底100中还包括除字线结构102和有源区101外的其他半导体结构，例如浅沟槽隔离结构110(参考图2)等，由于其他半导体结构并不涉及到本申请的核心技术，在此不过多进行赘述；本领域技术人员可以理解基底100中还包括除字线结构102和有源区101外的其他半导体结构，用于半导体结构的正常运行。
位线结构103延伸的方向与字线结构102延伸的方向相互垂直。位线结构103包括依次堆叠设置的位线接触层113、金属层123以及顶层介质层133。在垂直位线结构103延伸方向上的截面上，相邻的两个位线结构103中只有一个位线结构103连接基底100中的有源区101。
位线接触层113的材料包括钨或多晶硅；金属层123可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等；顶层介质层133的材料包括氮化硅、二氧化硅或氮氧化硅，在本实施例中，顶层介质层133采用氮化硅材料。
介质层201与顶层介质层133的材料相同；接触插塞109的材料为多晶硅或锗化硅，用于与基底100中的有源区101形成电连接。
接触结构202包括高于位线结构103顶部表面部分以及位线结构103之间的间隙中，其中，低于位线结构103顶部表面部分与接触插塞109共同构成接触窗。高于位线结构103顶部表面部分作为接触垫用于与后续形成的存储单元形成电连接。具体的，接触插塞109呈对齐阵列分布，接触结构202呈交错阵列分布。接触结构202和接触插塞109在基底上的投影部分相交，使得第一牺牲层104和第二牺牲层108至少被部分暴露出来，以利于后续刻蚀形成空气间隙。在本实施例中，接触结构202可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，接触结构202采用钨材料，钨的电阻小，可以进一步减少电流的传输损耗。
本实施例中，位于位线结构103侧壁的第一空气间隙203与第二空气间隙204相连通。
在本实施例中，第二空气间隙204的宽度大于第一空气间隙203的宽度。具体地，第二空气间隙204的宽度为1nm～6nm，例如1nm、2nm、3nm、4nm或者5nm；第一空气间隙203的宽度为0.1nm～5nm，例如0.5nm、1.0nm、1.5nm、2.0nm、2.5nm、3.0nm、3.5nm、4.0nm或者4.5nm。
在本实施例中，半导体结构还包括隔离层105，隔离层105位于第二空气间隙204与接触插塞109之间，即隔离层105环绕接触插塞109的侧壁设置，第二空气间隙204环绕隔离层105的侧壁设置。隔离层105的材料为绝缘材料，例如氮化硅、氮氧化硅或氧化硅等材料。本实施例中，隔离层105的材料与顶层介质层133材料相同，即隔离层105采用氮化硅材料。
与相关技术相比，本实施例包括位于位线结构侧壁的第一空气间隙和位于接触插塞侧壁的第二空气间隙。两层空气间隙与相关技术的一层空气间隙相 比，降低寄生电容的效果较好，且形成的空气间隙容易进行密封。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (20)

  1. 一种半导体结构的形成方法，其特征在于，包括：
    提供基底，所述基底上形成有分立的位线结构；
    在所述位线结构侧壁形成第一牺牲层；
    形成填充所述位线结构之间间隙的第一介质层；
    图形化所述第一介质层与所述第一牺牲层形成通孔，在沿所述位线结构延伸的方向上，所述通孔与剩余的所述第一介质层和所述第一牺牲层交替排布，所述通孔暴露出所述基底中的有源区以及所述位线结构侧壁；
    在所述通孔的侧壁形成第二牺牲层，并填充所述通孔形成接触插塞；
    于所述接触插塞上形成接触结构；
    去除所述第一牺牲层形成第一空气间隙，去除所述第二牺牲层形成第二空气间隙。
  2. 根据权利要求1所述的半导体结构的形成方法，其特征在于，所述图形化所述第一介质层与所述第一牺牲层形成通孔，包括：
    在所述位线结构以及所述第一介质层上形成第一掩膜层；
    图形化所述第一掩膜层，形成第一刻蚀开口，在所述位线结构延伸的方向上，所述第一掩膜层与所述第一刻蚀开口交替排布；
    基于所述第一刻蚀开口刻蚀暴露出的所述第一介质层和位线结构侧壁上的所述第一牺牲层，形成所述通孔。
  3. 根据权利要求1所述的半导体结构的形成方法，其特征在于，所述图形化所述第一介质层与所述第一牺牲层形成通孔，包括：
    在所述位线结构以及所述第一介质层上形成第一掩膜层；
    图形化所述第一掩膜层，形成第一刻蚀开口，在所述位线结构延伸的方向上，所述第一掩膜层与所述第一刻蚀开口交替排布；
    利用所述第一刻蚀开口去除部分所述第一介质层；
    在剩余的所述第一介质层上形成第二掩膜层；
    图形化所述第二掩膜层，形成第二刻蚀开口，所述第二刻蚀开口暴露出所述第一刻蚀开口侧壁的所述第一牺牲层；
    基于所述第二刻蚀开口，去除所述第二刻蚀开口侧壁的所述第一牺牲层，形成所述通孔。
  4. 根据权利要求2所述的半导体结构的形成方法，其特征在于，还包括：所述通孔暴露出的所述基底被部分刻蚀。
  5. 根据权利要求1所述的半导体结构的形成方法，其特征在于，所述填充所述通孔形成接触插塞之后，且所述于所述接触插塞上形成接触结构之前，还包括：去除所述第一介质层形成介质开口；形成填充所述介质开口的第二介质层。
  6. 根据权利要求1所述的半导体结构的形成方法，其特征在于，所述第二牺牲层的厚度大于所述第一牺牲层的厚度。
  7. 根据权利要求1所述的半导体结构的形成方法，其特征在于，所述填充所述通孔形成接触插塞，包括：
    形成填充所述通孔的底导电层；
    刻蚀部分所述底导电层形成所述接触插塞，所述接触插塞顶部表面的高度低于所述位线结构顶部表面的高度。
  8. 根据权利要求7所述的半导体结构的形成方法，其特征在于，所述形成填充 所述通孔的底导电层之前，还包括：在所述通孔的侧壁形成隔离层。
  9. 根据权利要求1所述的半导体结构的形成方法，其特征在于，所述填充所述通孔形成接触插塞之后，且所述于所述接触插塞上形成接触结构之前，还包括：在所述接触插塞上形成电连接层。
  10. 根据权利要求1所述的半导体结构的形成方法，其特征在于，还包括：对所述第一空气间隙和所述第二空气间隙进行封口处理，形成位于所述第一空气间隙和所述第二空气间隙顶部的封口层。
  11. 根据权利要求10所述的半导体结构的形成方法，其特征在于，所述对所述第一空气间隙和所述第二空气间进行封口处理之前，还包括：在所述接触结构的侧壁形成阻挡层。
  12. 一种半导体结构，其特征在于，包括：
    基底以及位于所述基底上分立的位线结构；
    介质层以及接触插塞，所述介质层与所述接触插塞位于分立的位线结构之间的间隙中，且于所述位线结构延伸的方向上，所述接触插塞与所述介质层交替排布；
    接触结构，位于所述接触插塞上；
    第一空气间隙，位于所述介质层与所述位线结构之间；
    第二空气间隙，环绕所述接触插塞，且部分所述第二空气间隙位于所述位线结构与所述接触插塞之间。
  13. 根据权利要求12所述的半导体结构，其特征在于，位于所述位线结构侧壁的所述第一空气间隙与所述第二空气间隙相连通。
  14. 根据权利要求12所述的半导体结构，其特征在于，所述第二空气间隙的宽 度大于所述第一空气间隙的宽度。
  15. 根据权利要求12所述的半导体结构，其特征在于，还包括隔离层，所述隔离层位于所述第二空气间隙与所述接触插塞之间。
  16. 根据权利要求14所述的半导体结构，其特征在于，所述第一空气间隙的宽度范围为0.1nm-5nm。
  17. 根据权利要求12所述的半导体结构，其特征在于，还包括：隔离层，所述隔离层位于所述第二空气间隙与所述接触插塞之间。
  18. 根据权利要求12所述的半导体结构，其特征在于，所述接触结构和所述接触插塞在所述基底上的投影部分相交。
  19. 根据权利要求18所述的半导体结构，其特征在于，所述接触插塞呈对齐阵列分布，所述接触结构呈交错阵列分布。
  20. 根据权利要求19所述的半导体结构，其特征在于，所述接触结构部分位于所述位线结构之间的所述间隙中。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12237215B2 (en) 2020-09-18 2025-02-25 Changxin Memory Technologies, Inc. Semiconductor structure and method for manufacturing same
US12512374B2 (en) 2020-09-18 2025-12-30 Changxin Memory Technologies, Inc. Semiconductor structure with void and manufacturing method thereof
EP3998631B1 (en) * 2020-09-18 2024-01-24 Changxin Memory Technologies, Inc. Semiconductor structure and manufacturing method therefor
US12376288B2 (en) * 2022-01-07 2025-07-29 Changxin Memory Technologies, Inc. Memory and method for forming same
CN114582796A (zh) * 2022-05-06 2022-06-03 成都高真科技有限公司 一种半导体器件制造工艺中位线空气间隔的形成方法
CN115132777B (zh) * 2022-08-31 2022-11-25 睿力集成电路有限公司 半导体结构及其形成方法、存储器
CN118829189A (zh) * 2023-04-03 2024-10-22 长鑫存储技术有限公司 半导体结构及其制备方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100285662A1 (en) * 2009-05-11 2010-11-11 Samsung Electronics Co., Ltd. Methods of fabricating integrated circuit devices including air spacers separating conductive structures and contact plugs
US20160211215A1 (en) * 2015-01-21 2016-07-21 Samsung Electronics Co., Ltd. Semiconductor devices
CN106941097A (zh) * 2016-01-05 2017-07-11 华邦电子股份有限公司 半导体装置及其制造方法
CN107706179A (zh) * 2016-08-08 2018-02-16 三星电子株式会社 半导体存储器件
CN107833872A (zh) * 2012-05-03 2018-03-23 三星电子株式会社 半导体器件
CN108054153A (zh) * 2012-09-14 2018-05-18 三星电子株式会社 利用空气间隔分离导电结构的半导体器件及其制造方法
CN110718550A (zh) * 2018-07-12 2020-01-21 三星电子株式会社 半导体器件及制造其的方法
CN110875314A (zh) * 2018-08-30 2020-03-10 长鑫存储技术有限公司 位线结构及其制备方法、存储器

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8778749B2 (en) 2011-01-12 2014-07-15 Sandisk Technologies Inc. Air isolation in high density non-volatile memory
KR102238951B1 (ko) 2014-07-25 2021-04-12 에스케이하이닉스 주식회사 에어갭을 구비한 반도체장치 및 그 제조 방법
KR102289376B1 (ko) 2015-01-19 2021-08-17 에스케이하이닉스 주식회사 에어갭을 구비한 반도체 장치 및 그 제조방법
KR102395192B1 (ko) * 2015-11-27 2022-05-06 삼성전자주식회사 에어 스페이서를 포함하는 반도체 소자
KR102705036B1 (ko) 2016-12-19 2024-09-10 삼성전자주식회사 반도체 메모리 장치
KR102606784B1 (ko) * 2018-07-13 2023-11-28 에스케이하이닉스 주식회사 에어갭을 구비한 반도체장치 및 그 제조 방법
CN108777253B (zh) 2018-08-10 2023-10-27 长鑫存储技术有限公司 一种动态随机存储器结构及其形成方法
US10607996B1 (en) 2018-12-26 2020-03-31 Micron Technology, Inc. Construction of integrated circuitry, DRAM circuitry, a method of forming a conductive line construction, a method of forming memory circuitry, and a method of forming DRAM circuitry
CN113937059A (zh) * 2020-07-14 2022-01-14 长鑫存储技术有限公司 半导体结构的形成方法及半导体结构

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100285662A1 (en) * 2009-05-11 2010-11-11 Samsung Electronics Co., Ltd. Methods of fabricating integrated circuit devices including air spacers separating conductive structures and contact plugs
CN107833872A (zh) * 2012-05-03 2018-03-23 三星电子株式会社 半导体器件
CN108054153A (zh) * 2012-09-14 2018-05-18 三星电子株式会社 利用空气间隔分离导电结构的半导体器件及其制造方法
US20160211215A1 (en) * 2015-01-21 2016-07-21 Samsung Electronics Co., Ltd. Semiconductor devices
CN106941097A (zh) * 2016-01-05 2017-07-11 华邦电子股份有限公司 半导体装置及其制造方法
CN107706179A (zh) * 2016-08-08 2018-02-16 三星电子株式会社 半导体存储器件
CN110718550A (zh) * 2018-07-12 2020-01-21 三星电子株式会社 半导体器件及制造其的方法
CN110875314A (zh) * 2018-08-30 2020-03-10 长鑫存储技术有限公司 位线结构及其制备方法、存储器

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