WO2021213130A1 - 存储器的形成方法及存储器 - Google Patents

存储器的形成方法及存储器 Download PDF

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Publication number
WO2021213130A1
WO2021213130A1 PCT/CN2021/083067 CN2021083067W WO2021213130A1 WO 2021213130 A1 WO2021213130 A1 WO 2021213130A1 CN 2021083067 W CN2021083067 W CN 2021083067W WO 2021213130 A1 WO2021213130 A1 WO 2021213130A1
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Prior art keywords
isolation layer
bit line
layer
isolation
line structure
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PCT/CN2021/083067
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English (en)
French (fr)
Inventor
赵哲
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长鑫存储技术有限公司
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Priority to US17/412,692 priority Critical patent/US20210383843A1/en
Publication of WO2021213130A1 publication Critical patent/WO2021213130A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

Definitions

  • This application relates to the field of semiconductors, and in particular to a method for forming a memory and a memory.
  • DRAM Dynamic Random Access Memory
  • the embodiments of the present application provide a method for forming a memory and a memory to reduce the parasitic capacitance of the DRAM array area, and by increasing the contact area of the capacitor contact hole, the resistance of the subsequently formed capacitor contact window is reduced, thereby increasing the DRAM array area The saturation current.
  • an embodiment of the present application provides a method for forming a memory, including: providing a substrate.
  • the substrate includes an array area and a peripheral area.
  • the array area has a plurality of discrete bit line structures, and the bit line structure sidewalls
  • An isolation layer is formed; a first dielectric layer covering the bit line structure is formed on the array area and the peripheral area; the first dielectric layer in the array area is patterned and etched to form an opening, and the first dielectric layer is removed by etching Part of the isolation layer is etched during the process of the electrical layer, and the remaining isolation layer has gaps; a second dielectric film is formed on the top surface of the isolation layer and the bit line structure, and the second dielectric film is also located on the sidewall of the isolation layer and the bit line On the substrate between the structures; using the first etching process to etch the second dielectric film on the sidewall of the isolation layer to form the second dielectric layer; using the second etching process to etch part of the substrate at the bottom of the opening to form
  • the present application reduces the parasitic capacitance of the DRAM array area by forming an isolation structure.
  • a gap will appear between the top of the isolation layer and the bit line structure.
  • the gap is filled by forming a second dielectric layer or the isolation layer is filled.
  • the second dielectric layer on the sidewall of the isolation layer and the substrate at the bottom of the partial opening are respectively etched to increase the contact of the capacitor contact hole Area, thereby reducing the resistance of the subsequently formed capacitive contact window, thereby increasing the saturation current of the DRAM array area.
  • forming the second dielectric film located on the top surface of the isolation layer and the bit line structure includes forming a second dielectric film filling the gap, and the second dielectric film is also located on the top surface of the isolation layer and the bit line structure.
  • the parasitic capacitance in the DRAM array area is reduced by forming a NON stacked isolation structure.
  • forming the second dielectric film on the top surface of the isolation layer and the bit line structure includes: forming a second dielectric film for sealing the gap, the second dielectric film is partially located on the top of the gap, and the second dielectric film is also Located on the isolation layer and the top surface of the bit line structure.
  • the parasitic capacitance in the DRAM array area is reduced by forming an air gap isolation structure.
  • the steps include: removing the isolation layer by etching and A second dielectric film on the top surface of the bit line structure and the substrate between the bit line structure.
  • the material of the second dielectric layer is the same as the material of the first dielectric layer.
  • removing the first dielectric layer located in the array area to form an opening includes: etching and removing the first dielectric layer located in the array area until the top surface of the bit line structure is exposed; and etching and removing located between the bit line structures The first dielectric layer forms an opening.
  • the etching material for removing the first dielectric layer by etching includes hydrofluoric acid.
  • the isolation layer includes a first isolation layer, a second isolation layer, and a third isolation layer; the first isolation layer is located on the sidewall of the bit line structure; the second isolation layer is located on the sidewall of the first isolation layer away from the bit line structure; The three isolation layers are located on the sidewalls of the second isolation layer away from the first isolation layer; part of the isolation layer is etched during the process of removing the first dielectric layer, including: part of the thickness of the second isolation layer is etched.
  • forming a first dielectric layer covering the bit line structure on the array area and the peripheral area includes: forming a first dielectric film filling the gap between the bit line structures on the array area and the peripheral area, and the first dielectric layer The film covers the top surface of the bit line structure; the top surface of the first dielectric film is planarized to form a first dielectric layer.
  • a spin coating process is used to form the first dielectric film.
  • An embodiment of the present application also provides a memory, including: a substrate, the substrate includes an array region and a peripheral region, the array region has a plurality of discrete bit line structures; an isolation layer located on the sidewall of the bit line structure, and the isolation layer and the bit line There are gaps between the line structures; the first dielectric layer covering the peripheral area and the second dielectric layer located in the gaps for forming the isolation structure; the substrate between the bit line structures has capacitive contact holes.
  • the second dielectric layer used to form the isolation structure includes: the second dielectric layer is used to fill the gap to form the isolation structure, or the second dielectric layer is used to seal the gap to form the isolation structure.
  • the isolation layer includes a first isolation layer, a second isolation layer, and a third isolation layer; the first isolation layer is located on the sidewall of the bit line structure; the second isolation layer is located on the sidewall of the first isolation layer away from the bit line structure; The three isolation layers are located on the sidewalls of the second isolation layer away from the first isolation layer.
  • the present application reduces the parasitic capacitance of the bit line structure through the isolation structure, and enlarges the capacitor contact window and the substrate formed by etching the capacitor contact hole formed on the substrate between the bit line structure.
  • the contact area is reduced to reduce the resistance of the subsequent capacitive contact window, thereby increasing the saturation current of the DRAM array area.
  • 1 to 12 are schematic structural diagrams corresponding to each step of a method for forming a memory provided by an embodiment of this application;
  • 13 to 16 are schematic structural diagrams corresponding to each step of a method for forming a memory provided by another embodiment of the application.
  • an embodiment of the present application provides a method for forming a memory, including: providing a substrate, the substrate includes an array area and a peripheral area, the array area has a plurality of discrete bit line structures, and the sidewalls of the bit line structure An isolation layer is formed; a first dielectric layer covering the bit line structure is formed on the array area and the peripheral area; the first dielectric layer in the array area is patterned and etched to form an opening, and the first dielectric layer is removed by etching Part of the isolation layer is etched during the process of the electrical layer, and the remaining isolation layer has gaps; a second dielectric film is formed on the top surface of the isolation layer and the bit line structure, and the second dielectric film is also located on the sidewall of the isolation layer and the bit line On the substrate between the structures; using the first etching process to etch the second dielectric film on the sidewall of the isolation layer to form the second dielectric layer; using the second etching process to etch part of the substrate at the bottom of the opening to form Cap
  • FIG. 1 to 12 are schematic structural diagrams corresponding to the steps of the memory forming method provided by this embodiment. The following describes the memory forming method of this embodiment in detail with reference to the accompanying drawings.
  • FIG. 1 is a schematic top view of the provided substrate and the subsequently formed capacitive contact window
  • FIG. 2 is a schematic cross-sectional view of the memory according to the direction of the dotted line 20 in FIG. 1.
  • the substrate 10 the substrate 10 includes an active area 11, a bit line contact window 13, a word line 14, a bit line 15 and a capacitor contact window 16, the subsequent memory forming method is given by the dashed line 12 in the memory formation
  • the cross-sectional schematic diagram of the method It should be noted that this embodiment mainly introduces the formation method of the DRAM array area, and the corresponding drawings only show the structural changes of the DRAM array area, which is convenient for those skilled in the art to understand the solution. Implement.
  • a substrate 10 is provided.
  • the substrate 10 includes an array area and a peripheral area.
  • a plurality of discrete bit line structures 15 are provided on the array area, and an isolation layer is formed on the sidewalls of the bit line structures 15.
  • the substrate 10 includes structures such as buried word lines, shallow trench isolation layers, and active regions.
  • the bit line structure 15 includes a bit line contact layer 101, a bottom dielectric layer 102, a metal layer 103, and a top dielectric layer 104.
  • the bit line contact layer 101 includes a bit line contact window 13, in the cross-sectional direction of the dashed line 12 in FIG. 1, Only one of the three consecutive bit line structures 15 is connected to the active area in the substrate 10 through the bit line contact window 13; in this embodiment, the middle bit line structure 15 is connected to the active area in the substrate 10 through the bit line contact window 13 Take the active area as an example for illustration.
  • the material of the bit line contact window 13 includes tungsten or polysilicon
  • the material of the bottom dielectric layer 102 and the top dielectric layer 104 includes silicon nitride, silicon dioxide or silicon oxynitride
  • the metal layer 103 is formed of one conductive material or multiple conductive materials , Such as doped polysilicon, titanium, titanium nitride, tungsten and tungsten composites.
  • the isolation layer includes a first isolation layer, a second isolation layer, and a third isolation layer; the first isolation layer is located on the sidewall of the bit line structure 15; the second isolation layer is located on the sidewall of the first isolation layer away from the bit line structure 15; The three isolation layers are located on the sidewalls of the second isolation layer away from the first isolation layer.
  • a first isolation layer 201 is formed on the top surface, sidewalls of the bit line structure 15 and the substrate 10 between the bit line structure 15. The sidewalls of the line structure 15.
  • the material of the first isolation layer 201 includes materials such as silicon nitride, silicon oxynitride, or silicon oxide.
  • the material of the first isolation layer 201 is an insulating material containing nitrogen, that is, the first isolation layer 201 is made of silicon nitride.
  • the material of the third isolation layer formed subsequently is the same as that of the first isolation layer 201. In other embodiments, the material of the third isolation layer formed subsequently may be the same as that of the first isolation layer. The materials are not the same.
  • a second isolation layer 202 is formed on the top surface and sidewalls of the first isolation layer 201.
  • the second isolation layer 202 is formed by means of atomic layer deposition.
  • Atomic layer deposition has the characteristics of slow deposition rate, high density of the film formed by deposition, and good step coverage. In this way, the second isolation layer 202 can be effectively isolated and protected under the condition of a thinner thickness, and the second isolation layer 202 is prevented from occupying a small space between the adjacent bit line structures 15, which is beneficial to the subsequent enlargement of the bit line.
  • the cross-sectional area of the contact window is provided.
  • the material of the second isolation layer 202 includes materials such as silicon nitride, silicon oxynitride, or silicon oxide.
  • the material of the second isolation layer is an insulating material containing oxygen, that is, the second isolation layer 202 uses a silicon oxide material. It should be noted that the material of the second isolation layer 202 is different from the material of the first isolation layer 201, and the material of the third isolation layer formed later is also different.
  • the second isolation layer 202 on the top surface of the first isolation layer 201 is removed by etching, and the remaining second isolation layer 202 is located on the sidewall of the first isolation layer 201 away from the bit line structure 15.
  • a third isolation layer 203 is formed on the top surface of the first isolation layer 201 and the sidewall of the second isolation layer 202.
  • the material of the third isolation layer 203 includes materials such as silicon nitride, silicon oxynitride, or silicon oxide.
  • the material of the third isolation layer 203 is an insulating material containing nitrogen, that is, the third isolation layer 203 is made of silicon nitride. It should be noted that, in this embodiment, the third isolation layer 203 is made of the same material as the first isolation layer 201 formed above.
  • the third isolation layer 203 on the top surface of the first isolation layer 201 and the first isolation layer 201 and the second isolation layer 202 on the top surface of the bit line structure 15 are removed by etching.
  • the remaining third isolation layer 203 is located on the sidewall of the second isolation layer 202 away from the first isolation layer 201.
  • the first isolation layer 201, the second isolation layer 202, and the third isolation layer 203 stacked on the sidewalls of the bit line structure 15 together constitute the isolation layer 20.
  • the NON laminated isolation layer is used as the isolation layer 20 on the sidewall of the bit line structure 15 to reduce the parasitic capacitance of the bit line structure 15 and does not constitute a limitation to the solution.
  • the thickness can be determined according to The size of the device under the actual application can be set flexibly; in addition, other structures can be used as the isolation layer of the sidewall of the bit line structure in other embodiments.
  • a first dielectric layer 301 covering the bit line structure 15 is formed on the array region and the peripheral region.
  • the material of the first dielectric layer may be the same as or different from the material of the second isolation layer 202. In a specific application process, It can be adjusted according to the etching selection ratio of the etching material. In this embodiment, the material of the first dielectric layer 301 is the same as the material of the second isolation layer 202.
  • a first dielectric film (not shown) filling the gap between the bit line structures 15 is formed on the array region and the peripheral region, and the first dielectric film covers the top surface of the bit line structure 15.
  • the first dielectric film (not shown) is formed by a spin coating process, and the first dielectric film (not shown) formed by the spin coating method has the advantage of good filling properties.
  • the top surface of the first dielectric film (not shown) is planarized to form the first dielectric layer 301.
  • the top surface of the first dielectric film (not shown) is planarized by means of chemical mechanical polishing. Compared with the etching process, the chemical mechanical polishing process has a higher removal rate, which is beneficial to shorten the process cycle.
  • the first dielectric layer 301 located in the array area is removed to form an opening 501, and part of the isolation layer 20 is etched during the removal of the first dielectric layer 301, and the remaining isolation layer 20 has gaps. That is, part of the second isolation layer 202 is etched. Since the present embodiment is a NON isolation structure forming the sidewall of the bit line structure 15, the second isolation layer 202 will not be etched to a short height.
  • the first dielectric layer 301 located in the array area is etched and removed until the top surface of the bit line structure 15 is exposed; the first dielectric layer 301 located between the bit line structures 15 is etched away to form an opening 501.
  • the etching material for removing the first dielectric layer 301 by etching includes hydrofluoric acid, and etching with hydrofluoric acid material has a higher removal rate, which is beneficial to shorten the process cycle.
  • the removed first dielectric layer 301 still covers the surface of the peripheral area. Since the material of the first dielectric layer 301 is the same as the material of the second isolation layer 202, at this time, the top of the second isolation layer 202 in the isolation layer 20 will be etched away by a part of the height, forming a gap. In this embodiment, a partial thickness of the second isolation layer 202 is etched.
  • a second dielectric film 401 is formed on the top surface of the isolation layer 20 and the bit line structure 15.
  • the second dielectric film 401 is also located on the sidewall of the isolation layer 20 and the substrate 10 between the bit line structure 15 superior.
  • a second dielectric film 401 filling the gap is formed, and the second dielectric film 401 is also located on the top surface of the isolation layer 20 and the bit line structure 15.
  • a second dielectric film 401 filling the gap is formed on the array area, and the second dielectric film 401 also covers the top surface of the bit line structure 15 and the isolation layer 20, the sidewalls of the isolation layer 20, and the substrate 10 between the bit line structures. superior.
  • the second dielectric film 401 on the substrate 10 between the bit line structure 15 and the top surface of the isolation layer 20 and between the bit line structure 15 is removed by etching.
  • the material of the second dielectric film 401 is the same as the material of the first dielectric layer 301.
  • the second dielectric film 401 is formed by means of atomic layer deposition.
  • Atomic layer deposition has the characteristics of slow deposition rate, high density of the deposited film and good step coverage; in this way, the second dielectric film can be 401 can completely fill the gaps in the isolation layer 20.
  • a first etching process is used to etch and remove the second dielectric film 401 on the sidewall of the isolation layer 20 to form a second dielectric layer 402.
  • the isolation structure of the sidewall of the bit line structure 15 is a NON stacked isolation structure, the isolation effect is good, and the second dielectric layer 402 outside the isolation layer 20 will cause the horizontal position of the subsequently formed bit line contact window.
  • the cross-sectional area becomes smaller. Therefore, the first etching process is used to etch and remove the second dielectric layer 402 on the sidewall of the isolation layer 20.
  • the first etching process is isotropic etching
  • the etching gas used is a mixed gas of CF 4 , CHF 3 and O 2 , wherein the gas flow rate of CF 4 ranges from 100 sccm to 300 sccm, and the gas flow rate of CHF 3
  • the range is 50sccm ⁇ 200sccm
  • the gas flow range of O 2 is 1sccm ⁇ 20sccm
  • the etching pressure range is 5mtor ⁇ 16mtor
  • the etching power range is 200W ⁇ 600W
  • the etching voltage is 0V
  • the etching temperature is 20°C ⁇ 80°C
  • the etching time is 5s ⁇ 30s.
  • the second dielectric layer 402 on the sidewall of the isolation layer 20 can be completely etched or the second dielectric layer having the thickness of the sidewall of the isolation layer 20 can be completely etched
  • the electrical layer 402 increases the cross-sectional area of the openings between the bit line structures 15, that is, increases the cross-sectional area of the subsequently formed capacitive contact window, so as to reduce the resistance of the subsequently formed capacitive contact window.
  • the parameter range of the first etching process is: the etching gas is used: a mixed gas composed of 180 sccm ⁇ 220 sccm CF 4 , 100 sccm ⁇ 150 sccm CHF 3 and 5 sccm ⁇ 10 sccm O 2; the etching pressure range It is 7mtor ⁇ 12mtor; the etching power is 350W ⁇ 450W; the etching voltage is 0V; the etching temperature is 60°C; and the etching time is 15s ⁇ 20s.
  • the etching gas is used: a mixed gas composed of 180 sccm ⁇ 220 sccm CF 4 , 100 sccm ⁇ 150 sccm CHF 3 and 5 sccm ⁇ 10 sccm O 2; the etching pressure range It is 7mtor ⁇ 12mtor; the etching power is 350W ⁇ 450W; the etching voltage is 0V
  • a second etching process is used to etch a portion of the substrate 10 at the bottom of the opening 501 to form a capacitor contact hole 502.
  • the second etching process uses different etching selection ratios for the polysilicon and oxide layers in the first isolation layer 201 and the substrate 10, and the difference in the etching rate is the etching rate for the first isolation layer 201 (nitride) The fastest, the slowest etching rate for the polysilicon in the substrate 10, and the moderate etching rate for the oxide layer (oxide) in the substrate 10.
  • the second etching process is used to etch and remove the first isolation layer 201 at the bottom of the opening 501, and then a part of the substrate 10 at the bottom of the opening 501 is continued to be etched by the second etching process to form the capacitor contact hole 502.
  • the first isolation layer 201 can be etched away faster, which shortens the etching time, thereby preventing the top of the bit line structure 15 from being etched away.
  • the thick height causes the height difference between the array area and the peripheral area to be too large, which affects the subsequent process.
  • the second etching process Since the second etching process has a slower etching rate for the polysilicon in the substrate 10, the second etching process is prevented from etching more polysilicon in the substrate 10, thereby avoiding the problem of electrical failure of the DRAM.
  • the second etching process has different etching rates for the polysilicon and oxide layer in the substrate 10, so that the bottom morphology of the etched capacitor contact hole 502 is not a flat surface, which increases the subsequent formation of capacitor contacts compared to the flat surface.
  • the contact area between the window and the substrate 10 reduces the resistance of the subsequently formed capacitive contact window, which is beneficial to increase the saturation current of the DRAM array area.
  • the material selection of the second etching process only needs to ensure a larger etching selection ratio for the oxide layer and polysilicon in the substrate.
  • the etching gas used in the second etching process is a mixed gas of CF 4 and He, wherein the gas flow rate of CF 4 ranges from 30 sccm to 70 sccm, the gas flow rate of He ranges from 50 sccm to 150 sccm, and the etching pressure ranges from 5 mtor. ⁇ 16mtor; the etching power range is 300W ⁇ 700W; the etching voltage is 100V ⁇ 400V; the etching temperature is 20°C ⁇ 80°C.
  • the parameter range of the second etching process is as follows: the etching gas adopts a mixed gas composed of 45 sccm ⁇ 55 sccm CF 4 and 100 sccm He; the etching pressure range is 7 mtor ⁇ 12 mtor; the etching power is 450W ⁇ 550W; etching voltage is 200V ⁇ 300V; etching temperature is 60°C.
  • the present application reduces the parasitic capacitance of the DRAM array area by forming an isolation structure.
  • the electrical layer 402 fills the gap to ensure the isolation effect of the isolation structure; and through the first etching process and the second etching process, the second dielectric film 401 on the sidewall of the isolation layer 20 and the base 10 at the bottom of part of the opening 501 are respectively etched , To increase the contact area of the capacitor contact hole, thereby reducing the resistance of the capacitor contact window formed subsequently, thereby increasing the saturation current of the DRAM array area.
  • Another embodiment of the present application relates to a method for forming a memory.
  • the difference from the foregoing embodiment is that the final isolation structure formed in this embodiment is an air isolation structure, and the details are as follows:
  • the third isolation layer on the top surface of the first isolation layer and the first isolation layer and the third isolation layer on the top surface of the bit line structure are removed by etching.
  • the remaining third isolation layer is located on the sidewall of the second isolation layer away from the first isolation layer.
  • the first isolation layer, the second isolation layer, and the third isolation layer sequentially stacked on the sidewalls of the bit line structure together constitute an isolation layer.
  • the air gap isolation structure is used as the isolation structure of the sidewall of the bit line structure, that is, the second isolation layer needs to be removed in the subsequent process to form the air gap.
  • the air gap is used as the isolation structure to reduce the parasitic capacitance of the bit line structure.
  • a first dielectric layer covering the bit line structure is formed on the array area and the peripheral area.
  • FIGS 13 to 16 are schematic structural diagrams corresponding to the steps of the memory forming method provided by this embodiment.
  • the implementation details of this embodiment will be described in detail below with reference to the accompanying drawings. The same parts as the above embodiment are not included in this embodiment. Then describe accordingly:
  • the first dielectric layer located in the array area is removed to form an opening 501, and part of the isolation layer 60 is etched during the removal of the first dielectric layer, and there is a gap between the remaining isolation layer 60 and the bit line structure 15 . That is, part of the second isolation layer 602 is etched. Since the air gap needs to be formed in this embodiment, the second isolation layer 602 is etched to a higher height;
  • a second dielectric film 701 is formed on the top surface of the isolation layer 60 and the bit line structure 15, and the second dielectric film 701 is also located on the substrate 10 between the sidewall of the isolation layer 60 and the bit line structure 15;
  • the second dielectric film 701 is formed to seal the gap, and the second dielectric film 701 is partially located on the top of the gap, and the second dielectric film 701 is also located on the top surface of the isolation layer 60 and the bit line structure 15.
  • a second dielectric film 701 is formed on the top surface of the isolation layer 60 and the bit line structure 15.
  • the second dielectric film 701 also covers the sidewall of the isolation layer 60 and the substrate 10 between the bit line structure 15 .
  • the second dielectric film 701 on the substrate 10 between the isolation layer 60 and the top surface of the bit line structure 15 and the bit line structure 15 is removed by etching.
  • the material of the second dielectric film 701 is the same as the material of the first dielectric layer. In other embodiments, the material of the second dielectric film is the same as the material of the first dielectric layer. It can also be different.
  • the second dielectric film 701 is formed by a rapid sealing process, which has the effect of rapid deposition.
  • the formed second dielectric film 701 is used to seal the top of the isolation layer 60 to form an air isolation structure.
  • the second dielectric film 701 on the sidewall of the isolation layer 60 is etched and removed by the first etching process, and the second dielectric layer 702 is formed.
  • the isolation structure on the sidewall of the bit line structure 15 is an air gap isolation structure, the isolation effect is good, and the second dielectric film 701 on the outer layer of the isolation layer 60 will cause the cross-section of the subsequently formed bit line contact window.
  • the second dielectric film 701 By reasonably controlling the time of the first etching process, it is possible to completely etch the second dielectric film 701 on the sidewall of the isolation layer 60 or etch the second dielectric film 701 with a partial thickness of the sidewall of the isolation layer 60, thereby increasing the bit line
  • the cross-sectional area of the opening 501 between the structures 15 is to increase the cross-sectional area of the subsequently formed capacitive contact window to reduce the resistance of the subsequently formed capacitive contact window.
  • the remaining second dielectric film 701 After etching, the remaining second dielectric film 701 is formed
  • the second dielectric layer 702 is located on the top of the gap in the isolation layer 60, so that the isolation layer 60 forms an air gap isolation structure.
  • a second etching process is used to etch a portion of the substrate 10 at the bottom of the opening 501 to form a capacitor contact hole 502.
  • the second etching process uses different etching selection ratios for the polysilicon and oxide layers in the first isolation layer 201 and the substrate 10, and the difference in the etching rate is the etching rate for the first isolation layer 201 (nitride) The fastest, the slowest etching rate for the polysilicon in the substrate 10, and the moderate etching rate for the oxide layer (oxide) in the substrate 10.
  • the second etching process is used to etch and remove the first isolation layer 201 at the bottom of the opening 501, and then a part of the substrate 10 at the bottom of the opening 501 is continued to be etched by the second etching process to form the capacitor contact hole 502.
  • the present application reduces the parasitic capacitance of the DRAM array area by forming an isolation structure.
  • the electrical layer 702 seals the isolation layer 60 to ensure the formation of an air gap isolation structure; and through the first etching process and the second etching process, the second dielectric film 701 and part of the opening on the sidewall of the isolation layer 60 are etched respectively
  • the substrate 10 at the bottom of 501 increases the contact area of the capacitor contact hole, thereby reducing the resistance of the subsequently formed capacitor contact window, thereby increasing the saturation current of the DRAM array area.
  • the above embodiments use the NON isolation structure and the air isolation structure respectively to introduce the method of increasing the contact area of the capacitor contact window formed subsequently through the first etching process and the second etching process in the present application. It constitutes a limitation on the application of the first etching process and the second etching process in the present application.
  • the embodiment of the above-mentioned etching process to increase the contact area of the subsequently formed capacitor contact window can also be applied to other isolation structures In the structure of the DRAM array area.
  • Another embodiment of the present application relates to a memory, which can be formed by the above-mentioned forming method.
  • the memory provided in this embodiment will be described in detail below with reference to the accompanying drawings. The parts that are the same or corresponding to the above-mentioned embodiment will not be described below. Go into details.
  • the memory includes: a substrate 10, the substrate 10 includes an array area and a peripheral area, the array area has a plurality of discrete bit line structures 15; an isolation layer 20 located on the sidewall of the bit line structure 15, and the isolation layer 20 has A gap; a first dielectric layer covering the peripheral area and a second dielectric layer 402 located in the gap for forming an isolation structure; a capacitor contact hole 502 is provided on the substrate 10 between the bit line structures 15.
  • the second dielectric layer 402 is used to fill the gap to form an isolation structure.
  • the substrate 10 includes structures such as buried word lines, shallow trench isolation layers, and active regions.
  • the bit line structure 15 includes a bit line contact layer 101, a bottom dielectric layer 102, a metal layer 103, and a top dielectric layer 104.
  • the bit line contact layer 101 includes a bit line contact window 13
  • the material of the bit line contact window 13 includes tungsten or Polysilicon
  • the material of the bottom dielectric layer 102 and the top dielectric layer 104 includes silicon nitride, silicon dioxide or silicon oxynitride
  • the metal layer 103 is formed of one conductive material or multiple conductive materials, such as doped polysilicon, titanium, nitride Compounds of titanium, tungsten and tungsten, etc.
  • the isolation layer 20 includes a first isolation layer 201, a second isolation layer 202, and a third isolation layer 203; the first isolation layer 201 is located on the sidewall of the bit line structure 15; the second isolation layer 202 is located far away from the first isolation layer 201 The sidewall of the bit line structure 15, and the material of the second isolation layer 202 is the same as the material of the first dielectric layer; the third isolation layer 203 is located on the sidewall of the second isolation layer 202 away from the first isolation layer 201.
  • the material of the first isolation layer 201 includes materials such as silicon nitride, silicon oxynitride, or silicon oxide. In this embodiment, the material of the first isolation layer 201 is an insulating material containing nitrogen, that is, the first isolation layer 201 is made of nitride. Silicon material.
  • the material of the second isolation layer 202 includes materials such as silicon nitride, silicon oxynitride, or silicon oxide. In this embodiment, the material of the second isolation layer is an insulating material containing oxygen, that is, the second isolation layer 202 is made of silicon oxide. .
  • the material of the third isolation layer 203 includes materials such as silicon nitride, silicon oxynitride, or silicon oxide. In this embodiment, the material of the third isolation layer 203 is an insulating material containing nitrogen. That is, the third isolation layer 203 is made of silicon nitride material.
  • the material of the third isolation layer 203 is the same as the material of the first isolation layer 201, the material of the second isolation layer 202 is different from the material of the first isolation layer 201, and the material of the third isolation layer 203 is also different.
  • the material of the first dielectric layer 301 is the same as the material of the second isolation layer 202, and the material of the second dielectric layer 402 is the same as the material of the first dielectric layer 301.
  • the memory includes: a substrate 10, the substrate 10 includes an array area and a peripheral area, the array area has a plurality of discrete bit line structures 15; an isolation layer 60 located on the sidewall of the bit line structure 15 , And the isolation layer 60 has a gap; a first dielectric layer covering the peripheral area and a second dielectric layer 702 located in the gap for forming an isolation structure; a capacitor contact hole 502 is provided on the substrate 10 between the bit line structures 15.
  • the second dielectric layer 702 is used to seal the gap to form an isolation structure.
  • the present application reduces the parasitic capacitance of the bit line structure through the isolation layer, and enlarges the capacitor contact window and the substrate formed by etching the capacitor contact hole formed on the substrate 10 between the bit line structure 15
  • the contact area of 10 reduces the resistance of the subsequently formed capacitive contact window, thereby increasing the saturation current of the DRAM array area.

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Abstract

本申请实施例提供一种存储器的形成方法及存储器，形成方法包括：提供基底(10)，基底(10)包括阵列区以及外围区，阵列区上具有多个分立的位线结构(15)，且位线结构(15)侧壁形成有隔离层(20)；在阵列区以及外围区上形成第一介电层(301)；图形化位于阵列区的第一介电层(301)，形成开口(501)，且在刻蚀去除第一介电层(301)的过程中部分隔离层(20)被刻蚀，剩余隔离层(20)中具有间隙；形成位于隔离层(20)以及位线结构(15)顶部表面的第二介电膜(401)；用第一刻蚀工艺，刻蚀隔离层(20)侧壁的第二介电膜(401)，形成第二介电层(402)；用第二刻蚀工艺，刻蚀开口(501)底部的部分基底(10)，形成电容接触孔(502)。

Description

存储器的形成方法及存储器
交叉引用
本申请引用于2020年4月23日递交的名称为“存储器的形成方法及存储器”的第202010326652.X号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请涉及半导体领域，特别涉及一种存储器的形成方法及存储器。
背景技术
随着制程工艺的提高，动态随机存取存储器(Dynamic Random Access Memory，DRAM)的集成度增加，特征尺寸和线宽会进一步缩小，相邻位线结构之间间距也变得越来越小。而相邻位线结构之间间距变小，会导致相邻位线结构之间的开口的深宽比变大，影响DRAM阵列区的饱和电流，进而影响DRAM的运行效率。
在DRAM的线宽不断减小的情况下，如何增大DRAM阵列区的饱和电流，是当前亟待解决的问题。
发明内容
本申请实施例提供一种存储器的形成方法及存储器，降低DRAM阵列区的寄生电容，并通过增大电容接触孔的接触面积，减小后续形成的电容接触窗的电阻，进而增大DRAM阵列区的饱和电流。
为解决上述技术问题，本申请实施例提供了一种存储器的形成方法，包括：提供基底，基底包括阵列区以及外围区，阵列区上具有多个分立的位线结构，且位线结构侧壁形成有隔离层；在阵列区以及外围区上形成覆盖位线结构 的第一介电层；图形化并刻蚀位于阵列区的第一介电层，形成开口，且在刻蚀去除第一介电层的过程中部分隔离层被刻蚀，剩余隔离层中具有间隙；形成位于隔离层以及位线结构顶部表面的第二介电膜，第二介电膜还位于隔离层侧壁以及位线结构之间的基底上；采用第一刻蚀工艺，刻蚀隔离层侧壁的第二介电膜，形成第二介电层；采用第二刻蚀工艺，刻蚀开口底部的部分基底，形成电容接触孔。
由于相邻位线结构之间间距变小，会导致相邻位线结构之间的开口的深宽比变大，影响DRAM阵列区的饱和电流，进而影响DRAM的运行效率。本申请通过形成隔离结构降低DRAM阵列区的寄生电容，在后续的工艺制程中，会导致隔离层的顶部与位线结构之间出现间隙，通过形成第二介电层填充间隙或者对隔离层进行封口，保证隔离结构的隔离效果；并通过第一刻蚀工艺和第二刻蚀工艺，分别刻蚀隔离层侧壁的第二介电层和部分开口底部的基底，增大电容接触孔的接触面积，从而减少后续形成的电容接触窗的电阻，从而增大DRAM阵列区的饱和电流。
另外，形成位于隔离层以及位线结构顶部表面的第二介电膜，包括：形成填充间隙的第二介电膜，第二介电膜还位于隔离层以及位线结构顶部表面。通过形成NON叠层隔离结构降低DRAM阵列区的寄生电容。
另外，形成位于隔离层以及位线结构顶部表面的第二介电膜，包括：形成对间隙进行封口的第二介电膜，第二介电膜部分位于间隙的顶部，第二介电膜还位于隔离层以及位线结构顶部表面。通过形成空气间隙隔离结构降低DRAM阵列区的寄生电容。另外，形成位于隔离层以及位线结构顶部表面的第二介电膜之后，且采用第一刻蚀工艺，刻蚀隔离层侧壁的第二介电膜之前，包 括：刻蚀去除隔离层和位线结构顶部表面以及位线结构之间的基底上的第二介电膜。
另外，第二介电层的材料与第一介电层的材料相同。
另外，去除位于阵列区的第一介电层，形成开口，包括：刻蚀去除位于阵列区的第一介电层，直至暴露出位线结构的顶部表面；刻蚀去除位于位线结构之间的第一介电层，形成开口。
另外，刻蚀去除第一介电层的刻蚀材料包括氢氟酸。
另外，隔离层包括第一隔离层、第二隔离层和第三隔离层；第一隔离层位于位线结构的侧壁；第二隔离层位于第一隔离层远离位线结构的侧壁；第三隔离层位于第二隔离层远离第一隔离层的侧壁；在去除第一介电层过程中部分隔离层被刻蚀，包括：部分厚度的第二隔离层被刻蚀。
另外，在阵列区以及外围区上形成覆盖位线结构的第一介电层，包括：在阵列区以及外围区上形成填充位线结构间的间隙的第一介电膜，且第一介电膜覆盖位线结构的顶部表面；对第一介电膜的顶部表面进行平坦化处理形成第一介电层。
另外，采用旋转涂覆工艺形成第一介电膜。
本申请实施例还提供了一种存储器，包括：基底，基底包括阵列区以及外围区，阵列区上具有多个分立的位线结构；位于位线结构侧壁的隔离层，且隔离层与位线结构之间具有间隙；覆盖外围区的第一介电层以及位于所述间隙中用于形成隔离结构的第二介电层；位线结构之间的基底上具有电容接触孔。
另外，用于形成隔离结构的第二介电层，包括：第二介电层用于填充间隙以形成隔离结构，或第二介电层用于对间隙进行封口以形成隔离结构。
另外，隔离层包括第一隔离层、第二隔离层和第三隔离层；第一隔离层位于位线结构的侧壁；第二隔离层位于第一隔离层远离位线结构的侧壁；第三隔离层位于第二隔离层远离第一隔离层的侧壁。
相比于相关技术而言，本申请通过隔离结构降低位线结构的寄生电容，并通过在位线结构之间的基底上刻蚀形成的电容接触孔，增大后续形成的电容接触窗与基底的接触面积，减小后续形成的电容接触窗的电阻，从而增大DRAM阵列区的饱和电流。
附图说明
图1至图12为本申请一实施例提供的存储器的形成方法各步骤对应的结构示意图；
图13至图16为本申请另一实施例提供的存储器的形成方法各步骤对应的结构示意图。
具体实施方式
目前，在DRAM的线宽不断减小的情况下，DRAM阵列区的饱和电流也会逐渐减小，如何增大DRAM阵列区的饱和电流，是当前亟待解决的问题。
为解决上述问题，本申请一实施例提供了一种存储器的形成方法，包括：提供基底，基底包括阵列区以及外围区，阵列区上具有多个分立的位线结构，且位线结构侧壁形成有隔离层；在阵列区以及外围区上形成覆盖位线结构的第一介电层；图形化并刻蚀位于阵列区的第一介电层，形成开口，且在刻蚀去除第一介电层的过程中部分隔离层被刻蚀，剩余隔离层中具有间隙；形成位于隔离层以及位线结构顶部表面的第二介电膜，第二介电膜还位于隔离层侧壁以及位线结构之间的基底上；采用第一刻蚀工艺，刻蚀隔离层侧壁的第二介电膜， 形成第二介电层；采用第二刻蚀工艺，刻蚀开口底部的部分基底，形成电容接触孔。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1至图12为本实施例提供的存储器的形成方法各步骤对应的结构示意图，下面结合附图对本实施例的存储器的形成方法进行具体说明。
参考图1至图7，图1为提供的基底以及后续形成的电容接触窗的俯视示意图，图2为根据图1中虚线20方向上存储器的剖面示意图。
参考图1，基底10，基底10上包括有源区11、位线接触窗13、字元线14、位元线15以及电容接触窗16，后续存储器形成方法中以虚线12给出的存储器形成方法的剖面示意图，需要说明的是，本实施例主要对DRAM的阵列区的形成方法进行介绍，相应的附图也只画出的DRAM阵列区的结构变化，便于本领域技术人员理解本方案的实施。
提供基底10，基底10包括阵列区以及外围区，阵列区上具有多个分立的位线结构15，且位线结构15侧壁形成有隔离层。
参考图2，基底10内包括埋入式字线、浅沟槽隔离层、有源区等结构。位线结构15包括位线接触层101、底层介质层102、金属层103以及顶层介质 层104，具体地，位线接触层101包括位线接触窗13，以图1中虚线12的剖面方向，连续三个位线结构15中只有一个位线结构15通过位线接触窗13连接基底10中的有源区；本实施例以中间的位线结构15通过位线接触窗13连接基底10中的有源区为例进行举例说明。
位线接触窗13的材料包括钨或多晶硅，底层介质层102和顶层介质层104的材料包括氮化硅、二氧化硅或氮氧化硅，金属层103由一种导电材料或者多种导电材料形成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等。
隔离层包括第一隔离层、第二隔离层和第三隔离层；第一隔离层位于位线结构15的侧壁；第二隔离层位于第一隔离层远离位线结构15的侧壁；第三隔离层位于第二隔离层远离第一隔离层的侧壁，以下将结合附图对隔离层的形成步骤进行详细说明：
参考图3，在位线结构15的顶部表面、侧壁以及位线结构15之间的基底10上形成第一隔离层201，第一隔离层201作为隔离层的内层侧壁，紧贴位线结构15的侧壁。
第一隔离层201的材料包括氮化硅、氮氧化硅或氧化硅等材料。在本实施例中，第一隔离层201的材料为含氮的绝缘材料，即第一隔离层201采用氮化硅材料。需要说明的是，在本实施例中，后续形成的第三隔离层与第一隔离层201的材料相同，在其他实施例中，后续形成的第三隔离层的材料可与第一隔离层的材料不相同。
参考图4，在第一隔离层201的顶部表面以及侧壁形成第二隔离层202。
具体地，采用原子层沉积的方式形成第二隔离层202，原子层沉积具有沉积速率慢，沉积形成的膜层致密性高和阶梯覆盖率好等特点。如此，能够使 得第二隔离层202能够在厚度较薄的条件下进行有效地隔离保护，避免第二隔离层202占据相邻位线结构15之间较小的空间，有利于后续增大位线接触窗的横截面积。
第二隔离层202的材料包括氮化硅、氮氧化硅或氧化硅等材料。在本实施例中，第二隔离层的材料为含氧的绝缘材料，即第二隔离层202采用氧化硅材料。需要说明的是，第二隔离层202的材料与第一隔离层201的材料不同，与后续形成的第三隔离层的材料亦不相同。
参考图5，刻蚀去除第一隔离层201顶部表面的第二隔离层202，剩余的第二隔离层202位于第一隔离层201远离位线结构15的侧壁。
参考图6，在第一隔离层201的顶部表面以及第二隔离层202的侧壁形成第三隔离层203。
第三隔离层203的材料包括氮化硅、氮氧化硅或氧化硅等材料。在本实施例中，第三隔离层203的材料为含氮的绝缘材料，即第三隔离层203采用氮化硅材料。需要说明的是，在本实施例中，第三隔离层203与上述形成的第一隔离层201的材料相同。
参考图7，刻蚀去除第一隔离层201顶部表面的第三隔离层203，以及位线结构15顶部表面的第一隔离层201与第二隔离层202。
剩余的第三隔离层203位于第二隔离层202远离第一隔离层201的侧壁。位线结构15侧壁依次堆叠的第一隔离层201、第二隔离层202以及第三隔离层203共同组成隔离层20。
需要说明的是，本实施例以NON叠层隔离层作为位线结构15侧壁的隔离层20，是为了减小位线结构15的寄生电容，并不构成对本方案的限定，其 厚度可以根据实际的应用下的器件尺寸进行灵活设置；另外，在其他实施例中可以采用其他结构作为位线结构侧壁的隔离层。
参考图8，在阵列区以及外围区上形成覆盖位线结构15的第一介电层301，第一介电层材料可以与第二隔离层202材料相同也可不同，在具体应用过程中，可以根据刻蚀材料的刻蚀选择比进行调整。在本实施例中，第一介电层301的材料与第二隔离层202的材料相同。
具体地，在阵列区以及外围区上形成填充位线结构15间的间隙的第一介电膜(未图示)，且第一介电膜覆盖位线结构15的顶部表面。第一介电膜(未图示)采用旋转涂覆工艺形成，采用旋转涂覆的方式形成的第一介电膜(未图示)具有填充性好的优点。
对第一介电膜(未图示)的顶部表面进行平坦化处理形成第一介电层301。具体地，采用化学机械研磨的方式将第一介电膜(未图示)顶部表面进行平坦化处理，化学机械研磨工艺相对于刻蚀工艺具有较高的去除速率，有利于缩短工艺周期。
参考图8以及图9，去除位于阵列区的第一介电层301，形成开口501，且在去除第一介电层301过程中部分隔离层20被刻蚀，剩余隔离层20中具有间隙，即部分第二隔离层202被刻蚀。由于本实施例为形成位线结构15侧壁的NON隔离结构，第二隔离层202并不会被刻蚀至较矮的高度。
具体地，刻蚀去除位于阵列区的第一介电层301，直至暴露出位线结构15的顶部表面；刻蚀去除位于位线结构15之间的第一介电层301，形成开口501。刻蚀去除第一介电层301的刻蚀材料包括氢氟酸，采用氢氟酸材料进行刻蚀具有较高的去除速率，有利于缩短工艺周期。
去除后的第一介电层301仍然覆盖外围区表面。由于第一介电层301的材料与第二隔离层202的材料相同，此时隔离层20中的第二隔离层202的顶部会被刻蚀掉部分高度，形成间隙。在本实施例中，即部分厚度的第二隔离层202被刻蚀。
参考图10～图12，形成位于隔离层20以及位线结构15顶部表面的第二介电膜401，第二介电膜401还位于隔离层20侧壁以及位线结构15之间的基底10上。
具体地，形成填充间隙的第二介电膜401，第二介电膜401还位于隔离层20以及位线结构15顶部表面。
在阵列区上形成填充间隙的第二介电膜401，第二介电膜401还覆盖位线结构15和隔离层20的顶部表面、隔离层20的侧壁以及位线结构之间的基底10上。
刻蚀去除位线结构15和隔离层20顶部表面以及位线结构15之间基底10上的第二介电膜401。在本实施例中，第二介电膜401的材料与第一介电层301的材料相同。
具体地，采用原子层沉积的方式形成第二介电膜401，原子层沉积具有沉积速率慢，沉积形成的膜层致密性高和阶梯覆盖率好等特点；如此，能够使得第二介电膜401能够完全填充隔离层20中的间隙。
参考图11，采用第一刻蚀工艺，刻蚀去除隔离层20侧壁的第二介电膜401，形成第二介电层402。
由于在本实施例中，位线结构15侧壁的隔离结构为NON叠层隔离结构，隔离效果好，隔离层20外层的第二介电层402会导致后续形成的位线接触窗的 横截面积变小。因此，采用第一刻蚀工艺，刻蚀去除隔离层20侧壁的第二介电层402。
具体地，第一刻蚀工艺为各向同性刻蚀，采用的刻蚀气体为CF 4、CHF 3以及O 2的混合气体，其中CF 4的气体流量范围为100sccm～300sccm，CHF 3的气体流量范围为50sccm～200sccm，O 2的气体流量范围为1sccm～20sccm；刻蚀压强范围为5mtor～16mtor；刻蚀功率范围为200W～600W；刻蚀电压为0V；刻蚀温度为20℃～80℃；刻蚀时间为5s～30s，通过合理控制第一刻蚀工艺的时间，可以完全刻蚀隔离层20侧壁的第二介电层402或刻蚀隔离层20侧壁部分厚度的第二介电层402，从而增大位线结构15之间的开口的横截面积，即增大后续形成的电容接触窗的横截面积，用于降低后续形成的电容接触窗的电阻。
在本实施例中，第一刻蚀工艺的参数范围为：刻蚀气体采用：180sccm～220sccm的CF 4、100sccm～150sccm的CHF 3以及5sccm～10sccm的O 2构成的混合气体；刻蚀压强范围为7mtor～12mtor；刻蚀功率为350W～450W；刻蚀电压为0V；刻蚀温度为60℃；刻蚀时间为15s～20s。
参考图12，采用第二刻蚀工艺，刻蚀开口501底部的部分基底10，形成电容接触孔502。
第二刻蚀工艺采用对第一隔离层201和基底10中的多晶硅和氧化层的刻蚀选择比不同，其刻蚀速率的大小差异为对第一隔离层201(氮化物)的刻蚀速率最快，对基底10中的多晶硅的刻蚀速率最慢，对基底10中的氧化层(氧化物)的刻蚀速率适中。
具体地，首先采用第二刻蚀工艺，刻蚀去除开口501底部的第一隔离层201，然后继续采用第二刻蚀工艺刻蚀开口501底部的部分基底10形成电容接 触孔502。
由于第二刻蚀工艺对第一隔离层201的刻蚀速率最快，能够较快的刻蚀掉第一隔离层201，缩短刻蚀时间，进而避免位线结构15顶部可能被刻蚀掉较厚的高度，从而造成阵列区与外围区的高度差过大从而影响后续的工艺制程。
由于第二刻蚀工艺对基底10中的多晶硅的刻蚀速率较慢，避免第二刻蚀工艺刻蚀掉基底10中较多的多晶硅，从而避免了导致DRAM电性失效的问题。且第二刻蚀工艺对基底10中的多晶硅和氧化层的刻蚀速率不同，使得刻蚀后的电容接触孔502的底部形貌并不是平整表面，相对于平整表面增加了后续形成的电容接触窗与基底10的接触面积，从而减小了后续形成的电容接触窗的电阻，有利于增大DRAM阵列区的饱和电流。在其他实施例中，第二刻蚀工艺的材料选择只需要保证对基底中的氧化层和多晶硅有较大的刻蚀选择比即可。
具体地，第二刻蚀工艺采用的刻蚀气体为CF 4以及He的混合气体，其中CF 4的气体流量范围为30sccm～70sccm，He的气体流量范围为50sccm～150sccm；刻蚀压强范围为5mtor～16mtor；刻蚀功率范围为300W～700W；刻蚀电压为100V～400V；刻蚀温度为20℃～80℃。
在本实施例中，第二刻蚀工艺的参数范围为：刻蚀气体采用：45sccm～55sccm的CF 4以及100sccm的He构成的混合气体；刻蚀压强范围为7mtor～12mtor；刻蚀功率为450W～550W；刻蚀电压为200V～300V；刻蚀温度为60℃。
相对于相关技术而言，本申请通过形成隔离结构降低DRAM阵列区的寄生电容，在后续的工艺制程中，会导致隔离层20的顶部与位线结构15之间出现间隙，通过形成第二介电层402填充间隙，保证隔离结构的隔离效果；并通 过第一刻蚀工艺和第二刻蚀工艺，分别刻蚀隔离层20侧壁的第二介电膜401和部分开口501底部的基底10，增大电容接触孔的接触面积，从而减少后续形成的电容接触窗的电阻，从而增大DRAM阵列区的饱和电流。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请另一实施例涉及一种存储器的形成方法，与上述实施例不同的是，本实施例中最终形成的隔离结构为空气隔离结构，具体如下：
刻蚀去除第一隔离层顶部表面的第三隔离层，以及位线结构顶部表面的第一隔离层与第三隔离层。
剩余的第三隔离层位于第二隔离层远离第一隔离层的侧壁。位线结构侧壁依次堆叠的第一隔离层、第二隔离层以及第三隔离层共同组成隔离层。
需要说明的是，本实施例以空气间隙隔离结构作为位线结构侧壁的隔离结构，即在后续的工艺中需要去除第二隔离层以形成空气间隙。采用空气间隙作为隔离结构，是为了减小位线结构的寄生电容。
在阵列区以及外围区上形成覆盖位线结构的第一介电层。
图13至图16为本实施例提供的存储器的形成方法各步骤对应的结构示意图，下面结合附图对本实施例的实现细节进行详细说明，与上述实施例相同的部分，在本实施例中不再进行相应描述：
参考图13，去除位于阵列区的第一介电层，形成开口501，且在去除第一介电层过程中部分隔离层60被刻蚀，剩余隔离层60与位线结构15之间具有 间隙。即部分第二隔离层602被刻蚀，由于本实施例需要形成空气间隙，第二隔离层602被刻蚀较高的高度；
参考图14，形成位于隔离层60以及位线结构15顶部表面的第二介电膜701，第二介电膜701还位于隔离层60侧壁以及位线结构15之间的基底10上；
具体地，形成对间隙进行封口的第二介电膜701，701第二介电膜部分位于间隙的顶部，第二介电膜701还位于隔离层60以及位线结构15顶部表面。
采用快速封口工艺，在隔离层60和位线结构15的顶部表面形成第二介电膜701，第二介电膜701还覆盖隔离层60的侧壁以及位线结构15之间的基底10上。
刻蚀去除隔离层60和位线结构15顶部表面以及位线结构15之间的基底10上的第二介电膜701。需要说明的是，在本实施例中，第二介电膜701的材料与第一介电层的材料相同，在其他实施例中，第二介电膜的材料与第一介电层的材料也可以不同。
具体地，采用快速封口工艺的方式形成第二介电膜701，具有快速沉积的作用，形成的第二介电膜701用于对隔离层60的顶部进行封口，以形成空气隔离结构。
参考图15和图16，采用第一刻蚀工艺，刻蚀去除隔离层60侧壁的第二介电膜701，形成第二介电层702。
由于在本实施例中，位线结构15侧壁的隔离结构为空气间隙隔离结构，隔离效果好，隔离层60外层的第二介电膜701会导致后续形成的位线接触窗的横截面积变小。因此采用第一刻蚀工艺，刻蚀去除隔离层60侧壁的第二介电膜701。
通过合理控制第一刻蚀工艺的时间，可以完全刻蚀隔离层60侧壁的第二介电膜701或刻蚀隔离层60侧壁部分厚度的第二介电膜701，从而增大位线结构15之间的开口501的横截面积，即增大后续形成的电容接触窗的横截面积，用于降低后续形成的电容接触窗的电阻，刻蚀之后剩余的第二介电膜701形成第二介电层702，第二介电层702位于隔离层60中间隙的顶部，使得隔离层60形成空气间隙隔离结构。
参考图16，采用第二刻蚀工艺，刻蚀开口501底部的部分基底10，形成电容接触孔502。
第二刻蚀工艺采用对第一隔离层201和基底10中的多晶硅和氧化层的刻蚀选择比不同，其刻蚀速率的大小差异为对第一隔离层201(氮化物)的刻蚀速率最快，对基底10中的多晶硅的刻蚀速率最慢，对基底10中的氧化层(氧化物)的刻蚀速率适中。
具体地，首先采用第二刻蚀工艺，刻蚀去除开口501底部的第一隔离层201，然后继续采用第二刻蚀工艺刻蚀开口501底部的部分基底10形成电容接触孔502。
相对于相关技术而言，本申请通过形成隔离结构降低DRAM阵列区的寄生电容，在后续的工艺制程中，会导致隔离层60的顶部与位线结构15之间出现间隙，通过形成第二介电层702对隔离层60进行封口，保证空气间隙隔离结构的形成；并通过第一刻蚀工艺和第二刻蚀工艺，分别刻蚀隔离层60侧壁的第二介电膜701和部分开口501底部的基底10，增大电容接触孔的接触面积，从而减少后续形成的电容接触窗的电阻，从而增大DRAM阵列区的饱和电流。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或 者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
需要说明的是，上述实施例分别以NON隔离结构和空气隔离结构，介绍了本申请中通过第一刻蚀工艺和第二刻蚀工艺增大后续形成的电容接触窗接触面积的方法，并不构成对本申请中第一刻蚀工艺和第二刻蚀工艺的应用限定，本领域技术人员知晓，上述刻蚀工艺以增大后续形成的电容接触窗接触面积的实施例还可以应用于其他隔离结构的DRAM阵列区结构中。
本申请又一实施例涉及一种存储器，该存储器可采用上述的形成方法形成，以下将结合附图对本实施例提供的存储器进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
参考图12，存储器，包括：基底10，基底10包括阵列区以及外围区，阵列区上具有多个分立的位线结构15；位于位线结构15侧壁的隔离层20，且隔离层20具有间隙；覆盖外围区的第一介电层以及位于所述间隙中用于形成隔离结构的第二介电层402；位线结构15之间的基底10上具有电容接触孔502。
在本实施例中，第二介电层402用于填充间隙以形成隔离结构。
基底10内包括埋入式字线、浅沟槽隔离层、有源区等结构。位线结构15包括位线接触层101、底层介质层102、金属层103以及顶层介质层104，具体地，位线接触层101包括位线接触窗13，位线接触窗13的材料包括钨或多晶硅，底层介质层102和顶层介质层104的材料包括氮化硅、二氧化硅或氮氧化硅，金属层103由一种导电材料或者多种导电材料形成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等。
其中，隔离层20包括第一隔离层201、第二隔离层202和第三隔离层203；第一隔离层201位于位线结构15的侧壁；第二隔离层202位于第一隔离层201远离位线结构15的侧壁，且第二隔离层202的材料与第一介电层的材料相同；第三隔离层203位于第二隔离层202远离第一隔离层201的侧壁。
第一隔离层201的材料包括氮化硅、氮氧化硅或氧化硅等材料，在本实施例中，第一隔离层201的材料为含氮的绝缘材料，即第一隔离层201采用氮化硅材料。第二隔离层202的材料包括氮化硅、氮氧化硅或氧化硅等材料，在本实施例中，第二隔离层的材料为含氧的绝缘材料，即第二隔离层202采用氧化硅材料。第三隔离层203的材料包括氮化硅、氮氧化硅或氧化硅等材料，在本实施例中，第三隔离层203的材料为含氮的绝缘材料。即第三隔离层203采用氮化硅材料。
需要说明的是，第三隔离层203与第一隔离层201的材料相同，第二隔离层202的材料与第一隔离层201的材料不同，与第三隔离层203的材料亦不相同。
在本实施例中，第一介电层301的材料与第二隔离层202的材料相同，第二介电层402的材料与第一介电层301的材料相同。
在其他实施例中，参考图16，存储器，包括：基底10，基底10包括阵列区以及外围区，阵列区上具有多个分立的位线结构15；位于位线结构15侧壁的隔离层60，且隔离层60具有间隙；覆盖外围区的第一介电层以及位于间隙中用于形成隔离结构第二介电层702；位线结构15之间的基底10上具有电容接触孔502。
此时，第二介电层702用于对间隙进行封口以形成隔离结构。
与相关技术相比，本申请通过隔离层降低位线结构的寄生电容，并通过在位线结构15之间的基底10上刻蚀形成的电容接触孔，增大后续形成的电容接触窗与基底10的接触面积，减小后续形成的电容接触窗的电阻，从而增大DRAM阵列区的饱和电流。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (10)

  1. 一种存储器的形成方法，其特征在于，包括：
    提供基底，所述基底包括阵列区以及外围区，所述阵列区上具有多个分立的位线结构，且所述位线结构侧壁形成有隔离层；
    在所述阵列区以及所述外围区上形成覆盖所述位线结构的第一介电层；
    图形化并刻蚀位于所述阵列区的所述第一介电层，形成开口，且在刻蚀去除所述第一介电层的过程中部分所述隔离层被刻蚀，剩余所述隔离层中具有间隙；
    形成位于所述隔离层以及所述位线结构顶部表面的第二介电膜，所述第二介电膜还位于所述隔离层侧壁以及所述位线结构之间的所述基底上；
    采用第一刻蚀工艺，刻蚀所述隔离层侧壁的所述第二介电膜，形成第二介电层；
    采用第二刻蚀工艺，刻蚀所述开口底部的部分所述基底，形成电容接触孔。
  2. 根据权利要求1所述的存储器的形成方法，其特征在于，所述形成位于所述隔离层以及所述位线结构顶部表面的第二介电膜，包括：形成填充所述间隙的所述第二介电膜，所述第二介电膜还位于所述隔离层以及所述位线结构顶部表面。
  3. 根据权利要求1所述的存储器的形成方法，其特征在于，所述形成位于所述隔离层以及所述位线结构顶部表面的第二介电膜，包括：形成对所述间隙进行封口的所述第二介电膜，所述第二介电膜部分位于所述间隙的顶部，所述第二介电膜还位于所述隔离层以及所述位线结构顶部表面。
  4. 根据权利要求2或3所述的存储器的形成方法，其特征在于，所述形成位于 所述隔离层以及所述位线结构顶部表面的第二介电膜之后，且所述采用第一刻蚀工艺，刻蚀所述隔离层侧壁的所述第二介电膜之前，包括：刻蚀去除所述隔离层和所述位线结构顶部表面以及所述位线结构之间的所述基底上的所述第二介电膜。
  5. 根据权利要求1所述的存储器的形成方法，其特征在于，所述去除位于所述阵列区的所述第一介电层，形成开口，包括：
    刻蚀去除位于所述阵列区的所述第一介电层，直至暴露出所述位线结构的顶部表面；
    刻蚀去除位于所述位线结构之间的所述第一介电层，形成开口。
  6. 根据权利要求1所述的存储器的形成方法，其特征在于，包括：
    所述隔离层包括第一隔离层、第二隔离层和第三隔离层；
    所述第一隔离层位于所述位线结构的侧壁；
    所述第二隔离层位于所述第一隔离层远离所述位线结构的侧壁；
    所述第三隔离层位于所述第二隔离层远离所述第一隔离层的侧壁；
    在去除所述第一介电层过程中部分所述隔离层被刻蚀，包括：部分厚度的所述第二隔离层被刻蚀。
  7. 根据权利要求6所述的存储器的形成方法，其特征在于，所述在所述阵列区以及外围区上形成覆盖所述位线结构的第一介电层，包括：
    在所述阵列区以及所述外围区上形成填充所述位线结构间的间隙的第一介电膜，且所述第一介电膜覆盖所述位线结构的顶部表面；
    对所述第一介电膜的顶部表面进行平坦化处理形成所述第一介电层。
  8. 一种存储器，其特征在于，包括：
    基底，所述基底包括阵列区以及外围区，所述阵列区上具有多个分立的位线结构；
    位于所述位线结构侧壁的隔离层，且所述隔离层具有间隙；
    覆盖所述外围区的第一介电层以及位于所述间隙中用于形成隔离结构的第二介电层；
    所述位线结构之间的所述基底上具有电容接触孔。
  9. 根据权利要求8所述的存储器，其特征在于，所述用于形成隔离结构的第二介电层，包括：第二介电层用于填充所述间隙以形成隔离结构，或所述第二介电层用于对所述间隙进行封口以形成隔离结构。
  10. 根据权利要求8所述的存储器，其特征在于，包括：
    所述隔离层包括第一隔离层、第二隔离层和第三隔离层；
    所述第一隔离层位于所述位线结构的侧壁；
    所述第二隔离层位于所述第一隔离层远离所述位线结构的侧壁；
    所述第三隔离层位于所述第二隔离层远离所述第一隔离层的侧壁。
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