WO2021232901A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2021232901A1
WO2021232901A1 PCT/CN2021/080208 CN2021080208W WO2021232901A1 WO 2021232901 A1 WO2021232901 A1 WO 2021232901A1 CN 2021080208 W CN2021080208 W CN 2021080208W WO 2021232901 A1 WO2021232901 A1 WO 2021232901A1
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WO
WIPO (PCT)
Prior art keywords
display panel
line
data
data switch
switch
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PCT/CN2021/080208
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English (en)
French (fr)
Inventor
蓝平
蔡佳作
刘甲定
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云谷（固安）科技有限公司
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Application filed by 云谷（固安）科技有限公司 filed Critical 云谷（固安）科技有限公司
Publication of WO2021232901A1 publication Critical patent/WO2021232901A1/zh
Priority to US17/740,701 priority Critical patent/US11881132B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the present disclosure relates to the field of display technology, for example, to a display panel and a display device.
  • the display panel usually includes a test circuit, and the data switch line in the test circuit has a greater risk of short circuit, which causes a problem of poor display of the display panel, which seriously affects the display effect.
  • the present disclosure provides a display panel and a display device to reduce the risk of short circuit of data switch lines in the display panel, thereby improving the display effect.
  • the present disclosure provides a display panel.
  • the display panel includes a test circuit located in a non-display area, and the test circuit includes:
  • a plurality of switch transistors in each switch transistor, a first terminal is electrically connected to a data line in the display panel, and a second terminal is configured to receive a test data signal;
  • a data switch line extending in the first direction is arranged in the same layer as the source and drain layer of each switch transistor, and the data switch line is set to control the switch transistor to be turned on or off.
  • the present disclosure also provides a display device including the display panel as described above.
  • the display panel used in the present disclosure includes a test circuit located in the non-display area, the test circuit includes a plurality of switch transistors, the first end of the switch transistor is electrically connected to the data line in the display panel, and the second end is set to receive the test data signal;
  • the circuit also includes a data switch line extending along the first direction, the data switch line is arranged in the same layer as the source and drain layer of the switch transistor, and the data switch line is set to control the switch transistor to be turned on or off.
  • the data switching line and the subsequent film can be reduced in the yellow light and dry etching process and the roller ( ROLLOR), step (STADGE), pad (PAD) or pin (PIN) contact to generate the risk of electric charge, and at the same time can reduce the accumulation process, that is, the following conductive film layer of the film layer where the data switch line is located is less, Therefore, the charge accumulated on the data switch line is reduced, the risk of the data switch line being short-circuited due to the breakdown of the gate insulating layer caused by the charge release of the data switch line, avoids poor display of the display panel, and ensures that the display panel has a better display effect.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment
  • FIG. 2 is a schematic diagram of a film structure of a display panel provided by an embodiment
  • FIG. 3 is a cross-sectional view of the film along the A1-A2 direction in FIG. 2 provided by an embodiment
  • FIG. 4 is a cross-sectional view of the film along the A3-A4 direction in FIG. 2 provided by an embodiment
  • FIG. 5 is a schematic diagram of the film structure of a display panel in which the vertical projection of the data switch line on the plane where the active layer of the switch transistor is located does not overlap with the active layer of the switch transistor according to an embodiment
  • FIG. 6 is a cross-sectional view of the film along the direction A5-A6 in FIG. 5 provided by an embodiment
  • FIG. 7 is a cross-sectional view of the film along the direction A7-A8 in FIG. 5 provided by an embodiment
  • FIG. 8 is a schematic diagram of a film structure of a display panel including via holes according to an embodiment
  • FIG. 9 is a schematic structural diagram of a display device provided by an embodiment.
  • the reason for the greater risk of short circuit in the data switch line in the display panel is that the data switch line in the display panel is arranged on the same layer as the gate electrode of the thin film transistor of the display panel.
  • the process will cause serious charge accumulation.
  • the gate insulating layer will break down, which will cause the data switch line to be short-circuited, resulting in poor display of the display panel, and seriously affecting the display effect.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment.
  • the display panel includes a test circuit located in a non-display area (NAA), and the test circuit includes a plurality of switching transistors 101.
  • the first end of 101 is electrically connected to the data line 111 in the display panel, and the second end is set to receive the test data signal;
  • the test circuit further includes a data switch line 102 extending along the first direction X, the data switch line 102 and the switch transistor 101
  • the source and drain layers are arranged in the same layer, and the data switch line 102 is arranged to control the switching transistor 101 to be turned on or off.
  • the display panel may include a plurality of data lines 111 and scan lines 112 interlaced horizontally and vertically in the display area AA.
  • the data lines 111 and the scan lines 112 are interlaced to form a plurality of pixel regions, and each pixel region may include a pixel driving circuit 113
  • the scan line 112 and the data line 111 respectively provide scan signals and data signals for the pixel driving circuit 113, and the circuit structure and working method of the pixel driving circuit 113 are not repeated here.
  • a series of tests are required, such as a cell test (CT) test, etc., to determine whether the display panel is intact.
  • the test circuit can be set to test the display panel.
  • Multiple switching transistors 101 It can be electrically connected to multiple data lines 111 in the display panel in a one-to-one correspondence.
  • the test data signal is transmitted to the data line 111 and then to the corresponding pixel driving circuit 113 to drive the corresponding light-emitting structure to emit light to complete the test.
  • FIG. 1 only exemplarily shows four rows and four columns of pixel regions and four switching transistors, but the number of pixel regions and switching transistors of the present disclosure is not limited to this, and the number of switching transistors 101 in FIG. 1
  • the second end is electrically connected to the same test pad. In some other embodiments, the second ends of different switching transistors 101 can also be connected to different test pads, as long as the test data signal can be input.
  • FIG. 2 is a schematic diagram of a film structure of a display panel provided by an embodiment
  • FIG. 3 is a cross-sectional view of the film along the A1-A2 direction in FIG. 2 provided by an embodiment
  • FIG. 4 is a cross-sectional view provided by an embodiment 2.
  • the interlayer insulating layer between the drain electrode layers, etc., in other embodiments, may also include a capacitor electrode layer and an interlayer insulating layer between the capacitor electrode layer and the source and drain electrode layers.
  • the active layer may include a heavily doped region 1016 and lightly doped regions located on both sides of the heavily doped region 1016, that is, a first lightly doped region 1015 and a second lightly doped region 1017, through which the first lightly doped region 1015 passes
  • the first via 1019 is electrically connected to the first electrode 1013
  • the first electrode 1013 may be the source of the switching transistor 101
  • the second lightly doped region 1017 is electrically connected to the second electrode 1014 of the switching transistor 101 through the second via 1010
  • the second electrode 1014 may be the drain of the switching transistor 101; under the action of the control signal on the switching data line 102, the first lightly doped region 1015 and the second lightly doped region 1017 are turned on, so that the first transistor There is conduction between the first end and the second end of 101.
  • the switching transistor 101 may be a P-type transistor or an N-type transistor.
  • the yellow light and dryness of the data switch line 102 and subsequent films can be reduced.
  • the risk of charge generated by contact with ROLLOR, STADGE, PAD or PIN can also be reduced.
  • the accumulation process can be reduced.
  • the charge accumulated on the data switch line 102 reduces the risk of the data switch line 102 being short-circuited due to the breakdown of the gate insulating layer 1012 due to the discharge of the charge, avoids poor display of the display panel, and ensures that the display panel has a better display effect.
  • the active layer, gate layer, gate insulating layer, and source and drain layers of the switching transistor 101 are respectively the same as the active layer, gate layer, and gate layer of the transistor in the display area of the display panel.
  • the polar insulating layer and the source and drain layers are the same layer.
  • the adopted display panel includes a test circuit located in the non-display area.
  • the test circuit includes a plurality of switch transistors. The first end of the switch transistor is electrically connected to the data line in the display panel. Test the data signal; the test circuit also includes a data switch line extending along the first direction, the data switch line is arranged in the same layer as the source and drain layer of the switch transistor, and the data switch line is set to control the switch transistor to be turned on or off.
  • PAD or PIN contact to generate the risk of charge, and can also reduce the accumulation process, that is, the film layer where the data switch line is located, there are fewer subsequent conductive film layers, thereby reducing the charge accumulated on the data switch line, and reducing the cost of the data switch line.
  • the discharge of charge causes the gate insulating layer to break down and cause the risk of short-circuiting of the data switch lines, avoiding poor display of the display panel, and ensuring that the display panel has a better display effect.
  • a third via 1018 may be provided. One end of the third via 1018 is electrically connected to the data switch line 102, and the other end is connected to the gate.
  • the insulating layer 1012 is connected to a side close to the data switch line 102.
  • FIG. 5 is a schematic diagram of the film structure of another display panel provided by an embodiment.
  • the vertical projection of the data switch line 102 on the plane where the active layer of the switch transistor 101 is located is similar to that of the switch transistor 101.
  • the active layers do not overlap.
  • the vertical projection of the data switch line 102 on the plane where the active layer of the switch transistor 101 is located does not overlap with the active layer of the switch transistor. Even if the charge on the data switch line 102 is released, it will not As a result, the data switch line 102 and the data line 111 are short-circuited, which reduces the risk of poor display of the display panel and ensures that the display panel has a higher display effect.
  • the display panel further includes a plurality of branch lines 201 corresponding to the plurality of switching transistors 101 one-to-one.
  • One end of each branch line 201 is electrically connected to the data switching line 102, and the other end is connected to the switching transistor 101.
  • the gate electrode 202 is electrically connected.
  • the control signal of the data switch line 102 can be transmitted to the gate electrode 202 of the switch transistor 101, and the conduction between the first terminal and the second terminal of the switch transistor 101 is controlled, so that the test data signal is written into
  • the data line 111 of the display panel further completes the test function.
  • the branch line 201 includes a first metal wiring 2011 and a second metal wiring 2012, the first metal wiring 2011 extends along the first direction X and is electrically connected to the gate electrode 202 of the switching transistor 101; the second metal The trace 2012 is electrically connected to the first metal trace 2011, and the second metal trace 2012 extends along the second direction Y and is electrically connected to the data switch line 102; wherein the first direction X is perpendicular to the second direction Y.
  • the gate electrode 202 of the switching transistor 101 can extend along the first direction X, and the branch line 201 and the gate electrode 202 can form an "L"-shaped structure.
  • the pole electrode 202 is equivalent to being divided into a plurality of small segments.
  • the risk of charge accumulation in a long trace can be reduced.
  • the second metal trace 2012 extends along the second direction Y, which is perpendicular to the substrate conveying direction during the process, which can reduce the risk that the process accumulated charges will accumulate on the second metal trace 2012, thereby preventing data switching
  • the defect rate of the data line 111 in the display area of the display panel due to the short circuit of the data switch line 102 is reduced by more than 99.5%, thereby avoiding display defects.
  • FIG. 6 is a cross-sectional view of the film along the direction A5-A6 in FIG. 5 provided by an embodiment
  • FIG. 7 is a cross-sectional view of the film along the direction A7-A8 in FIG. 5 to 7, the branch line 201 and the gate electrode 202 of the switching transistor 101 are arranged in the same layer.
  • This arrangement can reduce the difficulty of connecting the branch line 201 and the gate electrode 202, and the branch line 201 and the gate electrode 202 can be the same metal trace.
  • the gate electrode 202 of the switching transistor 101 is located on the same layer as the gate electrode of the thin film transistor in the display area AA.
  • the second metal wiring can be realized by providing the fourth via 2013. 2012 and the electrical connection of the data switch line 102.
  • FIG. 8 is a schematic diagram of a film structure of another display panel provided by an embodiment.
  • the vertical projection of the data switch line 102 on the plane where the active layer of the switch transistor 101 is located is the same as that of the switch transistor 101.
  • the active layer overlaps;
  • the display panel further includes a via 301 connected to the active layer, and the distance d between the data switch line 102 and the via 301 along the second direction Y is greater than 4 microns; wherein the second direction Y and the first direction X is vertical.
  • the via 301 may be a via connecting the active layer of the switching transistor 101 and its source or drain.
  • the charge on the data switch line 102 needs to have a high and low potential difference before it can be released.
  • the charge generated on the data switch line 102 in the yellow light and dry etching process and the stripping process in the via 301 manufacturing process form a high and low potential, thereby releasing ⁇ Out of charge.
  • the defect rate of the data line 111 in the display area of the display panel due to the short circuit of the data switch line 102 is reduced by more than 99.0%, which improves the display effect.
  • the data switch line 102 can also be arranged in the same layer as the gate electrode of the thin film transistor in the display area, and can be arranged according to actual conditions, which is not limited here.
  • the distance d between the data switch line 102 and the via 301 along the second direction Y may be greater than or equal to 13 microns.
  • the risk of charge release can be reduced and the data switch line 102 is short-circuited. The risk is reduced.
  • the defect rate of the data line 111 in the display area of the display panel due to the short circuit of the data switch line 102 is reduced by more than 99.3%, which improves the display effect of the display panel.
  • the distance d between the data switch line 102 and the via hole 301 along the second direction Y can be less than 16 microns. If the distance d is too large, the corresponding active layer area of the switch transistor 101 is also larger, because the switch diode 101 It is set in the non-display area NAA, which will increase the width of the non-display area NAA, which in turn leads to an increase in the frame of the display panel. However, by setting the distance d to be less than 16 microns, it is advantageous for the display panel to realize a narrow frame.
  • the test circuit further includes a test pad 401, and the data switch line 102 is electrically connected to the test pad 401.
  • the test device can be electrically connected to the test pad 401, and then a control signal can be input to the data switch line 102 to control the corresponding switch transistor 101 to be turned on or off, so as to facilitate subsequent testing of the data signal Writing into the data line 111 through the switching transistor 101.
  • the material of the data switch line 102 is Ti/Al/Ti (titanium aluminum titanium).
  • the risk of charge accumulation on the Ti/Al/Ti alloy is small. This configuration can reduce the risk of charge accumulation on the data switch line 102, reduce the risk of poor display of the display panel, and improve the display effect.
  • the risk of short-circuit of the data switch line is reduced, and the defective rate of the data line in the display area of the display panel due to the short-circuit of the data switch line is reduced by more than 99%, which greatly improves the display effect.
  • FIG. 9 is a schematic structural diagram of a display device provided by an embodiment.
  • the display device provided in this embodiment includes the display panel provided in any of the foregoing embodiments, and therefore has the same effect, and will not be repeated here.
  • the display device may be a mobile phone, a tablet, a display, a smart watch, a Moving Picture Experts Group Audio Layer 3 (MP3) player, an MP4 player, or other wearable devices.
  • MP3 Moving Picture Experts Group Audio Layer 3
  • MP4 MP4 player

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Abstract

一种显示面板和显示装置。显示面板包括位于非显示区(NAA)的测试电路，测试电路包括：多个开关晶体管(101)，每个开关晶体管(101)中，第一端与显示面板中的数据线(111)电连接，第二端设置为接收测试数据信号；沿第一方向(X)延伸的数据开关线(102)，数据开关线(102)与每个开关晶体管(101)的源漏极层同层设置，数据开关线(102)设置为控制开关晶体管(101)导通或关断。

Description

显示面板和显示装置
本申请要求在2020年05月19日提交中国专利局、申请号为202010427125.8的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，例如涉及一种显示面板和显示装置。
背景技术
随着显示技术的发展，显示面板的应用也越来越广泛，相应地对显示面板的要求也越来越高。
显示面板中通常包括测试电路，测试电路中的数据开关线存在较大的短路风险，从而造成显示面板出现显示不良的问题，严重影响显示效果。
发明内容
本公开提供一种显示面板和显示装置，以降低显示面板中数据开关线短路的风险，进而提高显示效果。
本公开提供了一种显示面板，所述显示面板包括位于非显示区的测试电路，所述测试电路包括：
多个开关晶体管，每个开关晶体管中，第一端与所述显示面板中的数据线电连接，第二端设置为接收测试数据信号；
沿第一方向延伸的数据开关线，所述数据开关线与每个开关晶体管的源漏极层同层设置，所述数据开关线设置为控制所述开关晶体管导通或关断。
本公开还提供了一种显示装置，包括如上所述的显示面板。
本公开采用的显示面板包括位于非显示区的测试电路，测试电路包括多个开关晶体管，开关晶体管的第一端与显示面板中的数据线电连接，第二端设置为接收测试数据信号；测试电路还包括沿第一方向延伸的数据开关线，数据开关线与开关晶体管的源漏极层同层设置，数据开关线设置为控制开关晶体管导通或关断。通过将数据开关线与源漏电极同层设置，而不是与显示区的薄膜晶体管的栅极同层设置，可降低数据开关线以及后续膜层在黄光及干刻工艺过程中与滚轴(ROLLOR)、台阶(STADGE)、焊盘(PAD)或引脚(PIN)接触从而产生的电荷的风险，同时还能够减少累加工艺，也即数据开关线所在膜层 后续的导电膜层较少，从而减少在数据开关线上积累的电荷，降低数据开关线因电荷释放造成栅极绝缘层击穿而导致数据开关线短路的风险，避免显示面板显示不良，保证显示面板具有较好的显示效果。
附图说明
图1为一实施例提供的一种显示面板的结构示意图；
图2为一实施例提供的一种显示面板的膜层结构示意图；
图3为一实施例提供的沿图2中A1-A2方向的膜层剖面图；
图4为一实施例提供的沿图2中A3-A4方向的膜层剖面图；
图5为一实施例提供的一种数据开关线在开关晶体管的有源层所在平面上的垂直投影与开关晶体管的有源层不交叠的显示面板的膜层结构示意图；
图6为一实施例提供的沿图5中A5-A6方向的膜层剖面图；
图7为一实施例提供的沿图5中A7-A8方向的膜层剖面图；
图8为一实施例提供的一种包括过孔的显示面板的膜层结构示意图；
图9为一实施例提供的一种显示装置的结构示意图。
具体实施方式
下面结合附图和实施例对本公开进行说明。
造成显示面板中数据开关线存在较大的短路风险的原因在于，显示面板中的数据开关线与显示面板薄膜晶体管的栅极电极同层设置，在数据开关线制作过程中，黄光和干刻工艺会造成严重的电荷积累，电荷释放时会造成栅极绝缘层击穿，从而导致数据开关线短路，造成显示面板显示不良，严重影响显示效果。
图1为一实施例提供的一种显示面板的结构示意图，参考图1，显示面板包括位于非显示区(Non-display Area，NAA)的测试电路，测试电路包括多个开关晶体管101，开关晶体管101的第一端与显示面板中的数据线111电连接，第二端设置为接收测试数据信号；测试电路还包括沿第一方向X延伸的数据开关线102，数据开关线102与开关晶体管101的源漏极层同层设置，数据开关线102设置为控制开关晶体管101导通或关断。
显示面板可包括位于显示区AA中的多条横纵交错的数据线111和扫描线112，数据线111和扫描线112交错形成多个像素区域，每个像素区域中均可包括像素驱动电路113，扫描线112和数据线111分别为像素驱动电路113提供扫 描信号和数据信号，像素驱动电路113的电路结构及工作方法在此不再赘述。显示面板在制作完成后，需要进行一系列的测试，如点屏测试(Cell Test，CT)测试等，以确定显示面板是否完好，测试电路可设置为对显示面板进行测试，多个开关晶体管101可与显示面板中的多条数据线111一一对应电连接，通过向开关晶体管101的第二端输入测试数据信号，且开关晶体管101在数据开关线102上的控制信号的作用下导通，使得测试数据信号传输至数据线111，进而传输至相应的像素驱动电路113，驱动相应的发光结构发光，以完成测试。图1中仅示例性地示出了四行四列的像素区域，以及四个开关晶体管，但本公开的像素区域以及开关晶体管的数量并不局限于此，且在图1中开关晶体管101的第二端电连接在了同一测试焊盘上，在其他一些实施方式中，不同开关晶体管101的第二端也可连接在不同的测试焊盘上，只要能够输入测试数据信号即可。
图2为一实施例提供的一种显示面板的膜层结构示意图，图3为一实施例提供的沿图2中A1-A2方向的膜层剖面图，图4为一实施例提供的沿图2中A3-A4方向的膜层剖面图，结合图1-图4，显示面板可包括基底1011、栅极绝缘层1012，有源层，栅极层，源漏电极层以及栅极层与源漏电极层之间的层间绝缘层等，在其他一些实施方式中，还可包括电容电极层以及电容电极层与源漏电极层之间的层间绝缘层。有源层可包括重掺杂区1016和位于重掺杂区1016两侧的轻掺杂区，即第一轻掺杂区1015和第二轻掺杂区1017，第一轻掺杂区1015通过第一过孔1019与第一电极1013电连接，第一电极1013可为开关晶体管101的源极，第二轻掺杂区1017通过第二过孔1010与开关晶体管101的第二电极1014电连接，第二电极1014可为开关晶体管101的漏极；在开关数据线102上的控制信号的作用下，第一轻掺杂区1015和第二轻掺杂区1017导通，从而使得第一晶体管101的第一端与第二端之间导通。开关晶体管101可以是P型晶体管，也可以是N型晶体管。在本实施例中，通过将数据开关线102与源漏电极同层设置，而不是与显示区的薄膜晶体管的栅极同层设置，可降低数据开关线102以及后续膜层在黄光及干刻工艺过程中与ROLLOR、STADGE、PAD或PIN接触从而产生的电荷的风险，同时还能够减少累加工艺，也即数据开关线102所在膜层后续的导电膜层较少，从而减少在数据开关线102上积累的电荷，降低数据开关线102因电荷释放造成栅极绝缘层1012击穿而导致数据开关线102短路的风险，避免显示面板显示不良，保证显示面板具有较好的显示效果。在本实施例中，如非说明，则开关晶体管101的有源层、栅极层、栅极绝缘层及源漏极层分别与显示面板显示区中晶体管的有源层、栅极层、栅极绝缘层及源漏极层同层。
本实施例的技术方案，采用的显示面板包括位于非显示区的测试电路，测试电路包括多个开关晶体管，开关晶体管的第一端与显示面板中的数据线电连 接，第二端设置为接收测试数据信号；测试电路还包括沿第一方向延伸的数据开关线，数据开关线与开关晶体管的源漏极层同层设置，数据开关线设置为控制开关晶体管导通或关断。通过将数据开关线与源漏电极同层设置，而不是与显示区的薄膜晶体管的栅极同层设置，可降低数据开关线以及后续膜层在黄光及干刻工艺过程中与ROLLOR、STADGE、PAD或PIN接触从而产生电荷的风险，同时还能够减少累加工艺，也即数据开关线所在膜层后续的导电膜层较少，从而减少在数据开关线上积累的电荷，降低数据开关线因电荷释放造成栅极绝缘层击穿而导致数据开关线短路的风险，避免显示面板显示不良，保证显示面板具有较好的显示效果。
当数据开关线102在有源层所在平面上的垂直投影与重掺杂区1016交叠时，数据开关线102上交叠的部分可作为开关晶体管101的栅极电极。在其它一些实施方式中，为了提高数据开关线102对重掺杂区1016的控制能力，可设置第三过孔1018，第三过孔1018一端与数据开关线102电连接，另一端与栅极绝缘层1012靠近数据开关线102的一侧相接。
可选地，图5为一实施例提供的又一种显示面板的膜层结构示意图，参考图5，数据开关线102在开关晶体管101的有源层所在平面上的垂直投影与开关晶体管101的有源层不交叠。
在本实施例中，通过设置数据开关线102在开关晶体管101的有源层所在平面上的垂直投影与开关晶体管的有源层不交叠，即使数据开关线102上的电荷释放，也不会导致数据开关线102与数据线111短路，降低显示面板显示不良的风险，保证显示面板具有较高的显示效果。
可选地，参考图5，显示面板还包括与多个开关晶体管101一一对应的多条分支线201，每条分支线201的一端与数据开关线102电连接，另一端与开关晶体管101的栅极电极202电连接。
通过设置分支线201，使得数据开关线102的控制信号能够传输至开关晶体管101的栅极电极202，进而控制开关晶体管101的第一端与第二端之间导通，使得测试数据信号写入显示面板的数据线111，进而完成测试功能。
可选地，分支线201包括第一金属走线2011和第二金属走线2012，第一金属走线2011沿第一方向X延伸并与开关晶体管101的栅极电极202电连接；第二金属走线2012与第一金属走线2011电连接，第二金属走线2012沿第二方向Y延伸并与数据开关线102电连接；其中，第一方向X与第二方向Y垂直。
开关晶体管101的栅极电极202可沿第一方向X延伸，分支线201与栅极电极202可构成“L”字型结构，在多个开关晶体管101的有源层所在的区域， 多个栅极电极202等效于分成了多个小段，相对于栅极电极202为沿第一方向X贯通的金属走线的情况，能够减少长走线电荷的累积风险。同时，第二金属走线2012沿第二方向Y延伸，其在工艺制程中为垂直于基板运送的方向，可降低工艺累积的电荷在第二金属走线2012上累积的风险，从而防止数据开关线102与数据线111发生短路的风险。本实施例中，因数据开关线102短路而造成显示面板显示区中数据线111不良的不良率降低了99.5％以上，避免了显示不良。
可选地，图6为一实施例提供的沿图5中A5-A6方向的膜层剖面图，图7为一实施例提供的沿图5中A7-A8方向的膜层剖面图，结合图5至图7，分支线201与开关晶体管101的栅极电极202同层设置。这样设置，可降低分支线201与栅极电极202的连接难度，分支线201和栅极电极202可为同一金属走线。在本实施例中，开关晶体管101的栅极电极202与显示区AA中薄膜晶体管的栅极电极位于同一层，如图7中所示，可通过设置第四过孔2013实现第二金属走线2012与数据开关线102的电连接。
可选地，图8为一实施例提供的又一种显示面板的膜层结构示意图，参考图8，数据开关线102在开关晶体管101的有源层所在平面上的垂直投影与开关晶体管101的有源层交叠；显示面板还包括与有源层连接的过孔301，数据开关线102与过孔301沿第二方向Y的距离d大于4微米；其中，第二方向Y与第一方向X垂直。
过孔301可为开关晶体管101的有源层与其源极或漏极连接的过孔。数据开关线102上的电荷需要有高低电位差才能够释放，黄光及干刻工艺制程中在数据开关线102上产生的电荷与该过孔301制作工艺中的剥离工艺形成高低电位，从而释放出电荷。通过设置距离d大于4微米，降低电荷释放的风险，进而降低数据开关线102与数据线111短路的风险，降低显示面板显示不良的风险。本实施例中，因数据开关线102短路而造成显示面板显示区中数据线111不良的不良率降低了99.0％以上，提升了显示效果。在本实施例中，数据开关线102也可与显示区中薄膜晶体管的栅极电极同层设置，可根据实际情况进行设置，在此不做限定。
可选地，数据开关线102与过孔301沿第二方向Y的距离d可以大于或等于13微米，通过将距离d设置在此范围内，能够降低电荷释放的风险，使得数据开关线102短路的风险降低。本实施例中，因数据开关线102短路而造成显示面板显示区中数据线111不良的不良率降低了99.3％以上，提高了显示面板的显示效果。
数据开关线102与过孔301沿第二方向Y的距离d可以小于16微米，若所述的距离d过大，相应的开关晶体管101对应地有源层的面积也较大，由于开 关二极管101设置于非显示区NAA，这样将会增加非显示区NAA的宽度，进而导致显示面板的边框增加。而通过设置所述的距离d小于16微米，有利于显示面板实现窄边框。
可选地，参考图1，测试电路还包括测试焊盘401，数据开关线102与测试焊盘401电连接。
在显示面板需要进行测试时，可将测试设备与测试焊盘401电连接，进而向数据开关线102上输入控制信号，以控制相应的开关晶体管101导通或关断，方便后续将测试数据信号通过开关晶体管101写入到数据线111中。
可选地，数据开关线102的材料为Ti/Al/Ti(钛铝钛)。Ti/Al/Ti合金上电荷积累的风险较小，这样设置，可降低数据开关线102上电荷积累的风险，降低显示面板显示不良的风险，提升显示效果。
采用本公开的技术方案，数据开关线短路的风险降低，因数据开关线短路而造成显示面板显示区中数据线不良的不良率降低了99％以上，极大地提升了显示效果。
图9为一实施例提供的一种显示装置的结构示意图，参考图9，本实施例提供的显示装置包括上述任意实施例提供的显示面板，因此也具有相同的效果，在此不再赘述。显示装置可为手机、平板、显示器、智能手表、动态图像专家组音频层3(Moving Picture Experts Group Audio Layer 3，MP3)播放器、MP4播放器或者其他可穿戴设备等。

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  1. 一种显示面板，包括位于非显示区的测试电路，所述测试电路包括：
    多个开关晶体管，每个开关晶体管的第一端与所述显示面板中的数据线电连接，第二端设置为接收测试数据信号；
    沿第一方向延伸的数据开关线，所述数据开关线与每个所述开关晶体管的源漏极层同层设置，所述数据开关线设置为控制所述开关晶体管导通或关断。
  2. 根据权利要求1所述的显示面板，还包括有源层，所述有源层包括重掺杂区和位于所述重掺杂区两侧的第一轻掺杂区和第二轻掺杂区，在所述开关数据线的控制信号的作用下，所述第一轻掺杂区和所述第二轻掺杂区导通。
  3. 根据权利要求1所述的显示面板，其中，所述数据开关线在所述开关晶体管的有源层所在平面上的垂直投影与所述开关晶体管的有源层交叠，所述数据开关线交叠的部分为所述开关晶体管的栅极电极。
  4. 根据权利要求1所述的显示面板，其中，所述数据开关线在所述开关晶体管的有源层所在平面上的垂直投影与所述开关晶体管的有源层不交叠。
  5. 根据权利要求4所述的显示面板，还包括与所述多个开关晶体管一一对应的多条分支线；每条分支线的一端与所述数据开关线电连接，另一端与对应的开关晶体管的栅极电极电连接。
  6. 根据权利要求5所述的显示面板，其中，所述分支线包括电连接的第一金属走线和第二金属走线，所述第一金属走线沿所述第一方向延伸并与所述开关晶体管的栅极电极电连接；
    所述第二金属走线沿第二方向延伸并与所述数据开关线电连接；其中，所述第一方向与所述第二方向垂直。
  7. 根据权利要求6所述的显示面板，其中，所述分支线与所述开关晶体管的栅极电极同层设置。
  8. 根据权利要求3所述的显示面板，还包括与所述有源层连接的过孔，所述数据开关线与所述过孔沿第二方向的距离大于4微米；其中，所述第二方向与所述第一方向垂直。
  9. 根据权利要求8所述的显示面板，其中，所述数据开关线与所述过孔沿所述第二方向的距离小于16微米。
  10. 根据权利要求1所述的显示面板，其中，所述测试电路还包括测试焊盘，所述数据开关线与所述测试焊盘电连接。
  11. 根据权利要求1所述的显示面板，其中，所述数据开关线的材料为钛铝钛Ti/Al/Ti。
  12. 根据权利要求1所述的显示面板，其中，所述多个开关晶体管的第二端与同一测试焊盘电连接。
  13. 根据权利要求1所述的显示面板，其中，所述多个开关晶体管的第二端与不同测试焊盘电连接。
  14. 根据权利要求6所述的显示面板，其中，所述开关晶体管的栅极电极沿所述第一方向延伸，所述分支线与所述栅极电极构成“L”字型结构。
  15. 根据权利要求8所述的显示面板，其中，所述过孔为所述开关晶体管中，有源层与源极或漏极连接的过孔。
  16. 根据权利要求8所述的显示面板，还包括第三过孔，所述第三过孔的一端与所述数据开关线电连接，所述第三过孔的另一端与所述开关晶体管的栅极绝缘层靠近所述数据开关线的一侧连接。
  17. 根据权利要求8所述的显示面板，其中，所述数据开关线与所述过孔沿所述第二方向的距离大于13微米。
  18. 一种显示装置，包括权利要求1-17任一项所述的显示面板。
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