WO2021227372A1 - 一种提升芯片硬宏供电能力的方法 - Google Patents

一种提升芯片硬宏供电能力的方法 Download PDF

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WO2021227372A1
WO2021227372A1 PCT/CN2020/123585 CN2020123585W WO2021227372A1 WO 2021227372 A1 WO2021227372 A1 WO 2021227372A1 CN 2020123585 W CN2020123585 W CN 2020123585W WO 2021227372 A1 WO2021227372 A1 WO 2021227372A1
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power supply
metal
wiring
hard macro
chip
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PCT/CN2020/123585
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English (en)
French (fr)
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赵少峰
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东科半导体(安徽)股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions

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  • the invention relates to the field of microelectronics technology, and in particular to a method for improving the power supply capability of a chip's hard macro.
  • the macro unit In the digital back-end integrated circuit (IC) design, the macro unit (Macro) is the most common unit in the design. Macro is a broad concept, usually we divide it into hard macro (Hard Macro) and soft macro (Soft Macro). Hard macros refer to specific functional modules, such as various IP cores including memory, phase-locked loop PLL, and phase-locked loop DLL, which are used in application-specific integrated circuits (ASIC) or field programmable logic arrays (FPGA) The pre-designed circuit function module, the logic of the hard macro has been integrated in itself, and it can be called according to the process library.
  • ASIC application-specific integrated circuits
  • FPGA field programmable logic arrays
  • the chip power network (power mesh) of the chip itself is usually used to supply power to the hard macro.
  • the purpose of the present invention is to provide a method for improving the power supply capability of the chip's hard macro in view of the defects of the prior art. It is mainly aimed at the sparse design of the hard macro's own power supply pin PG PIN.
  • the wiring structure of the metal wire is optimized, and a dedicated hard macro power supply network is built inside the chip above the hard macro to improve the power supply capability of the hard macro of the chip.
  • an embodiment of the present invention provides a method for improving the hard macro power supply capability of a chip, including:
  • the metal layer where the power supply pins are located is divided into units according to the spacing of the traces of the metal layer where the power supply pins are located, to obtain a plurality of repeated units to be encrypted;
  • Each unit to be encrypted has at least one wiring track covered by metal and at least two empty wiring tracks not covered by metal;
  • the metal wire of the encrypted wiring and the chip power supply network are connected through a stack via.
  • the preset coverage rate is not greater than 30%.
  • the method further includes:
  • the topological structure of the chip power supply network of the chip is determined based on the design requirements of the chip and the wiring resource constraints; the chip has multiple metal layers, and the metal lines of adjacent metal layers are perpendicular to each other; the topological structure of the chip power supply network includes: The number of metal layers, the number of general wiring layers, the layer number of the metal layer where the general wiring layer is located, the physical position, direction, line width and spacing of the metal lines on each general wiring layer;
  • a stack via is provided, and the metal wires of different layers are connected through the stack via.
  • performing the metal wire wiring of the hard macro dedicated power supply network specifically includes:
  • the dedicated wiring layer of the hard macro dedicated power supply network is divided into multiple wiring units according to the spacing of the metal wires in the topology of the chip power supply network and the spacing of the wiring tracks;
  • Each wiring unit has at least two wiring tracks;
  • At least one wiring track is selected in the wiring unit for metal wire wiring; the metal wire wiring positions in the multiple wiring units are the same .
  • the metal wire directions of adjacent dedicated wiring layers in the hard macro dedicated power supply network are perpendicular to each other, and the metal wire directions of the dedicated wiring layers in the hard macro dedicated power supply network closest to the metal layer where the power supply pins are located are the same.
  • the metal wire directions of the metal layer where the power supply pins are located are perpendicular to each other.
  • the number of metal wire wiring in different dedicated wiring layers is the same or different.
  • the positions of the metal wire wiring of different dedicated wiring layers are the same or different.
  • the present invention provides a method for improving the power supply capability of the chip's hard macro, mainly aiming at the sparse design of the hard macro's own power supply pin PG PIN, by optimizing the metal wire wiring structure of the PG PIN layer inside the hard macro, and In the hard macro, the metal wire of the hard macro dedicated power supply network is wired in one or more metal layers above the metal layer where the PG PIN is located, and then the stack via stack is used to achieve the power supply between the PG PIN and the power ground pin and the chip power supply The connection between the networks enhances the power supply driving capability of the chip's hard macro and effectively improves the power supply capability of the chip's hard macro.
  • Figure 1 is a schematic diagram of a topological structure of a chip power supply network
  • FIG. 2 is a flowchart of a method for improving the hard macro power supply capability of a chip by encrypting the metal wiring of the PG PIN according to an embodiment of the present invention
  • FIG. 3 is one of the process schematic diagrams of the method for improving the power supply capability of the chip's hard macro provided by the embodiment of the present invention
  • FIG. 4 is a flowchart of a method for improving the power supply capability of a chip's hard macro by establishing a dedicated hard macro power supply network according to an embodiment of the present invention
  • FIG. 5 is a second schematic diagram of the process of a method for improving the power supply capability of a chip's hard macro provided by an embodiment of the present invention.
  • the feature size of the chip is continuously reduced, and the number of available metal layers of the chip is also different under different processes.
  • the number of available metal layers is usually 4, 5, and 6, and in the 0.13um process, generally 4-8 layers are optional, and in the 65nm process, the available metal layers are up to 11 floors.
  • the chip power supply network will occupy several metal layers on the top of the chip.
  • the topological structure of the chip power supply network is a complex metal network.
  • Figure 1 shows an example of a chip power network. It can be seen that there are 11 layers of metal from the top package contact point (C4 BUMP) to the bottom transistor circuit (Logic). There is a through hole (Via) connection between every two layers of metal lines. Of course, the connection relationship is determined according to the chip wiring design requirements.
  • the topological structure of the chip power supply network has multiple metal layers, and the metal lines of adjacent metal layers are perpendicular to each other; the topological structure of the chip power supply network includes: the number of metal layers, the number of common wiring layers, and the metal layer where the common wiring layer is located. The layer number, the physical position, direction, line width and spacing of the metal lines on each general wiring layer.
  • the metal layer is 11 layers, and the number of general wiring layers is 3 layers, occupying 9-11 layers of metal layers.
  • M9, M10, and M11 are the layer numbers of the metal layers where the general wiring layer is located.
  • the general wiring layer is used to provide a global power supply for the entire chip.
  • Different hard macros have their own separate LEF files, that is, the layout and routing files are based on the file format file of the cell geometry information library used, which will define the shape of the hard macro and the location of the pins and other information, including the power supply pin location information.
  • the logic of the hard macro has been integrated within itself, and it can be called according to the process library.
  • the hard macro itself occupies one or several metal layers. For example, a hard macro occupies the highest metal layer M4, then the M1-M3 below M4 in the hard macro position are also occupied by the hard macro. Among these 4 layers of metal, the lead-out layer of the power supply pins will be specified according to the LEF file, such as M4.
  • the pins drawn from M4 are connected to the metal of one or more general wiring layers of M9, M10, and M11 through through holes (usually using laminated holes).
  • the embodiment of the present invention provides a method for improving the power supply capability of the hard macro of a chip, which is mainly aimed at the situation that the design of the power supply pin (PG PIN) of the hard macro is relatively sparse.
  • FIG. 2 The main steps of the method for improving the power supply capability of the chip's hard macro provided by the embodiment of the present invention are shown in FIG. 2 and include the following steps:
  • Step 110 Determine the metal line coverage of the track on the metal layer where the power supply pin (PG PIN) in the hard macro of the chip is located;
  • this solution mainly focuses on the sparse design of the hard macro's own power supply pin PG PIN, which is likely to cause the hard macro's insufficient power supply capability to improve the power supply capacity, so it is necessary to confirm the hard macro's own design first.
  • hard macros are directly called according to the process library, and more than one kind of hard macros are called. Therefore, the method of the present invention is executed separately for each hard macro to optimize the power supply capability. Different hard macros in the same chip It may be necessary to improve the optimized power supply capacity or not need to improve the optimized power supply capacity.
  • track refers to the routing track, which can constrain the routing direction of the routing device.
  • the signal line must usually go on the track.
  • the spacing of the track is usually greater than the minimum spacing of the metal lines allowed in the design rules.
  • the minimum spacing of the metal lines is determined based on the physical design check (Design Rule Checking, DRC) rules.
  • DRC Design Rule Checking
  • Step 120 When the metal wire coverage is less than the preset coverage, the metal layer where the power supply pins are located is divided into units according to the spacing of the traces of the metal layer where the power supply pins are located, to obtain multiple repeated units to be encrypted;
  • the preset coverage rate is not more than 30%.
  • the proportion of the track covered by the PG PIN layer is less than 30%, the PG PIN is relatively sparse, and the power supply capacity of the hard macro is relatively weak. In this case, the power supply capacity needs to be carried out according to this method. The promotion.
  • the units to be encrypted are divided by an integer multiple of the track of the PG PIN layer as the width, and each divided unit to be encrypted has at least one trace covered by metal and at least two empty traces not covered by metal. ;
  • Step 130 Under the condition of not exceeding the first preset laying ratio, select at least one vacant routing track in the units to be encrypted for metal wire encryption wiring, and the positions of the metal wires of the encrypted wiring in each unit to be encrypted are the same;
  • the first preset laying ratio is preferably 80%.
  • Step 140 Connect the metal wire of the encrypted wiring and the chip power supply network through a stack via.
  • Figure 3 shows a specific example, showing the process of performing the above method on the M4 layer where the PG PIN is located.
  • the dashed line is the track
  • the dashed box is a cell to be encrypted obtained after the cell is divided
  • the slashed part of the solid box is the metal wire of the PGPIN itself.
  • the present invention optimizes the metal wire wiring structure of the PG PIN layer within the hard macro, enhances the power supply driving capability of the chip hard macro, and effectively improves the power supply capability of the chip hard macro.
  • the hard macro power supply capability of the chip is further improved by establishing a hard macro dedicated power supply network.
  • FIG. 4 is a flowchart of a method for improving the power supply capability of a chip's hard macro by establishing a dedicated hard macro power supply network provided by an embodiment of the present invention. As shown in FIG. 3, the method includes the following steps:
  • Step 210 Determine the topological structure of the chip power supply network of the chip based on the design requirements of the chip and the wiring resource constraints;
  • the design requirements of the chip will be determined, and these requirements will be converted into various important parameter indicators of the chip, and the design architecture of the chip will be formed based on the design requirements.
  • register transfer level circuit (Register Transfer Level, RTL) code design and verification, the selection of the process library is determined, and then synthesis and timing analysis are performed to generate a circuit netlist based on the adopted process for automatic placement and routing.
  • the topological structure of the chip power supply network of the chip can be determined according to the design requirements of the chip and the wiring resource constraints. For example, as shown in Figure 1 above.
  • Step 220 Determine the layer number of the metal layer where the power supply pin (PG PIN) in the hard macro of the chip is located;
  • the lead-out layer of the power supply pin can be known.
  • Step 230 Perform metal wire wiring of the hard macro dedicated power supply network in one or more metal layers other than the general wiring layer above the metal layer where the power supply pins are located in the hard macro;
  • this step can be specifically executed according to the following process.
  • Step 231 Select one or more metal layers other than the general wiring layer above the metal layer where the power supply pin (PGPIN) in the hard macro is used as the dedicated wiring layer of the hard macro dedicated power supply network;
  • Step 232 Determine the track of each dedicated wiring layer
  • Step 233 For each dedicated wiring layer, the dedicated wiring layer of the hard macro dedicated power supply network is divided into multiple wiring units according to the spacing of the metal lines and the spacing of the traces in the topological structure of the chip power supply network;
  • each wiring unit has at least two wiring tracks.
  • Step 234 For each dedicated wiring layer, at least one wiring track is selected in the wiring unit for metal wire wiring under the condition of not exceeding a preset laying ratio;
  • the wiring positions of the metal wires in the multiple wiring units are the same.
  • the number of metal wire wirings of different dedicated wiring layers is the same or different.
  • the metal wire wiring positions of different dedicated wiring layers are the same or different.
  • the metal wire directions of adjacent dedicated wiring layers in the hard macro dedicated power supply network are perpendicular to each other, and the metal wire direction of the dedicated wiring layer closest to the metal layer where the power supply pin (PG PIN) is located in the hard macro dedicated power supply network and the power supply pin (PG PIN)
  • the metal lines of the metal layer are perpendicular to each other. The selection of the dedicated wiring layer from the metal layer is performed in accordance with the above constraints.
  • Figure 5 shows a specific example, which shows a schematic diagram of a specific method for improving the reliability of chip hard macro power supply to illustrate the above process intuitively. This example is only to illustrate the above process more clearly. For example.
  • the metal wires from M1 to M11 are arranged in the longitudinal direction, the transverse direction, the longitudinal direction, and the transverse direction in sequence.
  • the metal layers M5 and M6 are selected for the metal wire wiring of the hard macro dedicated power supply network.
  • the traces are shown as dashed lines in the figure, and each wiring unit has three traces.
  • the preset laying ratio is no more than 80%, and two of the routing tracks are selected in the design for metal wire routing.
  • the wiring of the metal wires on the M5 and M6 after wiring is shown in the rectangular frame on the two layers in FIG. 5.
  • M7 and M8 have no metal wires at the corresponding positions of the hard macros.
  • the dotted frame marks here only illustrate the locations of the two layers, and do not mean that there is metal wire wiring.
  • Step 240 According to the power supply logic of the hard macro, between the metal wires of two adjacent layers in the hard macro dedicated power supply network, between the metal wires of the hard macro dedicated power supply network and the power supply pins, and the metal of the hard macro dedicated power supply network Between the wire and the chip power supply network, a stack via is provided, and the metal wires of different layers are connected through the stack via.
  • the metal line wiring of the hard macro dedicated power supply network is performed in one or more metal layers above the metal layer where the PG PIN is located in the hard macro, and then the stack via is used to realize the connection between the PG PIN and the power ground pin PG PIN.
  • the connection between the chip power supply network can further enhance the power supply driving capability of the chip hard macro and improve the power supply capability of the chip hard macro.

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Abstract

一种提升芯片硬宏供电能力的方法，所述方法包括：确定芯片的硬宏hard macro中的供电引脚PG PIN所在金属层上，走线轨道track的金属线覆盖率（110）；当所述金属线覆盖率小于预设覆盖率时，根据所述供电引脚所在金属层的走线轨道的间距对供电引脚所在金属层进行单元划分，得到多个重复的待加密单元（120）；每个待加密单元具有至少一条被金属覆盖的走线轨道和至少两条未被被金属覆盖的空置走线轨道；在不超过第一预设铺设比例条件下，在所述待加密单元中选择至少一条空置走线轨道进行金属线加密布线，每个所述待加密单元中加密布线的金属线位置相同（130）；在所述加密布线的金属线与芯片电源网络之间通过叠层孔stack via进行连通（140）。

Description

一种提升芯片硬宏供电能力的方法
本申请要求于2020年05月09日提交中国专利局、申请号为202010387501.5，发明名称为“一种提升芯片硬宏供电能力的方法”的中国专利申请的优先权。
技术领域
本发明涉及微电子技术领域，尤其涉及一种提升芯片硬宏供电能力的方法。
背景技术
数字后端集成电路(IC)设计中，宏单元(Macro)是设计中最常见的单元。Macro是一个宽泛的概念，通常我们把它分为硬宏(Hard Macro)和软宏(Soft Macro)。硬宏是指特定的功能模块，例如包括存储器(Memory)、锁相环PLL、锁相环DLL等各种IP核，即用于专用集成电路(ASIC)或现场可编程逻辑阵列(FPGA)中的预先设计好的电路功能模块，硬宏的逻辑在其本身内部已经集成好，根据工艺库进行调用即可。
在常规的数字电路设计中，通常是采用芯片本身的芯片电源网络(power mesh)对硬宏进行供电，芯片电源网络平铺整个芯片，硬宏上方位置的芯片电源网络通过叠层孔(stack via)与硬宏的供电引脚PG PIN相连通。
但有些硬宏本身供电引脚PG PIN的设计比较稀疏，导致硬宏的供电能力较弱，在苛刻条件下，硬宏的供电无法满足需求，可能会因此影响整个芯片性能。
发明内容
本发明的目的是针对现有技术的缺陷，提供一种提升芯片硬宏供电能力的方法，主要针对硬宏本身供电引脚PG PIN的设计比较稀疏的情况，通过在硬宏内部对PG PIN层的金属线布线结构进行优化，以及在硬宏上方的芯片内部构建硬宏专用电源网络，来提升芯片硬宏供电能力。
有鉴于此，本发明实施例提供了一种提升芯片硬宏供电能力的方法，包括：
确定芯片的硬宏hard macro中的供电引脚PG PIN所在金属层上，走线轨道track的金属线覆盖率；
当所述金属线覆盖率小于预设覆盖率时，根据所述供电引脚所在金属层的走线轨道的间距对供电引脚所在金属层进行单元划分，得到多个重复的待加密单元；每个待加密单元具有至少一条被金属覆盖的走线轨道和至少两条未被被金属覆盖的空置走线轨道；
在不超过第一预设铺设比例条件下，在所述待加密单元中选择至少一条空置走线轨道进行金属线加密布线，每个所述待加密单元中加密布线的金属线位置相同；
在所述加密布线的金属线与芯片电源网络之间通过叠层孔stack via进行连通。
优选的，所述预设覆盖率不大于30％。
优选的，所述方法还包括：
基于芯片的设计需求和走线资源约束确定芯片的芯片电源网络的拓扑结构；所述芯片具有多层金属层，相邻金属层的金属线方向相互垂直；所述芯片电源网络的拓扑结构包括：金属层的层数、通用布线层的层数、通用布线层所在金属层的层号、每一层通用布线层上金属线的物理位置、方向、线宽和间距；
确定芯片的硬宏中的供电引脚所在金属层的层号；
在所述硬宏中供电引脚所在金属层上方，除通用布线层以外的一层或多 层金属层中，进行硬宏专用电源网络的金属线布线；
根据硬宏的供电逻辑，在所述硬宏专用电源网络中相邻两层的金属线之间、所述硬宏专用电源网络的金属线与所述供电引脚之间、以及所述硬宏专用电源网络的金属线与所述芯片电源网络之间，设置叠层孔stack via，并通过叠层孔进行不同层金属线之间的连通。
优选的，所述在所述硬宏中供电引脚所在金属层上方，除通用布线层以外的一层或多层金属层中，进行硬宏专用电源网络的金属线布线具体包括：
在所述硬宏中所在金属层上方选定通用布线层以外的一层或多层金属层用于硬宏专用电源网络的专用布线层；
确定每层专用布线层的走线轨道；所述走线轨道等间距排布；
对于每一层专用布线层，根据所述芯片电源网络的拓扑结构中金属线的间距和所述走线轨道的间距将所述硬宏专用电源网络的专用布线层划分为多个布线单元；每个布线单元具有至少两条走线轨道；
对于每一层专用布线层，在不超过预设的铺设比例条件下，在所述布线单元中选定至少一条走线轨道进行金属线布线；所述多个布线单元中的金属线布线位置相同。
优选的，所述硬宏专用电源网络中相邻的专用布线层的金属线方向相互垂直，并且所述硬宏专用电源网络中最接近供电引脚所在金属层的专用布线层的金属线方向与所述供电引脚所在金属层的金属线方向相互垂直。
优选的，不同专用布线层的金属线布线的数量相同或不同。
优选的，不同专用布线层的金属线布线的位置相同或不同。
优选的，相邻的专用布线层之间具有未进行金属线布线的金属层。
本发明提供了一种提升芯片硬宏供电能力的方法，主要针对硬宏本身供电引脚PG PIN的设计比较稀疏的情况，通过在硬宏内部对PG PIN层的金属线布线结构进行优化，并且在硬宏中PG PIN所在金属层上方的一层或多层金属层中进行硬宏专用电源网络的金属线布线，再通过叠层孔stack via 实现与电源地引脚PG PIN之间以及芯片电源网络之间的连接，增强芯片硬宏的供电驱动能力，有效提升芯片硬宏供电能力。
附图说明
下面通过附图和实施例，对本发明实施例的技术方案做进一步详细描述。
图1为一种芯片电源网络的拓扑结构示意图；
图2为本发明实施例提供的通过加密PG PIN的金属布线提升芯片硬宏供电能力的方法流程图；
图3为本发明实施例提供的提升芯片硬宏供电能力的方法过程示意图之一；
图4为本发明实施例提供的通过建立硬宏专用电源网络提升芯片硬宏供电能力的方法流程图；
图5为本发明实施例提供的提升芯片硬宏供电能力的方法过程示意图之二。
具体实施方式
在集成电路设计中，随着芯片面积不断减小和芯片设计在时序、逻辑复杂性要求的不断提升，芯片的特征尺寸不断减小，采用不同的工艺下，芯片的可用金属层数也有所不同，例如典型的，在0.18um工艺下，可用金属层数通常为4、5、6层，0.13um工艺下，一般为4-8层可选，而到了65nm工艺，可供选择的金属层达到了11层。通常情况下，芯片电源网络的会占据芯片顶层的几层金属层。
芯片电源网络的拓扑结构是个复杂的金属网络。图1给出了一个芯片电源网络的例子。可以看到，从最上面的封装接触点(C4 BUMP)到最下面的晶体管电路(Logic)之间共有11层金属。每两层金属线中间有通孔(Via)连接，当然其连接关系是根据芯片布线设计需求而定。
芯片电源网络的拓扑结构具有多层金属层，相邻金属层的金属线方向相互垂直；芯片电源网络的拓扑结构包括：金属层的层数、通用布线层的层数、通用布线层所在金属层的层号、每一层通用布线层上金属线的物理位置、方向、线宽和间距。
例如在图1中，金属层为11层，通用布线层的层数为3层，占据9-11层的金属层，M9、M10、M11就是通用布线层所在金属层的层号。通用布线层用于对整个芯片提供全局电源供应。
不同硬宏有其自己单独的LEF文件，也就是布局布线根据使用的单元几何信息库的文件格式文件，里面会定义硬宏的形状以及管脚的位置等等信息，其中包括了供电引脚的位置信息。
在芯片中，硬宏的逻辑在其本身内部已经集成好，根据工艺库进行调用即可。硬宏内部本身占据一层或几层金属层，例如一个硬宏内部最高占用到了金属层M4，那么在硬宏位置上M4以下的M1-M3的也被硬宏占据。在这4层金属中，会根据LEF文件规定其中供电引脚的引出层，例如M4。M4引出的引脚，通过通孔(通常选用叠层孔)与M9、M10、M11中的一层或几层的通用布线层的金属连通。
本发明实施例提供了一种提升芯片硬宏供电能力的方法，主要针对硬宏本身供电引脚(PG PIN)的设计比较稀疏的情况，在不增加芯片面积的情况下，通过在硬宏内部对PG PIN层的金属线布线结构进行优化，以及充分利用硬宏上方空置的一层或几层金属层进行硬宏专用电源网络的构建来提升硬宏的供电能力。
本发明实施例提供的提升芯片硬宏供电能力的方法，其主要步骤流程如图2所示，包括如下步骤：
步骤110，确定芯片的硬宏(hard macro)中的供电引脚(PG PIN)所在金属层上，走线轨道(track)的金属线覆盖率；
具体的，因为本方案主要针对硬宏本身供电引脚PG PIN的设计比较稀 疏，容易造成硬宏供电能力不足的情况进行供电能力提升改进，因此需要先确认硬宏本身的设计。对于芯片设计来说，硬宏直接根据工艺库进行调用，所调用的硬宏不止一种，因此对每个硬宏单独执行本发明的方法，进行供电能力的优化，同一芯片中不同的硬宏可能需要提升优化供电能力或不需要提升优化供电能力。
在数字后端芯片设计中，track是指走线轨道，可以约束走线器的走线方向。信号线通常必须走在track上。走线轨道(track)的间距通常会大于设计规则中允许的金属线最小间距，金属线最小间距是基于物理设计检查(Design Rule Checking，DRC)规则决定的，走线轨道(track)的间距具体结合所选用的工艺确定。
步骤120，当金属线覆盖率小于预设覆盖率时，根据供电引脚所在金属层的走线轨道的间距对供电引脚所在金属层进行单元划分，得到多个重复的待加密单元；
优选的，预设覆盖率不大于30％。我们认为在PG PIN这一层金属线覆盖track的比例不大于30％的情况下，PG PIN较为稀疏，硬宏的供电能力是比较弱的，在这种情况下，需要按本方法进行供电能力的提升。
待加密单元以PG PIN这一层track的整数倍为宽度进行划分，划分后的每个待加密单元具有至少一条被金属覆盖的走线轨道和至少两条未被被金属覆盖的空置走线轨道；
步骤130，在不超过第一预设铺设比例条件下，在待加密单元中选择至少一条空置走线轨道进行金属线加密布线，每个待加密单元中加密布线的金属线位置相同；
优选的，第一预设铺设比例优选为80％。
步骤140，在加密布线的金属线与芯片电源网络之间通过叠层孔(stack via)进行连通。
图3给出了一个具体的例子，示出了对PG PIN所在M4层执行上述方法 的过程。在图3的左侧图中，虚直线为track，虚线框内为单元划分后得到的一个待加密单元，实线框打斜线的部分为PG PIN本身的金属线。经过执行上述方法后，如图3的右侧图中所示，在每个待加密单元中空置的三条track上，占用其中两条用作加密布线的金属线。最后通过叠层孔与芯片电源网络进行连通，在图3上没有体现。
本发明通过在硬宏内部对PG PIN层的金属线布线结构进行优化，增强芯片硬宏的供电驱动能力，有效提升芯片硬宏供电能力。
在上述方法基础上，还可以进行进一步的优化，在执行完上述步骤后，再进一步的通过建立硬宏专用电源网络提升芯片硬宏供电能力。
图4为本发明实施例提供的通过建立硬宏专用电源网络提升芯片硬宏供电能力的方法流程图，如图3所示，包括如下步骤：
步骤210，基于芯片的设计需求和走线资源约束确定芯片的芯片电源网络的拓扑结构；
具体的，在芯片设计前，芯片的设计需求就会被确定，这些需求会被转化为芯片的各项重要参数指标，并基于设计需求形成芯片的设计架构。通过寄存器转换级电路(Register Transfer Level，RTL)代码设计和验证，工艺库的选择确定，再进行综合和时序分析，生成基于所采用的工艺的电路网表，用于自动布局布线。
根据不同的工艺库，具有不同的走线资源约束，例如确定不同区域、不同层金属走线的线宽、间距、走线形式等。
因此根据芯片的设计需求和走线资源约束能够确定出芯片的芯片电源网络的拓扑结构。例如前述图1所示。
步骤220，确定芯片的硬宏(hard macro)中的供电引脚(PG PIN)所在金属层的层号；
根据硬宏的LEF文件可知供电引脚的引出层。
步骤230，在硬宏中供电引脚所在金属层上方，除通用布线层以外的 一层或多层金属层中，进行硬宏专用电源网络的金属线布线；
具体的，本步骤可以具体按照如下流程执行。
步骤231，在硬宏中供电引脚(PG PIN)所在金属层上方选定通用布线层以外的一层或多层金属层用于硬宏专用电源网络的专用布线层；
步骤232，确定每层专用布线层的走线轨道(track)；
步骤233，对于每一层专用布线层，根据芯片电源网络的拓扑结构中金属线的间距和走线轨道(track)的间距将硬宏专用电源网络的专用布线层划分为多个布线单元；
其中，每个布线单元具有至少两条走线轨道。
步骤234，对于每一层专用布线层，在不超过预设的铺设比例条件下，在布线单元中选定至少一条走线轨道进行金属线布线；
其中，多个布线单元中的金属线布线位置相同。
不同专用布线层的金属线布线的数量相同或不同。
不同专用布线层的金属线布线的位置相同或不同。
相邻的专用布线层之间可以具有未进行金属线布线的金属层。
硬宏专用电源网络中相邻的专用布线层的金属线方向相互垂直，并且硬宏专用电源网络中最接近供电引脚(PG PIN)所在金属层的专用布线层的金属线方向与供电引脚(PG PIN)所在金属层的金属线方向相互垂直。从金属层中进行专用布线层的选定按照上述约束执行。
图5给出了一个具体的例子，展示了一个具体的提升芯片硬宏供电可靠性的方法过程示意图，用以对以上过程进行直观的说明，此例仅是为了更清楚的说明上述过程进行的举例。
在本例中，从M1到M11的金属线依次沿纵向、横向、纵向、横向……方向排布。选定金属层M5、M6用于硬宏专用电源网络的金属线布线。走线轨道(track)如图中虚直线所示，每个布线单元具有三条走线轨道。预设的铺设比例为不大于80％,在设计中选择其中两条走线轨道用于金属线布 线。布线后的M5、M6上的金属线布线如图5中在这两层上的长方形框体所示。M7、M8在硬宏对应位置上没有金属线，在这里用虚线框标记仅为说明这两层的位置所在，并不表示有金属线布线。
步骤240，根据硬宏的供电逻辑，在硬宏专用电源网络中相邻两层的金属线之间、硬宏专用电源网络的金属线与供电引脚之间、以及硬宏专用电源网络的金属线与芯片电源网络之间，设置叠层孔(stack via)，并通过叠层孔(stack via)进行不同层金属线之间的连通。
本发明通过在硬宏中PG PIN所在金属层上方的一层或多层金属层中进行硬宏专用电源网络的金属线布线，再通过叠层孔stack via实现与电源地引脚PG PIN之间以及芯片电源网络之间的连接，能够进一步的增强芯片硬宏的供电驱动能力，提升芯片硬宏供电能力。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (8)

  1. 一种提升芯片硬宏供电能力的方法，其特征在于，所述方法包括：
    确定芯片的硬宏hard macro中的供电引脚PG PIN所在金属层上，走线轨道track的金属线覆盖率；
    当所述金属线覆盖率小于预设覆盖率时，根据所述供电引脚所在金属层的走线轨道的间距对供电引脚所在金属层进行单元划分，得到多个重复的待加密单元；每个待加密单元具有至少一条被金属覆盖的走线轨道和至少两条未被被金属覆盖的空置走线轨道；
    在不超过第一预设铺设比例条件下，在所述待加密单元中选择至少一条空置走线轨道进行金属线加密布线，每个所述待加密单元中加密布线的金属线位置相同；
    在所述加密布线的金属线与芯片电源网络之间通过叠层孔stack via进行连通。
  2. 根据权利要求1所述的提升芯片硬宏供电能力的方法，其特征在于，所述预设覆盖率不大于30％。
  3. 根据权利要求1所述的提升芯片硬宏供电能力的方法，其特征在于，所述方法还包括：
    基于芯片的设计需求和走线资源约束确定芯片的芯片电源网络的拓扑结构；所述芯片具有多层金属层，相邻金属层的金属线方向相互垂直；所述芯片电源网络的拓扑结构包括：金属层的层数、通用布线层的层数、通用布线层所在金属层的层号、每一层通用布线层上金属线的物理位置、方向、线宽和间距；
    确定芯片的硬宏中的供电引脚所在金属层的层号；
    在所述硬宏中供电引脚所在金属层上方，除通用布线层以外的一层或多层金属层中，进行硬宏专用电源网络的金属线布线；
    根据硬宏的供电逻辑，在所述硬宏专用电源网络中相邻两层的金属线之 间、所述硬宏专用电源网络的金属线与所述供电引脚之间、以及所述硬宏专用电源网络的金属线与所述芯片电源网络之间，设置叠层孔stack via，并通过叠层孔进行不同层金属线之间的连通。
  4. 根据权利要求3所述的提升芯片硬宏供电能力的方法，其特征在于，所述在所述硬宏中供电引脚所在金属层上方，除通用布线层以外的一层或多层金属层中，进行硬宏专用电源网络的金属线布线具体包括：
    在所述硬宏中所在金属层上方选定通用布线层以外的一层或多层金属层用于硬宏专用电源网络的专用布线层；
    确定每层专用布线层的走线轨道；所述走线轨道等间距排布；
    对于每一层专用布线层，根据所述芯片电源网络的拓扑结构中金属线的间距和所述走线轨道的间距将所述硬宏专用电源网络的专用布线层划分为多个布线单元；每个布线单元具有至少两条走线轨道；
    对于每一层专用布线层，在不超过预设的铺设比例条件下，在所述布线单元中选定至少一条走线轨道进行金属线布线；所述多个布线单元中的金属线布线位置相同。
  5. 根据权利要求3所述的提升芯片硬宏供电能力的方法，其特征在于，所述硬宏专用电源网络中相邻的专用布线层的金属线方向相互垂直，并且所述硬宏专用电源网络中最接近供电引脚所在金属层的专用布线层的金属线方向与所述供电引脚所在金属层的金属线方向相互垂直。
  6. 根据权利要求3所述的提升芯片硬宏供电可靠性的方法，其特征在于，不同专用布线层的金属线布线的数量相同或不同。
  7. 根据权利要求3所述的提升芯片硬宏供电可靠性的方法，其特征在于，不同专用布线层的金属线布线的位置相同或不同。
  8. 根据权利要求3所述的提升芯片硬宏供电可靠性的方法，其特征在于，相邻的专用布线层之间具有未进行金属线布线的金属层。
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