TWI569303B - 產生待被平面規劃至一三維(3d)積體電路之電路區塊之一庫的方法及設備及非暫態電腦可讀取儲存媒體 - Google Patents
產生待被平面規劃至一三維(3d)積體電路之電路區塊之一庫的方法及設備及非暫態電腦可讀取儲存媒體 Download PDFInfo
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Description
所揭示之實施例大體上係有關於積體電路之有效平面規劃。更具體言之，所揭示之實施例係有關於用於平面規劃一3D積體電路之系統及方法，該3D積體電路最小化接線長且改良設計之總功率/效能包絡線(performance envelope)。
在電子設計自動化中，積體電路之平面規劃為其主要功能區塊之試驗性置放的示意性表示。在現代電子設計程序中，在平面規劃階段期間建立平面規劃，該平面規劃階段為晶片設計之階層式方法中之早期階段。平面規劃考量設計中之幾何約束中的一些幾何約束，包括(例如)用於晶片外連接之結合襯墊的位置。
以3D格式實施正反器及其他積體電路將為有利的。3D半導體裝置(或堆疊式IC裝置)可含有垂直堆疊之兩個或兩個以上半導體裝置，因此該兩個或兩個以上半導體裝置佔據比兩個或兩個以上習知配置之半導體裝置少的空間。堆疊式IC裝置為藉由堆疊矽晶圓及/或IC並將其垂直互連使得其充當單一裝置而建置成的單一積體電路。
習知地，在裝置之周邊處或跨越裝置之區域或既在裝置之周邊
處又跨越裝置之區域而使用輸入/輸出埠將堆疊式半導體裝置接線在一起。輸入/輸出埠略微地增加總成之長度及寬度。在一些新3D堆疊中，矽穿孔(TSV)藉由穿過半導體裝置之主體建立垂直連接而完全或部分地替代邊緣佈線。藉由使用TSV技術，堆疊式IC裝置可將大量功能性封裝至小佔據面積中。此TSV技術有時亦被稱作TSS(矽穿堆疊)。
裝置尺度縮放與互連效能失配已呈指數增加(亦即，對於全域互連，高達50倍，及對於區域互連，高達163倍)，且預期繼續更進一步增加。裝置與互連效能失配之此指數式增加已迫使設計者使用諸如全域互連之強緩衝的技術，該強緩衝隨後增加晶片面積及功率。當前3D方法僅試圖將2D區塊裝配成3D堆疊。此方法僅有助於減少區塊間網(若適用)，且並未充分利用區塊內之3D-IC，且不存在其他改良。以下兩個參考案分別揭示已知的3D區塊層級TSV規劃及2D區塊之3D平面規劃：D.H.Kim、R.O.Topaloglu及S.K.Lim之「Block-Level 3D IC Design with Through-Silicon-Via Planning」(Proc.ASPDAC，2011年，第335頁至340頁)；及J.Knechtel、I.Markov及J.Lienig之「Assembling 2-D Blocks Into 3-D Chips」(IEEE Trans.On CAD，2012年，第228頁至第241頁)。
因此，需要用於改良3D設計之能力藉此最小化接線長並改良3D設計之總功率/效率包絡線的系統及方法。
所揭示之實施例係有關於用於使用2D及3D區塊之混合體來平面規劃積體電路設計的系統及方法，其提供優於現有3D設計方法之顯著改良。所揭示之實施例提供進一步最小化接線長及改良設計之總功率/效能包絡線的較佳平面規劃解決方案。所揭示之實施例包括可用以建構待用於設計中之新3D IP區塊的方法，該等新3D IP區塊係使用
單片式3D整合技術來建置。在電子設計中，半導體智慧財產(IP)核心或IP區塊為邏輯、晶胞或晶片佈局設計之可再使用單元。IP區塊/核心通常為預先設計之電路，其可用作用於包括預先設計之區塊的大型設計之建置區塊。
更具體言之，所揭示之實施例包括一種產生待平面規劃之區塊之庫的方法，步驟包含：裝配包含2D實施及3D實施之複數個區塊；提供用於該複數個區塊中之至少一者的第一額外層且產生該複數個區塊中之該至少一者的一第一重新實施，其包括該第一額外層；評估該第一重新實施之至少一效能目標，以判定該至少一效能目標是否已得到改良；及若該評估步驟之結果為該至少一效能目標已得到改良，則將該第一重新實施添加至待平面規劃之區塊之庫。上文所描述之方法可進一步包含以下步驟：若該至少一效能目標得到改良，則提供用於該複數個區塊中之該至少一者的第二額外層且產生該複數個區塊中之該至少一者的一第二重新實施，其包括該第二額外層；進一步評估該第二重新實施之該至少一效能目標，以判定該至少一效能目標是否已得到改良；及若該進一步評估步驟之結果為該至少一效能目標已得到改良，則將該第二重新實施添加至待平面規劃之區塊之庫。
所揭示之實施例的上文所描述之方法可進一步包括：將該等3D實施添加至待平面規劃之區塊之庫的步驟；平面規劃區塊之庫，其中該平面規劃利用模擬退火3D平面規劃引擎且包含具有高密度通孔之網路的單片式3D平面規劃；及使用該3D平面規劃來產生IP區塊的步驟，該IP區塊可用於包括IP區塊之大型設計。
10‧‧‧總平面規劃/多層積體電路
12‧‧‧第一層
14‧‧‧第二層
20a‧‧‧區塊
20b‧‧‧區塊
20c‧‧‧區塊
20d‧‧‧區塊
20e‧‧‧區塊
30‧‧‧區塊
32‧‧‧箭頭
100‧‧‧將現有2D及/或3D特性化成經改良、重新實施之對應物區塊的方法
200‧‧‧進一步說明3D平面規劃之方法
300‧‧‧用於產生用於所揭示之實施例的3D區塊設計之插腳指派的方法
呈現隨附圖式以輔助描述所揭示之實施例，且僅為說明實施例而非限制實施例來提供隨附圖式。
圖1為說明基本方法的所揭示之實施例之流程圖，該基本方法用
以將現有2D及/或3D區塊特性化成經改良、重新實施之對應物區塊(若適用)，以相對於現有2D及/或3D區塊之功率/效能包絡線改良對應物區塊之功率/效能包絡線；圖2為進一步說明所揭示之實施例的3D平面規劃之流程圖，該3D平面規劃使用經改良、重新實施之2D及/或3D區塊的混合體及模擬退火框架以實施所揭示之3D平面規劃引擎；圖3為3D平面規劃之實例，其中一區塊以3D實施且剩餘區塊以2D實施；及圖4說明所揭示之實施例的區塊設計之3D插腳指派。
本專利申請案主張以下各案之優先權：2012年11月28日申請之題為「使用二維及三維區塊之三維平面規劃(3D FLOORPLANNING USING 2D AND 3D BLOCKS)」的臨時申請案第61/730,743號，且該案已讓與給其受讓人並藉此以引用之方式明確地併入本文中。
2012年11月28日申請之題為「CLOCK DISTRIBUTION NETWORK FOR 3D INTEGRATED CIRCUIT」的臨時申請案第61/730,755號，且該案已讓與給其受讓人並藉此以引用之方式明確地併入本文中。
本專利申請案係關於以下同在申請中之美國專利申請案：2013年3月5日申請之Yang Du、Jing Xie及Kambiz Samadi的「MONOLITHIC 3D IC FLIP-FLOP DESIGN」，具有代理人案號123412，該案已讓與給其受讓人並以引用之方式明確地併入本文中；2013年3月7日申請之Yang Du的「MONOLITHIC THREE DIMENSIONAL INTEGRATION OF SEMICONDUCTOR INTEGRATED
CIRCUITS」，具有代理人案號120600，該案已讓與給其受讓人並以引用之方式明確地併入本文中；及2013年3月11日申請之Kambiz Samadi、Shreepad Panth、Jing Xie及Yang Du的「CLOCK DISTRIBUTION NETWORK FOR 3D INTEGRATED CIRCUIT」，具有代理人案號124318，該案已讓與給其受讓人並以引用之方式明確地併入本文中。
本發明之態樣揭示於以下描述以及有關於本發明之特定實施例的相關圖式中。可設計出替代實施例而不脫離本發明之範疇。另外，將不詳細描述或將省略本發明之熟知元件以便不會混淆本發明之相關細節。
詞語「例示性」在本文中用以意謂「充當一實例、例子或說明」。不必將本文中描述為「例示性」之任何實施例解釋為比其他實施例較佳或有利。同樣，術語「本發明之實施例」並不要求本發明之所有實施例包括所論述之特徵、優點或操作模式。
本文中所使用之術語僅用於達成描述特定實施例之目的且不欲限制本發明之實施例。如本文中所使用，單數形式「一」及「該」意欲亦包括複數形式，除非上下文另有清晰指示。應進一步理解，術語「包含」、「包括」在本文中使用時指定所陳述之特徵、整體、步驟、操作、元件及/或組件之存在，但並不排除一或多個其他特徵、整體、步驟、操作、元件、組件及/或其群組之存在或添加。
另外，許多實施例係關於待由(例如)計算裝置之元件執行的動作之序列來描述。應認識到，本文中所描述之各種動作可藉由特定電路(例如，特殊應用積體電路(ASIC))、藉由一或多個處理器所執行之程式指令或藉由兩者之組合來執行。另外，可認為本文中所描述之動作序列完全體現於任何形式之電腦可讀儲存媒體內，該電腦可讀儲存媒體中儲存有在執行後便將使相關聯之處理器執行本文中所描述之功能性的電腦指令之對應集合。因此，本發明之各種態樣可以數種不同形式體現，其皆預期在所主張之標的物之範疇內。另外，對於本文中所
描述之實施例中的每一者，任何此等實施例之對應形式可在本文中被描述為(例如)「經組態以執行所描述之動作的邏輯」。
圖1為說明所揭示之實施例的基本方法之流程圖。圖1之方法100將現有2D及/或3D區塊特性化或重新實施成多個對應物區塊(其亦可為2D及/或3D)(若適用)，以相對於現有2D及/或3D區塊之功率/效能包絡線改良對應物區塊之功率/效能包絡線。當跨越額外層而摺疊一些區塊時，該等區塊可表現更好。目標為進一步擴展並重新實施現有區塊以產生優於其對應物的經改良之區塊之集合。方法100在步驟102處以包括現有2D及/或3D區塊之初始接線對照表開始。在步驟104處，增加層之數目，且接著在步驟106處重新實施初始區塊。重新實施包括跨越該等層而分割接線對照表，置放每一層且排定每一層之線路，及插入通孔。大體而言，接線對照表為經實施為一般閘或程序特定標準晶胞的邏輯功能之布林代數表示。對於單片式3D應用，通孔較佳為高密度層間通孔。步驟108評估目標以判定在步驟104處添加之額外層是否改良設計。舉例而言，可將總矽面積、時序及功率之加權和視為目標。因為區塊遠小於整個設計，所以較佳在步驟108處使用佈局後時序、功率及面積值以用於增加準確度。若在步驟108處之評估為令人滿意的(亦即，額外層改良區塊)，則在步驟110處，將經改良之區塊添加至區塊群集，且方法100返回至區塊104以進一步增加層之數目。若在步驟108處之評估不能令人滿意，則方法100判定最近添加之層無法改良區塊，且方法100停止。藉此，方法100識別在跨越額外層而摺疊時表現較好之區塊，從而產生優於其現有2D及/或3D對應物的經改良、重新實施之區塊的集合/庫(步驟110)。
圖2為進一步說明所揭示之實施例的3D平面規劃的另一方法200之流程圖，該3D平面規劃使用2D及3D區塊之經改良、重新實施之混合體。在所揭示之設計情形中，必須將區塊之集合(包括在圖1之步驟
110處產生的區塊群組)平面規劃成3D堆疊。每一區塊實行為具有變化數目個層、時序、功率及區域佔據面積的2D及3D實施。藉由區域佔據面積、接線長及延遲之加權和來判定目標。可取決於特定設計而考慮其他導出型目標函數。輸出為判定(i)用於每一區塊(亦即，2D或3D)之區塊實施的選擇，及(ii)最小化上述目標函數之每一區塊之(x,y,z)座標。
圖2之方法200展示用以實施所揭示之3D平面規劃引擎的模擬退火框架。模擬退火為基於冷卻金屬之行為的人工智慧技術。其可用以獲得針對困難或不可能之組合性最佳化問題的解決方案。方法200在步驟202處藉由識別初始解決方案而開始，在初始解決方案中將全域參數T設定為初始值T0。儘管全域參數T一般被稱作溫度，但T並不與物理溫度相關。實情為，T為用以控制基於模擬退火之3D平面規劃引擎之進展的全域參數。步驟204接著擾動解決方案，且步驟206評估服務品質(QoS)參數是否低於其最佳位準。QoS為向不同應用程式、使用者或資料流提供不同優先權，或保證資料流之某一效能等級的能力。舉例而言，可保證所需位元速率、延遲、抖動、封包丟棄機率及/或位元錯誤率。若在步驟206處之判定為否，則方法200在步驟208處接受具有與T成比例之機率的解決方案，接著繼續進行至步驟212。若在步驟206處之判定為是，則方法200在步驟210處接受解決方案，接著繼續進行至步驟212。步驟212判定移動之數目是否大於針對給定T之經設定為Mmax的最大移動數。若步驟212之答覆為否，則方法200返回至步驟204且進一步擾動解決方案。若步驟212之答覆為是，則步驟214降低全域參數T，接著在步驟216處評估T現在是否小於Tmin(停止「溫度」)。若步驟216之答覆為是，則方法200停止。若步驟216之答覆為否，則方法200返回至步驟204且進一步擾動解決方案。
圖3為可由圖1之方法100及圖2之方法200產生的多層積體電路平
面規劃10之實例。總平面規劃10為3D，其中一區塊以3D來實施且剩餘區塊以2D來實施。如所說明，多層積體電路10包括第一層12及第二層14。一區塊30橫跨層12及層14而以3D來實施。剩餘區塊20a、20b、20c、20d及20e以2D來實施且散佈於層12與層14之間。通孔(由箭頭32表示)之網路為多層積體電路10提供通信路徑。
圖4說明用於產生用於所揭示之實施例的3D區塊設計之插腳指派的方法300。評估區塊接線對照表，且步驟302判定3D區塊是否為硬巨集(hard macro)。將邏輯組件及組件之間的實體路徑及佈線圖案指定為硬巨集。因此，若3D區塊為硬巨集，則業已完成插腳指派以及區塊設計。若3D區塊並非硬巨集，則已指定所需邏輯元件之互連，但未指定實體佈線圖案。因此，該3D區塊為軟巨集。若3D區塊為軟巨集，則方法300在步驟304處允許插腳處於區塊之每一層上，接著執行3D平面規劃。在知曉平面規劃解決方案/區塊間連接性之情況下，現可固定插腳位置。藉由使用該插腳指派及跨越該等層之分割解決方案，步驟306實施區塊。可使用2D或3D方法來進行分割。
當3D實施技術為一般稱為「單片式」之類型時，所揭示之實施例特別有利。在單片式3D積體電路中，在單一半導體晶圓上之多個層體中順序地建置電子組件及其連接(佈線)，該單一半導體晶圓接著經切割成3D IC。最初，每一後續層中不具有裝置，因此無需對準，從而導致較大整合密度。高密度通孔之網路為單片式3D IC提供通信路徑。此外，所揭示之實施例包括可用以建構待用於設計中之新3D IP區塊的方法，該等新3D IP區塊係使用單片式3D整合技術來建置。所揭示之實施例的新3D IP區塊/核心可用作邏輯、晶胞或晶片佈局之可再使用單元，其可用於包括預先設計之區塊的大型設計。
雖然前述揭示內容及說明展示本發明之實施例，但應注意，在不脫離如由附加之申請專利範圍界定的本發明之範疇之情況下可對本
發明進行各種改變及修改。舉例而言，根據本文中所描述的本發明之實施例的方法請求項之功能、步驟及/或動作無需以任何特定次序來執行。此外，儘管可能以單數形式描述或主張本發明之元件，但除非明確陳述限於單數形式，否則亦預期複數形式。
熟習此項技術者亦將瞭解，可將結合本文中所揭示之實施例而描述的各種說明性邏輯區塊、模組、電路及演算法步驟實施為電子硬體、電腦軟體或兩者之組合。為了清楚地說明硬體與軟體之此可互換性，上文已大體上在功能性方面描述了各種說明性組件、區塊、模組、電路及步驟。此功能性係實施為硬體抑或軟體取決於特定應用及強加於整個系統上之設計約束。熟習此項技術者可針對每一特定應用以變化之方式實施所描述之功能性，但不應將此等實施決策解釋為導致脫離本發明之範疇。
結合本文中所揭示之實施例而描述之方法、序列及/或演算法可直接以硬體、以由處理器執行之軟體模組或以該兩者之組合來體現。
軟體模組可駐留於RAM記憶體、快閃記憶體、ROM記憶體、EPROM記憶體、EEPROM記憶體、暫存器、硬碟、抽取式碟片、CD-ROM或此項技術中已知之任何其他形式的儲存媒體中。例示性儲存媒體耦接至處理器，使得處理器可自儲存媒體讀取資訊及將資訊寫入至儲存媒體。在替代例中，儲存媒體可整合至處理器。因此，本發明之實施例可包括電腦可讀媒體，該電腦可讀媒體體現用於執行所揭示及主張之實施例的方法。因此，本發明不限於所說明之實例，且用於執行本文中所描述之功能性之任何構件包括於本發明之實施例中。
100‧‧‧將現有2D及/或3D特性化成經改良、重新實施之對應物區塊的方法
Claims (13)
- 一種產生待被平面規劃至一三維(3D)積體電路之電路區塊之一庫的方法，其步驟包含：藉由一計算裝置裝配包含二維(2D)電路實施及3D電路實施之複數個電路區塊；提供用於該複數個電路區塊中之至少一者的一第一額外層，且產生該複數個電路區塊中之該至少一者的一第一重新實施，其包括該第一額外層；評估該第一重新實施之至少一效能目標，以判定該至少一效能目標是否已得到改良；及若該評估步驟之一結果為該至少一效能目標已得到改良，則將該第一重新實施添加至待被平面規劃至該3D積體電路之電路區塊之該庫，其中待被平面規劃至該3D積體電路之電路區塊之該庫包含3D單片式電路區塊之一庫，其中至少一3D單片式電路區塊包含在一單一半導體晶圓上之二或多個層體中順序地建置之一或多個電組件。
- 如請求項1之方法，其進一步包含以下步驟：若該至少一效能目標得到改良，則提供用於該複數個電路區塊中之該至少一者的一第二額外層，且產生該複數個電路區塊中之該至少一者的一第二重新實施，其包括該第二額外層；進一步評估該第二重新實施之該至少一效能目標，以判定該至少一效能目標是否已得到改良；及若該進一步評估步驟之一結果為該至少一效能目標已得到改良，則將該第二重新實施添加至待被平面規劃至該3D積體電路 之3D單片式電路區塊之該庫。
- 如請求項2之方法，其進一步包含平面規劃3D單片式電路區塊之該庫至該3D積體電路的步驟。
- 如請求項3之方法，其中平面規劃3D單片式電路區塊之該庫之該步驟產生一智慧財產(IP)電路區塊，該IP電路區塊可用於包括該IP電路區塊之一大型電路設計。
- 如請求項4之方法，其中平面規劃3D單片式電路區塊之該庫之該步驟產生具有高密度通孔之一網路的一單片式3D電路平面規劃。
- 如請求項5之方法，其中高密度通孔之該網路包含層間通孔。
- 如請求項3之方法，其中平面規劃3D單片式電路區塊之該庫之該步驟包含使用一模擬退火3D平面規劃引擎而平面規劃3D單片式電路區塊之該庫。
- 如請求項3之方法，其進一步包含判定用於3D單片式電路區塊之經平面規劃之該庫之插腳指派，其中插腳指派係藉由以下步驟來判定：判定3D單片式電路區塊之經平面規劃之該庫是否包含一硬巨集；若3D單片式電路區塊之經平面規劃之該庫包含一硬巨集，則接受現有插腳指派；及若3D單片式電路區塊之經平面規劃之該庫包含一軟巨集，則允許插腳處於3D單片式電路區塊之經平面規劃之該庫之每一層上且使用2D分割方法固定該等插腳之一位置。
- 如請求項1之方法，其中該3D單片式電路區塊之至少一者包括在一單一半導體晶圓上之至少一電組件。
- 如請求項9之方法，其中該單一半導體晶圓係被切成3D積體電 路。
- 一種非暫態電腦可讀取儲存媒體，其包含體現電路區塊之一庫之資料，當其被一機器存取時，致使該機器執行下列操作：藉由該機器裝配包含電路區塊之該庫之2D實施及3D實施之複數個電路區塊；提供用於該複數個電路區塊中之至少一者的一第一額外層，且產生該複數個電路區塊中之該至少一者的一第一重新實施，其包括該第一額外層；評估該第一重新實施之至少一效能目標，以判定該至少一效能目標是否已得到改良；及若該評估步驟之一結果為該至少一效能目標已得到改良，則將該第一重新實施添加至待被平面規劃至一3D積體電路之電路區塊之該庫，其中待被平面規劃之電路區塊之該庫包含3D單片式電路區塊之一庫，其中至少一3D單片式電路區塊包含在一單一半導體晶圓上之二或多個層體中順序地建置之一或多個電組件。
- 如請求項11之非暫態電腦可讀取儲存媒體，其包含體現電路區塊之該庫之資料，當其被該機器存取時，致使該機器執行下列操作：若該至少一效能目標得到改良，則提供用於該複數個電路區塊中之該至少一者的一第二額外層，且產生該複數個電路區塊中之該至少一者的一第二重新實施，其包括該第二額外層；進一步評估該第二重新實施之該至少一效能目標，以判定該至少一效能目標是否已得到改良；及若該進一步評估步驟之一結果為該至少一效能目標已得到改良，則將該第二重新實施添加至待被平面規劃至該3D積體電路 之3D單片式電路區塊之該庫。
- 一種產生待被平面規劃至一三維(3D)積體電路之電路區塊之一庫的設備，該設備包含：用於裝配包含二維(2D)電路實施及3D電路實施之複數個電路區塊之構件；用於提供用於該複數個電路區塊中之至少一者的一第一額外層之構件；用於產生包括該第一額外層之該複數個電路區塊中之該至少一者的一第一重新實施之構件；用於評估該第一重新實施之至少一效能目標，以判定該至少一效能目標是否已得到改良之構件；及用於若用於評估之該構件的一結果為該至少一效能目標已得到改良，則將該第一重新實施添加至待被平面規劃至該3D積體電路之電路區塊之該庫之構件，其中待被平面規劃至該3D積體電路之電路區塊之該庫包含3D單片式電路區塊之一庫，其中至少一3D單片式電路區塊包含在一單一半導體晶圓上之二或多個層體中順序地建置之一或多個電組件。
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| WO2014085692A3 (en) | 2014-10-16 |
| US20140149958A1 (en) | 2014-05-29 |
| WO2014085692A2 (en) | 2014-06-05 |
| TW201428813A (zh) | 2014-07-16 |
| US9064077B2 (en) | 2015-06-23 |
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