WO2021197025A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2021197025A1
WO2021197025A1 PCT/CN2021/080361 CN2021080361W WO2021197025A1 WO 2021197025 A1 WO2021197025 A1 WO 2021197025A1 CN 2021080361 W CN2021080361 W CN 2021080361W WO 2021197025 A1 WO2021197025 A1 WO 2021197025A1
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layer
sidewall
forming
side wall
substrate
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PCT/CN2021/080361
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English (en)
French (fr)
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张黎
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长鑫存储技术有限公司
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Priority to US17/385,011 priority Critical patent/US20210351280A1/en
Publication of WO2021197025A1 publication Critical patent/WO2021197025A1/zh

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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions

  • the present invention relates to the field of semiconductors, in particular to semiconductor structures and preparation methods thereof.
  • CMOS devices As the size of CMOS devices continues to decrease to the sub-micron level, as predicted by Moore’s Law, the number of transistors in high-efficiency, high-density integrated circuits has risen to tens of millions, followed by the gate sidewall thickness and The thickness of the gate oxide layer is continuously reduced.
  • the sidewall oxide layer in the gate sidewall in the existing process is generally formed by the atomic layer deposition (ALD) process, and the sidewall oxide layer formed by the atomic layer deposition process has many defects , The breakdown voltage is lower, which will cause the gate leakage current to increase, which has a great impact on the reliability and service life of the device.
  • ALD atomic layer deposition
  • a semiconductor structure and a manufacturing method thereof are provided, which have the effect of reducing gate leakage current.
  • a method for preparing a semiconductor structure includes:
  • a gate layer is formed on the surface of the gate oxide layer.
  • the second side wall is formed by in-situ water vapor oxidation, the breakdown voltage of the second side wall is higher and there are fewer defects in the second side wall, and both sides of the first side wall are formed Having a second side wall, on the one hand, it improves the ability of the first side wall and the second side wall to reduce the gate leakage current.
  • the second side wall is formed on both sides of the first side wall so that the first side wall has two The thickness of the second side wall can be reduced, thereby reducing the possibility of defects in the second side wall, thereby further improving the ability of the first side wall and the second side wall to reduce the gate leakage current, and improving the device's Reliability and service life.
  • forming the first sidewall on the substrate includes:
  • the sacrificial layer is removed.
  • the first sidewall includes a silicon-containing dielectric layer.
  • the first sidewall includes a silicon nitride layer or a silicon dioxide layer; the second sidewall includes a silicon dioxide layer.
  • a shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure isolates a plurality of active regions in the substrate; the first sidewall, the The second sidewall and the gate oxide layer are both located on the active region.
  • the gate layer after forming the gate layer, it further includes a step of forming a top dielectric layer on the surface of the gate layer.
  • the top dielectric layer includes a silicon nitride layer or a silicon oxide layer.
  • the reaction temperature for forming the second side wall by the in-situ water vapor oxidation process is 800° C. to 1100° C.
  • the reaction pressure is 6 Torr to 20 Torr.
  • the reaction gas used to form the second side wall by the in-situ water vapor oxidation process includes a mixed gas of oxygen and hydrogen, a mixed gas of nitric oxide and hydrogen, or a mixed gas of nitrogen dioxide and hydrogen.
  • the volume concentration of the hydrogen in the mixed gas is 1% to 33%.
  • the semiconductor structure is prepared based on the above-mentioned method for preparing the semiconductor structure.
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure shown in an embodiment
  • FIG. 2 is another embodiment showing a flow chart of a method of manufacturing a semiconductor structure
  • FIG. 3 is a schematic diagram of a cross-sectional structure after forming a sacrificial layer on a substrate according to an embodiment
  • FIG. 4 is a schematic diagram of a cross-sectional structure after forming a photoresist layer in an embodiment
  • FIG. 5 is a schematic diagram of a cross-sectional structure after forming a sidewall groove in an embodiment
  • FIG. 6 is a schematic diagram of a cross-sectional structure after forming the first side wall in an embodiment
  • FIG. 7 is a schematic diagram of a cross-sectional structure after removing the sacrificial layer according to an embodiment
  • FIG. 8 is a schematic cross-sectional structure diagram of another embodiment after a sacrificial layer is formed on the substrate;
  • FIG. 9 is a schematic cross-sectional structure diagram of another embodiment after forming the first sidewall material layer
  • FIG. 10 is a schematic cross-sectional structure diagram of another embodiment after removing the first sidewall material layer on the upper surface of the substrate and the upper surface of the sacrificial layer;
  • FIG. 11 is a schematic diagram of a cross-sectional structure after removing the sacrificial layer in another embodiment
  • FIG. 12 is a schematic diagram of a cross-sectional structure after forming a second sidewall and a gate oxide layer in an embodiment
  • FIG. 13 is a schematic cross-sectional structure diagram of another embodiment after forming the second side wall
  • FIG. 14 is a schematic diagram of a cross-sectional structure after forming a gate oxide layer in another embodiment
  • FIG. 15 is a schematic diagram of a cross-sectional structure after forming a gate layer according to an embodiment
  • FIG. 16 is a schematic diagram of a cross-sectional structure after forming a top dielectric layer in an embodiment.
  • a method for manufacturing a semiconductor structure which specifically includes the following steps:
  • Step S10 The substrate 10 is provided.
  • Step S20 forming at least a pair of first sidewalls 11 on the substrate 10, and there is a gap between the two first sidewalls 11 in each pair.
  • Step S30 using an in-situ water vapor oxidation process to form second sidewalls 12 on both sides of the first sidewall 11, and form a gate oxide layer 13 on the substrate 10 between the two first sidewalls 11 in each pair .
  • Step S40 forming a gate layer 14 on the surface of the gate oxide layer 13.
  • the substrate 10 may be a silicon substrate, a silicon-on-insulator substrate, or other semiconductor materials including group III, group IV, and group V. .
  • a shallow trench isolation structure 19 is formed in the substrate 10.
  • the shallow trench isolation structure 19 isolates a number of active regions in the substrate 10.
  • the active regions may be regions doped with doped ions, for example, N-type Ions or P-type ions, etc.; a number of active regions are arranged at intervals in the substrate 10.
  • step S20 specifically includes the following steps:
  • Step S201 forming a sacrificial layer 15 on the substrate 10, as shown in FIG. 3;
  • Step S202 forming a sidewall groove 16 in the sacrificial layer 15, as shown in FIG. 5;
  • Step S203 forming a first side wall 11 in the side wall groove 16, as shown in FIG. 6;
  • Step S204 the sacrificial layer 15 is removed, as shown in FIG. 7.
  • the sacrificial layer 15 may be an oxide layer.
  • the material of the sacrificial layer 15 and the first sidewall 11 has a higher etching selection ratio.
  • the material of the first sidewall 11 may be a silicon-containing dielectric layer formed by deposition.
  • the first sidewall 11 includes a silicon nitride layer or a silicon dioxide layer.
  • the sacrificial layer 15 may be a silicon dioxide layer. After 11, the sacrificial layer 15 is removed by a wet etching process. There is a gap between the two first sidewalls 11, and the size of the gap depends on the size of the gate layer 14 obtained in the subsequent process. The two first sidewalls 11 are located at both ends of the gate layer 14.
  • step S20 it specifically includes the following steps:
  • Step S201 forming a sacrificial layer 15 on the substrate 10, as shown in FIG. 8.
  • Step S202 forming a first sidewall material layer 20 on the upper surface of the sacrificial layer 15, the sidewalls of the sacrificial layer 15 and the upper surface of the substrate 10, as shown in FIG. 9.
  • Step S203 Remove the first sidewall material layer 20 on the upper surface of the sacrificial layer 15 and the upper surface of the substrate 10, and leave the first sidewall material layer 20 on the sidewall of the sacrificial layer 15 to form the first sidewall 11, as shown in FIG. Shown.
  • Step S204 the sacrificial layer 15 is removed, as shown in FIG. 11.
  • the sacrificial layer 15 may be formed on the upper surface of the substrate 10 by a deposition process, and the material of the sacrificial layer 15 may be oxide, such as silicon dioxide.
  • the first sidewall material layer 20 can also be formed on the upper surface of the substrate 10, the upper surface of the sacrificial layer 15 and the sidewalls of the sacrificial layer 15 by a deposition process.
  • the material of the first sidewall material layer 20 can be a silicon-containing medium. Electric layer.
  • the material of the first sidewall material layer 20 includes a silicon nitride layer or a silicon dioxide layer, wherein there is a larger etching choice between the sacrificial layer 15 and the first sidewall material layer 20
  • the sacrificial layer 15 may be a silicon dioxide layer.
  • the sacrificial layer 15 can be removed by a wet etching process. There is a gap between the two first sidewalls 11 obtained after the sacrificial layer 15 is removed. The size of the gap depends on the size of the gate layer 14 obtained in the subsequent process. The two first sidewalls 11 are located on the gate layer 14 Both ends.
  • the temperature at which the in-situ water vapor oxidation process is used to form the second side wall 12 includes 800°C to 1100°C. In an optional embodiment, The temperature at which the second sidewall 12 is formed may be 800°C, 900°C, 1000°C, or 1100°C.
  • the reaction pressure of the in-situ water vapor oxidation process includes 6 Torr to 20 Torr. In an optional embodiment, the reaction pressure used can be 6 Torr, 8 Torr, 12 Torr, or 20 Torr.
  • the reaction gas for forming the second side wall 12 includes a mixed gas of oxygen and hydrogen, a mixed gas of nitric oxide and hydrogen, or a mixed gas of nitrogen dioxide and hydrogen, wherein the volume concentration of hydrogen is 1 % ⁇ 33%. In an optional embodiment, the volume concentration of hydrogen may be 1%, 10%, 20%, or 33%.
  • a gate oxide layer 13 is also formed between the pair of first sidewalls 11.
  • the second sidewall 12 and the gate The material of the oxide layer 13 is all oxide, which may be silicon dioxide.
  • the second sidewall 12 and the gate oxide layer 13 can be formed by the same in-situ water vapor oxidation process.
  • the thickness of the first side wall 11 is greater than the thickness of the second side wall 12.
  • the second sidewall 12 is formed by an in-situ water vapor oxidation process on both sides of the first sidewall 11, and then the second sidewall 12 is formed by an in-situ water vapor oxidation process or other methods.
  • a process such as a deposition process, is to form a gate oxide layer 13 on the upper surface of the substrate 10 between the two first sidewalls 11, and the materials of the second sidewall 12 and the gate oxide layer 13 are both oxides, which can be silicon dioxide. .
  • step S40 as shown in FIG. 15, specifically, polysilicon or metal is deposited on the upper surface of the gate oxide layer 13 between the pair of first sidewalls 11 to form a gate layer 14, and the gate layer 14 is filled in a pair of Between the second sidewalls 12 on the first sidewall 11, and the upper surface of the gate layer 14 is lower than the upper surface of the first sidewall 11.
  • step S50 is further included after step S40;
  • Step S50 forming a top dielectric layer 18 on the surface of the gate layer 14, as shown in FIG. 16.
  • step S50 specifically, silicon nitride or silicon oxide is deposited on the upper surface of the gate layer 14 through a deposition process to form a top dielectric material layer, after a planarization process, a top dielectric layer 18 is formed, and the upper surface of the top dielectric layer 18 It is flush with the upper surface of the first side wall 11.
  • the breakdown voltage of the second side wall 12 is higher and the defects generated in the second side wall 12 are fewer, and the first side A second side wall 12 is formed on both sides of the wall 11.
  • the ability of the first side wall 11 and the second side wall 12 to reduce the gate leakage current is improved.
  • both sides of the first side wall 11 are formed Having the second side wall 12 allows the thickness of the second side wall 12 on both sides of the first side wall 11 to be reduced, thereby reducing the possibility of defects in the second side wall 12, thereby further improving the first side wall 11
  • the ability of the second side wall 12 to reduce gate leakage current improves the reliability and service life of the device.
  • a semiconductor structure is also provided. As shown in FIG. 16, the semiconductor structure is prepared based on the above-mentioned method for preparing a semiconductor structure, and includes a substrate 10.
  • the substrate may be a silicon substrate, a silicon-on-insulator substrate, or a group III , Group IV and Group V other semiconductor materials.
  • a shallow trench isolation structure 19 is formed in the substrate 10.
  • the shallow trench isolation structure 19 isolates a number of active regions in the substrate 10.
  • the active regions may be regions doped with doped ions, for example, N-type Ions or P-type ions, etc.; a number of active regions are arranged at intervals in the substrate 10.
  • At least one pair of first sidewalls 11 is formed on the active area, and there is a gap between the first sidewalls 11 in each pair.
  • the material of the first sidewalls 11 may be a silicon-containing dielectric layer formed by deposition.
  • the first sidewall 11 includes a silicon nitride layer or a silicon dioxide layer.
  • a second sidewall 12 is formed on both sides of the first sidewall 11, and a gate oxide layer 13 is formed on the active area between the pair of first sidewalls 11, and the second sidewall 12 is connected to the gate oxide layer 13
  • the materials of the second sidewall 12 and the gate oxide layer 13 are both oxides, which may be silicon dioxide in an alternative embodiment.
  • the second sidewall 12 and the gate oxide layer 13 can be formed by the same in-situ water vapor oxidation process.
  • the upper surface of the gate oxide layer 13 is formed with a gate layer 14 by depositing polysilicon.
  • the gate layer 14 is filled between the second sidewalls 12 on the pair of first sidewalls 11, and the upper surface of the gate layer 14 is lower than The upper surface of the first side wall 11.
  • a top dielectric layer 18 is further formed on the upper surface of the gate layer 14, and the material of the top dielectric layer 18 may be silicon nitride or silicon oxide, which protects the gate layer 14.
  • the second side wall 12 is formed on both sides of the first side wall 11, which on the one hand improves the ability of the first side wall 11 and the second side wall 12 to reduce the gate leakage current
  • the second side wall A second side wall 12 is formed on both sides of a side wall 11 so that the thickness of the second side wall 12 on both sides of the first side wall 11 can be reduced, thereby reducing the possibility of defects in the second side wall 12, thereby The ability of the first sidewall 11 and the second sidewall 12 to reduce gate leakage current is further improved, and the reliability and service life of the device are improved.

Abstract

一种半导体结构的制备方法，包括：提供衬底；于所述衬底上形成至少一对第一侧壁，每对中的两个第一侧壁之间存在间距；采用原位水汽氧化工艺于所述第一侧壁的两侧形成第二侧壁，并于每对中的所述两个第一侧壁之间的衬底上形成栅氧化层；及于所述栅氧化层的表面形成栅极层。

Description

半导体结构及其制备方法 技术领域
本发明涉及半导体领域，特别是涉及半导体结构及其制备方法。
背景技术
随着CMOS器件尺寸不断减小到次微米级，正如摩尔定律的预测，在高效率、高密度集成电路中的晶体管数量上升到几千万个，随之而来的是栅极侧壁厚度和栅氧化层厚度等的不断减小，现有工艺中的栅极侧壁中的侧壁氧化层一般采用原子层沉积(ALD)工艺形成，原子层沉积工艺形成侧壁氧化层内具有较多缺陷，击穿电压较低，这将导致栅极漏电流增加，这对器件的可靠性及使用寿命都有很大的影响。
发明内容
根据各个实施例，提供一种半导体结构及其制备方法，其具有减小栅极漏电流的效果。
一种半导体结构的制备方法，包括：
提供衬底；
于所述衬底上形成至少一对第一侧壁，各对中的两所述第一侧壁之间存在间距；
采用原位水汽氧化工艺于所述第一侧壁的两侧侧壁形成第二侧壁，并于各对中的两所述第一侧壁之间的衬底上形成栅氧化层；
于所述栅氧化层的表面形成栅极层。
通过上述技术方案，由于第二侧壁通过原位水汽氧化形成，因此第二侧壁的击穿电压更高且第二侧壁内产生的缺陷更少，且第一侧壁的两侧均形成有第二侧壁，一方面提高了第一侧壁与第二侧壁降低栅极漏电流的能力，另一方面，第一侧壁两侧均形成有第二侧壁使得第一侧壁两侧第二侧壁在厚度上可以降低，从而减小了第二侧壁中出现缺陷的可能性，从而进一步的提高第一侧壁与第二侧壁降低栅极漏电流的能力，提高器件的可靠性和使用寿命。
在其中一个实施例中，于所述衬底上形成所述第一侧壁包括：
于所述衬底上形成牺牲层；
于所述牺牲层内形成侧壁凹槽；
于所述侧壁凹槽内形成第一侧壁；
去除所述牺牲层。
在其中一个实施例中，所述第一侧壁包括含硅介电层。
在其中一个实施例中，所述第一侧壁包括氮化硅层或二氧化硅层；所述第二侧壁包二氧化硅层。
在其中一个实施例中，所述衬底内形成有浅沟槽隔离结构，所述浅沟槽隔离结构于所述衬底内隔离出若干个有源区；所述第一侧壁、所述第二侧壁及所述栅氧化层均位于所述有源区上。
在其中一个实施例中，形成所述栅极层后还包括于所述栅极层的表面形成顶层介质层的步骤。
在其中一个实施例中，所述顶层介质层包括氮化硅层或氧化硅层。
在其中一个实施例中，采用所述原位水汽氧化工艺形成所述第二侧壁的反应温度为包括800℃～1100℃，反应压力包括6Torr～20Torr。
在其中一个实施例中，采用所述原位水汽氧化工艺形成所述第二侧壁的反应气体包括氧气与氢气混合气体、一氧化氮与氢气混合气体或二氧化氮与氢气混合气体。
在其中一个实施例中，所述混合气体中所述氢气的体积浓度为1％～33％。
在其中一个实施例中，所述半导体结构基于上述半导体结构的制备方法制备而成。
附图说明
图1为一个实施例展示的半导体结构的制备方法流程图；
图2为另一个实施例展示半导体结构的制备方法流程图；
图3为一个实施例于衬底上形成牺牲层后的截面结构示意图；
图4为一个实施例形成光刻胶层后的截面结构示意图；
图5为一个实施例形成侧壁凹槽后的截面结构示意图；
图6为一个实施例形成第一侧壁后的截面结构示意图；
图7为一个实施例去除牺牲层后的截面结构示意图；
图8为另一个实施例于衬底上形成牺牲层后的截面结构示意图；
图9为另一个实施例形成第一侧壁材料层后的截面结构示意图；
图10为另一个实施例去除衬底上表面及牺牲层上表面的第一侧壁材料层后的截面结构示意图；
图11为另一个实施例去除牺牲层后的截面结构示意图；
图12为一个实施例形成第二侧壁和栅氧化层后的截面结构示意图；
图13为另一个实施例形成第二侧壁后的截面结构示意图；
图14为另一个实施例形成栅氧化层后的截面结构示意图；
图15为一个实施例形成栅极层后的截面结构示意图；
图16为一个实施例形成顶层介质层后的截面结构示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本发明的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
如图1所示，根据一实施例，提供了一种半导体结构的制备方法，具体包括以下步骤：
步骤S10：提供衬底10。
步骤S20：于衬底10上形成至少一对第一侧壁11，每对中的两个第一侧壁11之间存在间距。
步骤S30：采用原位水汽氧化工艺于第一侧壁11的两侧形成第二侧壁12，并于每对中的两个第一侧壁11之间的衬底10上形成栅氧化层13。
步骤S40：于栅氧化层13的表面形成栅极层14。
在一个可选的实施例中，对于步骤S10，如图3所示，具体的，衬底10可以为硅衬底、绝缘体上硅衬底或者包括III族、IV族和V族的其他半导体材料。衬底10内形成有浅沟槽隔离结构19，浅沟槽隔离结构19于衬底10内隔离出若干个有源区，有源区可以为掺杂有掺杂离子的区域，譬如，N型离子或P型离子等等；若干个有源区于衬底10内间隔排布。
在一个可选的实施例中，对于步骤S20，具体的包括以下步骤：
步骤S201：于衬底10上形成牺牲层15，如图3所示；
步骤S202：于牺牲层15内形成侧壁凹槽16，如图5所示；
步骤S203：于侧壁凹槽16内形成第一侧壁11，如图6所示；
步骤S204：去除牺牲层15，如图7所示。
上述步骤中，如图4所示，通过在牺牲层15上形成光刻胶层17，并通过曝光显影对光刻胶层17进行图形化处理，暴露出部分牺牲层15，通过干法刻蚀去除暴露的牺牲层15从而得到两个侧壁凹槽16。牺牲层15可以为氧化层，牺牲层15与第一侧壁11的材质有较高的刻蚀选择比，第一侧壁11的材质可以为沉积形成的含硅介电层，在一个可选的实施例中，第一侧壁11包括氮化硅层或二氧化硅层，当第一侧壁11为氮化硅层时，牺牲层15可以为二氧化硅层，在形成第一侧壁11后采用湿法刻蚀工艺去除牺牲层15。两个第一侧壁11之间存在间距，间距的大小根据后续工艺中所得的栅极层14的大小而定，两个第一侧壁11位于栅极层14的两端。
在一个其他可选的实施例中，，对于步骤S20，具体的包括以下步骤：
步骤S201：于衬底10上形成牺牲层15，如图8所示。
步骤S202：于牺牲层15的上表面、牺牲层15的侧壁及衬底10的上表面形成第一侧壁材料层20，如图9所述。
步骤S203：去除牺牲层15上表面及衬底10上表面的第一侧壁材料层20，保留牺牲层15侧壁上的第一侧壁材料层20以形成第一侧壁11，如图10所示。
步骤S204：去除牺牲层15，如图11所示。
具体的，可以通过沉积工艺在衬底10的上表面形成牺牲层15，牺牲层15的材质可以为氧化物，如二氧化硅。第一侧壁材料层20同样可通过沉积工艺形成于衬底10的上表面、牺牲层15的上表面和牺牲层15的侧壁上，第一侧壁材料层20的材质可以为含硅介电层。在一个可选的实施例中，第一侧壁材料层20的材质包括氮化硅层或二氧化硅层，其中牺牲层15与第一侧壁材料层20之间具有较大的刻蚀选择比，当第一侧壁材料层20的材质为氮化硅层时，牺牲层15可以为二氧化硅层。在去除牺牲层15上表面及衬底10上表面的第一侧壁材料层20时可以通过干法刻蚀工艺，对于牺牲层15上表面的第一侧壁材料层20还可以通过化学机械研磨工艺去除，牺牲层15则可通过湿法刻蚀工艺去除。去除牺牲层15后得到的两个第一侧壁11之间存在间距，间距的大小根据后续工艺中所得的栅极层14的大小而定，两个第一侧壁11位于栅极层14的两端。
在一个可选的实施例中，对于步骤S30，如图12所示，采用的原位水汽氧化工艺形成第二侧壁12的温度包括800℃～1100℃，在一个可选的实施例中，形成第二侧壁12的温度可以为800℃、900℃、1000℃或1100℃。原位水汽氧化工艺打的反应压力包括6Torr～20Torr，在一个可选的实施例中，采 用的反应压力可以为6Torr、8Torr、12Torr或20Torr。在采用原位水汽氧化(ISSG)工艺形成第二侧壁12的反应气体包括氧气与氢气混合气体、一氧化氮与氢气混合气体或二氧化氮与氢气混合气体，其中，氢气的体积浓度为1％～33％，在一个可选的实施例中，氢气的体积浓度可以采用1％、10％、20％或33％。
在第一侧壁11的两侧形成第二侧壁12的同时还于一对第一侧壁11之间形成栅氧化层13，在一个可选的实施例中，第二侧壁12与栅氧化层13的材质均为氧化物，可以为二氧化硅。第二侧壁12与栅氧化层13可以采用同一原位水汽氧化工艺形成。第一侧壁11的厚度大小大于第二侧壁的12的厚度大小。
在其他可选的实施例中，如图13和图14所示，先于第一侧壁11的两侧通过原位水汽氧化工艺形成第二侧壁12，再通过原位水汽氧化工艺或其他工艺，如沉积工艺，于两第一侧壁11之间的衬底10上表面形成栅氧化层13，第二侧壁12与栅氧化层13的材质均为氧化物，可以同为二氧化硅。
对于步骤S40，如图15所示，具体的，于一对第一侧壁11之间的栅氧化层13上表面沉积多晶硅或金属以形成栅极层14，并栅极层14填充于一对第一侧壁11上的第二侧壁12之间，且栅极层14的上表面低于第一侧壁11的上表面。
如图2所示，在一个可选的实施例中，步骤S40之后还包括步骤S50；
步骤S50：于栅极层14的表面形成顶层介质层18，如图16所示。
对于步骤S50，具体的，通过沉积工艺与栅极层14的上表面沉积氮化硅或氧化硅以形成顶层介质材料层，经过平坦化工艺后形成顶层介质层18，顶层介质层18的上表面与第一侧壁11的上表面平齐。
通过上述半导体结构的制备方法，由于第二侧壁12通过原位水汽氧化形成，因此第二侧壁12的击穿电压更高且第二侧壁12内产生的缺陷更少，且第一侧壁11的两侧均形成有第二侧壁12，一方面提高了第一侧壁11与第二侧壁12降低栅极漏电流的能力，另一方面，第一侧壁11两侧均形成有第二侧壁12使得第一侧壁11两侧第二侧壁12在厚度上可以降低，从而减小了第二侧壁12中出现缺陷的可能性，从而进一步的提高第一侧壁11与第二侧壁12降低栅极漏电流的能力，提高器件的可靠性和使用寿命。
还提供了一种半导体结构，如图16所示，该半导体结构基于上述半导体结构的制备方法制备而成，包括衬底10，衬底可以为硅衬底、绝缘体上硅衬底或者包括III族、IV族和V族的其他半导体材料。衬底10内形成有浅沟槽隔离结构19，浅沟槽隔离结构19于衬底10内隔离出若干个有源区，有源区可以为掺杂有掺杂离子的区域，譬如，N型离子或P型离子等等；若干个有源区于衬底10内间隔排布。
有源区上形成有至少一对第一侧壁11，且各对中的第一侧壁11之间存在间距，第一侧壁11的材质可以为沉积形成的含硅介电层，在一个可选的实施例中，第一侧壁11包括氮化硅层或二氧化硅层。
第一侧壁11的两侧均形成有第二侧壁12，且一对第一侧壁11之间的有源区上形成有栅氧化层13，第二侧壁12与栅氧化层13相连，第二侧壁12与栅氧化层13的材质均为氧化物，在一个可选的实施例中可以为二氧化硅。第二侧壁12与栅氧化层13可以采用同一原位水汽氧化工艺形成。
栅氧化层13的上表面通过沉积多晶硅形成有栅极层14，栅极层14填充于一对第一侧壁11上的第二侧壁12之间，且栅极层14的上表面低于第一侧壁11的上表面。
在其可选的实施例中，栅极层14的上表面还形成有顶层介质层18，顶层介质层18的材料可以为氮化硅或氧化硅，对栅极层14起到保护作用。
通过上述半导体结构，第一侧壁11的两侧均形成有第二侧壁12，一方面提高了第一侧壁11与第二侧壁12降低栅极漏电流的能力，另一方面，第一侧壁11两侧均形成有第二侧壁12使得第一侧壁11两侧第二侧壁12在厚度上可以降低，从而减小了第二侧壁12中出现缺陷的可能性，从而进一步的提高第一侧壁11与第二侧壁12降低栅极漏电流的能力，提高器件的可靠性和使用寿命。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (11)

  1. 一种半导体结构的制备方法，包括：
    提供衬底；
    于所述衬底上形成至少一对第一侧壁，每对中的两个第一侧壁之间存在间距；
    采用原位水汽氧化工艺于所述第一侧壁的两侧形成第二侧壁，并于每对中的所述两个第一侧壁之间的衬底上形成栅氧化层；及
    于所述栅氧化层的表面形成栅极层。
  2. 根据权利要求1所述的方法，其特征在于，于所述衬底上形成所述第一侧壁包括：
    于所述衬底上形成牺牲层；
    于所述牺牲层上形成第一侧壁；及
    去除所述牺牲层。
  3. 根据权利要求2所述的方法，其特征在于，于所述牺牲层上形成所述第一侧壁包括：
    于所述牺牲层内形成侧壁凹槽；及
    于所述侧壁凹槽内形成第一侧壁。
  4. 根据权利要求1所述的方法，其特征在于，所述第一侧壁包括含硅介电层。
  5. 根据权利要求1所述的方法，其特征在于，所述第一侧壁为氮化硅层或二氧化硅层；所述第二侧壁为二氧化硅层。
  6. 根据权利要求1所述的方法，其特征在于，形成所述栅极层后，所述方法还包括：于所述栅极层的表面形成顶层介质层。
  7. 根据权利要求6所述的方法，其特征在于，所述顶层介质层包括氮化硅层或氧化硅层。
  8. 根据权利要求1所述的方法，其特征在于，
    采用所述原位水汽氧化工艺形成所述第二侧壁的反应温度为包括800℃～1100℃，反应压力包括6Torr～20Torr。
  9. 根据权利要求1所述的方法，其特征在于，
    采用所述原位水汽氧化工艺形成所述第二侧壁的反应气体包括氧气与氢气混合气体、一氧化氮与氢气混合气体或二氧化氮与氢气混合气体。
  10. 根据权利要求9所述的方法，其特征在于，
    所述混合气体中所述氢气的体积浓度为1％～33％。
  11. 一种半导体结构，基于权利要求1至10中任一项所述的方法制备而成。
PCT/CN2021/080361 2020-03-30 2021-03-12 半导体结构及其制备方法 WO2021197025A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050077565A1 (en) * 2003-10-10 2005-04-14 Renesas Technology Corp. Semiconductor memory device
CN101572230A (zh) * 2008-04-30 2009-11-04 中芯国际集成电路制造(北京)有限公司 提高栅极侧壁氧化层厚度一致性的方法及栅极的制造方法
CN103730341A (zh) * 2012-10-10 2014-04-16 中国科学院微电子研究所 半导体器件制造方法
CN103730345A (zh) * 2012-10-16 2014-04-16 中国科学院微电子研究所 半导体器件制造方法
CN109494191A (zh) * 2018-11-19 2019-03-19 武汉新芯集成电路制造有限公司 半导体器件及其制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030155582A1 (en) * 2002-02-19 2003-08-21 Maitreyee Mahajani Gate dielectric structures for integrated circuits and methods for making and using such gate dielectric structures
WO2007086304A1 (ja) * 2006-01-25 2007-08-02 Nec Corporation 半導体装置および半導体装置の製造方法
US9559184B2 (en) * 2015-06-15 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Devices including gate spacer with gap or void and methods of forming the same
US9627510B1 (en) * 2015-12-02 2017-04-18 International Business Machines Corporation Structure and method for replacement gate integration with self-aligned contacts
US10297510B1 (en) * 2018-04-25 2019-05-21 Internationel Business Machines Corporation Sidewall image transfer process for multiple gate width patterning
US10236364B1 (en) * 2018-06-22 2019-03-19 International Busines Machines Corporation Tunnel transistor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050077565A1 (en) * 2003-10-10 2005-04-14 Renesas Technology Corp. Semiconductor memory device
CN101572230A (zh) * 2008-04-30 2009-11-04 中芯国际集成电路制造(北京)有限公司 提高栅极侧壁氧化层厚度一致性的方法及栅极的制造方法
CN103730341A (zh) * 2012-10-10 2014-04-16 中国科学院微电子研究所 半导体器件制造方法
CN103730345A (zh) * 2012-10-16 2014-04-16 中国科学院微电子研究所 半导体器件制造方法
CN109494191A (zh) * 2018-11-19 2019-03-19 武汉新芯集成电路制造有限公司 半导体器件及其制备方法

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